Intrusion blocking device having unique id generated on basis of physical characteristics

Abstract

The present invention relates to an intrusion blocking device comprising: a printed circuit board (PCB) on which a processor to be protected is mounted; and an intrusion blocking cover comprising a controller having a storage space, the intrusion blocking cover being manufactured in a shape such that same can cover the processor to be protected, and bonded to the printed circuit board so as to seal the processor to be protected from the outside. The intrusion blocking cover comprises multiple connecting lines. The controller measures resistance values regarding multiple connecting line pairs and compare the measured resistance values. The controller generates binary values on the basis of the compared values and arranges the generated binary values, thereby generating a unique ID. In the storage space of the controller, data regarding which connecting lines are to be measured and compared, among the multiple connecting lines, is stored.

Description

Intrusion prevention device with a unique ID generated based on physical characteristics

[0001] The present invention relates to a penetration blocking device, and more particularly, to a penetration blocking device having a unique ID generated based on physical characteristics.

[0002] In today's information technology environment, data security has become a critical issue. Protecting sensitive data is essential for both businesses and individuals, who store and transmit it electronically. Encryption is widely used for data protection, encrypting data using encryption keys to protect it from unauthorized access.

[0003] Typically, encryption keys are stored within integrated circuits (ICs) using internal fuse ROM or non-volatile memory. However, the key information can be hacked using techniques such as X-ray imaging, and non-volatile memory can be hacked by reading the state of the device through a probe. Furthermore, encryption keys can be deduced by analyzing indirect indicators, such as power consumption patterns or electromagnetic emissions during normal IC operation. Therefore, measures are needed to effectively block external access to core components.

[0004] Previously, these protective measures involved methods for restricting the opening of cases or chassis or detecting opening events. For example, Korean Patent Laid-Open Publication No. 2013-0126804 (published on November 21, 2013, hereinafter referred to as “Patent Document 1”) discloses a tamper-responsive cover that uses a cover-like structure to cover exposed parts of a product, such as ICs or communication connectors that transmit data, and stores security and authentication-related data exposed on the inside or outside of the product, and protects the exposed parts from illegal modification and tampering. When the cover is separated from the PCB board or a hole is made in the cover for hacking purposes, the cover reacts to this by deleting important data or rendering it inoperable, thereby protecting the data from illegal modification and tampering. However, the structure disclosed in Patent Document 1 has limitations in effectively blocking external access to components containing important information.

[0005] An object of the present invention is to provide an intrusion prevention device having a unique ID generated based on physical characteristics when using an intrusion prevention device that effectively blocks external access.

[0006] Another object of the present invention is to enable the use of different private keys in different intrusion prevention devices.

[0007] Another object of the present invention is to provide a penetration barrier device that does not require the use of an internal battery.

[0008] However, the technical task that this embodiment seeks to achieve is not limited to the technical task described above, and other technical tasks may exist.

[0009] According to one embodiment of the present invention, an intrusion prevention device includes a printed circuit board (PCB) on which a processor to be protected is mounted, and an intrusion prevention cover including a controller having a storage space and manufactured in a shape capable of covering the processor to be protected and bonded to the printed circuit board (PCB) to seal the processor to be protected from the outside, wherein the intrusion prevention cover includes a plurality of connection lines, and the controller measures resistance values ​​for pairs of the plurality of connection lines, compares the measured resistance values, generates binary values ​​for the connection line pairs based on the compared values, and arranges the generated binary values ​​to generate a unique ID, and data regarding which connection lines among the plurality of connection lines are to be measured and compared can be stored in the storage space of the controller.

[0010] According to one embodiment, the penetration barrier cover may be a flexible printed circuit board (FPCB).

[0011] According to one embodiment, the storage space of the controller may be volatile memory.

[0012] According to one embodiment, when an attack from outside is detected, the controller can delete the private key stored in the storage space so that the external attacker cannot read the important information.

[0013] According to one embodiment, the number of pairs of connecting lines may be equal to the bit-wise length of the unique ID.

[0014] According to one embodiment, the measurement of the resistance value can be implemented by an ADC included in the controller.

[0015] According to one embodiment, the bits of the unique ID can be determined from an array of any two non-duplicate combinations of the measured resistances by measuring the resistance of all connecting lines.

[0016] According to one embodiment, the bits of the unique ID can be determined by having an array of any two combinations of the number of resistances measured on the connecting line, but allowing for duplication.

[0017] According to one embodiment, the first bit of the unique ID compares the measured values ​​of two resistors forming a first combination and assigns 1 if the former value is greater, otherwise 0; the second bit compares the measured values ​​of two resistors forming a second combination and assigns 1 if the former value is greater, otherwise 0; the third bit compares the measured values ​​of two resistors forming a third combination and assigns 1 if the former value is greater, otherwise 0; and by repeating the process of comparing the measured values ​​of two resistors and assigning 1 if the former value is greater, otherwise 0, up to the nth bit, n bits can be generated.

[0018] According to the present invention, it is possible to provide an intrusion prevention device having a unique ID generated based on physical characteristics.

[0019] Additionally, according to the present invention, different private keys can be used in different intrusion prevention devices.

[0020] In addition, according to the present invention, a penetration blocking device that does not require the use of an internal battery can be provided.

[0021] FIG. 1 is a side cross-sectional view showing a penetration blocking device according to one embodiment of the present invention.

[0022] Figure 2 is a plan view showing a penetration blocking cover according to one embodiment of the present invention.

[0023] Figure 3 is a perspective view showing a penetration blocking cover according to one embodiment of the present invention.

[0024] Figure 4 is a block diagram showing the configuration of a controller that generates a unique ID of an intrusion prevention device.

[0025] FIG. 5 is a schematic diagram illustrating a method for generating a unique ID by combining arbitrary pairs of connecting lines according to another embodiment of the present invention.

[0026] FIG. 6 is a schematic diagram illustrating a method for reducing the number of connecting lines according to another embodiment of the present invention.

[0027] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily implement them. The present invention is susceptible to various modifications and embodiments, and specific embodiments are illustrated in the drawings and specifically described in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0028] To clearly explain the present invention, parts irrelevant to the description have been omitted from the drawings, and similar parts have been designated with similar drawing reference numerals throughout the specification. In addition, when describing with reference to the drawings, even if components are indicated by the same name, the drawing numbers may vary depending on the drawing. The drawing numbers are described merely for the convenience of explanation, and the concept, feature, function, or effect of each component is not limited by the drawing numbers.

[0029] In describing each drawing, similar reference numerals are used to refer to similar components. Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component, without departing from the scope of the present invention. The term "and / or" includes any combination of multiple related listed items or any one of multiple related listed items.

[0030] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0031] Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0032] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "electrically connected" with another element in between. Furthermore, when a part is said to "include" a component, this should be understood to mean that it may include other components rather than excluding other components unless specifically stated to the contrary, and does not preclude the presence or possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0033] In this specification, the term 'unit' includes a unit realized by hardware or software, and a unit realized using both, and one unit may be realized using two or more pieces of hardware, or two or more units may be realized by one piece of hardware.

[0034] Hereinafter, a penetration blocking device having a unique ID generated based on physical characteristics according to the present invention will be described in detail with reference to the attached drawings.

[0035] FIG. 1 is a side cross-sectional view showing a penetration blocking device according to one embodiment of the present invention.

[0036] Referring to FIG. 1, a penetration blocking device (100) according to one embodiment of the present invention is for taking necessary measures against physical penetration into a digital device, and may include a printed circuit board (110), a protected processor (120) mounted on the printed circuit board (110), a memory (130), an penetration blocking cover (140), a controller (150), and a storage space (151) included in the controller. Parts indicated by dotted lines in FIG. 1 represent electronic components (161, 162) mounted on the printed circuit board.

[0037] The printed circuit board (110) may be configured by stacking multiple layers, and the internal configuration of the printed circuit board (110) may be configured with a variety of layers, such as a signal layer, a power layer, a ground layer, and an insulating layer. However, the present invention is not limited thereto, and the design of each layer may be changed according to various applications, and a combination of each layer is also possible.

[0038] The processor (120) to be protected is mounted on a printed circuit board (110) and may correspond to a processor provided in various types of computing devices such as a personal computer (PC), a server device, a mobile device, an embedded device, an Internet of Things (IoT) device, etc. For example, the processor may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), or a neural processing unit (NPU). In the embodiment of the present invention, the processor (120) to be protected is located within a range covered by the penetration prevention cover (140) and may control the operation of the digital device.

[0039] The memory (130) is a hardware that stores various data processed by the processor (120) to be protected, and can store various programs or applications to be driven by the processor (120) to be protected. The memory (130) may include at least one of volatile memory and nonvolatile memory. The nonvolatile memory may include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FeRAM (Ferroelectric RAM), etc. The volatile memory may include DRAM (Dynamic RAM), SRAM (Static RAM), SDRAM (Synchronous DRAM), PRAM, MRAM (Magnetic RAM), RRAM (Resistive RAM), etc.

[0040] The penetration blocking cover (140) is implemented in a three-dimensional shape to prevent the processor (120) and memory (130) to be protected from external intrusion, and may be formed to completely cover the processor (120) and / or memory (130) to be protected. In addition, the penetration blocking cover (140) may be formed to be sealed by being bonded to a printed circuit board (110). The penetration blocking cover (140) may be manufactured in various shapes and materials that can defend against physical attacks from the outside, and may preferably be manufactured as a flexible printed circuit board (FPCB). When a flexible circuit board is used, it may be manufactured in a two-dimensional shape and then transformed into a three-dimensional shape that surrounds the processor (120) and / or memory (130) to be protected using an origami technique. More preferably, the penetration blocking cover (140) may be manufactured in a three-dimensional shape using, for example, a no-cut technique among origami techniques, and then installed by being bonded to a printed circuit board. The materials and structures of flexible circuit boards can be selected in various ways depending on their heat transfer characteristics.

[0041] The penetration blocking cover (140) may include a controller (150). The controller (150) may be implemented as, for example, an MCU (Micro Control Unit), and input / output ports and other peripheral devices may be integrated into a single chip.

[0042] A separate storage space (151) may be included within the controller (150). Here, the storage space (151) may be composed of volatile memory. The volatile memory may include DRAM, SRAM, SDRAM, PRAM, MRAM, RRAM, etc.

[0043] The protected processor (120) can record important information in a separate storage space (151) provided inside the controller (150). Here, the important information may be settings required for the protected processor (120) to operate and / or an encryption key used to encrypt these settings.

[0044] If an external attacker obtains a digital device and attempts to attack core hardware or steal important information, the external attacker must destroy the intrusion prevention cover (140) to access the internal core hardware (e.g., the protected processor (120) and / or memory (130)). In the present invention, the intrusion prevention cover (140) itself operates as an encryption key or a secret key, so that if the intrusion prevention cover (140) is destroyed by an external attack, the encryption key or secret key can be destroyed. The specific operation thereof will be described with reference to FIG. 6.

[0045] The protected processor (120), memory (130), and controller (150) may be directly or indirectly connected via a communication interface that transmits and receives data signals. The communication interface defines the format, transmission speed, connection method, etc. of the data, and may communicate via digital or analog signals. For example, UART (Universal Asynchronous Receiver / Transmitter), I2C (Inter-Integrated Circuit), and USB (Universal Serial Bus) may be used.

[0046] FIG. 2 is a plan view showing a penetration blocking cover according to one embodiment of the present invention, and FIG. 3 is a perspective view showing a penetration blocking cover according to one embodiment of the present invention.

[0047] Referring to FIGS. 1 to 3, the penetration barrier cover (140) may be manufactured using a flexible printed circuit board (FPCB). Unlike traditional rigid PCBs, FPCBs have the ability to bend and fold. FPCBs are typically formed by laminating a copper layer on a flexible film, such as polyimide or polyester, to form a conductive pattern (e.g., a circuit), and then adding a protective layer to protect the conductive pattern.

[0048] In some embodiments, a conductor pattern may be formed in the first layer and / or the second layer, and a ground layer may be formed between the first layer and the second layer.

[0049] In another embodiment, the FPCB may be composed of multiple layers, each of which may have a conductive pattern formed thereon. Furthermore, ground layers may be sequentially arranged between each layer, or ground layers may be arranged between layers depending on various applications. The number and order of the layers to be laminated are not limited to the examples described above, and various applications are possible as required by those skilled in the art.

[0050] The conductive pattern implemented in the first layer and / or the second layer includes a plurality of circuits / connections. The plurality of circuits / connections are electrically connected to a controller contained within the intrusion-resistant cover, enabling detection of intrusion or security risks and transmission of signals. The circuits / connections located within each layer may be electrically connected to each other via vias.

[0051] Due to the nature of FPCBs, even if the length and width of the connecting wires are identical, slight errors in resistance can occur. When a penetration barrier is used to protect the processor and / or memory being protected from physical attacks, the connecting wires that constitute the penetration barrier have different resistance values ​​even if they are of the same length. This can be exploited to derive the private / public key pair used by the penetration barrier from its physical characteristics, allowing the penetration barrier to operate without an internal battery and with an unlimited lifespan.

[0052] In some embodiments, the intrusion prevention device can generate a unique ID (unique digital ID data) using the physical characteristics of the intrusion prevention device itself. If the intrusion prevention device is damaged by an external attack, the physical characteristics of the intrusion prevention device change, and thus the unique ID that can be read from it changes. In other words, the unique ID that was read before the intrusion prevention device was damaged is damaged. If this unique ID is used as an encryption key to encrypt and store some information, the unique ID will also be damaged when the intrusion prevention cover (140) is damaged, making it impossible to read the encrypted and stored important information. If this unique ID is used as a private key in a public key pair and a certificate is issued using this private key, the private key will also be damaged when the intrusion prevention cover (140) is damaged, making it impossible to perform a signing act using the certificate. In the present invention, the intrusion prevention cover (140) is configured to operate with an encryption key or a private key.

[0053] Fig. 4 is a block diagram showing the configuration of a controller (300) that generates a unique ID of an intrusion prevention device.

[0054] Referring to FIG. 4, the controller (300) of the penetration blocking device may include a measuring unit (310) that obtains a resistance value of a pair of connecting lines, a comparison unit (320) that compares the obtained resistance values, a binarization unit (330) that generates a binary value based on the compared values, and a unique ID generation unit (340) that generates a unique ID.

[0055] The measuring unit (310) selects any two connecting lines and acquires the resistance value for each connecting line in order to generate the first digital data that becomes the input of the unique ID. The 'resistance value' may not only directly measure the resistance, but may also include data that shows a direct correlation with the resistance value. This may include the resistance value itself or a differential value that changes in proportion to the resistance. The resistance value may be determined according to the resolution of the measuring unit (310) (e.g., 1 / 4000Ω). Preferably, the resistance value can be measured and calculated through an ADC (analog-to-digital converter). Generally, an ADC can only measure voltage, so in order to directly measure the resistance, the relationship between voltage and current must be utilized. By measuring the voltage applied across the resistor through the ADC and using the measured voltage and a known reference resistance value, the flowing current can be calculated, and thereby the resistance value to be measured can also be calculated.

[0056] The comparison unit (320) can compare each measured resistance value with each other and determine which one is greater.

[0057] The binary unit (330) can assign a value of '1' or '0' as the first digital data based on the result determined by the comparison unit (320). These values ​​become unique values ​​that do not change unless the circuit is damaged.

[0058] The controller (300) selects another two arbitrary connection lines, and causes the measurement unit (310) to obtain the resistance values ​​for another two arbitrary connection lines. As described above, the comparison unit (320) compares each resistance value with each other to determine which one is greater, and the binarization unit (330) can binarize the resistance values ​​and assign a value of '1' or '0' as second digital data. By repeating this process, the nth digital data can be obtained. Here, the number of n is preferably the same as the number of connection line pairs, but the number of n need not be limited thereto, and can be selected in various ways according to design changes by a person skilled in the art.

[0059] The unique ID generation unit (340) can generate a unique ID by arranging the binary values ​​generated from the binarization unit (330). That is, the first digital data, the second digital data, …, n-th digital data can be arranged to generate a unique ID of the intrusion prevention device. By arranging the binary values ​​of the connection line pairs in this way and using them as the unique ID of the intrusion prevention device and deriving them as a private key, different private keys can be used in different intrusion prevention devices.

[0060] In Fig. 4, the measurement unit (310), comparison unit (320), binarization unit (330), and unique ID generation unit (340) are individually described to aid understanding, but the functions performed by each unit may be integrated and operated in one processor or IC, or may be implemented in various applications through combinations.

[0061] FIG. 5 is a schematic diagram illustrating a method for generating a unique ID by combining arbitrary pairs of connection lines according to another embodiment of the present invention.

[0062] Referring to Fig. 5, the number of pairs of connecting lines is set to be equal to the bit-unit length (N) of the unique ID to be created. In other words, the number of connecting lines must be twice the bit-unit length of the unique ID (2N). The controller of the intrusion prevention device measures the resistance of all connecting lines using the ADC function. The controller of the intrusion prevention device has an array that randomly combines numbers from 1 to 2N without duplication.

[0063] The first bit of the unique ID can be assigned a '1' if A1 is greater than A2 by comparing A1 and A2, otherwise it can be assigned a '0'. The second bit of the unique ID can be assigned a '1' if A1 is greater than A2 by comparing A3 and A4, and the third bit of the unique ID can be assigned a '1' if A1 is greater than A2 by comparing A3 and A4. By repeating this process, N bits can be created. The array of N bits can be stored in the internal space of the intrusion prevention device's controller and can be used continuously until it is erased.

[0064] Additionally, the controller can be configured to prevent external reading of the array of N bits. For example, a Debug Protection Mechanism (DPM) can be configured to prevent external access to the controller's internal state and control of its operation. Debugging may be necessary during the development phase of a controller (e.g., an MCU), but debugging can be restricted after mass production to protect the developer or operator's assets. When the controller is powered on and the pre-recorded firmware is executed, setting the debug control value to a specific value (e.g., 1) prevents external access to the debug function.

[0065] Meanwhile, in the event of an intrusion, the unique ID can be removed by deleting the array of N bits stored within the controller of the intrusion prevention device. Specifically, the deletion process can utilize the functionality provided by the controller hardware. By utilizing a specific register in the tamper controller included in the intrusion prevention cover, the hardware can be configured to delete information stored within the controller without software intervention when an intrusion occurs.

[0066] FIG. 6 is a schematic diagram illustrating a method for reducing the number of connecting lines according to another embodiment of the present invention.

[0067] Referring to Fig. 6, the bit length of the unique ID to be generated is set to N. The number of connection lines is set to M, which corresponds to the capacity that can be measured by the ADC provided by the controller of the infiltration prevention cover. The resistance values ​​measured at each connection line through the ADC are R1, R2, ..., R M can be expressed as

[0068] The controller of the penetration blocking cover is from R1 to R M An array is formed by randomly combining two resistance values ​​from among the resistance values ​​up to , but duplicate combinations can be allowed. For example, each bit that constitutes a unique ID is a combination of two resistance values, B1, B2, ..., B N It can be composed of . Here, B1 can be a combination of R1 and R2, or a combination of R3 and R4.

[0069] These combinations determine the value of the first bit of the unique ID. For example, the actual measured values ​​of the two resistors R that form the B1 combination are compared, and if the first resistance value is greater than the second resistance value, the first bit of the unique ID is assigned a '1', otherwise a '0'. This comparison and assignment process is similarly applied to the B2 combination for the second bit, and the B3 combination for the third bit, and this is repeated until N bits are completed to form the entire unique ID.

[0070] B1 to B N The R combination array up to is the information required to create a unique ID, which is securely stored in the internal memory of the intrusion prevention cover controller and is protected from external access. This setting includes disabling the debug function. This measure enhances the security of the intrusion prevention cover system and prevents the unique ID from being exposed to the outside. Since disabling the debug function is the same as described in other embodiments, a detailed description thereof will be omitted here.

[0071] If the system experiences an external intrusion, the unique ID can be immediately removed by deleting the stored R combination array. Specifically, the deletion process can utilize functions provided by the controller hardware. By using a specific register in the tamper controller included in the intrusion prevention cover, the hardware can be configured to delete information stored within the controller without software intervention in the event of an intrusion.

[0072] The embodiments of the present invention described above may also be implemented in the form of a recording medium containing computer-executable instructions, such as program modules executed by a computer. Computer-readable recording media may include computer storage media, and computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data.

[0073] Although the devices and methods of the present invention have been described with respect to specific embodiments, some or all of their components or operations may be implemented using a computer system having a general-purpose hardware architecture.

[0074] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will readily appreciate that the present invention can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single entity may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined manner.

[0075] The scope of the present invention is indicated by the claims described below rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

Claims

1. As an intrusion prevention device, A printed circuit board on which a protected processor is mounted; and A penetration-blocking cover including a controller having a storage space, which is manufactured in a shape that can cover the above-mentioned processor to be protected and is bonded to a printed circuit board (PCB) to seal the above-mentioned processor from the outside, The above penetration blocking cover comprises a plurality of connecting lines, The controller measures resistance values ​​for pairs of the plurality of connecting lines, compares the measured resistance values, generates binary values ​​for pairs of the connecting lines based on the compared values, and arranges the generated binary values ​​to generate a unique ID. A penetration prevention device in which data regarding which of the plurality of connection lines are to be measured and compared is stored in the storage space of the above controller.

2. In paragraph 1, The above penetration blocking cover is a penetration blocking device that is a flexible printed circuit board (FPCB).

3. In paragraph 1, The storage space of the above controller is a volatile memory, an intrusion prevention device.

4. In paragraph 1, An intrusion prevention device that, when an attack from outside is detected, deletes the data stored in the storage space so that an external attacker cannot read important information.

5. In paragraph 1, A penetration blocking device in which the number of pairs of the above connecting lines is equal to the bit length of the unique ID.

6. In paragraph 1, A penetration blocking device, wherein the measurement of the above resistance value is implemented by an ADC included in the controller.

7. In paragraph 1, A device for preventing intrusion, wherein the bits of the above unique ID are determined from an array of two random combinations of the number of resistances measured by measuring the resistance of all connecting lines without duplication.

8. In paragraph 1, A penetration blocking device in which the bits of the above unique ID are arranged to have an array of two random combinations of the number of resistances measured on the connection line, but allowing duplication.

9. In paragraph 7 or 8, The first bit of the above unique ID compares the measured values ​​of the two resistors that constitute the first combination and assigns 1 if the former value is greater, otherwise 0; the second bit compares the measured values ​​of the two resistors that constitute the second combination and assigns 1 if the former value is greater, otherwise 0; the third bit compares the measured values ​​of the two resistors that constitute the third combination and assigns 1 if the former value is greater, otherwise 0; A device that generates n bits by comparing the measured values ​​of two resistors and repeating the process of assigning 1 if the former value is larger, or 0 if not, up to the nth bit.

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