Packaging substrate of duplexer, and duplexer

Abstract

The embodiments of the present application relate to the field of semiconductors, in particular to a packaging substrate of a duplexer, and a duplexer. The packaging substrate comprises a plurality of wiring layers and a plurality of conductive through holes provided between adjacent wiring layers, wherein the plurality of wiring layers comprise a first wiring layer, a second wiring layer and a third wiring layer, which are located in an intermediate wiring layer; at least a part of a first inductor and a first grounding portion are provided on the first wiring layer, the first inductor is connected to a transmission filter by means of a conductive through hole, and the transmission filter is grounded by means of the conductive through hole and the first grounding portion; at least a part of a second inductor and a second grounding portion are provided on the second wiring layer, the second inductor is connected to a reception filter by means of a conductive through hole, and the reception filter is grounded by means of the conductive through hole and the second grounding portion; and a third inductor and a fourth inductor are provided on the third wiring layer, wherein the area of the first grounding portion and / or the area of the second grounding portion are at least twice the area of a conductive through hole connected to an inductor in a corresponding wiring layer.

Description

Duplexer packaging substrate and duplexer

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of a Chinese patent application with application number 202410185868.7, application date February 19, 2024, and invention name “Packaging substrate for duplexer and duplexer”. The entire content of the Chinese patent application is hereby incorporated into this disclosure as a reference. Technical Field

[0003] The embodiments of the present application relate to, but are not limited to, a packaging substrate for a duplexer and a duplexer. Background Art

[0004] Currently, 5G technology is driving a comprehensive upgrade of mobile phone terminal RF systems. With the exponential increase in the number of base station antenna channels, the demand for RF filters and duplexers has increased significantly to add communication capabilities in new frequency bands. With the continuous advancement of communication technology and mobile terminal manufacturing technology, market requirements for RF filter size, power consumption, and performance are constantly increasing. The demand for high-performance RF filters is increasing, and improving filter performance is a topic of active research in the communications industry.

[0005] Summary of the Invention

[0006] An embodiment of the present application provides a packaging substrate for a duplexer, which includes multiple wiring layers and multiple conductive vias arranged between adjacent wiring layers; the multiple wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer; at least a portion of a first inductor and a first ground portion are arranged on the first wiring layer, the first inductor is connected to a transmitting filter through a conductive via, and the transmitting filter is grounded through the conductive via and the first ground portion; at least a portion of a second inductor and a second ground portion are arranged on the second wiring layer, the second inductor is connected to a receiving filter through a conductive via, and the receiving filter is grounded through the conductive via and the second ground portion; a third inductor and a fourth inductor are arranged on the third wiring layer, the third inductor is respectively connected to the transmitting filter and the antenna end of the duplexer through the conductive via, and the fourth inductor is respectively connected to the receiving filter and the antenna end of the duplexer through the conductive via; wherein the area of ​​the first ground portion and / or the area of ​​the second ground portion is at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer.

[0007] The embodiment of the present application also provides a duplexer, which includes: a packaging substrate and a transmitting filter and a receiving filter located on the packaging substrate; wherein the transmitting filter is configured to send a transmitting signal to an antenna end; the receiving filter is configured to receive a signal from the antenna end; the transmitting filter and the receiving filter are connected to an inductor of the packaging substrate; wherein the packaging substrate includes a plurality of wiring layers and a plurality of conductive vias arranged between adjacent wiring layers; the plurality of wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in an intermediate wiring layer; at least a portion of a first inductor and a first ground portion are arranged on the first wiring layer, and the first inductor is connected to the transmitting signal through the conductive vias. The transmitting filter is connected, and the transmitting filter is grounded through a conductive through-hole and a first grounding portion; at least a part of the second inductor and the second grounding portion is arranged on the second wiring layer, the second inductor is connected to the receiving filter through the conductive through-hole, and the receiving filter is grounded through the conductive through-hole and the second grounding portion; the third inductor and the fourth inductor are arranged on the third wiring layer, the third inductor is respectively connected to the transmitting filter and the antenna end of the duplexer through the conductive through-hole, and the fourth inductor is respectively connected to the receiving filter and the antenna end of the duplexer through the conductive through-hole; wherein the area of ​​the first grounding portion and / or the area of ​​the second grounding portion is at least twice the area of ​​the conductive through-hole connected to the inductor in the corresponding wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG1A is an equivalent circuit diagram of an example of a duplexer using the first packaging substrate provided in an embodiment of the present application;

[0009] FIG1B is an equivalent circuit diagram of an example of a duplexer using the second packaging substrate provided in an embodiment of the present application;

[0010] FIG2 is a schematic cross-sectional view of a packaging substrate provided in an embodiment of the present application;

[0011] 3A and 3B are schematic diagrams of the planar layouts of a first wiring layer and a second wiring layer of a package substrate provided as a first comparative example in an embodiment of the present application;

[0012] FIG3C is a perspective view of a package substrate according to a first comparative example provided in an embodiment of the present application;

[0013] 4A , 4B , and 4C are schematic diagrams of planar layouts of a first wiring layer, a second wiring layer, and a third wiring layer of a first packaging substrate provided in an embodiment of the present application, respectively;

[0014] FIG4D is a schematic top view of a first packaging substrate provided in an embodiment of the present application;

[0015] FIG4E is a perspective view of a first packaging substrate provided in an embodiment of the present application;

[0016] FIG5 shows a graph comparing the isolation between the TX and RX frequency bands of the first packaging substrate of the present application and the packaging substrate of the first comparative example;

[0017] 6 is a graph comparing the isolation between TX and RX frequency bands of the first, third, and fifth packaging substrates of the present application and a packaging substrate as a second comparative example;

[0018] FIG7 is a graph showing the comparison of the isolation between the TX and RX frequency bands of the first packaging substrate, the sixth packaging substrate, and the packaging substrate as a second comparative example of the present application;

[0019] FIG8 is a graph comparing the isolation between TX and RX frequency bands of the first packaging substrate, the seventh packaging substrate, and the packaging substrate as a second comparative example of the present application;

[0020] FIG9 is a graph comparing the isolation between the TX and RX frequency bands of the first packaging substrate, the third packaging substrate, and the packaging substrate as a second comparative example of the present application;

[0021] 10A , 10B , and 10C are schematic diagrams of planar layouts of a first wiring layer, a second wiring layer, and a third wiring layer of a second packaging substrate provided in an embodiment of the present application, respectively;

[0022] 11A , 11B , and 11C are schematic diagrams of the planar layouts of the first wiring layer, the second wiring layer, and the third wiring layer of the third packaging substrate provided in an embodiment of the present application, respectively;

[0023] FIG11D is a schematic top view of a third packaging substrate provided in an embodiment of the present application;

[0024] 12A and 12B are schematic diagrams of the planar layout of the first wiring layer and the second wiring layer of the fourth packaging substrate provided in an embodiment of the present application, respectively;

[0025] 13A and 13B are respectively schematic diagrams of the second planar layout of the first wiring layer and the second wiring layer of the fourth packaging substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solution of the present application will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings show exemplary implementation methods of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0027] The following paragraphs describe the present application in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present application.

[0028] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0030] The demand for high-performance RF devices is increasing. For duplexers, isolation is one of the key performance factors. Therefore, obtaining high-isolation duplexers without sacrificing other performance factors is a topic of active research in the communications industry.

[0031] The wire-wound inductors of the transmit (TX) filter and the receive (RX) filter on the duplexer's package substrate are prone to coupling, which affects the duplexer's isolation. To improve duplexer isolation, the inductance of the wire-wound inductors on the package substrate is often increased, or devices such as inductors or capacitors are added. However, this introduces more losses and requires a larger footprint.

[0032] In view of this, an embodiment of the present application provides a packaging substrate and a duplexer for a duplexer, which can improve the isolation between the winding inductor of the TX filter and the winding inductor of the RX filter without changing the inductance value and volume of the winding inductor on the packaging substrate.

[0033] FIG1A is an equivalent circuit diagram of an example of a duplexer using the first package substrate provided in an embodiment of the present application. As shown in FIG1A , the duplexer 100 may include a resonator and a matching inductor. The matching inductor includes a series inductance (e.g., the first inductor L) of a parallel resonator (e.g., the third resonator S3) of a TX filter. TX ), the series inductance (eg, the second inductor L) of the parallel resonator (eg, the fourth resonator S4) of the RX filter RX ), the inductance between the resonator of the TX filter and the antenna terminal ANT (for example, the third inductor L TXA ), and the inductance between the resonator of the RX filter and the antenna terminal ANT (eg, the fourth inductor L RXA ). The series inductance (eg, the first inductor L) of the parallel resonator (eg, the third resonator S3) of the TX filter TX) is grounded GND, and the series inductance (eg, the second inductor L) of the parallel resonator (eg, the fourth resonator S4) of the RX filter is connected to the ground GND. RX ) is grounded to GND.

[0034] FIG1B is an equivalent circuit diagram of an example of a duplexer using the second package substrate provided in an embodiment of the present application. As shown in FIG1B , the duplexer 100 may include a resonator and a matching inductor. The matching inductor includes a series inductor (e.g., the first inductor L) of a parallel resonator (e.g., the third resonator S3) of a TX filter. TX ), the series inductance (eg, the second inductor L) of the parallel resonator (eg, the fourth resonator S4) of the RX filter RX ), a series inductor (e.g., a fifth inductor L) between the first resonator S1 of the TX filter and the input / output terminal I / O TXO ), a series inductor (e.g., a sixth inductor L) between the second resonator S2 of the RX filter and the input / output terminal I / O RXO ), the inductance between the resonator of the TX filter and the antenna terminal ANT (for example, the third inductor L TXA ), and the inductance between the resonator of the RX filter and the antenna terminal ANT (eg, the fourth inductor L RXA ). The series inductance (eg, the first inductor L) of the parallel resonator (eg, the third resonator S3) of the TX filter TX ) is grounded GND, and the series inductance (eg, the second inductor L) of the parallel resonator (eg, the fourth resonator S4) of the RX filter is connected to the ground GND. RX ) is grounded to GND.

[0035] In some embodiments, the matching inductor may be formed in the package substrate of the duplexer in the form of a wire wound inductor.

[0036] Those skilled in the art will recognize that although the transmitting end and the receiving end of the duplexer 100 shown in FIG1A and FIG1B each have five series resonators and four parallel resonators and corresponding four matching inductors, the present application is not limited thereto. Those skilled in the art may use other numbers and connection forms of resonators and corresponding matching inductors according to specific application scenarios and design requirements, and all variations shall be included within the scope of the present application.

[0037] FIG2 is a cross-sectional schematic diagram of a packaging substrate provided by an embodiment of the present application. As shown in FIG2, in a first aspect, an embodiment of the present application provides a packaging substrate for a duplexer, wherein the packaging substrate 200 includes multiple wiring layers and multiple conductive vias CV disposed between adjacent wiring layers; the multiple wiring layers include a first wiring layer A, a second wiring layer B, and a third wiring layer C located in the middle wiring layer; at least a portion of a first inductor L is disposed on the first wiring layer A. TX and the first ground portion G TX , the first inductor L TX The transmitting filter is connected to the transmitting filter through the conductive through hole CV, and the transmitting filter is connected to the first grounding portion G through the conductive through hole CV. TX Ground; at least part of the second inductor L is provided on the second wiring layer B RX and the second ground portion G RX , the second inductor L RX The receiving filter is connected to the ground through the conductive through hole CV and the grounding portion G. RX ; A third inductor L is provided on the third wiring layer C TXA With the fourth inductor L RXA , the third inductor L TXA The fourth inductor L is connected to the transmitting filter and the antenna terminal ANT of the duplexer through the conductive via CV. RXA The first grounding portion G is connected to the receiving filter and the antenna terminal ANT of the duplexer through the conductive via CV. TX The area and / or the second ground portion G RX The area of ​​the conductive via CV connected to the inductor in the corresponding wiring layer is at least twice the area of ​​the conductive via CV connected to the inductor in the corresponding wiring layer.

[0038] In some other embodiments, the third inductor L TXA Through the conductive via CV and the first inductor L TX After the connection, it is connected to the antenna terminal ANT of the transmitting filter and duplexer, and the fourth inductor L RXA Through the conductive via CV and the second inductor L RX After connection, connect to the antenna terminal ANT of the receiving filter and duplexer.

[0039] In some specific embodiments, the material of the wiring layer and the material of the conductive via include a conductive material. For example, the material of the first wiring layer A, the second wiring layer B, and the third wiring layer C and the material of the conductive via CV can be a conductive metal material, and the conductive metal material includes but is not limited to copper (Cu).

[0040] In some specific embodiments, the package substrate 200 further includes a dielectric layer (not shown in FIG. 2 ) disposed between adjacent wiring layers, and the dielectric layer is made of an insulating dielectric material. For example, the dielectric layer may be made of an insulating dielectric material having a dielectric constant greater than 3.6.

[0041] Those skilled in the art will recognize that although the present application describes the embodiments of the present application by taking the package substrate 200 including the first to third wiring layers and conductive vias between adjacent wiring layers as an example, the present application is not limited thereto. Those skilled in the art may use other numbers of wiring layers and corresponding conductive vias according to application scenarios and design requirements, and all such variations shall be included within the scope of the present application.

[0042] 3A and 3B are schematic diagrams of the planar layout of the first wiring layer and the second wiring layer of the packaging substrate provided as the first comparative example in an embodiment of the present application, and FIG3C is a schematic perspective view of the packaging substrate provided as the first comparative example in an embodiment of the present application.

[0043] Figures 4A, 4B, and 4C are schematic diagrams of the planar layouts of the first wiring layer, the second wiring layer, and the third wiring layer of the first packaging substrate provided in an embodiment of the present application, respectively; Figure 4D is a schematic top view of the first packaging substrate provided in an embodiment of the present application; and Figure 4E is a schematic perspective view of the first packaging substrate provided in an embodiment of the present application. It should be noted that Figure 4E does not show the conductive vias between adjacent wiring layers, but shows the pattern of the contact portion of the conductive via (the portion in the wiring layer that contacts the conductive via) in the wiring layer. For example, the conductive vias described in the following embodiments are all presented in the wiring layer that contacts the conductive via in the form of the contact portion of the conductive via.

[0044] Compared with the first packaging substrate shown in Figures 4A to 4E, in the packaging substrate as the first comparative example shown in Figures 3A to 3C, the first wiring layer includes a first inductor and does not include a large-area first grounding portion, the second wiring layer includes a second inductor and does not include a large-area second grounding portion, and the first grounding portion of the first wiring layer and the second grounding portion of the second wiring layer are both arranged in the form of conductive through-holes.

[0045] FIG5 shows one of the graphs comparing the isolation between the TX and RX frequency bands of the first package substrate and the package substrate as the first comparative example. Specifically, FIG5 shows a graph comparing the isolation between the package substrate as the first comparative example shown in FIG3A to FIG3C (hereinafter referred to as the first comparative example) and the first package substrate shown in FIG4A to FIG4E (hereinafter referred to as case 1).

[0046] In the isolation curves of the duplexers shown in Figures 5 to 9, taking Figure 5 as an example, the frequency band between 1.910 GHz and 1.930 GHz is the transition band between the frequency band of the TX filter and the frequency band of the RX filter, the frequency band between 1.850 GHz and 1.910 GHz is the frequency band of the TX filter (hereinafter referred to as the "left side"), and the frequency band between 1.930 GHz and 1.990 GHz is the frequency band of the RX filter (hereinafter referred to as the "right side"). Isolation on the left refers to isolation within the TX filter band, and isolation on the right refers to isolation within the RX filter band.

[0047] The differences between the first comparative example in FIG5 and case 1 include that, compared with case 1 in FIG5, the wiring layer of the first comparative example in FIG5 does not have the third wiring layer C in case 1 (refer to FIG4E and FIG4C), and the first wiring layer and the second wiring layer do not have the first ground portion G in case 1. TX and the second ground portion G RX (See Figures 4E, 4A, and 4B.) The similarities between the first comparative example in Figure 5 and Case 1 include that the first inductor and the second inductor are separated and distributed on the first wiring layer and the second wiring layer, respectively. That is, the first inductor and the second inductor in the first comparative example in Figure 5 and Case 1 are both located in different wiring layers.

[0048] As shown in FIG5 , compared with the first comparative example, Case 1 includes a third wiring layer C, a first ground portion G TX and the second ground portion G RX , the isolation within the TX and RX filter bands has been significantly improved, that is, the overall isolation of the duplexer has been significantly improved.

[0049] As shown in FIG. 4E and FIG. 4A to FIG. 4D , in some embodiments, the plurality of wiring layers further include: a fifth inductor L TXO , arranged in the first wiring layer A, and connected to the input / output terminal I / O of the transmission filter and the duplexer respectively through conductive vias; the sixth inductor L RXO , arranged in the second wiring layer B, and connected to the input / output terminals I / O of the receiving filter and the duplexer respectively through conductive through-holes.

[0050] As shown in FIG. 4E and FIG. 4A to FIG. 4D , in some embodiments, the first inductor L TX , the third inductor L TXA and the fifth inductor L TXO The second inductor L is provided on the first side of the plurality of wiring layers. RX , the fourth inductor L RXA and the sixth inductor L RXO The first side and the second side are disposed on the second side of the plurality of wiring layers; wherein the first side and the second side are opposite sides of the plurality of wiring layers.

[0051] As shown in FIG4A, FIG4B and FIG4C, in some embodiments, the pattern of the first wiring layer A and the pattern of the second wiring layer B both include an inductor pattern, a conductive via pattern and a ground pattern; within the plane of the first wiring layer A and / or within the plane of the second wiring layer B, the plane other than the inductor pattern and the conductive via pattern is arranged as a ground pattern; wherein, within the plane of the first wiring layer A, the inductor pattern includes at least a portion of the first inductor L TX The conductive through hole pattern includes a conductive through hole pattern connected to the first wiring layer, and the grounding portion pattern includes a first grounding portion G TX wherein, within the plane of the second wiring layer B, the inductor pattern includes at least a portion of the second inductor L RX The conductive through hole pattern includes a conductive through hole pattern connected to the second wiring layer, and the ground portion pattern includes a second ground portion G RX pattern.

[0052] 4A, 4B and 4C, in some specific embodiments, the pattern of the third wiring layer C includes a third ground portion G AA The pattern of the third inductor L TXA The pattern of the fourth inductor L RXA pattern, and, with the third inductor L TXA and the fourth inductor L RXA The pattern of the conductive vias CV1 and CV2 connected to each other; the pattern of the second wiring layer B includes the second grounding portion G RX The pattern of the second inductor L RX pattern, with the second inductor L RX Connect the conductive via CV6 pattern, and the third inductor L TXA and the fourth inductor L RXA The pattern of the conductive vias CV4 and CV5 connected to each other; the pattern of the first wiring layer A includes the first grounding portion G TX pattern, the first inductor L TX pattern, with the first inductor L TX Connect the conductive via CV10 pattern to the second inductor L RX Connect the conductive via pattern CV9, and the third inductor L TXA and the fourth inductor L RXA Pattern of connected conductive vias CV7 and CV8.

[0053] Continuing to refer to FIG. 4A , FIG. 4B and FIG. 4C , in some other specific embodiments, the first wiring layer A further includes a fifth inductor L TXO , the second wiring layer B further includes a sixth inductor L RXOThe pattern of the second wiring layer B also includes a sixth inductor L RXO The pattern, as well as, with the sixth inductor L RXO The pattern of the conductive via CV21 connected to the first wiring layer A also includes a fifth inductor L TXO , and the fifth inductor L TXO The conductive vias CV23 are connected to the pattern, and the sixth inductor L RXO The pattern of the connected conductive vias CV22.

[0054] Still referring to FIG. 4A , FIG. 4B and FIG. 4C , in some other specific embodiments, the pattern of the first wiring layer A further includes the fifth inductor L TXO The pattern of the conductive via CV36 connected to the second wiring layer B also includes the pattern of the fifth inductor L TXO The conductive vias CV35 are connected to the pattern, and the sixth inductor L RXO The pattern of the third wiring layer C also includes a pattern of the third inductor L TXA and the fourth inductor L RXA Connect the conductive via pattern CV31 to the fifth inductor L TXO The conductive vias CV33 are connected to the pattern, and the sixth inductor L RXO The pattern of the conductive vias CV32 is connected.

[0055] As shown in FIG. 4A to FIG. 4D , in some embodiments, the first ground portion G TX The area and / or the second ground portion G RX The area of ​​the first ground portion G is at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer. TX The area and / or the second ground portion G RX The area of ​​the first ground portion G is at least twice the area of ​​all conductive vias in the corresponding wiring layer. TX The area and / or the second ground portion G RX The area of ​​the first ground portion G is in the range of 5 to 8 times the area of ​​all conductive vias in the corresponding wiring layer. TX The area and / or the second ground portion G RX The area of ​​the conductive via connected to the inductor in the corresponding wiring layer ranges from 40 times to 50 times the area of ​​the conductive via connected to the inductor.

[0056] As shown in FIG. 4A to FIG. 4D , in some embodiments, a third ground portion G is further provided on the third wiring layer C. AA , the third ground portion G AA With the third inductor L TXA , the fourth inductor L RXAAre isolated, wherein the third grounding part G AA The area of ​​the third ground portion G is at least twice the area of ​​the conductive via connected to the inductor in the third wiring layer C. Preferably, the third ground portion G AA The area of ​​the third ground portion G is 5 to 12 times the area of ​​the conductive via connected to the inductor in the third wiring layer C. AA The area of ​​the third ground portion G is at least twice the area of ​​all conductive vias in the third wiring layer C. AA The area range is at least 10 times the area of ​​all conductive vias in the third wiring layer C.

[0057] In some specific embodiments, as shown in FIG4A, FIG4B and FIG4C, the pattern of the third wiring layer C includes an inductor pattern, a conductive via pattern and a ground pattern; in the plane of the third wiring layer C, except for the inductor pattern and the conductive via pattern, all planes are arranged as ground patterns; wherein, in the plane of the third wiring layer C, the inductor pattern includes a third inductor L TXA and the fourth inductor L RXA The conductive via pattern includes a third inductor L TXA and the third inductor L RXA The pattern of the conductive through hole connected to the ground portion includes a third ground portion G AA pattern.

[0058] Figure 6 shows a graph comparing the isolation between the TX and RX bands of the first packaging substrate, the third packaging substrate, the fifth packaging substrate and the packaging substrate as the second comparative example of the present application. Specifically, Figure 6 shows a graph comparing the isolation between the second comparative example, case1, the third packaging substrate provided in the embodiment of the present application (refer to the third packaging substrate shown in Figures 11A to 11D, hereinafter referred to as case3), and the fifth packaging substrate provided in the embodiment of the present application (hereinafter referred to as case5). The difference between the second comparative example of Figure 6 and case1 includes that, compared with case1 of Figure 6, the first inductor and the second inductor of the second comparative example of Figure 6 are located in the same wiring layer, and the wiring layer of the second comparative example of Figure 6 has one less layer, namely 4 layers. At this time, since there are 2 inductors (the first inductor and the second inductor) in the same wiring layer, the proportion of the 2 inductors in the same wiring layer is relatively large, and the proportion of the grounding portion is relatively small. The similarities between the second comparative example of Figure 6 and case1 include that the wiring layers of the second comparative example of Figure 6 and case1 both include the third wiring layer C (refer to Figures 4E and 4C). The differences between case 1 and case 3 in FIG6 include that, compared with case 1 in FIG6, the first grounding portion G in case 3 in FIG6 TX The projection on the surface of the third wiring layer C and the second ground portion G RXThe projections on the surface of the third wiring layer C do not overlap. The difference between Case 1 and Case 5 in Figure 6 is that, compared to Case 1 in Figure 6 , the first wiring layer in Case 5 does not include a large-area first ground portion, and the second wiring layer does not include a large-area second ground portion. The first ground portion of the first wiring layer and the second ground portion of the second wiring layer are both arranged in the form of conductive vias.

[0059] As shown in Figure 6, compared with the second comparative example, the first and second inductors of case 1, case 3, and case 5 are separated and distributed on the first and second wiring layers, respectively. The isolation within the TX and RX filter bands is significantly improved, that is, the overall isolation of the duplexer is significantly improved.

[0060] As shown in Figure 6, compared to case 1, case 5 has worse isolation on the left side and better isolation on the right side. In practical applications, if higher requirements are placed on the RX filter's frequency band isolation, case 5 is the preferred design.

[0061] As shown in FIG. 2 and FIG. 4A to FIG. 4E , in some embodiments, the first inductor L TX Set in the first wiring layer A, and the second inductor L RX Set in the second wiring layer B.

[0062] In some other embodiments, the first inductor L TX The first part is provided on the first wiring layer A, the second part is provided on the second wiring layer B, and the second inductor L RX The first portion is disposed on the second wiring layer B, and the second portion is disposed on the first wiring layer A (not shown in FIG. 2 and FIG. 4E ).

[0063] FIG7 shows a graph comparing the isolation between the TX and RX frequency bands of the first package substrate, the sixth package substrate, and the package substrate as the second comparative example of the present application. Specifically, FIG7 shows a graph comparing the isolation between the second comparative example, case 1, and the sixth package substrate provided by the embodiment of the present application (hereinafter referred to as case 6). The structural details of case 6 provided by the present application can be referred to as the first inductor L in FIG4E. TX and the second inductor L RX After adjusting the distribution, we get: the first inductor L TX The first part is provided on the first wiring layer A, the second part is provided on the second wiring layer B, and the second inductor L RXThe first part is arranged in the second wiring layer B, and the second part is arranged in the first wiring layer A. The difference between the second comparative example of Figure 7 and case 1 is that, compared with case 1 of Figure 7, the first inductor and the second inductor of the second comparative example of Figure 7 are located in the same wiring layer, and the wiring layer of the second comparative example of Figure 7 has one less layer, that is, four layers. At this time, since there are two inductors (the first inductor and the second inductor) in the same wiring layer, the proportion of the two inductors in the same wiring layer is relatively large, and the proportion of the grounding part is relatively small. The similarities between the second comparative example of Figure 7 and case 1 are that the wiring layers of the second comparative example of Figure 7 and case 1 both include a third wiring layer C (refer to Figures 4E and 4C).

[0064] As shown in FIG7 , compared with the second comparative example, the isolation between the RX and TX frequency bands of case 1 and case 6 provided in the present application is significantly better than the isolation between the RX and TX frequency bands of the comparative example.

[0065] As shown in FIG7 , compared with case 1, the isolation between the RX and TX frequency bands of case 7 provided in the present application is better than that of case 1. The sixth packaging substrate structure of case 6 provided in the present application can be preferentially adopted for application in a duplexer to improve the isolation between the RX and TX frequency bands of the duplexer.

[0066] As shown in FIG. 2 and FIG. 4E , in some embodiments, the first wiring layer A, the second wiring layer B, and the third wiring layer C are adjacent wiring layers among the plurality of wiring layers.

[0067] In some embodiments, the third wiring layer C is disposed between the first wiring layer A and the second wiring layer B (not shown in FIG. 2 and FIG. 4E ).

[0068] FIG8 shows a graph comparing the isolation between the TX and RX bands of the first package substrate, the seventh package substrate, and the package substrate as the second comparative example of the present application. Specifically, FIG8 shows a graph comparing the isolation between the second comparative example, case 1, and the seventh package substrate provided in the embodiment of the present application (hereinafter referred to as case 7), wherein the structural details of case 7 provided in the present application can be understood by referring to the positions of the second wiring layer B and the third wiring layer C in FIG4E being interchanged: the first wiring layer A, the second wiring layer B, and the third wiring layer C are adjacent wiring layers among the plurality of wiring layers, and the third wiring layer C is arranged between the first wiring layer A and the second wiring layer B.

[0069] As shown in FIG8 , compared with the second comparative example, the isolation between the RX and TX frequency bands of case 1 and case 7 provided in the present application is significantly better than the isolation between the RX and TX frequency bands of the comparative example.

[0070] As shown in FIG8 , compared with case 1, the isolation between the RX and TX frequency bands of case 7 provided in the present application is better than the isolation between the Rx and Tx frequency bands of case 1. The seventh packaging substrate structure of case 7 provided in the present application can be preferentially adopted for application in a duplexer to improve the isolation between the RX and TX frequency bands of the duplexer.

[0071] In some embodiments, in the first wiring layer, the first inductor is connected to or not connected to the first ground portion, and / or, in the second wiring layer, the second inductor is connected to or not connected to the second ground portion.

[0072] As shown in FIG. 4A and FIG. 4B , in some specific embodiments, in the first wiring layer A, the first inductor L TX and the first ground portion G TX connected, and, in the second wiring layer B, the second inductor L RX and the second ground portion G RX connected.

[0073] As shown in FIG. 10A , FIG. 10B and FIG. 10C , in some specific embodiments, in the first wiring layer A, the first inductor L TX and the first ground portion G TX Not connected, the first inductor L TX Through the conductive through hole and the first ground portion G TX connected, and, in the second wiring layer B, the second inductor L RX and the second ground portion G RX Not connected, the second inductor L RX Through the conductive through hole and the second ground portion G RX connected.

[0074] As shown in FIG. 4A , FIG. 4B , FIG. 4C and FIG. 4D , in some embodiments, the first ground portion G TX The projection on the surface of the third wiring layer C and the second ground portion G RX The projections on the surface of the third wiring layer C partially overlap.

[0075] As shown in FIG. 11A , FIG. 11B , FIG. 11C and FIG. 11D , in some embodiments, the first ground portion G TX The projection on the surface of the third wiring layer C and the second ground portion G RX The projections on the surface of the third wiring layer C do not overlap.

[0076] Continuing to refer to FIG. 11A , FIG. 11B , FIG. 11C and FIG. 11D , in some embodiments, the first ground portion G TX The projection on the surface of the third wiring layer C and the second ground portion G RX The projections on the surface of the third wiring layer C do not overlap; and the first ground portion GTX The outer contour of the projection on the surface of the third wiring layer C covers the second inductor L RX The projection on the surface of the third wiring layer C, the second ground portion G RX The outer contour of the projection on the surface of the third wiring layer C covers the first inductor L TX Projection on the surface of the third wiring layer C.

[0077] FIG9 shows a graph comparing the isolation between the TX and RX frequency bands of the first and third packaging substrates of the present application, and the packaging substrate of the second comparative example. Specifically, FIG9 shows a graph comparing the isolation between the second comparative example, case 1, and the third packaging substrate provided by an embodiment of the present application (referring to the third packaging substrate shown in FIG11A to FIG11D , hereinafter referred to as case 3).

[0078] The difference between the second comparative example in Figure 9 and Case 1 is that, compared to Case 1 in Figure 9, the first and second inductors in the second comparative example in Figure 9 are located in the same wiring layer. The wiring layer in the second comparative example in Figure 9 is one less layer, totaling four layers. At this time, since there are two inductors (the first inductor and the second inductor) in the same wiring layer, the proportion of the two inductors in the same wiring layer is relatively large, and the proportion of the ground portion is relatively small. The similarities between the second comparative example in Figure 9 and Case 1 are that the wiring layers in both the second comparative example in Figure 9 and Case 1 include a third wiring layer C (see Figures 4E and 4C).

[0079] The differences between case 1 and case 3 in FIG9 include that, compared with case 1 in FIG9 , the first grounding portion G in case 3 in FIG9 TX The projection on the surface of the third wiring layer C and the second ground portion G RX The projections on the surface of the third wiring layer C do not overlap.

[0080] As shown in Figure 9, compared with the second comparative example, the first and second inductors of Case 1 and Case 3 are separated and distributed on the first and second wiring layers, respectively. The isolation within the TX and RX filter bands is significantly improved, that is, the overall isolation of the duplexer is significantly improved.

[0081] As shown in Figure 9, compared to case 1, case 3 has better isolation on the left side and worse isolation on the right side. In practical applications, if higher requirements are placed on the TX filter's frequency band isolation, case 3 is the preferred design.

[0082] In some embodiments, the outer contour of the pattern of the first ground portion includes a closed figure, and all parts of the first wiring layer except the pattern of the first ground portion are within the closed figure; and / or, the outer contour of the pattern of the second ground portion includes a closed figure, and all parts of the second wiring layer except the pattern of the second ground portion are within the closed figure.

[0083] As shown in FIG. 12A and FIG. 12B , and FIG. 13A and FIG. 13B , in some specific embodiments, the first ground portion G TX The outer contour of the pattern includes a closed figure, and the first wiring layer A is removed from the first ground portion G TX The pattern outside is all in the closed figure; and the second ground portion G RX The outer contour of the pattern includes a closed pattern, and the second wiring layer B is removed from the second ground portion G RX In some specific embodiments, as shown in FIG12A and FIG12B, in the first wiring layer A, the first inductor L TX and the first ground portion G TX are not connected, and in the second wiring layer B, the second inductor L RX and the second ground portion G RX In some specific embodiments, as shown in FIG13A and FIG13B , in the first wiring layer A, the first inductor L TX and the first ground portion G TX connected, and, in the second wiring layer B, the second inductor L RX and the second ground portion G RX connected.

[0084] As shown in FIG. 4A , FIG. 4B , FIG. 4C and FIG. 4D , in some embodiments, in the first wiring layer A, the first inductor L TX and the first ground portion G TX The minimum spacing between them is 0.5 times the minimum line width, and the conductive via connected to the first wiring layer A and the first grounding portion G TX The minimum spacing between them is 0.5 times the minimum line width; and / or, in the second wiring layer B, the second inductor L RX and the second ground portion G RX The minimum spacing between them is 0.5 times the minimum line width, and the conductive via connected to the second wiring layer B and the second grounding portion G RX The minimum spacing between them is 0.5 times the minimum line width.

[0085] In some specific embodiments, in the first wiring layer A or the second wiring layer B, the minimum distance between the portion of the inductor not connected to the ground portion and the ground portion is 0.5 times the minimum line width, and the minimum distance between the conductive via and the ground portion is 0.5 times the minimum line width; the first inductor L TXand the first ground portion G TX The minimum spacing between the patterns at the non-contact position is 10μm, and the second inductor L RX and the second ground portion G RX The minimum pattern pitch at non-contact locations is 10 μm.

[0086] In some embodiments, the number of conductive vias connected to the inductor in each wiring layer is at least 2; and the number of conductive vias in the wiring layer is at least 5.

[0087] 4A, 4B and 4C, in some specific embodiments, the pattern of the first wiring layer A includes the first inductor L TX Connect the conductive via CV10 pattern to the second inductor L RX Connect the conductive via pattern CV9 to the third inductor L TXA and the fourth inductor L RXA The pattern of the conductive vias CV7 and CV8 connected to the fifth inductor L TXO The conductive vias CV23 are connected to the pattern, and the sixth inductor L RXO The conductive vias CV22 are connected to the pattern, and the fifth inductor L TXO The pattern of the conductive vias CV36 is connected.

[0088] 4A, 4B and 4C, in some specific embodiments, the pattern of the second wiring layer B includes the second inductor L RX Connect the conductive via pattern CV6 to the third inductor L TXA and the fourth inductor L RXA The pattern of the conductive vias CV4 and CV5 connected to the sixth inductor L RXO The pattern of the conductive via CV21 connected to the second wiring layer B also includes the fifth inductor L TXO The conductive vias CV35 are connected to the pattern, and the sixth inductor L RXO The pattern of the conductive vias CV34 is connected.

[0089] 4A, 4B and 4C, in some specific embodiments, the pattern of the third wiring layer C includes the third inductor L TXA and the fourth inductor L RXA The pattern of the conductive vias CV1 and CV2 connected to the third inductor L TXA and the fourth inductor L RXA Connect the conductive via pattern CV31 to the fifth inductor L TXO The conductive vias CV33 are connected to the pattern, and the sixth inductor L RXO The pattern of the conductive vias CV32 is connected.

[0090] In some embodiments, the conductive via has a shape including a circle, a rounded rectangle, or a dumbbell.

[0091] 4B, in some specific embodiments, in the second wiring layer B, the third inductor L TXA The conductive via CV4 is a rounded rectangle connected to the fourth inductor L. RXA The conductive via CV5 is in the shape of a dumbbell and is connected to the fifth inductor L TXO The connected conductive via CV35 has a circular shape.

[0092] In some embodiments, the number of first inductors and / or the number of second inductors includes one or more.

[0093] In some specific embodiments, multiple inductors connected together via conductive vias are used to achieve a single inductor with a high inductance value. The multiple inductors can be considered a single inductor. For example, a first inductor with an inductance value of 1 nH (nanohenry) can be formed by connecting two inductors with an inductance value of 0.3 nH and an inductance value of 0.7 nH via conductive vias.

[0094] Although as shown in Figures 4E, 4A, 4B and 4C, the number of the first inductor and the number of the second inductor are one. Those skilled in the art will recognize that the number of the first inductor and / or the number of the second inductor can include, for example, 2, 3 or more. Those skilled in the art can use multiple numbers of first inductors and / or second inductors according to specific application scenarios and design requirements to apply to the packaging substrate 200 of the duplexer provided in each embodiment of the present application, and all variations should be included within the scope of the present application.

[0095] In some embodiments, the third wiring layer C is located outside the first wiring layer A and the second wiring layer B as a whole; the multiple wiring layers also include: a fourth wiring layer, located between the third wiring layer and the whole, configured as a separate ground layer.

[0096] Refer to Figure 2 and Figure 4E for understanding. In some specific embodiments, a fourth wiring layer is arranged between the third wiring layer C and the second wiring layer B (not shown in Figure 2 and Figure 4E), and the fourth wiring layer serves as a separate ground layer. The packaging substrate includes a third wiring layer C, a fourth wiring layer, a second wiring layer B and a first wiring layer A stacked in sequence.

[0097] As shown in Figures 2 and 4E, in some embodiments, the multiple wiring layers further include a first pad layer D and a second pad layer E located on two relatively outer sides of the multiple wiring layers; the first pad layer D is configured to include connecting the transmit filter and the receive filter to the packaging substrate 200; and the second pad layer E is configured to include connecting the duplexer to other RF devices.

[0098] Exemplarily, the first pad layer D is configured to connect the inductor of the package substrate 200 to the transmit filter and the receive filter. Exemplarily, the second pad layer E is configured to connect the inductor of the package substrate 200 to the antenna terminal ANT and the ground terminal GND of the duplexer. Exemplarily, the second pad layer E is also configured to connect the inductor of the package substrate 200 to the input / output terminal I / O of the duplexer.

[0099] In some embodiments, the first inductor L is located directly below the TX filter. TX , a large area of ​​the first ground portion G TX Located directly below the RX filter, similarly, directly below the RX filter is the second inductor L RX , a large area of ​​the second ground portion G RX Located just below TX, the first inductor L TX With the second inductor L RX Being farther apart helps improve isolation.

[0100] In some specific embodiments, the third inductor L TXA and the fourth inductor L RXA They are located directly below the TX filter and the RX filter respectively, which is convenient for wiring. TXA and the fourth inductor L RXA The positions of the RX and TX filters can be interchanged and are located just below the RX and TX filters respectively.

[0101] In some specific embodiments, the first pad layer D and the second pad layer E are provided with pins connected to the transmission filter and the reception filter, and one end of the ground portion is connected to the pins of the transmission filter and the reception filter through a conductive through hole and an inductor. TX One end passes through the conductive via CV, the first inductor L TX Connect to the transmit filter pin.

[0102] In some specific embodiments, the first pad layer D and the second pad layer E are provided with a ground pin (connected to the external ground), an I / O terminal pin, an inductor pin, and a pin connected to the antenna terminal, and the other end of the ground portion is connected to the ground pin (connected to the external ground), the I / O terminal pin, the inductor pin, and the antenna terminal pin through a conductive through-hole. For example, the first ground portion G TXThe other end is connected to the ground pin through a conductive via CV.

[0103] 2 and 4E , in a second aspect, an embodiment of the present application provides a duplexer, comprising: a packaging substrate 200 according to any one of the items provided in the first aspect and a transmitting filter and a receiving filter located on the packaging substrate 200; wherein the transmitting filter is configured to send a transmit signal to the antenna terminal ANT; the receiving filter is configured to receive a signal from the antenna terminal ANT; the transmitting filter and the receiving filter are connected to the inductor of the packaging substrate 200.

[0104] It should be noted that the resonator structure of the duplexer can be specifically divided into: the first type of cavity-type film bulk acoustic wave resonator (FBAR) structure, the second type of cavity-type FBAR, the solid-mounted resonator (SMR) resonant structure, etc. The solution provided in the embodiment of this application can be applied to the above different types of BAW resonator structures.

[0105] In some embodiments, when the BAW resonator structure includes a first type cavity-type FBAR, the reflective structure includes a first cavity formed between an upwardly protruding first electrode layer and a surface of the substrate.

[0106] In some embodiments, when the BAW resonator structure includes a second-type cavity-type FBAR, the reflective structure includes a second cavity formed between a surface depression of the substrate and the first electrode layer.

[0107] In some embodiments, when the bulk acoustic wave resonant structure includes an SMR resonant structure, the reflective structure includes a plurality of first dielectric layers and second dielectric layers having different acoustic impedances and alternately stacked.

[0108] It should be noted that the reflective structure can be a cavity or a solid structure. When the reflective structure is a cavity, the reflective structure includes a first cavity or a second cavity; when the reflective structure is a solid structure, the reflective structure includes a plurality of first dielectric layers and second dielectric layers alternately stacked.

[0109] In some specific embodiments, the resonator of the duplexer includes an FBAR. In some specific embodiments, the package substrate includes multiple wiring layers and multiple conductive vias disposed between adjacent wiring layers; the multiple wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer; at least a portion of a first inductor and a first ground portion are disposed on the first wiring layer, the first inductor being connected to a transmit filter via the conductive via, and the transmit filter being grounded via the conductive via and the first ground portion; at least a portion of a second inductor and a second ground portion are disposed on the second wiring layer, the second inductor being connected to a receive filter via the conductive via, and the receive filter being grounded via the conductive via and the second ground portion; a third inductor and a fourth inductor are disposed on the third wiring layer, the third inductor being connected to the transmit filter and the antenna terminal of the duplexer, respectively, via the conductive via, and the fourth inductor being connected to the receive filter and the antenna terminal of the duplexer, respectively, via the conductive via; wherein the area of ​​the first ground portion and / or the area of ​​the second ground portion is at least twice the area of ​​the conductive via connected to the inductor in the corresponding wiring layer.

[0110] In some specific embodiments, the multiple wiring layers also include: a fifth inductor, which is arranged on the first wiring layer and connected to the I / O terminals of the transmitting filter and the duplexer through conductive vias; a sixth inductor, which is arranged on the second wiring layer and connected to the I / O terminals of the receiving filter and the duplexer through conductive vias.

[0111] In some specific embodiments, the first inductor, the third inductor, and the fifth inductor are arranged on a first side of the multiple wiring layers, and the second inductor, the fourth inductor, and the sixth inductor are arranged on a second side of the multiple wiring layers; wherein the first side and the second side are opposite sides of the multiple wiring layers.

[0112] In some specific embodiments, the pattern of the first wiring layer and the pattern of the second wiring layer both include an inductor pattern, a conductive via pattern and a grounding pattern; within the plane of the first wiring layer and / or within the plane of the second wiring layer, the planes other than the inductor pattern and the conductive via pattern are arranged as grounding patterns; wherein, within the plane of the first wiring layer, the inductor pattern includes a pattern of at least a portion of the first inductor, the conductive via pattern includes a pattern of conductive vias connected to the first wiring layer, and the grounding pattern includes a pattern of the first grounding portion; wherein, within the plane of the second wiring layer, the inductor pattern includes a pattern of at least a portion of the second inductor, the conductive via pattern includes a pattern of conductive vias connected to the second wiring layer, and the grounding pattern includes a pattern of the second grounding portion.

[0113] In some specific embodiments, the first inductor is arranged in the first wiring layer, and the second inductor is arranged in the second wiring layer; or, the first part of the first inductor is arranged in the first wiring layer, and the second part is arranged in the second wiring layer, and the first part of the second inductor is arranged in the second wiring layer, and the second part is arranged in the first wiring layer.

[0114] In some specific embodiments, the first wiring layer, the second wiring layer, and the third wiring layer are adjacent wiring layers among the plurality of wiring layers.

[0115] In some specific embodiments, the third wiring layer is disposed between the first wiring layer and the second wiring layer.

[0116] In some specific embodiments, in the first wiring layer, the first inductor is connected to or not connected to the first ground portion, and / or in the second wiring layer, the second inductor is connected to or not connected to the second ground portion.

[0117] In some specific embodiments, a projection of the first ground portion on the surface of the third wiring layer partially overlaps or does not overlap a projection of the second ground portion on the surface of the third wiring layer.

[0118] In some specific embodiments, the projection of the first ground portion on the surface of the third wiring layer does not overlap with the projection of the second ground portion on the surface of the third wiring layer; and the outer contour of the projection of the first ground portion on the surface of the third wiring layer covers the projection of the second inductor on the surface of the third wiring layer, and the outer contour of the projection of the second ground portion on the surface of the third wiring layer covers the projection of the first inductor on the surface of the third wiring layer.

[0119] In some specific embodiments, the outer contour of the pattern of the first ground portion includes a closed figure, and all wiring layers except the pattern of the first ground portion are within the closed figure; and / or, the outer contour of the pattern of the second ground portion includes a closed figure, and all wiring layers except the pattern of the second ground portion are within the closed figure.

[0120] In some specific embodiments, in the first wiring layer, the minimum spacing between the first inductor and the first ground portion is 0.5 times the minimum line width, and the minimum spacing between the conductive via connected to the first wiring layer and the first ground portion is 0.5 times the minimum line width; and / or, in the second wiring layer, the minimum spacing between the second inductor and the second ground portion is 0.5 times the minimum line width, and the minimum spacing between the conductive via connected to the second wiring layer and the second ground portion is 0.5 times the minimum line width.

[0121] In some specific embodiments, the number of conductive vias connected to the inductor in each wiring layer is at least 2; and the number of conductive vias in the wiring layer is at least 5.

[0122] In some specific embodiments, the conductive via has a shape including a circle, a rounded rectangle, or a dumbbell.

[0123] In some specific embodiments, the number of first inductors and / or the number of second inductors include one or more.

[0124] In some specific embodiments, the third wiring layer is located outside the first wiring layer and the second wiring layer as a whole; the multiple wiring layers further include: a fourth wiring layer, located between the third wiring layer and the whole, configured as a separate ground layer.

[0125] In some specific embodiments, the multiple wiring layers also include a first pad layer and a second pad layer located on two relatively outer sides of the multiple wiring layers; the first pad layer is configured to connect the transmit filter and the receive filter to the packaging substrate; and the second pad layer is configured to connect the duplexer to other RF devices.

[0126] The packaging substrate in the duplexer provided in the embodiment of the present application is similar to the packaging substrate in the embodiments of the first aspect mentioned above. For the technical features not fully disclosed in the embodiment of the present application, please refer to the embodiments of the first aspect mentioned above for understanding, and no further details will be given here.

[0127] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0128] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0129] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application. Industrial Applicability

[0130] An embodiment of the present application provides a packaging substrate for a duplexer and a duplexer. In the packaging substrate for the duplexer, a first wiring layer, a second wiring layer, and a third wiring layer are located in a middle wiring layer of the plurality of wiring layers, a first inductor and a second inductor are located in different layers, wherein the first inductor is located in the first wiring layer and the second inductor is located in the second wiring layer, and an area of ​​the first ground portion and / or an area of ​​the second ground portion is at least twice the area of ​​a conductive via connected to the inductor in the corresponding wiring layer. In this way, in the first wiring layer and the second wiring layer, the first ground portion and / or the second ground portion, excluding the inductor and the conductive via, is a large-area ground, which can reduce coupling between the first inductor and the second inductor and improve the isolation of the duplexer.

Claims

1. A packaging substrate for a duplexer, comprising a plurality of wiring layers and a plurality of conductive vias disposed between adjacent wiring layers; the plurality of wiring layers comprising a first wiring layer, a second wiring layer, and a third wiring layer located in the middle wiring layer; at least a portion of a first inductor and a first grounding portion are disposed on the first wiring layer, the first inductor being connected to a transmit filter via the conductive vias, and the transmit filter being grounded via the conductive vias and the first grounding portion; at least a portion of a second inductor and a second grounding portion are disposed on the second wiring layer, the second inductor being connected to a receive filter via the conductive vias, and the receive filter being grounded via the conductive vias and the second grounding portion; a third inductor and a fourth inductor are disposed on the third wiring layer, the third inductor being connected to the transmit filter and an antenna terminal of the duplexer, respectively, via the conductive vias, and the fourth inductor being connected to the receive filter and an antenna terminal of the duplexer, respectively, via the conductive vias; in, An area of ​​the first ground portion and / or an area of ​​the second ground portion is at least twice an area of ​​a conductive via connected to the inductor in a corresponding wiring layer.

2. The packaging substrate according to claim 1, wherein: The plurality of wiring layers further include: a fifth inductor, disposed in the first wiring layer and connected to the transmit filter and the I / O terminal of the duplexer through the conductive vias; A sixth inductor is provided in the second wiring layer and is connected to the receiving filter and the I / O terminal of the duplexer through the conductive vias.

3. The packaging substrate according to claim 2, wherein: The first inductor, the third inductor and the fifth inductor are arranged on a first side of the multiple wiring layers, and the second inductor, the fourth inductor and the sixth inductor are arranged on a second side of the multiple wiring layers; wherein the first side and the second side are opposite sides of the multiple wiring layers.

4. The packaging substrate according to claim 1, wherein The pattern of the first wiring layer and the pattern of the second wiring layer each include an inductor pattern, a conductive via pattern, and a ground pattern; In the plane of the first wiring layer and / or in the plane of the second wiring layer, except for the inductor pattern and the conductive via pattern, the ground pattern is arranged; Wherein, within the plane of the first wiring layer, the inductor pattern includes a pattern of at least a portion of the first inductor, the conductive via pattern includes a pattern of conductive vias connected to the first wiring layer, and the ground portion pattern includes a pattern of the first ground portion; In the plane of the second wiring layer, the inductor pattern includes a pattern of at least part of the second inductor, the conductive via pattern includes a pattern of conductive vias connected to the second wiring layer, and the ground portion pattern includes a pattern of the second ground portion.

5. The packaging substrate according to claim 1, wherein The first inductor is provided in the first wiring layer, and the second inductor is provided in the second wiring layer; or, A first portion of the first inductor is provided in the first wiring layer, and a second portion is provided in the second wiring layer. Also, a first portion of the second inductor is provided in the second wiring layer, and a second portion is provided in the first wiring layer. The package substrate according to claim 1 , wherein: The first wiring layer, the second wiring layer, and the third wiring layer are adjacent wiring layers among the plurality of wiring layers.

7. The packaging substrate according to claim 6, wherein: The third wiring layer is provided between the first wiring layer and the second wiring layer.

8. The package substrate according to claim 1, wherein: In the first wiring layer, the first inductor is connected to or not connected to the first ground portion, and / or in the second wiring layer, the second inductor is connected to or not connected to the second ground portion.

9. The package substrate according to claim 1, wherein: The projection of the first ground portion on the surface of the third wiring layer partially overlaps or does not overlap with the projection of the second ground portion on the surface of the third wiring layer.

10. The package substrate according to claim 9, wherein: The projection of the first ground portion on the surface of the third wiring layer does not overlap with the projection of the second ground portion on the surface of the third wiring layer; and the outer contour of the projection of the first ground portion on the surface of the third wiring layer covers the projection of the second inductor on the surface of the third wiring layer, and the outer contour of the projection of the second ground portion on the surface of the third wiring layer covers the projection of the first inductor on the surface of the third wiring layer.

11. The package substrate according to claim 1, wherein: The outer contour of the pattern of the first ground portion comprises a closed figure, and all parts of the first wiring layer except the pattern of the first ground portion are within the closed figure; And / or, the outer contour of the pattern of the second ground portion includes a closed figure, and all parts of the second wiring layer except the pattern of the second ground portion are within the closed figure.

12. The package substrate according to claim 1, wherein: In the first wiring layer, the minimum spacing between the first inductor and the first ground portion is 0.5 times the minimum line width, and the minimum spacing between the conductive via connected to the first wiring layer and the first ground portion is 0.5 times the minimum line width; and / or, in the second wiring layer, the minimum spacing between the second inductor and the second ground portion is 0.5 times the minimum line width, and the minimum spacing between the conductive via connected to the second wiring layer and the second ground portion is 0.5 times the minimum line width.

13. The package substrate according to claim 1, wherein: The number of conductive vias connected to the inductor in each wiring layer is at least 2; and the number of conductive vias in the wiring layer is at least 5.

14. The package substrate according to claim 1, wherein: The conductive through hole may be in a circular shape, a rounded rectangle shape, or a dumbbell shape.

15. The packaging substrate according to claim 1, wherein The number of the first inductors and / or the number of the second inductors include one or more.

16. The package substrate according to claim 1, wherein: The third wiring layer is located outside the first wiring layer and the second wiring layer as a whole; the plurality of wiring layers further include: The fourth wiring layer is located between the third wiring layer and the one integral body and is configured to serve as a single ground layer.

17. The package substrate according to claim 1, wherein: The plurality of wiring layers further include a first pad layer and a second pad layer located at two opposite outer sides of the plurality of wiring layers; The first pad layer is configured to connect the transmit filter and the receive filter to the package substrate; The second pad layer is configured to connect the duplexer to other radio frequency devices.

18. A duplexer, comprising: The package substrate and the transmit filter and receive filter located on the package substrate according to any one of claims 1 to 17; wherein, The transmitting filter is configured to send the transmitting signal to the antenna end; The receiving filter is configured to receive the signal from the antenna end; The transmission filter and the reception filter are connected to an inductor of the package substrate.

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