SOI ESD protection device and manufacturing method therefor

Abstract

The present invention relates to an SOI ESD protection device and a manufacturing method therefor. The device comprises: a bottom semiconductor layer having P-type doping; a buried dielectric layer, located on the bottom semiconductor layer; a conductive structure, located on the bottom semiconductor layer, the bottom of the conductive structure being electrically connected to the bottom semiconductor layer; a P-type region, located on the buried dielectric layer and electrically connected to the conductive structure; an N-type region, located on the P-type region; a first P-type doped region, part of the N-type region being located below the first P-type doped region; and an insulating structure, which is located on the conductive structure, and the side surfaces of the first P-type doped region and the N-type region. The present invention uses the bottom semiconductor layer of an SOI as a grounding port of an ESD device, and optimizes the direction of a current discharge path of the SOI ESD protection device from a transverse direction into a longitudinal direction, thus improving the current discharge capacity of unit area of the SOI ESD protection device. Therefore, the area occupied by the SOI ESD protection device on a chip is small.

Description

SOI ESD protection device and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to application number 202410206456.7, filing date February 23, 2024, entitled “SOI ESD protection device and method for manufacturing the same,” and the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to an SOI ESD protection device and a manufacturing method of the SOI ESD protection device. Background Art

[0004] ESD (Electro-Static Discharge) protection is a critical component of integrated circuit (IC) design. ESD protection devices protect internal circuits from static electricity damage. SOI (Silicon-on-Insulator) technology, due to its unique structure, offers advantages such as excellent isolation, low leakage current, high speed, radiation resistance, and low power consumption.

[0005] ESD protection is limited by the current discharge capacity per unit area of ​​the ESD protection device. It's generally believed that the greater the current a device can discharge per unit area, the stronger its ESD protection capability. In SOI processes, the SOI lateral PNP transistor is a commonly used ESD device. However, due to size, area, and process limitations, its current discharge capacity per unit area is relatively weak and difficult to improve. Summary of the Invention

[0006] Based on this, it is necessary to provide an SOI ESD protection device that occupies a smaller chip area and a manufacturing method thereof.

[0007] A SOI ESD protection device includes: a bottom semiconductor layer having P-type doping; a buried dielectric layer located on the bottom semiconductor layer; a conductive structure located on the bottom semiconductor layer, the bottom of the conductive structure being electrically connected to the bottom semiconductor layer; a P-type region located on the buried dielectric layer and electrically connected to the conductive structure; an N-type region located on the P-type region; a first P-type doped region, with part of the N-type region located below the first P-type doped region; and an insulating structure located on the conductive structure and on the sides of the first P-type doped region and the N-type region; wherein the bottom semiconductor layer is used for grounding, and the first P-type doped region and the N-type region are used for connecting to an ESD port.

[0008] The above-mentioned SOI ESD protection device uses the bottom semiconductor layer of SOI as the ground port of the ESD device, optimizes the current discharge path of the SOI ESD protection device from horizontal to vertical, and improves the current discharge capacity per unit area of ​​the SOI ESD protection device. Therefore, the chip area occupied by the SOI ESD protection device is relatively small.

[0009] In one embodiment, the SOI ESD protection device further includes a back electrode, and the bottom semiconductor layer is located on the back electrode and is grounded through the back electrode.

[0010] In one embodiment, an upper portion of the P-type region is located on a side surface of the insulating structure, and a lower portion of the P-type region is located on a side surface of the conductive structure.

[0011] In one embodiment, the SOI ESD protection device further includes a second P-type doped region located at the bottom of the conductive structure, the conductive structure is electrically connected to the bottom semiconductor layer through the second P-type doped region, and the doping concentration of the second P-type doped region is greater than the doping concentration of the bottom semiconductor layer.

[0012] In one embodiment, the SOI ESD protection device further includes an N-type doped region located on top of the N-type region, the N-type doped region is located on a side of the first P-type doped region away from the insulating structure, the doping concentration of the N-type doped region is greater than the doping concentration of the N-type region, and the N-type region is connected to the ESD port through the N-type doped region.

[0013] In one embodiment, the buried dielectric layer and the P-type region are provided on both sides of the conductive structure, and the N-type region and the first P-type doped region are provided on both sides of the insulating structure.

[0014] A method for manufacturing an SOI ESD protection device comprises: forming a trench in an SOI wafer that penetrates a top semiconductor layer and a buried dielectric layer and exposes a bottom semiconductor layer, wherein the bottom semiconductor layer has a P-type doping; forming a conductive structure in the trench, wherein the top of the conductive structure is higher than the bottom of the top semiconductor layer; forming an insulating structure on the conductive structure; forming a P-type region and an N-type region in the top semiconductor layer, wherein the N-type region is formed on the P-type region; forming a first P-type doped region on top of the N-type region; wherein the bottom semiconductor layer is used for grounding, and the first P-type doped region and the N-type region are used for connecting to an ESD port.

[0015] The SOI ESD protection device manufactured by the above-mentioned manufacturing method of the SOI ESD protection device uses the bottom semiconductor layer of the SOI as the ground port of the ESD device, optimizes the current discharge path of the SOI ESD protection device from the horizontal to the vertical, and improves the current discharge capacity per unit area of ​​the SOI ESD protection device. Therefore, the chip area occupied by the SOI ESD protection device is smaller.

[0016] In one embodiment, after the step of forming the first P-type doping region on the N-type top, the step of forming a back electrode on the bottom of the bottom semiconductor layer is further included.

[0017] In one embodiment, before the step of forming a conductive structure in the trench, the step further includes forming a second P-type doping region in the bottom semiconductor layer at the bottom of the trench, and the doping concentration of the second P-type doping region is greater than the doping concentration of the bottom semiconductor layer.

[0018] In one embodiment, after the step of forming a P-type region and an N-type region in the top semiconductor layer, the step further includes forming an N-type doped region on top of the N-type region, wherein the N-type doped region is formed on a side of the first P-type doped region away from the insulating structure, and the doping concentration of the N-type doped region is greater than the doping concentration of the N-type region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0020] FIG1 is a schematic structural diagram of an SOI ESD protection device according to an embodiment of the present application;

[0021] FIG2 is a circuit diagram of a PNP transistor in a SOI ESD protection device according to an embodiment of the present application;

[0022] 3 is a flow chart of a method for manufacturing an SOI ESD protection device according to an embodiment of the present application;

[0023] FIG4 is a flowchart of sub-steps of step S310 in one embodiment of the present application;

[0024] 5a to 5h are schematic cross-sectional views of a device during the process of manufacturing an SOI ESD protection device using the method shown in FIG3 . DETAILED DESCRIPTION

[0025] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0028] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0031] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0032] This application proposes a new SOI ESD protection device, which changes the lateral PNP structure in the related art into a vertical structure design, uses the back substrate of the SOI wafer as the GND port of the ESD device, and improves the current discharge capacity per unit area of ​​the SOI ESD protection device. Therefore, the chip area occupied by the SOI ESD protection device is smaller.

[0033] FIG1 is a schematic structural diagram of an SOI ESD protection device according to one embodiment of the present application. The SOI ESD protection device shown in FIG1 is bilaterally symmetrical, so some structures are numbered only on one side. In the embodiment shown in FIG1 , the SOI ESD protection device includes a bottom semiconductor layer 110, a buried dielectric layer 122, a conductive structure 152, a P-type region 132, an N-type region 142, a first P-type doped region 134, and an insulating structure 124. In the embodiment shown in FIG1 , the bottom semiconductor layer 110 is a P-type substrate (P-sub). The buried dielectric layer 122 and the conductive structure 152 are located on the bottom semiconductor layer 110, and the bottom of the conductive structure 152 is electrically connected to the bottom semiconductor layer 110. The P-type region 132 is located on the buried dielectric layer 122 and is electrically connected to the conductive structure 152. The N-type region 142 is located on the P-type region 132, and a portion of the N-type region 142 is located below the first P-type doped region 134. The insulating structure 124 is located on the conductive structure 152 and on the sides of the first P-type doped region 134 and the N-type region 142. The bottom semiconductor layer 110 is used for grounding (ESD GND), that is, for connecting to the cathode electrode; the first P-type doped region 134 and the N-type region 142 are used to connect to the ESD high-voltage port, that is, for connecting to the anode electrode. The first P-type doped region 134 serves as the emitter of the vertical PNP transistor, the N-type region 142 serves as the base of the vertical PNP transistor, and the P-type region 132 and the bottom semiconductor layer 110 serve as the collector of the vertical PNP transistor. The circuit diagram of the vertical PNP transistor is shown in Figure 2. When an electrostatic surge arrives at the ESD high-voltage port, the vertical PNP transistor turns on, and the ESD current generated by the static electricity reaches the bottom semiconductor layer 110 in the direction indicated by the arrow in Figure 1, and is then discharged through the ESD GND port.

[0034] The above-mentioned SOI ESD protection device uses the bottom semiconductor layer 110 of the SOI as the ground port of the ESD device, optimizes the current discharge path of the SOI ESD protection device from horizontal to vertical, and improves the current discharge capacity per unit area of ​​the SOI ESD protection device. Therefore, the chip area occupied by the SOI ESD protection device is relatively small.

[0035] In one embodiment of the present application, the SOI ESD protection device further includes a back electrode 156. The bottom semiconductor layer 110 is located on the back electrode 156 and is grounded (ESD GND) through the back electrode 156.

[0036] In one embodiment of the present application, the upper portion of the P-type region 132 is located on the side of the insulating structure 124, and the lower portion of the P-type region 132 is located on the side of the conductive structure 152, that is, the bottom of the insulating structure 124 / the top of the conductive structure 152 is located at a position higher than the bottom of the P-type region 132 and lower than the top of the P-type region 132, so that the vertical PNP transistor obtains a suitable withstand voltage.

[0037] In one embodiment of the present application, the SOI ESD protection device further includes a second P-type doping region 136 located at the bottom of the conductive structure 152. The conductive structure 152 is electrically connected to the bottom semiconductor layer 110 via the second P-type doping region 136, and the doping concentration of the second P-type doping region 136 is greater than the doping concentration of the bottom semiconductor layer 110.

[0038] In one embodiment of the present application, the SOI ESD protection device further includes an N-type doped region 144 located on top of the N-type region 142. The doping concentration of the N-type doped region 144 is greater than the doping concentration of the N-type region 142, thereby reducing contact resistance. The N-type region 142 is connected to the ESD high-voltage port via the N-type doped region 144. In the embodiment shown in FIG1 , the first P-type doped region 134 and the N-type doped region 144 are electrically connected to the upper metal layer 154 through conductive materials (e.g., tungsten plugs) in the contact holes 162. The metal layer 154 is used to connect to the ESD high-voltage port.

[0039] In the embodiment shown in FIG. 1 , buried dielectric layers 122 and P-type regions 132 are provided on both sides of the conductive structure 152 , and N-type regions 142 and first P-type doped regions 134 are provided on both sides of the insulating structure 124 .

[0040] In some embodiments of the present application, the conductive structure 152 may be made of a metal or alloy. In one embodiment of the present application, the buried dielectric layer 122 may be made of silicon oxide, such as silicon dioxide. In one embodiment of the present application, the insulating structure 124 may be made of silicon oxide, such as silicon dioxide.

[0041] The present application accordingly provides a method for manufacturing an SOI ESD protection device, which is used to manufacture the SOI ESD protection device described in any of the above embodiments. FIG3 is a flow chart of the method for manufacturing an SOI ESD protection device in an embodiment of the present application, comprising the following steps:

[0042] S310 , forming a trench in the SOI wafer, which penetrates the top semiconductor layer and the buried dielectric layer and exposes the bottom semiconductor layer.

[0043] The SOI wafer includes a bottom semiconductor layer 110 , a buried dielectric layer 122 , and a top semiconductor layer 130 stacked sequentially from bottom to top, and the bottom semiconductor layer 110 has a P-type doping.

[0044] Referring to FIG. 4 , in one embodiment of the present application, step S310 includes:

[0045] S312 , forming a patterned hard mask on the upper surface of the SOI wafer.

[0046] In one embodiment of the present application, a pad oxide layer (PAD Oxide) 172 may be formed on the surface of the top semiconductor layer 130 by thermal oxidation, and then a hard mask may be formed on the pad oxide layer 172. In one embodiment of the present application, the hard mask includes a silicon nitride layer 174 and a silicon oxide layer 176 on the silicon nitride layer 174, as shown in FIG5 a.

[0047] In one embodiment of the present application, a photoresist may be coated on the silicon oxide layer 176, and then exposed and developed to remove the photoresist above the location where the trench is to be formed, thereby obtaining a photoresist layer 192. The hard mask is then etched using the photoresist layer 192 as an etch barrier, as shown in FIG5 b.

[0048] S314 , using the hard mask as an etching barrier layer, etching to form a trench.

[0049] In one embodiment of the present application, after removing the photoresist layer 192, the hard mask is used as an etch barrier and an etchant suitable for etching the top semiconductor layer 130 is used to etch down the pad oxide layer 172 and the top semiconductor layer 130, stopping at the buried dielectric layer 122. Then, an etchant suitable for etching the buried dielectric layer 122 is used to further etch down the buried dielectric layer 122 to form the trench 141. During this process, the silicon oxide layer 176 is also partially or completely removed (see FIG. 5 c ). In one embodiment of the present application, the buried dielectric layer 122 and the top semiconductor layer 130 are formed on both sides of the trench 141.

[0050] At this point, step S310 is completed and the process proceeds to step S320.

[0051] S320 , forming a conductive structure in the trench, wherein a top of the conductive structure is higher than a bottom of the top semiconductor layer.

[0052] In one embodiment of the present application, before forming the conductive structure 152, a step is also included to form a second P-type doped region 136 in the bottom semiconductor layer 110 at the bottom of the trench 141. Specifically, ion implantation (implanting P-type ions) is performed into the bottom semiconductor layer 110 at the bottom of the trench 141, using the remaining hard mask as an implantation barrier, to form the second P-type doped region 136 (see FIG5 d). The doping concentration of the second P-type doped region 136 is greater than the doping concentration of the bottom semiconductor layer 110.

[0053] In one embodiment of the present application, metal is filled into the trench 141 to form a conductive structure 152 , and then the metal is etched back until the top of the conductive structure 152 is higher than the bottom of the top semiconductor layer 130 , see FIG. 5 e .

[0054] S330 , forming an insulating structure on the conductive structure.

[0055] An oxide layer (silicon oxide) is filled into the trench 141 (not labeled in FIG5 f ) above the conductive structure 152 to form the insulating structure 124. Excess oxide layer is then removed by chemical mechanical polishing (CMP) and / or wet etching, leaving the upper surface of the insulating structure 124 slightly higher than the upper surface (top) of the top semiconductor layer 130 and lower than the upper surface of the silicon nitride layer 174.

[0056] S340 , forming a P-type region and an N-type region in the top semiconductor layer, wherein the N-type region is formed on the P-type region.

[0057] In one embodiment of the present application, after removing the remaining hard mask (silicon nitride layer 174), ion implantation is performed to form a P-type region 132 and an N-type region 142, respectively, to form a vertical PN junction. In one embodiment of the present application, the height of the junction between the P-type region 132 and the N-type region 142 is greater than the height of the top of the conductive structure 152, as shown in Figure 5g. In one embodiment of the present application, the P-type region 132 and the N-type region 142 are formed on both sides of the trench 141 (not shown in Figure 5g).

[0058] S350 , forming a first P-type doping region on the N-type region.

[0059] In one embodiment of the present application, the first P-type doping region 134 is formed on the top of the N-type region 142 by patterning (eg, photolithography) and ion implantation (implanting P-type ions).

[0060] In one embodiment of the present application, step S350 further includes the step of forming an N-type doping region 144 on top of the N-type region 142, as shown in FIG5h. Specifically, the N-type doping region 144 can be formed on the side of the first P-type doping region 134 facing away from the insulating structure 124 by patterning (e.g., photolithography) and ion implantation (implanting N-type ions). The doping concentration of the N-type doping region 144 is greater than the doping concentration of the N-type region 142. In one embodiment of the present application, the first P-type doping region 134 and the N-type doping region 144 are formed on both sides of the insulating structure 124.

[0061] The SOI ESD protection device manufactured by the above-mentioned manufacturing method of the SOI ESD protection device uses the bottom semiconductor layer 110 of the SOI as the ground port of the ESD device, optimizes the current discharge path of the SOI ESD protection device from the horizontal to the vertical, and improves the current discharge capacity per unit area of ​​the SOI ESD protection device. Therefore, the chip area occupied by the SOI ESD protection device is smaller.

[0062] In one embodiment of the present application, after step S350, an interlayer dielectric layer (ILD) is formed on the front side of the wafer. In one embodiment of the present application, after forming the ILD, a contact hole 162 is formed by photolithography and etching the ILD, and a conductive material is filled into the contact hole 162. In one embodiment of the present application, after filling the contact hole 162 with the conductive material, a metal layer 154 is formed on the front side of the wafer to be electrically connected to the conductive material in the contact hole 162. Referring to FIG. 1 , the metal layer 154 is used to connect to the ESD high-voltage port.

[0063] In one embodiment of the present application, after forming the metal layer 154, a step of forming a back electrode 156 on the bottom of the bottom semiconductor layer 110 (ie, the back side of the wafer) is further included. The back electrode 156 is used for grounding (ESD GND).

[0064] The manufacturing method of the SOI ESD protection device of the present application and the SOI ESD protection device are based on the same inventive concept. For matters not specifically described in the manufacturing method of the SOI ESD protection device, reference can be made to the above introduction to the SOI ESD protection device.

[0065] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0066] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0067] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A SOIESD protection device, characterized in that: include: A bottom semiconductor layer having a P-type doping; a buried dielectric layer located on the bottom semiconductor layer; a conductive structure, located on the bottom semiconductor layer, wherein a bottom of the conductive structure is electrically connected to the bottom semiconductor layer; a P-type region, located on the buried dielectric layer and electrically connected to the conductive structure; An N-type region, located on the P-type region; a first P-type doped region, located above the N-type region; an insulating structure, located on the conductive structure and on sides of the first P-type doped region and the N-type region; The bottom semiconductor layer is used for grounding, and the first P-type doped region and the N-type region are used for connecting to an ESD port.

2. The SOIESD protection device according to claim 1, characterized in that: A back electrode is further included, and the bottom semiconductor layer is located on the back electrode and is grounded through the back electrode.

3. The SOIESD protection device according to claim 1, characterized in that: The upper portion of the P-type region is located on a side surface of the insulating structure, and the lower portion of the P-type region is located on a side surface of the conductive structure.

4. The SOIESD protection device according to claim 1, characterized in that: It also includes a second P-type doping region located at the bottom of the conductive structure, the conductive structure is electrically connected to the bottom semiconductor layer through the second P-type doping region, and the doping concentration of the second P-type doping region is greater than the doping concentration of the bottom semiconductor layer.

5. The SOIESD protection device according to claim 1, characterized in that: It also includes an N-type doped region located on the top of the N-type region, the N-type doped region is located on the side of the first P-type doped region away from the insulating structure, the doping concentration of the N-type doped region is greater than the doping concentration of the N-type region, and the N-type region is connected to the ESD port through the N-type doped region.

6. The SOIESD protection device according to claim 1, characterized in that: The buried dielectric layer and the P-type region are provided on both sides of the conductive structure, and the N-type region and the first P-type doped region are provided on both sides of the insulating structure.

7. The SOIESD protection device according to claim 5, characterized in that: The method further includes a contact hole formed above the first P-type doping region and the N-type doping region, wherein the contact hole is filled with a conductive material.

8. The SOIESD protection device according to claim 7, characterized in that: It also includes a metal layer electrically connected to the conductive material in the contact hole, and the metal layer is used to connect to the ESD port.

9. A method for manufacturing a SOIESD protection device, characterized in that: include: forming a trench in the SOI wafer, penetrating the top semiconductor layer and the buried dielectric layer to expose the bottom semiconductor layer, wherein the bottom semiconductor layer has a P-type doping; forming a conductive structure in the trench, wherein a top of the conductive structure is higher than a bottom of the top semiconductor layer; forming an insulating structure on the conductive structure; forming a P-type region and an N-type region in the top semiconductor layer, wherein the N-type region is formed on the P-type region; forming a first P-type doping region on top of the N-type region; The bottom semiconductor layer is used for grounding, and the first P-type doped region and the N-type region are used for connecting to an ESD port.

10. The method for manufacturing a SOIESD protection device according to claim 9, wherein: After the step of forming the first P-type doping region on the N-type top, the method further includes the step of forming a back electrode at the bottom of the bottom semiconductor layer.

11. The method for manufacturing a SOIESD protection device according to claim 9, wherein: Before the step of forming a conductive structure in the trench, the method further includes forming a second P-type doping region in the bottom semiconductor layer at the bottom of the trench, wherein the doping concentration of the second P-type doping region is greater than the doping concentration of the bottom semiconductor layer.

12. The method for manufacturing a SOIESD protection device according to claim 9, wherein: After the step of forming a P-type region and an N-type region in the top semiconductor layer, the method further includes forming an N-type doped region on top of the N-type region, wherein the N-type doped region is formed on a side of the first P-type doped region away from the insulating structure, and the doping concentration of the N-type doped region is greater than the doping concentration of the N-type region.

13. The method for manufacturing a SOIESD protection device according to claim 12, wherein: After the step of forming the N-type doped region, the method further includes: forming an interlayer dielectric layer on the front side of the SOI wafer, forming a contact hole by photolithography and etching the interlayer dielectric layer, and filling the contact hole with a conductive material.

14. The method for manufacturing a SOIESD protection device according to claim 13, wherein: The method further includes forming a metal layer on the front surface of the SOI wafer, the metal layer being electrically connected to the conductive material in the contact hole, wherein the metal layer is used to connect to the ESD port.

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