Display driver chip, display control method, and related device

Abstract

The present application relates to the field of display, and discloses a display driver chip, a display control method, and a related device. The display driver chip comprises: an interface unit, which is used for receiving input data signals transmitted from a first quantity of input ends; a plurality of data processing units, wherein each data processing unit is connected to the interface unit, and each data processing unit comprises a data decompressor and a decoder; a plurality of data storage units, wherein each data storage unit is connected to one corresponding data processing unit, and each data storage unit is used for storing decoded signals of a second quantity of input ends; and a plurality of output units, wherein the second quantity of output units are connected to one data storage unit by means of respective corresponding data transmission units, respectively, each output unit is used for outputting output data signals of a plurality of display columns or display rows, and the first quantity is greater than the second quantity.

Description

Display driving chip, display control method and related device TECHNICAL FIELD

[0001] The present disclosure relates to the field of display, and in particular, to a display driving chip, a display control method and related device. BACKGROUND

[0002] To meet the needs of narrow frame of products, the height of the display driving chip needs to be as low as possible. The output channel of the ultra-high output channel output chip needs more area than the conventional chip to place the output port and the related analog design, and the length of the chip will be longer. Such shape will bring great challenges to the digital automatic layout and layout wiring as well as the placement of the memory.

[0003] The current display driving chip has a limited number of output channels. In order to increase the number of channels, the length of the chip must be increased, which leads to a significant decrease in the efficiency of the design. With the increase of the length of the chip, not only the design complexity increases, but also the power consumption and the area required by the chip increase. In related chips, the problem of voltage drop is prone to occur due to the large width, and the designer needs to use more power and ground pins for optimization, but the optimization effect is limited. At the same time, the existing chip usually lacks the function of partition refreshing. Due to the above limitations, the current display driving chip is difficult to adapt to more extensive resolution use scenarios, which limits their application in diversified display requirements, especially in the field of ultra-high resolution and flexible display functions. SUMMARY

[0004] In order to solve the problem that the current display driving chip is difficult to adapt to more extensive resolution use scenarios, the first aspect of the present disclosure provides a display driving chip, comprising:

[0005] an interface unit, configured to receive input data signals transmitted by a first number of input terminals;

[0006] a plurality of data processing units, each of which is connected with the interface unit, and each of the data processing units comprises a data decompressor and a decoder, and each of the data processing units is configured to perform decompression and decoding operations on the input data signals of a second number of input terminals, and generate decoded signals of the second number of input terminals;

[0007] a plurality of data storage units, each of which is connected with a corresponding data processing unit, and each of the data storage units is configured to store the decoded signals of the second number of input terminals

[0008] a plurality of output units, a second number of the output units are connected with one of the data storage units through a respective corresponding data transmission unit, each of the output units is configured to output output data signals of a plurality of display columns or display rows, wherein the first number is greater than the second number.

[0009] In some embodiments, the display driving chip further comprises:

[0010] a logic integrated circuit core unit, the logic integrated circuit core unit is connected with the interface unit, each of the data processing units, each of the data storage units and each of the output units, and the logic integrated circuit core unit is configured to control data transmission operation of the display driving chip.

[0011] In some embodiments, the data transmission unit does not overlap in the orthogonal projection of the thickness direction of the display driving chip.

[0012] In some embodiments, each of the data storage units, each of the data processing units, a second number of the output units and a second number of the data transmission units form a regional display function module, any two of the regional display function modules do not overlap in the orthogonal projection of the thickness direction of the display driving chip, and each of the regional display function modules is configured to process display data of a partial display region of a display unit.

[0013] In some embodiments, the distance between the data storage unit and the middle line of the width direction of the regional display function module is less than a preset distance.

[0014] In some embodiments, the data transmission unit comprises a first data transmission unit and a second data transmission unit, the first data transmission unit is connected with the output unit and the second data transmission unit, the second data transmission unit is further connected with the data storage unit, and the second data transmission unit comprises a compensation circuit configured to perform impedance matching.

[0015] In some embodiments, the first data transmission unit does not overlap with the logic integrated circuit core unit in the thickness direction of the display driving chip, and the second data transmission unit at least partially overlaps with the logic integrated circuit core unit in the thickness direction of the display driving chip.

[0016] In some embodiments, the first number is twice the second number, the number of data processing units and the number of data storage units are 2, and each of the data storage units and each of the output units are configured to process display data of 1 / 2 display region of a display unit.

[0017] In some embodiments, the interface unit comprises a first interface unit and a second interface unit, the first interface unit is connected with the first data processing unit, the second interface unit is connected with the second data processing unit, the first interface unit is configured to receive input data signals transmitted by a first number of input terminals, and the second interface unit is configured to receive input data signals transmitted by the remaining input terminals, the distance between the interface unit and the center line of the display driving chip in the width direction is less than a preset distance, and the first interface unit and the second interface unit do not overlap in the thickness direction of the display driving chip.

[0018] In a second aspect of the present disclosure, a display control method is provided for the display driving chip of any one of the first aspect, and the method comprises:

[0019] controlling the interface unit to receive input data signals of a first number of input terminals;

[0020] controlling the interface unit to distribute the received input data signals of the first number of input terminals to a plurality of data processing units, so that each data processing unit performs data decompression and decoding operations to generate decoding signals of a second number of input terminals;

[0021] controlling each data processing unit to transmit each group of decoding signals of the second number of input terminals to a corresponding data storage unit for data storage;

[0022] controlling each data transmission unit to transmit the decoding signals stored in the data storage unit to an output unit, so that the output unit outputs output data signals of a plurality of display columns or display rows.

[0023] In some embodiments, the method comprises:

[0024] In the case where the interface unit receives input data signals of a third number of input terminals, controlling the output unit corresponding to the third number of input terminals to be in an active state, and controlling the remaining output units to be in an inactive state or a sleep state, wherein the third number is less than the first number.

[0025] In a third aspect of the present disclosure, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the steps of the display control method of any one of the second aspect.

[0026] In a fourth aspect of the present disclosure, a display module is provided, comprising the display driving chip of any one of the first aspect, and further comprising a display unit.

[0027] In a fifth aspect, the present disclosure provides a display device comprising the display module of the fourth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 shows a structural schematic diagram of a display driving chip according to the present disclosure;

[0029] FIG. 2 shows a structural schematic diagram of a display driving chip in the related art;

[0030] FIG. 3 shows a structural schematic diagram of another display driving chip according to the present disclosure;

[0031] FIG. 4 shows a structural schematic diagram of still another display driving chip according to the present disclosure;

[0032] FIG. 5 shows a structural schematic diagram of yet another display driving chip according to the present disclosure;

[0033] FIG. 6 shows a flowchart of a display control method according to the present disclosure;

[0034] FIG. 7 shows a structural schematic diagram of an electronic device according to the present disclosure;

[0035] FIG. 8 shows a structural schematic diagram of a display module according to the present disclosure;

[0036] FIG. 9 shows a structural schematic diagram of a display device according to the present disclosure;

[0037] The correspondence between the component names and the reference numerals in FIGS. 1-5 is as follows:

[0038] 100 display driving chip; 101 interface unit; 102 data processing unit; 103 data storage unit; 104 data transmission unit; 105 output unit; 106 logic integrated circuit core unit;

[0039] 1041 first data transmission unit, 1042 second data transmission unit, 1011 first interface unit, 1012 second interface unit; 10 area display function module. DETAILED DESCRIPTION

[0040] The display driving chip in the related art is limited by the upper limit of the resolution application and the limitation of the conventional package. The highest output channel is within 4000 pins, and the total length is about 20000 um, which cannot meet the market demand of increasing resolution. The increase in the number of channels will increase the length of the chip. When the length of the chip is expanded to about 30000 um in width, the traditional data transmission architecture, i.e., after the data is processed centrally, the transmission is performed in blocks, which will greatly reduce the digital wiring efficiency and increase the area and power consumption.

[0041] Current display driver chips support less than 4000 channels. To achieve ultra-high resolution applications, multiple chips are needed to work together in a cascading manner. This cascading implementation increases the complexity and coordination requirements of the system. To support more channels, the length of the chip increases. This growth not only leads to a larger physical size, but also brings the problem of inefficient data transmission architecture. Traditional data transmission methods result in extremely low wire wrapping efficiency in such long chip designs, thereby increasing the overall chip area. The increase in chip width causes a significant IR Drop problem. This requires designers to invest a large number of GND / POWER pins and networks for optimization. However, even after these efforts, the optimization effect may not be particularly obvious, which poses a challenge to the stability and performance of the chip. And the conventional chip usually does not have a partition function, which means that in the scene that needs to be refreshed locally, it can only update all the data in the whole frame refresh mode. This method not only consumes high power, but also occupies a large amount of data bandwidth. Due to these limitations, current display driver chips are difficult to support a wide range of resolution use scenarios. This limits their application in diversified display requirements, especially in the field of modern display technology that pursues ultra-high resolution and flexible display functions.

[0042] Therefore, in order to solve the above-mentioned part of the problem, the present disclosure proposes a brand-new display driver chip data transmission architecture, which divides the chip into two parts from data transmission, each processing its own block of data and displaying. While ensuring complete data transmission, higher wire wrapping efficiency is achieved, reducing the size of the chip. Please refer to FIG. 1, which is a structural schematic diagram of a display driver chip 100 according to the present disclosure, comprising:

[0043] An interface unit 101, the interface unit 101 is used for receiving input data signals transmitted by a first number of input terminals;

[0044] A plurality of data processing units 102, each data processing unit 102 is connected with the interface unit 101, each data processing unit 102 comprises a data decompressor and a decoder, each data processing unit 102 is used for decompressing and decoding the input data signals of a second number of input terminals, and generating decoded signals of the second number of input terminals;

[0045] A plurality of data storage units 103, each data storage unit 103 is connected with a corresponding data processing unit 102, each data storage unit 103 is used for storing the decoded signals of the second number of input terminals;

[0046] A plurality of output units 105, a second number of the output units 105 are connected with one of the data storage units 103 through a respective data transmission unit 104 respectively, each of the output units 105 is configured to output output data signals of a plurality of display columns or display rows, wherein the first number is greater than the second number.

[0047] For example, the display driving chip 100 includes an interface unit 101, a plurality of data processing units 102, a plurality of data storage units 103 and a plurality of output units 105. The interface unit 101 is configured to receive data signals from a first number of input terminals. These signals can contain images, videos or other types of data, and the signal source can be, for example, a camera, a media file, etc. The role of the interface unit 101 is to ensure that all input data can smoothly enter the display driving for subsequent processing.

[0048] The input data received from the interface unit 101 flows to the plurality of data processing units 102. Each data processing unit 102 is connected with the interface unit 101, and the data processing unit 102 is responsible for the preliminary processing of the received data. Each data processing unit 102 is equipped with a data decompressor and a decoder, which are used to decompress and decode the data transmitted by a second number of input terminals. The data processing unit 102 can realize a variety of operations from compression format conversion, format analysis to color space adjustment, etc., and generate a second number of input terminal decoding signals after processing. The decoding signal is a more optimized and simplified data form than the original input signal.

[0049] It should be noted that the display driving chip 100 proposed by the present disclosure includes a plurality of data processing units 102, each data processing unit 102 can process the data signals transmitted by a second number of input terminals, that is, each data processing unit 102 can process part of the data signals transmitted by the input terminals, and the plurality of data processing units 102 collectively complete all the data signals transmitted by the first number of input terminals. The number of input terminals processed by different data processing units 102 can be the same or different.

[0050] The decoded data is then transmitted to the data storage unit 103 corresponding to each data processing unit 102. The main role of these units is to temporarily store the processed data to prepare for the final output. In this way, the chip can effectively manage the data flow and ensure that the data is safely and completely stored before output. Each data storage unit 103 corresponds to a corresponding data processing unit 102, and each data storage unit 103 is configured to store the decoding signals corresponding to the second number of input terminals.

[0051] Each output unit 105 is connected with a specific data storage unit 103 through a data transmission unit 104 to ensure accurate data transmission, and multiple output units 105 are connected with one data storage unit 103. The task of the output unit 105 is to convert the data into a signal suitable for driving a display device, such as a television screen, a smartphone display screen, etc.

[0052] As shown in FIG. 2, it is a structural schematic diagram of a display chip in the related art. The traditional data transmission architecture scheme is to transmit the data corresponding to the entire chip from the middle part to the left and right sides in turn. This brings the problem that the output unit 105 of the chip needs to reserve a very wide line to perform wiring. In addition, due to the distance difference between the two ends and the middle, timing matching needs to be performed in the line. The timing matching needs impedance matching, which increases the wiring difficulty and has limited adjustable precision. This will lead to an increase in the overall height of the chip, i.e., an increase in the distance in the L direction.

[0053] As shown in FIG. 1, it is a structural schematic diagram of a display chip proposed by the present disclosure. The data storage unit 103 and the data processing unit 102 are both two, and the output unit 105 includes N. Each output unit 105 is used to output an input data signal transmitted by an input end as an example:

[0054] The data transmission needs to be decomposed into multiple groups and transmitted to the display driver chip 100 by the front-end application processor (AP) system chip from the first number of input ends. After the display driver chip 100 receives the data, the input port corresponding to the partial picture enters the left and right sides of the chip. Multiple separate data processing units 102 and data storage units 103 are placed inside the chip. The output processing unit includes a data decompressor and a decoder. Multiple decoders can be placed in the decompressor. The number of decoder addresses is determined by the data volume. Multiple separate data storage units 103 are used for decompressor use and quality optimization IP data interaction.

[0055] At the output end, the entire chip is also divided into multiple parts, and the number of input ends is divided into multiple output units 105. The number of output units 105 can be equal to or less than the number of input ends. When full display is needed, all output units 105 perform display. When only partial display / resolution compatibility is needed, the output units 105 corresponding to the non-displayed parts are closed, and only the output units 105 corresponding to the display modules are opened for data transmission, which can reduce the digital power consumption of these modules.

[0056] Because the chip internal data architecture has split the chip into multiple parts, the interaction between each part is extremely small, and there is no intermediate part wiring back and forth during digital APR (Automatic Place and Route) routing, which greatly reduces the height of the chip, i.e., the size of the L direction. Back and forth threading can cause the width of the wire to increase, and the distance is far, and multiple level buffers are needed in the middle to increase the thrust.

[0057] In summary, the display driving chip 100 proposed in the present disclosure transmits the input data signals of the first number of input terminals to multiple functional areas for data processing. Each functional area corresponds to a data processing unit 102, a data storage unit 103, and multiple output units 105. Partial input signals are processed by different functional areas, which can improve the routing efficiency, reduce the area and power consumption, and thus improve the overall data transmission efficiency. Through the above-mentioned zone function, the display driving chip 100 proposed in the present disclosure can allow partial refresh instead of full-frame refresh by setting multiple output units 105, each of which corresponds to one or more input terminals. This can reduce power consumption and the demand for data bandwidth. The display driving chip 100 proposed in the present disclosure can adapt to a wider range of resolutions, thereby providing greater flexibility and applicability. It can improve the routing efficiency while maintaining data integrity, which helps to reduce the overall size of the chip and makes it more suitable for compact design requirements, meeting the requirements of narrow frame and light and thin design.

[0058] In some examples, the display driving chip 100 further comprises:

[0059] A logic integrated circuit core unit 106 is connected to the interface unit 101, each data processing unit 102, each data storage unit 103, and each output unit 105, respectively. The logic integrated circuit core unit 106 is used to control the data transmission operation of the display driving chip 100.

[0060] Exemplarily, as shown in FIG. 3, another structural schematic diagram of a display driving chip is disclosed. The logic integrated circuit core unit 106 is connected with the interface unit 101, each of the data processing units 102, each of the data storage units 103, and each of the output units 105. The logic core unit is responsible for coordinating and controlling all data flow and processing operations. It manages the data received from the interface unit 101, ensures that the data is effectively allocated to each data processing unit 102, and correctly flows from these units to the data storage unit 103. In the data processing unit 102, the logic core unit controls the decompression and decoding process of the data, ensuring that each unit effectively performs its assigned task. It also monitors and manages the storage of data in the storage unit, ensuring the safety and integrity of the data. In the output stage, the logic core unit controls how the data flows from the storage unit to the output unit 105 and is finally converted into a signal for driving the display device.

[0061] In some examples, the orthographic projection of each of the data transmission units 104 in the thickness direction of the display driving chip 100 does not overlap.

[0062] Exemplarily, the layout of each data transmission unit 104 in the thickness direction of the chip does not overlap. By ensuring that the data transmission units 104 do not overlap in the thickness direction, electrical interference can be reduced, and the efficiency and reliability of data transmission can be improved. This layout helps to maximize the use of limited space, making the chip more lightweight. Avoiding overlap helps to improve heat management, as the space between different units can act as a channel for heat dissipation, preventing overheating.

[0063] In some examples, each of the data storage units 103, each of the data processing units 102, a second number of the output units 105, and a second number of the data transmission units 104 form a regional display function module 10, and the orthographic projection of any two of the regional display function modules 10 in the thickness direction of the display driving chip 100 does not overlap. Each of the regional display function modules 10 is used to process display data for a partial display area of a display unit.

[0064] As shown in FIG. 4, the display driving chip provided by the present disclosure includes a plurality of region display function modules 10. Each region display function module 10 is responsible for processing display data of a partial display region of the display unit. In the thickness direction of the display driving chip 100, the projections of any two region display function modules 10 do not overlap, ensuring that the space inside the chip is used efficiently, while avoiding electrical interference between the modules. Each region display function module 10 can correspond to a corresponding display region in space, avoiding wiring of a large range of region display function modules 10.

[0065] In some examples, the distance between the data storage unit 103 and the center line in the width direction of the region display function module 10 is less than a preset distance.

[0066] As shown in FIG. 4, data is transmitted from the middle interface to both sides, and then evenly dispersed to the upper output module from the middle part of both sides. This can evenly distribute the data stream in the chip, and avoid the situation that a certain region needs most of the calculation. This effectively reduces the local pressure drop caused by uneven power consumption of the digital.

[0067] As shown in FIG. 4, the number of region display function modules 10 can be 2. The region display function modules 10 can be symmetrically arranged about the center of the display driving chip in the W direction. The distance between the data storage unit 103 and the center line in the width direction W of the region display function module 10 is less than a preset distance. The data storage unit 103 can be arranged at about 1 / 4 of the chip in the W direction. Compared with the conventional architecture, the length of the required impedance matching is shortened by nearly one time. Moreover, there is no need to concentrate all the transmission units 104 corresponding to the line in the output module, which greatly reduces the height of the chip and reduces the cost and stability of the chip.

[0068] In some examples, the data transmission unit 104 includes a first data transmission unit 1041 and a second data transmission unit 1042. The first data transmission unit 1041 is connected to the output unit 105 and the second transmission unit 1042. The second transmission unit 1042 is further connected to the data storage unit 103. The second data transmission unit 1042 includes a compensation circuit for impedance matching.

[0069] Exemplarily, as shown in FIG. 5, the first data transmission unit 1041 is connected to the output unit 105 and the second data transmission unit 1042. The second data transmission unit 1042 is responsible for transmitting the processed data to the first data transmission unit 1041, and the first data transmission unit 1041 is responsible for transmitting the data to the output unit 105, and the output unit 105 transmits the data to the corresponding display unit. The second data transmission unit 1042 is connected to the first data transmission unit 1041 and the data storage unit 103, and it not only undertakes the task of data transmission, but also includes a compensation circuit. The main function of the compensation circuit is impedance matching, which can reduce signal reflection and loss, and improve the quality and stability of signal transmission.

[0070] In some examples, the first data transmission unit 1041 and the logic integrated circuit core unit 106 do not overlap in the thickness direction of the display driving chip 100, and the second data transmission unit 1042 and the logic integrated circuit core unit 106 at least partially overlap in the thickness direction of the display driving chip 100.

[0071] Exemplarily, the first data transmission unit 1041 does not overlap with the logic core unit in the orthogonal projection in the thickness direction of the chip, which optimizes the use of internal space and improves signal integrity and layout efficiency. The second data transmission unit 1042 at least partially overlaps the logic core unit in the thickness direction, and in some area of the chip, the two units share the same space in the vertical direction. It can reasonably utilize the space. By adjusting the overlapping and non-overlapping layout of the units in the thickness direction, the internal space of the chip can be more effectively utilized,

[0072] In some examples, the first number is twice the second number, the number of data processing units 102 and the number of data storage units 103 are 2, and each data storage unit 103 and each output unit 105 is used to process the display data of 1 / 2 display area of the display unit.

[0073] Exemplarily, as shown in FIG. 1, a structural schematic diagram of a display chip is provided in the present disclosure, taking the data storage unit 103 and the data processing unit 102 as two, the output unit 105 including N, and each output unit 105 being used to output the input data signal transmitted by an input terminal as an example:

[0074] The data transmission needs to be split and transmitted to the display driver chip 100 in the front-end AP system chip according to the average distribution mode of the input data signals transmitted by the first number of input terminals. (The data input by the first to N / 2 input terminals is the left picture display of the display device, and the data input by the N / 2+1 to N input terminals is the right picture display of the display device. After receiving the data, the display driver chip 100 enters the left and right sides of the chip according to the corresponding input ports of the left and right pictures. Two separate data processing units 102 and data storage units 103 are placed inside the chip. The output processing unit includes a data decompressor and a decoder. Multiple decoder addresses can be placed in the decompressor. The number of decoder addresses depends on the data volume. The two separate data storage units 103 are used for decompressor and picture quality optimization IP data interaction.

[0075] On the output side, the entire chip is also divided into left and right two parts, and each side is again divided into multiple output modules (output module 1 to output module N) according to the number of input terminals. Each sub-module corresponds to a display resolution of 1 / A of the total number. When full display is required, all input terminals are output to the sub-modules as required and displayed. When only part of the module needs to be displayed / resolution compatible, the corresponding output unit 105 of the part that does not need to be displayed is closed, and only the output unit 105 corresponding to the module that needs to be displayed is opened for data transmission, which can reduce the digital power consumption of these modules.

[0076] Because the chip internal data architecture has split the chip into left and right two parts, the interaction between left and right is very small, and there is no back-and-forth threading of the middle part during digital APR (Automatic Place and Route) routing. This greatly reduces the height of the chip, i.e. the size of the L direction. Back-and-forth threading can increase the width of the wire and the distance, and multiple levels of buffers are needed in the middle to increase the thrust.

[0077] In some examples, the interface unit 101 includes a first interface unit 1011 and a second interface unit 1012, the first interface unit 1011 is connected with the first data processing unit 1021, the second interface unit 1012 is connected with the second data processing unit 1022, the first interface unit 1011 is used for receiving the input data signals transmitted by the second number of input terminals, the second interface unit 1012 is used for receiving the remaining input data signals, the distance between the interface unit 101 and the middle line of the width direction of the display driver chip 100 is less than a predetermined distance, and the first interface unit 101 and the second interface unit 101 do not overlap in the thickness direction of the display driver chip 100.

[0078] As shown in FIG. 5, another structural schematic diagram of a display driving chip is provided. The interface unit 101 includes a first interface unit 101 and a second interface unit 101. The first interface unit 101 is directly connected to the first data processing unit 102 and receives a part of the input data signals. The second interface unit 101 is connected to the second data processing unit 102 and receives the remaining input data signals. The interface unit 101 is located at a distance less than a preset distance from the center line in the width direction (W direction in the figure) of the display driving chip 100, i.e., the interface unit 101 is close to the center of the chip. Such a layout helps to minimize the signal transmission distance, thereby possibly reducing the delay and signal attenuation. In the thickness direction of the chip, the orthographic projections of the first interface unit 1011 and the second interface unit 1012 do not overlap. Such a design ensures that each interface unit occupies an independent position in the vertical space of the chip, reduces physical interference in the design, improves the integrity of the signal, and reduces the thickness of the chip.

[0079] In some embodiments, the two data processing units are symmetrically arranged about the interface unit in the width direction of the display chip, and the two data storage units are symmetrically arranged about the interface unit in the width direction of the display chip.

[0080] For example, the two data processing units and the two data storage units are symmetrically arranged about the interface unit in the width direction of the display chip. Such a layout can balance the load of data processing, improve processing efficiency and speed. For the data storage unit, the same symmetric arrangement helps to balance the storage access, reduce the delay of data access, and improve the overall performance. Through symmetric arrangement, it can be ensured that the distribution of processing and storage tasks on the chip is more balanced, thereby improving the overall performance. It helps to reduce the distance of data transmission within the chip, thereby reducing the delay. Balanced load distribution enables the chip to process and store data more efficiently. The symmetric layout also helps to achieve uniform distribution of heat on the chip and reduce the risk of overheating.

[0081] In a second aspect, referring to FIG. 6, a flow schematic diagram of a display control method is provided. The method is used for the display driving chip 100 of any one of the first aspect, and the method includes:

[0082] S210, controlling the interface unit 101 to receive input data signals from a first number of input terminals;

[0083] For example, the control unit activates the interface unit 101 to receive input data signals from a first number of input terminals. These data signals can include video, image or other graphic data, and the input data signals are used for display pictures.

[0084] S220, control the interface unit 101 to distribute the received input data signal of the first number of input terminals to a plurality of data processing units 102, so that each data processing unit 102 performs data decompression and decoding operation to generate a second number of input terminal decoding signals;

[0085] For example, the interface unit 101 distributes the received data signal to a plurality of data processing units 102. Each data processing unit 102 is responsible for processing a portion of data. By taking advantage of parallel processing, the efficiency of data processing is improved for data decompression and decoding.

[0086] S230, control each data processing unit 102 to transmit each group of the second number of input terminal decoding signals to the corresponding data storage unit 103 for data storage;

[0087] For example, each data processing unit 102 transmits the second number of input terminal decoding signals it is responsible for to the corresponding data storage unit 103 for storage. The decoded data signal is stored for the next output, and a data buffer is provided to balance the speed difference between processing and output.

[0088] S240, control each data transmission unit 104 to transmit the decoding signal stored in the data storage unit 103 to the output unit 105, so that the output unit 105 outputs a plurality of display columns or display rows of output data signals.

[0089] For example, control each data transmission unit 104 to transmit the decoding signal stored in the data storage unit 103 to the output unit 105. The output unit 105 generates an output data signal for controlling the display screen according to the received decoding signal, such as a display column or a display row.

[0090] In summary, the control method of the display driving chip 100 proposed in the present disclosure can improve the winding efficiency, reduce the area and power consumption, and improve the overall data transmission efficiency by distributing the input data signal transmitted by the first number of input terminals to a plurality of functional areas, each functional area corresponding to a data processing unit 102, a data storage unit 103 and a plurality of output units 105. Through the above functional areas, the display driving chip 100 proposed in the present disclosure can allow partial refresh instead of full frame refresh by setting a plurality of output units 105, each input terminal corresponding to an output unit 105, which can reduce power consumption and the demand for data bandwidth. The display driving chip 100 control method proposed in the present disclosure can adapt to a wider range of resolutions, thereby providing greater flexibility and applicability.

[0091] In some examples, the above method comprises:

[0092] In a case where the interface unit 101 receives the input data signal of the third number of input terminals, the output unit 105 corresponding to the third number of input terminals is controlled to be in an active state, and the remaining output units 105 are controlled to be in an inactive state or a sleep state, wherein the third number is less than the first number.

[0093] For example, in a case where the interface unit 101 receives the input data signal of the third number of input terminals, that is, only part of the input terminals input the data signal, only partial display is required, the output units 105 corresponding to the part not required to be displayed are turned off, and only the output units 105 corresponding to the display modules required to be displayed are opened for data transmission, so that the digital power consumption of these modules can be reduced.

[0094] As shown in FIG. 7, the display control method provided by the present disclosure further includes an electronic device 300, which includes a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor 320, and the processor 320 implements the steps of any method of the display control method when executing the computer program 311.

[0095] The device used to implement the method in the present disclosure is within the scope of protection of the present disclosure.

[0096] In the implementation process, the computer program 311 can implement any embodiment in the second aspect when executed by the processor.

[0097] As shown in FIG. 8, the display control method provided by the present disclosure further includes a display module 1000, which includes the display driving chip 100 in the first aspect and a display unit 200.

[0098] As shown in FIG. 9, the display control method provided by the present disclosure further includes a display device 2000, which includes the display module 1000.

[0099] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in an embodiment can be referred to the related description of other embodiments.

[0100] Those skilled in the art should understand that the embodiments of the present disclosure can be provided as a method, a system, or a computer program product. Therefore, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present disclosure can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0101] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in the flowchart one or more blocks and / or in the block or blocks of the block diagram.

[0102] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks or in the flowchart one or more blocks and / or in the block or blocks of the block diagram.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in the flowchart one or more blocks and / or in the block or blocks of the block diagram.

[0104] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in the flowchart one or more blocks and / or in the block or blocks of the block diagram.

[0105] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present disclosure are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that the computer can store or be integrated into a data storage device such as a server, data center, etc. containing one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0106] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0107] In several embodiments provided by the present disclosure, it should be understood that the disclosed system, device and method can be implemented by other manners. For example, the above-described device embodiments are only schematic, for example, the division of units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0108] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0109] In addition, each function unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0110] When the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present disclosure, essentially or in the form of a contribution to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various media that can store program codes.

[0111] The above, the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present disclosure.

Claims

1. A display driver chip, comprising: an interface unit, the interface unit being configured to receive input data signals transmitted from a first number of input terminals; a plurality of data processing units, each of the data processing units being connected to the interface unit, each of the data processing units comprising a data decompressor and a decoder, each of the data processing units being configured to perform decompression and decoding operations on the input data signals of the second number of input terminals and generate decoded signals of the second number of input terminals; a plurality of data storage units, each of the data storage units being connected to a corresponding data processing unit, and each of the data storage units being used to store decoded signals of the second number of input terminals; Multiple output units, a second number of the output units are respectively connected to one of the data storage units through their respective corresponding data transmission units, each of the output units is used to output output data signals for multiple display columns or display rows, wherein the first number is greater than the second number.

2. The display driver chip according to claim 1, further comprising: A logic integrated circuit core unit is connected to the interface unit, each of the data processing units, each of the data storage units and each of the output units respectively, and the logic integrated circuit core unit is used to control the data transmission operation of the display driver chip. 3 . The display driver chip according to claim 1 , wherein the orthographic projections of each of the data transmission units in the thickness direction of the display driver chip have no overlap.

4. The display driver chip according to claim 1, each of the data storage units, each of the data processing units, the second number of the output units, and the second number of the data transmission units constitute a regional display function module, and any two of the regional display function modules have no overlap in the orthographic projection in the thickness direction of the display driver chip, and each of the regional display function modules is used to process display data of a partial display area of ​​the display unit. 5 . The display driver chip according to claim 4 , wherein a distance between the data storage unit and a center line of the regional display function module in a width direction is less than a preset distance.

6. The display driver chip according to claim 2, wherein the data transmission unit comprises a first data transmission unit and a second data transmission unit, the first data transmission unit is connected to the output unit and the second data transmission unit, the second data transmission unit is further connected to the data storage unit, and the second data transmission unit comprises a compensation circuit, and the compensation circuit is used for impedance matching.

7. The display driver chip according to claim 6, wherein the first data transmission unit and the logic integrated circuit core unit do not overlap in a thickness direction of the display driver chip, and the second data transmission unit and the logic integrated circuit core unit at least partially overlap in the thickness direction of the display driver chip.

8. The display driver chip according to claim 1, wherein the first number is twice the second number, the number of the data processing units and the number of the data storage units are both 2, and each of the data storage units and each of the output units is used to process display data of 1 / 2 display area of ​​the display unit.

9. According to the display driver chip of claim 8, the interface unit includes a first interface unit and a second interface unit, the first interface unit is connected to the first data processing unit, and the second interface unit is connected to the second data processing unit, the first interface unit is used to receive input data signals transmitted by the second number of input terminals, and the second interface unit is used to receive input data signals transmitted by the remaining input terminals, the distance between the interface unit and the center line of the display driver chip in the width direction is less than a preset distance, and the first interface unit and the second interface unit have no overlap in their orthographic projections in the thickness direction of the display driver chip. 10 . The display driver chip according to claim 8 , wherein the two data processing units are symmetrically arranged with respect to the interface unit in a width direction of the display chip, and the two data storage units are symmetrically arranged with respect to the interface unit in the width direction of the display chip.

11. A display control method, used in the display driver chip according to any one of claims 1 to 8, the method comprising: Controlling the interface unit to receive input data signals from a first number of input terminals; Controlling the interface unit to distribute the received input data signals of the first number of input terminals to the plurality of data processing units, so that each of the data processing units performs data decompression and decoding operations to generate decoded signals of the second number of input terminals; controlling each of the data processing units to transmit the decoded signals of each group of the second number of input terminals to the corresponding data storage unit for data storage; Each of the data transmission units is controlled to transmit the decoded signal stored in the data storage unit to the output unit, so that the output unit outputs output data signals of a plurality of display columns or display rows.

12. The display control method according to claim 11, further comprising: When the interface unit receives input data signals from the third number of input terminals, the output units corresponding to the third number of input terminals are controlled to be in a working state, and the remaining output units are controlled to be in a closed state or a dormant state.

13. An electronic device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the display control method according to claim 11 or 12 when executing the computer program stored in the memory.

14. A display module, comprising the display driver chip according to any one of claims 1 to 10, the display module further comprising a display unit.

15. A display device comprising the display module according to claim 14.

Images