Semiconductor integrated circuit device

Abstract

An inverter cell (C1) having a logic function and a filler cell (C3) having no logic function are arranged adjacent to each other. The inverter cell (C1) is provided with an active region (2P1) and power supply wiring (11) formed in a back wiring layer. The filler cell (C3) is provided with an active region (2P3). In a second direction, a first-side end and a second-side end of the active region (2P1) are disposed between a first-side end and a second-side end of the active region (2P3) .

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter, also simply referred to as a cell, as appropriate) that includes a fork-sheet transistor.

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Standard cells include cells with logic functions such as NAND gates and NOR gates (hereinafter referred to as logic cells, as appropriate), as well as cells without logic functions. An example of a cell without logic functions is a "filler cell." A "filler cell" is a cell that does not have a logic function, does not contribute to the logic function of a circuit block, and is placed between logic cells.

[0005] Patent Document 1 discloses a filler cell that uses a CFET (Complementary FET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate in order to reduce the area of ​​a semiconductor integrated circuit device.

[0006] Patent Document 2 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a fork-shaped gate electrode, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 2 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0007] Patent Document 3 discloses a standard cell in which back wiring is provided on the back surface immediately below a transistor in order to reduce the area of ​​the semiconductor integrated circuit device, and the source and drain of the transistor are connected to this.

[0008] International Publication No. WO 2020 / 137660 International Publication No. WO 2021 / 075434 U.S. Patent Application Publication No. 2022 / 0375761

[0009] However, no specific study has been done on filler cells using fork-sheet transistors and backside wiring.

[0010] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including a filler cell using a fork-sheet transistor and backside wiring.

[0011] In an aspect of the present disclosure, there is provided a semiconductor integrated circuit device comprising: a first standard cell having a logic function; and a second standard cell arranged adjacent to the first standard cell and having no logic function, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, the channel comprising: a first active region including a first nanosheet extending in a first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction; a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; and a first gate wiring formed in a region where a region in the first active region that serves as a source of the first transistor overlaps with the first power supply wiring, the first gate wiring connecting the source of the first transistor in the first active region to the first power supply wiring. a first via connected to the first nanosheet, a surface on a first side which is one side in the second direction of the first nanosheet being exposed from the first gate wiring; the second standard cell constituting a channel, a source, and a drain of a first dummy transistor of a first conductivity type, the second active region including the second nanosheet extending in the first direction as the channel; a first dummy gate wiring extending in the second direction and surrounding the periphery of the second nanosheet in the second direction and the third direction; and a second power supply wiring formed on the back side of the first dummy transistor, extending in the first direction, and supplying the first power supply voltage; the surface on the first side of the second nanosheet being exposed from the first dummy gate wiring; and in the second direction, the first end and the second end of the first active region are arranged between the first end of the second active region and the second end of the second active region which is the other side in the second direction.

[0012] According to the present disclosure, in the second direction, the first and second ends of the first active region of the first standard cell having a logic function are arranged between the first and second ends of the second active region of the second standard cell not having a logic function. By arranging the second standard cell adjacent to the first standard cell, the second active region of the second standard cell can be arranged along the entire side surface of the first active region of the first standard cell in the first direction. Therefore, the distance from the first active region of the first standard cell to the second active region of the second standard cell is set to a predetermined value. This improves the accuracy of estimating the transistor performance of standard cells having a logic function.

[0013] According to the present disclosure, in a layout of a semiconductor integrated circuit device including filler cells using fork-sheet transistors and backside wiring, it is possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions.

[0014] 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a first embodiment. FIG. 2 is a plan view showing an example of the layout structure of an inverter cell according to the first embodiment. FIG. 3 is a circuit diagram of an inverter cell. FIG. 4 is a plan view showing an example of the layout structure of a filler cell according to the first embodiment. FIG. 5 is a cross-sectional view of the filler cell of FIG. 4. FIG. 6 is a plan view showing an example of the layout structure of a filler cell according to a modified example of the first embodiment. FIG. 7 is another configuration example of a semiconductor integrated circuit device according to the first embodiment. FIG. 8 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. FIG. 9 is a plan view showing an example of the layout structure of an inverter cell according to the second embodiment. FIG. 10 is a plan view showing an example of the layout structure of a filler cell according to the second embodiment.

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells, and at least some of the plurality of standard cells include fork sheet transistors, which are nanosheet FETs and have fork-shaped gate electrodes. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0017] (First Embodiment) (Circuit Block Configuration) Fig. 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a first embodiment. The block layout in Fig. 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a wiring layer (backside wiring layer) provided on the back side of a semiconductor chip on which transistors are formed.

[0018] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0019] 1 and other plan views, the dashed lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0020] In the layout of FIG. 1, a plurality of cells arranged in the X direction constitute a cell row CR. The plurality of cells include inverter cells C1 and C2 having a logic function and a filler cell C3. In the layout of FIG. 1, the filler cell C3 is arranged between the inverter cells C1 and C2. Note that a "filler cell" refers to a cell that does not have a logic function, does not contribute to the logic function of the circuit block, and is arranged between logic cells.

[0021] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0022] As will be described in detail later, each cell is configured with an active region that forms the channel, source, and drain of a P-type transistor, and an active region that forms the channel, source, and drain of an N-type transistor. Specifically, inverter cell C1 is configured with active regions 2P1 and 2N1. inverter cell C2 is configured with active regions 2P2 and 2N2. filler cell C3 is configured with active regions 2P3 and 2N3.

[0023] The active region 2P3 (2N3) of the filler cell C3 is arranged to the right of the active region 2P1 (2N1) of the inverter cell C1 in the X direction in the drawing. The active region 2P3 (2N3) of the filler cell C3 is arranged to the left of the active region 2P2 (2N2) of the inverter cell C2 in the X direction in the drawing. In other words, the active regions of the filler cells without logic functions are arranged adjacent to the active regions of the standard cells with logic functions in the X direction.

[0024] (Configuration of inverter cell C1) Fig. 2 is a plan view showing an example of the layout structure of inverter cells C1 and C2 according to the first embodiment, and Fig. 3 is a circuit diagram of the inverter cell. Specifically, Fig. 2(a) shows a plan view of inverter cell C1, and Fig. 2(b) shows a plan view of inverter cell C2.

[0025] In the following description, the dashed lines running vertically and horizontally in plan views such as Figure 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0026] As shown in FIG. 3, the inverter cell C1 has transistors P1 and N1, and an inverter circuit having an input A and an output Y is configured.

[0027] 2A, a BM0 wiring layer, which is a wiring layer, is formed on the back surface of a semiconductor chip on which transistors are formed. In the BM0 wiring layer, power supply wirings 11 and 12 extending in the X direction are formed at both ends of the cell in the Y direction in the drawing. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS. The power supply wirings 11 and 12 are shared with other cells in the cell string CR including the inverter cell C1, and serve as power supply wiring extending in the X direction.

[0028] An active region constituting the channel, source, and drain of the P-type transistor is formed in a P-type transistor region on an N-type well (NWell). Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0029] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheet structures (not shown) in a plan view and extends in the X direction. In the active region 2P1, the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in the region where the power supply wiring 11 and the active region 2P1 overlap in a plan view.

[0030] An active region constituting the channel, source, and drain of the N-type transistor is formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 overlaps with the power supply wiring 12 in a plan view.

[0031] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has a channel made of a nanosheet 22 extending in the X direction and consisting of three overlapping sheet structures (not shown) in a plan view. In the active region 2N1, the source of the transistor N1 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in the region where the power supply wiring 12 and the active region 2N1 overlap in a plan view.

[0032] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0033] Gate wirings 31a and 31b extending in the Y direction are formed in the center of the cell in the X direction. The nanosheet 21 overlaps with the gate wiring 31a in a planar view. The nanosheet 22 overlaps with the gate wiring 31b in a planar view. The gate wiring 31a corresponds to the gate of transistor P1. The gate wiring 31b corresponds to the gate of transistor N1.

[0034] Although not shown in the figure, gate wiring 31a covers the outer periphery of nanosheet 21 in the Y and Z directions so that a portion of the outer periphery of nanosheet 21 is exposed. Gate wiring 31b covers the outer periphery of nanosheet 22 in the Y and Z directions so that a portion of the outer periphery of nanosheet 22 is exposed. Specifically, the lower surface of nanosheet 21 in the Y direction is exposed from gate wiring 31a, and the upper surface of nanosheet 21 in the Y direction is covered by gate wiring 31a. The upper surface of nanosheet 22 in the Y direction is exposed from gate wiring 31b, and the lower surface of nanosheet 22 in the Y direction is covered by gate wiring 31b.

[0035] The gate wirings 31a and 31b are connected via a bridge portion 31c extending in the Y direction.

[0036] Dummy gate wirings 32a and 32b are formed on the cell frame on the left side of the drawing in the X direction. Dummy gate wirings 33a and 33b are formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wirings 32a and 32b are shared with other cells arranged on the left side of the drawing. The dummy gate wirings 33a and 33b are shared with other cells arranged on the right side of the drawing. The dummy gate wirings 32a and 32b are connected via a bridge portion 32c extending in the Y direction. The dummy gate wirings 33a and 33b are connected via a bridge portion 33c extending in the Y direction.

[0037] The local interconnect layer has a local interconnect (LI) 41 extending in the Y direction. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1 and a portion of the active region 2N1 that serves as the drain of the transistor N1.

[0038] Wirings 51 and 52 extending in the X direction are formed in the M0 wiring layer, which is a metal wiring layer above the local wiring layer. Wiring 51 is connected to gate wiring 31b through a via. Wiring 52 is connected to local wiring 41 through a via. Wiring 51 corresponds to input A, and wiring 52 corresponds to output Y.

[0039] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0040] As shown in FIG. 2A, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0041] (Configuration of Inverter Cell C2) The inverter cell C2 has almost the same configuration as the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C2 is a standard cell having a logic function.

[0042] As shown in FIG. 2B, in comparison with the inverter cell C1 shown in FIG. 2A, the inverter cell C2 has active regions 2P2 and 2N2 having different widths in the Y direction arranged therein instead of the active regions 2P1 and 2N1.

[0043] Specifically, the active regions 2P2 and 2N2 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0044] 2, the bottom edge of the active region 2P2 in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P1. The top edge of the active region 2N2 in the Y direction is located at the same position in the Y direction as the top edge of the active region 2N1. That is, the bottom edge of the active region 2P1 of the inverter cell C1 in the Y direction and the bottom edge of the active region 2P2 of the inverter cell C2 in the Y direction are aligned in the Y direction. The top edge of the active region 2N1 of the inverter cell C1 in the Y direction and the top edge of the active region 2N2 of the inverter cell C2 in the Y direction are aligned in the Y direction.

[0045] In the inverter cell C1 (C2) of FIG. 2, the surface of the nanosheet 21 on the lower side in the Y direction is exposed from the gate wiring 31a. The surface of the nanosheet 22 on the upper side in the Y direction is exposed from the gate wiring 31b. That is, the surfaces of the nanosheets 21 and 22 that face each other in the Y direction are exposed from the gate wiring 31a and 31b, respectively. This allows the distance d1 in the Y direction between the active regions 2P1 and 2N1 (2P2 and 2N2) in the inverter cell C1 (C2) to be reduced. This allows the area of ​​the semiconductor integrated circuit device to be reduced.

[0046] In the inverter cell C1 (C2) of FIG. 2, the upper surface of the nanosheet 21 in the Y direction is covered by the gate wiring 31a. The lower surface of the nanosheet 22 in the Y direction is covered by the gate wiring 31b. Each cell row CR is arranged in an inverted manner in the Y direction, with every other row being inverted. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their opposing surfaces not exposed to the gate wiring. Therefore, the distance in the Y direction between the active regions of cells adjacent to each other in the Y direction is greater than the distance d1 in the Y direction between the active regions 2P1, 2N1 (2P2, 2N2) in the inverter cell C1 (C2).

[0047] 2, the distance d2 in the Y direction between the power supply wiring 11 and 12 formed in the BM0 wiring layer is greater than the distance d1 in the Y direction between the active regions 2P1 and 2N1 (2P2 and 2N2). That is, in a plan view, the bottom end of the power supply wiring 11 in the Y direction is located above the bottom end of the active region 2P1 (2P2) in the Y direction. In a plan view, the top end of the power supply wiring 12 in the Y direction is located below the top end of the active region 2N1 (2N2) in the Y direction. In other words, in a plan view, the bottom end of the active region 2P1 (2P2) and the top end of the active region 2N1 (2N2) are located between the bottom end of the power supply wiring 11 and the top end of the power supply wiring 12 (i.e., inside the power supply wiring 11 and 12).

[0048] (Configuration of filler cell C3) Fig. 4 is a plan view showing an example of the layout structure of the filler cell according to the first embodiment, and Fig. 5 is a cross-sectional view showing an example of the layout structure of the filler cell according to the first embodiment. Specifically, Fig. 5(a) is a cross-section taken along X1-X1' in Fig. 4, Fig. 5(b) is a cross-section taken along Y1-Y1' in Fig. 4, and Fig. 5(c) is a cross-section taken along Y2-Y2' in Fig. 4.

[0049] In the BM0 wiring layer, power supply wirings 11 and 12 are formed on both ends of the cell in the Y direction in the drawing, extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0050] An active region 2P3 is formed in the P-type transistor region. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0051] P-type dummy transistors DP1 to DP3 are formed in the active region 2P3. The dummy transistors DP1 to DP3 each have a channel made of three overlapping sheets in a plan view, and have nanosheets 121 to 123 extending in the X direction.

[0052] An active region 2N3 is formed in the N-type transistor region. The active region 2N3 overlaps with the power supply wiring 12 in plan view.

[0053] N-type dummy transistors DN1 to DN3 are formed in the active region 2N3. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0054] Dummy gate wirings 131a to 133a and 131b to 133b are formed extending in the Y and Z directions. The nanosheets 121 to 126 overlap the dummy gate wirings 131a to 133a and 131b to 133b, respectively, in a plan view. The dummy gate wirings 131a to 133a and 131b to 133b correspond to the gates of the dummy transistors DP1 to DP3 and DN1 to DN3, respectively.

[0055] As shown in FIG. 5C, dummy gate wirings 131a-133a and 131b-133b cover the outer peripheries of nanosheets 121-126 in the Y and Z directions, respectively, so that a portion of the outer periphery of nanosheets 121-126 is exposed. Specifically, the right-hand side surfaces of nanosheets 121-123 in the drawing are not covered by dummy gate wirings 131a-133a. The left-hand side surfaces of nanosheets 124-126 in the drawing are not covered by dummy gate wirings 131b-133b. Therefore, in FIG. 4, the lower surfaces of nanosheets 121-123 in the Y direction are exposed from dummy gate wirings 131a-133a, respectively, and the upper surfaces in the Y direction are covered by dummy gate wirings 131a-133a. The upper surfaces of the nanosheets 124 to 126 in the Y direction are exposed from the dummy gate wirings 131b to 133b, respectively, and the lower surfaces of the nanosheets 124 to 126 in the Y direction are covered by the dummy gate wirings 131b to 133b, respectively.

[0056] Dummy gate wirings 134a and 134b are formed on the cell frame on the left side of the drawing in the X direction. Dummy gate wirings 135a and 135b are formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wirings 134a and 134b are shared with another cell arranged on the left side of the drawing (inverter cell C1 in FIG. 1). The dummy gate wirings 135a and 135b are shared with another cell arranged on the right side of the drawing (inverter cell C2 in FIG. 1). The dummy gate wirings 134a and 134b are connected via a bridge portion 134c extending in the Y direction. The dummy gate wirings 135a and 135b are connected via a bridge portion 135c extending in the Y direction.

[0057] Local wirings 141 to 144 extending in the Y direction are formed in the local wiring layer. Local wiring 141 is connected to a portion that will become the source of dummy transistor DP1 in active region 2P3 and a portion that will become the source of dummy transistor DN1 in active region 2N3. Local wiring 142 is connected to a portion that will become the drain of dummy transistor DP1 and a portion that will become the source of dummy transistor DP2 in active region 2P3, and to a portion that will become the drain of dummy transistor DN1 and a portion that will become the source of dummy transistor DN2 in active region 2N3. Local wiring 143 is connected to a portion that will become the drain of dummy transistor DP2 and a portion that will become the source of dummy transistor DP3 in active region 2P3, and to a portion that will become the drain of dummy transistor DN2 and a portion that will become the source of dummy transistor DN3 in active region 2N3. The local wiring 144 is connected to a portion that serves as the drain of the dummy transistor DP3 in the active region 2P3 and a portion that serves as the drain of the dummy transistor DN3 in the active region 2N3.

[0058] 4, unlike the inverter cells C1 and C2, the dummy gate wirings 131a to 133a, 131b to 133b and the local wirings 141 to 144 are not connected to any other wirings. In other words, the filler cell C3 is a standard cell that does not have a logic function.

[0059] In the block layout of FIG. 1 , a filler cell C3 without a logic function is arranged adjacent to an inverter cell C1 with a logic function. The inverter cell C1 includes an active region 2P1 and an active region 2N1. The filler cell C3 includes an active region 2P3 and an active region 2N3. The nanosheets 121-123 (124-126) of the filler cell C3 are arranged in the same position in the Y direction as the nanosheet 21 (22) of the inverter cell C1. The active region 2P3 (2N3) is arranged in the same position in the Y direction as the active region 2P1 (2N1). In other words, by arranging the active region in the filler cell C3, it is possible to suppress variations in the density of transistor arrangement. This reduces manufacturing variations in semiconductor integrated circuit devices and improves yield.

[0060] Furthermore, in the X direction, the active area closest to the active area 2P1 (2N1) of the inverter cell C1 is the active area 2P3 (2N3) of the filler cell C3. Therefore, the presence of the active area 2P3 (2N3) determines the distance of the active area 2P1 (2N1) to the adjacent transistor to a predetermined value. In other words, the presence of the active area in the filler cell C3 allows the distance from the active area closest to the cell edge of the logic cell (inverter cell C1) to the active area adjacent to that active area to be estimated to a predetermined value. This improves the accuracy of estimating the transistor performance of the logic cell.

[0061] Furthermore, the gate wiring 31a and dummy gate wirings 32a, 33a (134a) of the inverter cell C1, the gate wiring 31a and dummy gate wirings 32a (135a), 33a of the inverter cell C2, and the dummy gate wirings 131a to 133a of the filler cell C3 are arranged at the same pitch Pg in the X direction. The gate wiring 31b and dummy gate wirings 32b, 33b (134b) of the inverter cell C1, the gate wiring 31b and dummy gate wirings 32b (135b), 33b of the inverter cell C2, and the dummy gate wirings 131b to 133b of the filler cell C3 are arranged at the same pitch Pg in the X direction. That is, the gate wirings (including the dummy gate wirings) of the inverter cells C1, C2, and filler cell C3 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0062] Furthermore, the local wiring 41 of the inverter cell C1 and the local wirings 141 to 144 of the filler cell C3 are arranged at the same pitch P1 in the X direction. That is, the local wirings 41, 141 to 144 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0063] Furthermore, the lower end (upper end) in the Y direction of the active region 2P1 (2N1) of the inverter cell C1, the lower end (upper end) in the Y direction of the active region 2P2 (2N2) of the inverter cell C2, and the lower end (upper end) in the Y direction of the active region 2P3 (2N3) of the filler cell C3 are arranged at the same position in the Y direction. That is, the lower end (upper end) in the Y direction of the active region 2P1 (2N1) of the inverter cell C1, the lower end (upper end) in the Y direction of the active region 2P2 (2N2) of the inverter cell C2, and the lower end (upper end) in the Y direction of the active region 2P3 (2N3) of the filler cell C3 are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C1 and C2 and the nanosheets 121-123 (124-126) of the filler cell C3 have their surfaces on the lower side (upper side) of the drawing in the Y direction exposed from the gate wiring 31a (31b) and dummy gate wiring 131a-133a (131b-133b), respectively. That is, in the inverter cells C1 and C2 and the filler cell C3, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row CR in which standard cells are arranged in the X direction, as in the configuration of FIG. 1, by aligning the positions of the nanosheet surfaces exposed from the gate wiring in the Y direction, the shape of the structure, i.e., its size and layout area in the Y direction, can be made constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0064] The Y-direction width of the active region 2P1 (2N1) in the inverter cell C1 and the Y-direction width of the active region 2P3 (2N3) in the filler cell C3 are w1. The Y-direction width of the active region 2P2 (2N2) in the inverter cell C2 is w2, which is smaller than w1. The Y-direction bottom end (top end) of the active region 2P1 (2N1) in the inverter cell C1, the Y-direction bottom end (top end) of the active region 2P2 (2N2) in the inverter cell C2, and the Y-direction bottom end (top end) of the active region 2P3 (2N3) in the filler cell C3 are aligned in the Y-direction. By disposing the filler cell C3 between the inverter cells C1 and C2, which have active regions with different Y-direction widths, the active region of the filler cell C3 can be positioned along the entire right side of the active region of the inverter cell C1 and the entire left side of the active region of the inverter cell C2. Therefore, the distances from the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2 to the active region 2P3 (2N3) of the filler cell C3 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0065] In this embodiment, the size of the filler cell C3 in the X direction is set to four grids, but is not limited to this.

[0066] In addition, in this embodiment, the filler cell C3 includes the local wirings 141 to 144, but it is not necessary to include some or all of these.

[0067] In this embodiment, the dummy gate wirings 131a and 131b may be connected via a bridge portion. Similarly, the dummy gate wirings 132a and 132b may be connected via a bridge portion. The dummy gate wirings 133a and 133b may be connected via a bridge portion.

[0068] (Modification) FIGS. 6A and 6B are plan views showing another example of the layout structure of filler cells according to a modification of the first embodiment.

[0069] The filler cell C3 in FIG. 6A has a cell width (size in the X direction) that is half (2 grids) of the filler cell C3 in FIG.

[0070] Specifically, the nanosheets 122 and 123, the dummy gate wirings 132a, 133a, 132b and 133b, and the local wirings 143 and 144 are omitted, and the width of the active regions 2P3 and 2N3 in the X direction is halved.

[0071] The configuration of FIG. 6A can also provide the same effect as that of FIG.

[0072] In the filler cell C3 of FIG. 6B, compared to the filler cell C3 of FIG. 4, the dummy gate wirings aligned in the Y direction are connected via a bridge portion, and the local wiring is omitted.

[0073] Specifically, the dummy gate wirings 131a and 131b are connected via a bridge portion 131c. The dummy gate wirings 132a and 132b are connected via a bridge portion 132c. The dummy gate wirings 133a and 133b are connected via a bridge portion 133c. Furthermore, the local wirings 141 to 144 are omitted.

[0074] The configuration of FIG. 6B can also provide the same effect as that of FIG.

[0075] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0076] 7A shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in FIG. 7A is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0077] 7B shows a cross section of the filler cell of FIG. 4 taken along line Y1-Y1' in this configuration example. As shown in FIG. 7B, a power supply wiring 11 that supplies VDD and a power supply wiring 12 that supplies VSS are formed in a wiring layer provided on the surface of chip B. Although not shown, in inverter cell C1 (C2), power supply wiring 11 is connected to active region 2P1 (2P2) of chip A via via 61. Power supply wiring 12 is connected to active region 2N1 (2N2) of chip A via via 62.

[0078] This configuration example also provides the same effects as the inverter cell described above.

[0079] Second Embodiment (Circuit Block Configuration) Figure 8 is a plan view showing an example of the layout of a circuit block provided in a semiconductor integrated circuit device according to a second embodiment. The block layout in Figure 8 is configured by arranging standard cells. In this embodiment as well, the power supply wiring is formed in the BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0080] In the layout of Fig. 8, a plurality of cells arranged in the X direction constitute a cell column CR. The plurality of cells include inverter cells C4 and C5 having a logic function and a filler cell C6. In the layout of Fig. 8, the filler cell C6 is disposed between the inverter cells C4 and C5.

[0081] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0082] As will be described in detail later, each cell is configured with an active region that forms the channel, source, and drain of a P-type transistor, and an active region that forms the channel, source, and drain of an N-type transistor. Specifically, inverter cell C4 is configured with active regions 2P4 and 2N4. inverter cell C5 is configured with active regions 2P5 and 2N5. filler cell C6 is configured with active regions 2P6 and 2N6.

[0083] The active region 2P6 (2N6) of the filler cell C6 is arranged to the right of the active region 2P4 (2N4) of the inverter cell C4 in the X direction of the drawing. The active region 2P6 (2N6) of the filler cell C6 is arranged to the left of the active region 2P5 (2N5) of the inverter cell C5 in the X direction of the drawing. In other words, the active regions of the filler cells without a logic function are arranged adjacent to the active regions of the standard cells with a logic function in the X direction.

[0084] (Configuration of Inverter Cell C4) Figure 9 is a plan view showing an example of the layout structure of inverter cells C4 and C5 according to the second embodiment. Specifically, Figure 9(a) shows a plan view of inverter cell C4, and Figure 9(b) shows a plan view of inverter cell C5. Note that the inverter cells C4 and C5 in Figure 9 each have the inverter circuit shown in Figure 3 configured therein.

[0085] 9A, power supply wirings 11 and 12 extending in the X direction are formed on both ends of the cell in the Y direction in the drawing in the BM0 wiring layer. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0086] An active region 2P4 is formed in the P-type transistor region. The active region 2P4 overlaps with the power supply wiring 11 in plan view.

[0087] A transistor P1 is configured in the active region 2P4. The transistor P1 has a nanosheet 221 extending in the X direction. In the active region 2P4, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 261. The via 261 is formed in a region where the power supply wiring 11 and the active region 2P4 overlap in a plan view.

[0088] An active region 2N4 is formed in the N-type transistor region. The active region 2N4 overlaps with the power supply wiring 12 in plan view.

[0089] A transistor N1 is configured in the active region 2N4. The transistor N1 has a nanosheet 222 extending in the X direction. In the active region 2N4, a portion that serves as the source of the transistor N1 is connected to the power supply wiring 12 via a via 262. The via 262 is formed in a region where the power supply wiring 12 and the active region 2N4 overlap in a plan view.

[0090] A gate wiring 231 extending in the Y direction is formed in the center of the cell in the X direction. The nanosheets 221 and 222 overlap the gate wiring 231 in plan view. The gate wiring 231 corresponds to the gates of the transistors P1 and N1.

[0091] Gate wiring 231 covers the outer peripheries of nanosheets 221 and 222 in the Y and Z directions, respectively, so as to expose part of the outer peripheries of nanosheets 221 and 222. Specifically, the upper surface of nanosheet 221 in the Y direction in the drawing is exposed from gate wiring 231, and the lower surface of nanosheet 221 in the Y direction in the drawing is covered by gate wiring 231. The lower surface of nanosheet 222 in the Y direction in the drawing is exposed from gate wiring 231, and the upper surface of nanosheet 222 in the Y direction in the drawing is covered by gate wiring 231.

[0092] Dummy gate wirings 232 and 233 are formed on both sides of the cell frame in the X direction. The dummy gate wiring 232 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 233 is shared with other cells arranged on the right side of the drawing.

[0093] The local wiring layer is formed with a local wiring 241 extending in the Y direction. The local wiring 241 is connected to a portion in the active region 2P4 that serves as the drain of the transistor P1 and a portion in the active region 2N4 that serves as the drain of the transistor N1.

[0094] In the M0 wiring layer, wirings 251 and 252 extending in the X direction are formed. The wiring 251 is connected to the gate wiring 231 through a via. The wiring 252 is connected to the local wiring 241 through a via. The wiring 251 corresponds to the input A, and the wiring 252 corresponds to the output Y.

[0095] As described above, the inverter cell C4 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0096] As shown in FIG. 9A, the active regions 2P4 and 2N4 in the inverter cell C4 have a width w1 in the Y direction in plan view.

[0097] (Configuration of Inverter Cell C5) The inverter cell C5 has a configuration similar to that of the inverter cell C4. Specifically, the inverter cell C5 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C5 is a standard cell having a logic function.

[0098] As shown in FIG. 9B, in comparison with the inverter cell C4 shown in FIG. 9A, the inverter cell C5 has active regions 2P5 and 2N5 having different widths in the Y direction arranged therein instead of the active regions 2P4 and 2N4.

[0099] Specifically, the active regions 2P5 and 2N5 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0100] 9, the upper end of the active region 2P5 in the Y direction is located at the same position in the Y direction as the upper end of the active region 2P4 in the Y direction. The lower end of the active region 2N5 in the Y direction is located at the same position in the Y direction as the lower end of the active region 2N4 in the Y direction. That is, the upper end of the active region 2P4 of the inverter cell C4 in the Y direction and the upper end of the active region 2P5 of the inverter cell C5 in the Y direction are aligned in the Y direction. The lower end of the active region 2N4 of the inverter cell C4 in the Y direction and the lower end of the active region 2N5 of the inverter cell C5 in the Y direction are aligned in the Y direction.

[0101] In the inverter cell C4 (C5) of FIG. 9 , the nanosheet 221 has its upper surface in the Y direction exposed from the gate wiring 231. The nanosheet 222 has its lower surface in the Y direction exposed from the gate wiring 231. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring facing each other in the Y direction. This reduces the distance d13 from the top end of the active regions 2P4 and 2P5 in the Y direction to the top end of the cell frame in the Y direction, and the distance d13 from the bottom end of the active regions 2N4 and 2N5 in the Y direction to the bottom end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0102] 9, the lower surface of the nanosheet 221 in the Y direction is covered by the gate wiring 231. The upper surface of the nanosheet 222 in the Y direction is covered by the gate wiring 231. That is, the surfaces of the nanosheets 221 and 222 that face each other in the Y direction are not exposed from the gate wiring 231. Therefore, the distance d11 (d12) in the Y direction between the active regions 2P4 and 2N4 (2P5 and 2N5) in the inverter cell C4 (C5) is greater than the distance (2 × d13) in the Y direction between the active regions of cells adjacent in the Y direction.

[0103] (Configuration of Filler Cell C6) FIG. 10 is a plan view showing an example of the layout structure of the filler cell according to the second embodiment.

[0104] In the BM0 wiring layer, power supply wirings 11 and 12 are formed on both ends of the cell in the Y direction in the drawing, extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0105] An active region 2P6 is formed in the P-type transistor region. The active region 2P6 overlaps with the power supply wiring 11 in plan view.

[0106] P-type dummy transistors DP1 to DP3 are formed in the active region 2P6. The dummy transistors DP1 to DP3 have nanosheets 321 to 323 extending in the X direction as channels.

[0107] An active region 2N6 is formed in the N-type transistor region. The active region 2N6 overlaps with the power supply wiring 12 in plan view.

[0108] N-type dummy transistors DN1 to DN3 are formed in the active region 2N6. The dummy transistors DN1 to DN3 have nanosheets 324 to 326 extending in the X direction as channels.

[0109] Dummy gate wirings 331a to 333a and 331b to 333b are formed extending in the Y and Z directions. The nanosheets 321 to 326 overlap the dummy gate wirings 331a to 333a and 331b to 333b, respectively, in a plan view. The dummy gate wirings 331a to 333a and 331b to 333b correspond to the gates of the dummy transistors DP1 to DP3 and DN1 to DN3, respectively.

[0110] Dummy gate wirings 331a to 333a and 331b to 333b cover the outer peripheries of nanosheets 321 to 326 in the Y and Z directions, respectively, so that a portion of the outer peripheries of nanosheets 321 to 326 is exposed. Specifically, the upper surfaces of nanosheets 321 to 323 in the Y direction are exposed from dummy gate wirings 331a to 333a, respectively, and the lower surfaces of nanosheets 321 to 323 in the Y direction are covered by dummy gate wirings 331a to 333a, respectively. The lower surfaces of nanosheets 324 to 326 in the Y direction are exposed from dummy gate wirings 331b to 333b, respectively, and the upper surfaces of nanosheets 324 to 326 in the Y direction are covered by dummy gate wirings 331b to 333b, respectively.

[0111] A dummy gate wiring 334 is formed on the cell frame on the left side of the drawing in the X direction. A dummy gate wiring 335 is formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wiring 334 is shared with another cell arranged on the left side of the drawing (inverter cell C4 in FIG. 8 ). The dummy gate wiring 335 is shared with another cell arranged on the right side of the drawing (inverter cell C5 in FIG. 8 ).

[0112] Local wirings 341 to 344 extending in the Y direction are formed in the local wiring layer. Local wiring 341 is connected to the portion that will become the source of dummy transistor DP1 in active region 2P6 and the portion that will become the source of dummy transistor DN1 in active region 2N6. Local wiring 342 is connected to the portion that will become the drain of dummy transistor DP1 and the portion that will become the source of dummy transistor DP2 in active region 2P6, and to the portion that will become the drain of dummy transistor DN1 and the portion that will become the source of dummy transistor DN2 in active region 2N6. Local wiring 343 is connected to the portion that will become the drain of dummy transistor DP2 and the portion that will become the source of dummy transistor DP3 in active region 2P6, and to the portion that will become the drain of dummy transistor DN2 and the portion that will become the source of dummy transistor DN3 in active region 2N6. The local wiring 344 is connected to a portion that serves as the drain of the dummy transistor DP3 in the active region 2P6 and a portion that serves as the drain of the dummy transistor DN3 in the active region 2N6.

[0113] 10, unlike the inverter cells C4 and C5, the dummy gate wirings 331a to 333a, 331b to 333b and the local wirings 341 to 344 are not connected to any other wirings. In other words, the filler cell C6 is a standard cell that does not have a logic function.

[0114] In the block layout of FIG. 8, filler cell C6, which does not have a logic function, is arranged adjacent to inverter cell C4, which has a logic function. Inverter cell C4 has active region 2P4 and active region 2N4. Filler cell C6 has active region 2P6 and active region 2N6. Nanosheets 321-323 (324-326) of filler cell C6 are arranged in the same position in the Y direction as nanosheet 221 (222) of inverter cell C4. Active region 2P6 (2N6) is arranged in the same position in the Y direction as active region 2P4 (2N4). In other words, by arranging an active region in filler cell C6, it is possible to suppress variations in the density of transistor arrangement. This reduces manufacturing variations in semiconductor integrated circuit devices and improves yield.

[0115] Furthermore, in the X direction, the active area closest to the active area 2P4 (2N4) of the inverter cell C4 is the active area 2P6 (2N6) of the filler cell C6. Therefore, the presence of the active area 2P6 (2N6) determines the distance of the active area 2P4 (2N4) to the adjacent transistor to a predetermined value. That is, the presence of the active area in the filler cell C6 allows the distance from the active area closest to the cell edge of the logic cell (inverter cell C4) to the active area adjacent to that active area to be estimated to a predetermined value. This improves the accuracy of estimating the transistor performance of the logic cell.

[0116] Furthermore, the gate wiring 231 and dummy gate wiring 232, 233 (334) of inverter cell C4, the gate wiring 231 and dummy gate wiring 232 (335), 233 of inverter cell C5, and the dummy gate wiring 331a-333a (331b-333b) of filler cell C6 are arranged at the same pitch Pg in the X direction. That is, the gate wiring (including the dummy gate wiring) of inverter cells C4, C5 and filler cell C6 is arranged regularly. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices and improve yields.

[0117] Furthermore, the local interconnection 241 of the inverter cell C4 and the local interconnections 341 to 344 of the filler cell C6 are arranged at the same pitch P1 in the X direction. That is, the local interconnections 241, 341 to 344 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0118] Furthermore, the upper end (lower end) in the Y direction of the active region 2P4 (2N4) of the inverter cell C4, the upper end (lower end) in the Y direction of the active region 2P5 (2N5) of the inverter cell C5, and the upper end (lower end) in the Y direction of the active region 2P6 (2N6) of the filler cell C6 are arranged at the same position in the Y direction. That is, the upper end (lower end) in the Y direction of the active region 2P4 (2N4) of the inverter cell C4, the upper end (lower end) in the Y direction of the active region 2P5 (2N5) of the inverter cell C5, and the upper end (lower end) in the Y direction of the active region 2P6 (2N6) of the filler cell C6 are aligned in the Y direction. Furthermore, the nanosheets 221 (222) of the inverter cells C4 and C5 and the nanosheets 321 to 323 (324 to 326) of the filler cell C6 have their upper (lower) surfaces in the Y direction exposed from the gate wiring 231 and dummy gate wiring 331a to 333a (331b to 333b), respectively. That is, in the inverter cells C4 and C5 and the filler cell C6, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and placement area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0119] The Y-direction width of the active region 2P4 (2N4) in the inverter cell C4 and the Y-direction width of the active region 2P6 (2N6) in the filler cell C6 are w1. The Y-direction width of the active region 2P5 (2N5) in the inverter cell C5 is w2, which is smaller than w1. The Y-direction top end (bottom end) of the active region 2P4 (2N4) in the inverter cell C4, the Y-direction top end (bottom end) of the active region 2P5 (2N5) in the inverter cell C5, and the Y-direction top end (bottom end) of the active region 2P6 (2N6) in the filler cell C6 are aligned in the Y-direction. By disposing the filler cell C6 between the inverter cells C4 and C5, which have active regions with different Y-direction widths, the active region of the filler cell C6 can be positioned along the entire right side of the active region of the inverter cell C4 and the entire left side of the active region of the inverter cell C5. Therefore, the distances from the active region 2P4 (2N4) of the inverter cell C4 and the active region 2P5 (2N5) of the inverter cell C5 to the active region 2P6 (2N6) of the filler cell C6 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0120] In this embodiment, the size of the filler cell C6 in the X direction is set to four grids, but is not limited to this.

[0121] In addition, in this embodiment, the filler cell C6 includes the local wirings 341 to 344, but it is not necessary to include some or all of these.

[0122] In this embodiment, the dummy gate wirings 331a and 331b may be connected. Similarly, the dummy gate wirings 332a and 332b may be connected, or the dummy gate wirings 333a and 333b may be connected. In these cases, the dummy gate wirings 331a and 331b are formed as one dummy gate wiring, the dummy gate wirings 332a and 332b are formed as one dummy gate wiring, and the dummy gate wirings 333a and 333b are formed as one dummy gate wiring.

[0123] In the above-described embodiments and modifications, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0124] In the above-described embodiment and modified examples, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0125] Furthermore, in the above-described embodiments and modifications, the standard cells having logic functions are described as inverter cells, but the standard cells having logic functions may be other cells (NAND, NOR, flip-flops, etc.).

[0126] In the above-described embodiment and modifications, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same wiring width, but the power supply wirings 11 and 12 may have different wiring widths.

[0127] According to the present disclosure, in a layout of a semiconductor integrated circuit device including filler cells using fork-sheet transistors and backside wiring, it is possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions.

[0128] 11, 12 Power supply wiring 21, 22, 121 to 126, 221, 222, 231 to 236 Nanosheet 31a, 31b, 231 Gate wiring 32a, 33a, 32b, 33b, 131a to 133a, 131b to 133b, 232, 233, 331a to 133a, 331b to 333b Dummy gate wiring 51, 52, 251, 252 Wiring 61, 62, 261, 262 Via 2P1 to 2P6, 2N1 to 2N6 Active area P1, N1 Transistor DP1 to DP3, DN1 to DN3 Dummy transistor C1, C2, C4, C5 Inverter cell C3, C6 Filler cell

Claims

1. A semiconductor integrated circuit device comprising a first standard cell having a logic function and a second standard cell arranged adjacent to the first standard cell and having no logic function, wherein the first standard cell comprises: a first active region constituting the channel, source, and drain of a first transistor of a first conductivity type, the first active region including a first nanosheet extending in a first direction as the channel; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding the periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; and a first via formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, connecting the source of the first transistor in the first active region to the first power supply wiring, wherein a surface of the first nanosheet on one side in the second direction, which is exposed from the first gate wiring, the second standard cell comprises: a second active region that constitutes the channel, source, and drain of a first dummy transistor of the first conductivity type and includes a second nanosheet extending in the first direction as the channel; a first dummy gate wiring that extends in the second direction and surrounds the outer periphery of the second nanosheet in the second and third directions; and a second power supply wiring that is formed on the back side of the first dummy transistor, extends in the first direction, and supplies the first power supply voltage, wherein the first side surface of the second nanosheet is exposed from the first dummy gate wiring, and the first side end and the second side end of the first active region are arranged between the first side end of the second active region and the second side end that is the other side in the second direction.

2. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell further comprises: a third active region including a third nanosheet extending in the first direction, constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the channel; a second gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions; a third power supply wiring formed on the back side of the second transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the third active region where the region serving as the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the third active region to the third power supply wiring, wherein the second side surface of the third nanosheet is exposed from the second gate wiring; and the second standard cell further comprises: a fourth active region that constitutes the channel, source, and drain of the second conductivity type second dummy transistor and includes a fourth nanosheet extending in the first direction as the channel; a second dummy gate wiring that extends in the second direction and surrounds the outer periphery of the fourth nanosheet in the second direction and the third direction; and a fourth power supply wiring that is formed on the back side of the second dummy transistor, extends in the first direction, and supplies the second power supply voltage, wherein the second side surface of the fourth nanosheet is exposed from the second dummy gate wiring, and the first side end and the second side end of the third active region are arranged between the first side end and the second side end of the fourth active region in the second direction.

3. A semiconductor integrated circuit device according to claim 2, wherein the third nanosheet is arranged on the first side of the first nanosheet, and the fourth nanosheet is arranged on the first side of the second nanosheet.

4. A semiconductor integrated circuit device according to claim 2, wherein the third nanosheet is arranged on the second side of the first nanosheet, and the fourth nanosheet is arranged on the second side of the second nanosheet.

5. A semiconductor integrated circuit device according to claim 2, wherein, in a plan view, the first side end of the first active region and the second side end of the third active region are disposed between the first side end of the first power supply wiring and the second side end of the second power supply wiring.

6. A semiconductor integrated circuit device according to claim 1, wherein, in a plan view, the first side end of the first nanosheet and the first side end of the second nanosheet are arranged at the same position in the second direction.

7. A semiconductor integrated circuit device according to claim 1, further comprising a third standard cell having a logic function, wherein the third standard cell comprises: a fifth active region which constitutes the channel, source, and drain of the third transistor of the first conductivity type, and which includes a fifth nanosheet extending in the first direction as the channel; a third gate wiring which surrounds the periphery in the second and third directions; a fifth power supply wiring which is formed on the back side of the third transistor and extends in the first direction; and a third via which is formed in a region in the fifth active region which becomes the source of the third transistor and which overlaps with the fifth power supply wiring, and which connects the source of the third transistor in the fifth active region to the fifth power supply wiring, wherein the first side surface of the fifth nanosheet is exposed from the third gate wiring; and wherein, in a plan view, the width of the fifth active region in the second direction is smaller than the width of the first active region in the second direction.

8. A semiconductor integrated circuit device according to claim 7, wherein the first standard cell further comprises: a third active region including a third nanosheet extending in the first direction as the channel, constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type; a second gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions; a third power supply wiring formed on the back side of the second transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the third active region where a region serving as the source of the second transistor in the third active region overlaps with the third power supply wiring, connecting the source of the second transistor in the third active region with the third power supply wiring, wherein the second side surface of the third nanosheet is exposed from the second gate wiring; and the third standard cell further comprises: a sixth active region including a sixth nanosheet extending in the first direction as the channel, constituting the channel, source, and drain of a fourth transistor of the second conductivity type; a fourth gate wiring extending in the second direction and surrounding the periphery of the sixth nanosheet in the second direction and the third direction; a sixth power supply wiring formed on the back side of the fourth transistor, extending in the first direction, and supplying the second power supply voltage; and a fourth via formed in a region in the sixth active region where a region serving as a source of the fourth transistor and the sixth power supply wiring overlap, connecting the source of the fourth transistor in the sixth active region and the sixth power supply wiring, wherein the second side surface of the sixth nanosheet is exposed from the fourth gate wiring, and in a planar view, the width of the sixth active region in the second direction is smaller than the width of the third active region in the second direction.

9. A semiconductor integrated circuit device according to claim 7, wherein, in a plan view, the first side end of the first active region, the first side end of the second active region, and the first side end of the fifth active region are arranged at the same position in the second direction.

10. A semiconductor integrated circuit device according to claim 1, wherein a third dummy gate wiring extending in the second direction and the third direction is provided at the boundary between the first standard cell and the second standard cell, and the first gate wiring, the first dummy gate wiring and the third dummy gate wiring are arranged at the same pitch in the first direction.

11. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell further comprises a first local interconnection extending in the second direction and connected to the drain of the first transistor in the first active region; the second standard cell further comprises a second local interconnection extending in the second direction and connected to the source of the first dummy transistor in the second active region, and a third local interconnection extending in the second direction and connected to the drain of the first dummy transistor in the second active region; and the first, second and third local interconnections are arranged at the same pitch in the first direction.

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