Light detection device and light detection system

Abstract

A light detection device according to one embodiment of the present disclosure comprises a light-receiving element that can receive light and output a current, a control circuit that can output a first signal and a second signal, a connection circuit that is provided between the light-receiving element and a first potential line and is controlled by the first signal, and a detection circuit that can output a third signal that is based on the current from the light-receiving element in accordance with the second signal.

Description

Optical detection device and optical detection system

[0001] The present disclosure relates to optical detection devices and optical detection systems.

[0002] A photoelectric conversion device including a plurality of pixels each having an avalanche diode (APD) has been proposed (Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-106660

[0004] There is a demand for improved performance in light-detecting devices.

[0005] It is desirable to provide a photodetector device with good performance.

[0006] An optical detection device according to an embodiment of the present disclosure includes a light receiving element capable of receiving light and outputting a current, a control circuit capable of outputting a first signal and a second signal, a connection circuit provided between the light receiving element and a first potential line and controlled by the first signal, and a detection circuit capable of outputting a third signal based on the current of the light receiving element in response to the second signal. An optical detection system according to an embodiment of the present disclosure includes a light source capable of irradiating light onto an object, and an optical detection device that receives light from the object. The optical detection device includes a light receiving element capable of receiving light and outputting a current, a control circuit capable of outputting the first signal and the second signal, the connection circuit provided between the light receiving element and the first potential line and controlled by the first signal, and the detection circuit capable of outputting the third signal based on the current of the light receiving element in response to the second signal.

[0007] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection system according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example configuration of a pixel of a light detection device according to an embodiment of the present disclosure. FIG. 3 is a timing chart illustrating an example operation of the light detection system according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating another example configuration of a pixel of a light detection device according to an embodiment of the present disclosure. FIG. 5 is a timing chart illustrating an example operation of the light detection system according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example configuration of a pixel of a light detection device according to a first modification of the present disclosure. FIG. 7 is a diagram illustrating another example configuration of a pixel of a light detection device according to the first modification of the present disclosure. FIG. 8 is a diagram illustrating an example configuration of a light detection device according to a second modification of the present disclosure. FIG. 9 is a diagram illustrating an example configuration of a light detection device according to the second modification of the present disclosure. FIG. 10A is a diagram illustrating another example configuration of a light detection device according to the second modification of the present disclosure. FIG. 10B is a diagram illustrating another example configuration of a light detection device according to the second modification of the present disclosure. FIG. 11 is a diagram illustrating an example configuration of a light detection device according to a third modification of the present disclosure. FIG. 12 is a diagram for explaining another configuration example of a photodetection device according to Modification 3 of the present disclosure. FIG. 13 is a diagram for explaining a configuration example of a photodetection device according to Modification 4 of the present disclosure. FIG. 14 is a diagram for explaining a configuration example of a photodetection device according to Modification 5 of the present disclosure. FIG. 15 is a timing chart showing an operation example of a photodetection device according to Modification 5 of the present disclosure. FIG. 16A is a diagram for explaining an example pixel arrangement of a photodetection device according to Modification 6 of the present disclosure. FIG. 16B is a diagram for explaining an example pixel arrangement of a photodetection device according to Modification 6 of the present disclosure. FIG. 16C is a diagram for explaining an example pixel arrangement of a photodetection device according to Modification 6 of the present disclosure. FIG. 16D is a diagram for explaining an example pixel arrangement of a photodetection device according to Modification 6 of the present disclosure. FIG. 17 is a diagram for explaining an example configuration of a photodetection device according to Modification 7 of the present disclosure. FIG. 18A is a diagram for explaining an example configuration of a photodetection device according to Modification 7 of the present disclosure. FIG. 18B is a diagram for explaining an example configuration of a photodetection device according to Modification 7 of the present disclosure. FIG. 19A is a diagram for explaining another configuration example of a photodetector according to the seventh modification of the present disclosure.Fig. 19B is a diagram for explaining another example configuration of a light detection device according to Modification 7 of the present disclosure. Fig. 19C is a diagram for explaining another example configuration of a light detection device according to Modification 7 of the present disclosure. Fig. 19D is a diagram for explaining another example configuration of a light detection device according to Modification 7 of the present disclosure. Fig. 20 is a diagram for explaining an example configuration of a pixel of a light detection device according to Modification 8 of the present disclosure. Fig. 21 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 22 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. Embodiment 2. Modification 3. Usage example 4. Application example

[0009] 1 is a diagram illustrating an example of a schematic configuration of a light detection system according to an embodiment of the present disclosure. The light detection system 200 includes a light detection device 1, a light source control unit 210, and a light source 220. The light detection device 1 is a device capable of detecting incident light. The light detection device 1 has a plurality of pixels P including light receiving elements, and is configured to receive incident light and generate a signal.

[0010] The light receiving element of the pixel P of the photodetector 1 is, for example, an APD (Avalanche Photo Diode) and is configured to receive light and output a current. The light receiving element (light receiving unit) of each pixel P can be configured to generate a signal in response to receiving photons. The photodetector 1 receives light that has passed through an optical system (not shown) including, for example, an optical lens, and generates a signal.

[0011] The photodetector 1 is configured using, for example, a semiconductor substrate (e.g., a silicon substrate) on which a plurality of pixels P are provided. As an example, the photodetector 1 has a region (pixel section 100) in which the plurality of pixels P are two-dimensionally arranged in a matrix. The pixel section 100 of the photodetector 1 is a pixel array in which the plurality of pixels P are arranged.

[0012] The light-receiving element of each pixel P may be configured as a single-photon avalanche diode (SPAD). The photodetector 1 captures incident light from a measurement object via an optical system including an optical lens. The light-receiving element receives light from the measurement object (e.g., infrared light, visible light, etc.) and generates charges through photoelectric conversion, thereby generating a photocurrent.

[0013] The light detection device 1 can be configured as a distance measurement sensor, an image sensor, etc. The light detection device 1 is a device capable of performing distance measurement, and is configured to be able to perform distance measurement using a time-of-flight (TOF) method, for example. The light detection device 1 is applied, for example, as a distance measurement sensor capable of measuring distance using the TOF method.

[0014] The light source 220 is configured to be able to generate light (optical signals). The light source 220 has, for example, one or more light-emitting elements and is configured to be able to irradiate the measurement object with light. The light-emitting element is, for example, an LD (Laser Diode), an LED (Light Emitting Diode), or the like, and can output light (infrared light, visible light, etc.) to the outside.

[0015] The light source 220 (light source unit) may generate laser light and emit the laser light to the outside. The light source 220 may be configured using a semiconductor laser element, for example, a vertical cavity surface emitting laser (VCSEL).

[0016] The light source control unit 210 is configured to be able to control the light source 220. The light source control unit 210 is a drive unit (drive circuit) and is configured to drive the light source 220. The light source control unit 210 is configured by a plurality of circuits including, for example, a digital-to-analog converter (DAC), an amplifier circuit, etc., and can control the operation of the light source 220. The light source control unit 210 is configured to be able to control, for example, the current and voltage to the light-emitting element of the light source 220.

[0017] The light source control unit 210 supplies the light source 220 with a current and a voltage for driving the light emitting elements of the light source 220, and can control light emission by the light source 220 (for example, light emission timing, light emission duration, etc.). The light source control unit 210 can also be said to be a light source driving unit configured to be able to drive (the light emitting elements of) the light source 220. Note that the light source 220 and a part or all of the light source control unit 210 may be configured integrally as a light source device (light source unit).

[0018] The light detection system 200 can irradiate a measurement object with light (e.g., laser light) using a light source 220 and receive the light reflected by the measurement object. In the light detection device 1, for example, reflected light (returned light) reflected by the measurement object is incident on the pixel unit 100, and an electrical signal corresponding to the reception of the reflected light is detected. The electrical signal generated by receiving the reflected light from the measurement object is a signal corresponding to the distance to the measurement object.

[0019] The light detection system 200 including the light detection device 1 can transmit and receive light and measure the distance to a measurement target. As an example, the light detection device 1 is configured to detect the distance to the object (subject) that is the measurement target for each pixel P and generate image data (distance image data) related to the distance to the object. The light detection device 1 can generate, for example, a depth map.

[0020] The light detection device 1 can also be applied as a sensor capable of detecting an event, for example, an event-driven sensor (also called an EVS (Event Vision Sensor), an EDS (Event Driven Sensor), or a DVS (Dynamic Vision Sensor)). The light detection device 1 and the light detection system 200 can be applied to various electronic devices.

[0021] 1 , the photodetector 1 includes a pixel unit 100, a pixel control unit 110, a signal processing unit 112, and a control unit 113. The photodetector 1 may also include a light source control unit 210. The light source 220 may be mounted on the photodetector 1 or may be provided outside the photodetector 1.

[0022] The pixel control unit 110 is configured to be able to control each pixel P of the pixel unit 100. The pixel control unit 110 is a control circuit and is configured by a plurality of circuits including, for example, a buffer, a shift register, an address decoder, etc. The pixel control unit 110 (control circuit) is configured by, for example, a pulse generation circuit. The pixel control unit 110 generates signals for controlling the pixels P and outputs them to each pixel P of the pixel unit 100. The pixel control unit 110 is controlled by the control unit 113 and controls the pixels P of the pixel unit 100.

[0023] The pixel control unit 110 generates signals for controlling the pixels P, such as signals for controlling a readout circuit of the pixels P, and supplies the signals to each pixel P. The pixel control unit 110 can control the reading out of pixel signals from each pixel P. The pixel control unit 110 can also be called a pixel driving unit (pixel driving circuit) configured to be able to drive each pixel P. The pixel control unit 110 and the control unit 113 can also be called a pixel control unit collectively.

[0024] The control unit 113 is configured to be able to control each unit of the photodetector 1. The control unit 113 receives an externally provided clock, data instructing an operation mode, and the like, and can also output data such as internal information of the photodetector 1. The control unit 113 is a control circuit, and has, for example, a timing generator configured to be able to generate various timing signals.

[0025] The control unit 113 controls the driving of the pixel control unit 110, the signal processing unit 112, etc. based on various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. The control unit 113 may include circuits such as a PLL (Phase Locked Loop) and a DAC (Digital to Analog Converter).

[0026] The control unit 113 is also configured to supply a signal for controlling the light source control unit 210 to the light source control unit 210 and control the operation of the light source control unit 210. The control unit 113 can be configured to be able to control the generation process of pixel signals by the pixels P of the pixel unit 100, the timing of light irradiation by the light source 220, etc.

[0027] The signal processing unit 112 is a signal processing circuit configured to be able to perform signal processing. The signal processing unit 112 is configured with circuits that perform various types of signal processing on signals output from each pixel P. The signal processing unit 112 is configured to include an arithmetic circuit, a memory circuit, etc., and can perform various types of signal processing such as noise reduction processing, TD (Time to Digital) conversion processing, and counting (accumulation) processing.

[0028] The signal processing unit 112 is configured to acquire a signal from each pixel P and generate and output a signal related to the distance to the measurement target. The signal processing unit 112 may, for example, perform various signal processing on the signal from each pixel to generate and output distance image data representing the distance to the measurement target. The signal processing unit 112 and the control unit 113 may be configured integrally. The signal processing unit 112 and the control unit 113 may include a processor and a memory.

[0029] The signal processing unit 112 includes, for example, an arithmetic unit 120 and a memory unit 130, as shown in the example of FIG. 1 . The memory unit 130 is a memory circuit and includes a plurality of memories (memory cells). The memory unit 130 is, for example, a frame memory, and stores (records) pixel signals of each pixel P on a frame-by-frame basis. The arithmetic unit 120 can control writing of data to the memory unit 130 and reading of data from the memory unit 130.

[0030] The calculation unit 120 is configured to acquire pixel signals from the pixels P and perform signal processing. The calculation unit 120 is configured, for example, to generate a signal (distance signal) related to the distance to the measurement object based on the pixel signals. In the light detection system 200, for example, the light source 220 repeatedly starts and stops emitting light, and the pixel P repeatedly detects reflected light (returned light). The calculation unit 120 can generate and output image data (distance image data) including a distance signal for each pixel P by analyzing the pixel signals sequentially output from each pixel P through multiple distance measurements.

[0031] The calculation unit 120 has, for example, a histogram generation unit 125 and is configured to be able to generate a histogram of pixel signals. The histogram generation unit 125 (histogram generation circuit) is configured, for example, to generate a histogram of count values ​​corresponding to the signal values ​​of the pixel signals, i.e., the round-trip time of light, for each pixel P.

[0032] The histogram generating unit 125 generates data relating to the correspondence between count values ​​corresponding to the round-trip time of light and the frequency (number) of count values ​​as histogram data, and can store the data in, for example, the memory unit 130. As an example, the histogram generating unit 125 classifies the count values ​​into predetermined intervals (ranges), i.e., into classes (BIN), and generates histogram data showing the distribution of count values ​​according to the distance to the measurement target.

[0033] The calculation unit 120 is configured to be able to calculate the distance to the measurement target based on a peak value (maximum value) in a histogram of pixel signal values. For example, the calculation unit 120 calculates (estimates) the difference between the start time of light irradiation and the time of arrival of reflected light, i.e., the round-trip time (time of flight) of light, based on the pixel signal value (count value) at which the frequency in the histogram of pixel signals indicates a peak value.

[0034] The calculation unit 120 is configured to calculate the distance between the light detection device 1 and the measurement object using, for example, the calculated round-trip time. The calculation unit 120 calculates the distance to the object for each pixel P and generates a distance signal related to the distance to the object. The distance to the measurement object is determined based on the time it takes for light irradiated from the light source 220 to be reflected by the measurement object and reach the light detection device 1. The signal processing unit 112 can generate distance image data including the distance signal for each pixel P using the calculation unit 120 and output it to the outside of the light detection device 1.

[0035] The pixel unit 100, pixel control unit 110, signal processing unit 112, control unit 113, etc. may be provided on a single substrate or may be provided separately on multiple substrates. The photodetector 1 may have, for example, a structure (a stacked structure) formed by stacking multiple semiconductor layers. Some or all of the pixel control unit 110, signal processing unit 112, and control unit 113 may be integrally configured.

[0036] 2 is a diagram illustrating an example of the configuration of a pixel of a photodetector according to an embodiment. A pixel P of the photodetector 1 includes a light-receiving element 10 and a readout circuit 20. The light-receiving element 10 is configured to receive light and generate a signal. The readout circuit 20 is provided for each light-receiving element 10, for example.

[0037] The light receiving element 10 is, for example, a single photon avalanche diode (SPAD) and has a multiplication region (multiplication section) capable of avalanche multiplication. The light receiving element 10 converts incident photons into electric charges and outputs a signal S1, which is an electrical signal corresponding to the incident photons. The light receiving element 10 can also be referred to as a photoelectric conversion element (photoelectric conversion section) configured to be able to photoelectrically convert light.

[0038] The readout circuit 20 is configured to be able to output a signal based on the current of the light receiving element 10. The readout circuit 20 is configured to include circuits for reading out a signal based on the photocurrent flowing through the light receiving element 10, such as a connection circuit 30, an output circuit 40, and a detection circuit 50.

[0039] The connection circuit 30 is provided between the light receiving element 10 and the potential line L1 and is configured to be able to recharge the light receiving element 10. The potential line L1 is a wiring to which a predetermined potential (voltage) is applied. In the example shown in FIG. 2 , the potential line L1 is a power supply line to which a power supply voltage VDD is applied. The connection circuit 30 is electrically connected to the power supply line to which the power supply voltage VDD is supplied, and can supply current and voltage to the light receiving element 10.

[0040] The connection circuit 30 is controlled by a signal CK1 and is configured to be able to recharge the light receiving element 10. The pixel control unit 110 outputs the signal CK1 that controls the connection circuit 30 and can control the recharge of the light receiving element 10. The pixel control unit 110 supplies the signal CK1, which is, for example, a pulse signal, to the connection circuit 30 and controls the timing of recharging the light receiving element 10.

[0041] The connection circuit 30 is configured using, for example, a switch, and is electrically connected in series between the light receiving element 10 and the potential line L1. As an example, the connection circuit 30 is configured to electrically connect or disconnect the potential line L1 and the light receiving element 10 based on a signal CK1 input from the pixel control unit 110. The connection circuit 30 can also be said to be a control circuit that controls recharging.

[0042] The connection circuit 30 is configured, for example, by a switch that electrically connects or disconnects the power supply line and the light receiving element 10. The connection circuit 30 is configured, for example, by using a P-type transistor (e.g., a PMOS transistor). One of the source and drain of the transistor in the connection circuit 30 is electrically connected, for example, to a power supply line to which a power supply voltage VDD is applied, and the other of the source and drain of the transistor is electrically connected to the light receiving element 10.

[0043] The pixel control unit 110 repeatedly outputs, for example, a pulse signal CK1 to the connection circuit 30, turning on the connection circuit 30 at predetermined intervals (time intervals). The pixel control unit 110 can perform periodic recharge (i.e., clocked recharge) of the light receiving element 10 by controlling the connection circuit 30.

[0044] The light receiving element 10 is electrically connected to, for example, a power supply line, an electrode, etc. that can supply a predetermined voltage. In the example shown in Fig. 2, one electrode of the light receiving element 10, that is, a cathode, is electrically connected to the connection circuit 30. The other electrode of the light receiving element 10, that is, an anode, is connected to the reference potential line.

[0045] The anode of the light-receiving element 10 is electrically connected to, for example, a wiring, electrode, or the like to which a relatively low power supply voltage is supplied. In the example shown in Fig. 2, a voltage VSP is applied to the anode of the light-receiving element 10 from a power supply unit (voltage source) capable of supplying a voltage (current) via a potential line L2 serving as a power supply line. The voltage VSP is, for example, a negative voltage.

[0046] A voltage that results in a potential difference greater than the breakdown voltage of the light receiving element 10 can be applied between the cathode and anode of the light receiving element 10 by the voltage supplied via the connection circuit 30 and the voltage VSP supplied by the potential line L2. That is, the potential difference across the light receiving element 10 can be set to a potential difference greater than the breakdown voltage.

[0047] When a reverse bias voltage greater than the breakdown voltage is applied to the light receiving element 10, the element 10 enters a state in which it can operate in Geiger mode. In Geiger mode, the light receiving element 10 may experience an avalanche multiplication phenomenon in response to incident photons, generating a pulsed current. In the pixel P, a signal S1 corresponding to the photocurrent flowing through the light receiving element 10 due to the incident photons is output to the output circuit 40.

[0048] After avalanche multiplication occurs and the potential difference between the electrodes of the light-receiving element 10 becomes smaller than the breakdown voltage, the connection circuit 30 turns on and recharges the light-receiving element 10, making it possible for the light-receiving element 10 to operate in Geiger mode again. The connection circuit 30 can recharge the light-receiving element 10 with electric charge and recharge the voltage of the light-receiving element 10.

[0049] The output circuit 40 is configured to generate a signal P1 based on the signal S1 generated by the light receiving element 10. The output circuit 40 can output the signal P1 as a voltage signal based on the current of the light receiving element 10. The output circuit 40 is configured, for example, by an inverter. The output circuit 40 has, for example, an input section 41 and an output section 42, and can output an inverted signal of the input signal.

[0050] An input section 41 of the output circuit 40 is electrically connected to, for example, the cathode of the light receiving element 10 and the connection circuit 30. In the example shown in Fig. 2, the input section 41 of the output circuit 40 is electrically connected to a node N1 that connects the light receiving element 10 and the connection circuit 30. An output section 42 of the output circuit 40 is electrically connected to the detection circuit 50. The output circuit 40 may be configured by an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, or the like.

[0051] The output circuit 40 receives a signal S1 from the light-receiving element 10. The signal level of the signal S1, i.e., the voltage (potential) of the signal S1, varies depending on the current flowing through the light-receiving element 10. For example, when the voltage of the signal S1 is higher than a threshold, the output circuit 40 outputs a low-level signal P1. When the voltage of the signal S1 is lower than the threshold, the output circuit 40 outputs a high-level signal P1. The output circuit 40 can output a signal P1 based on the voltage of the signal S1 to the detection circuit 50.

[0052] The detection circuit 50 is configured using, for example, a logic circuit such as a flip-flop. A signal CK2 is input to the detection circuit 50 from the pixel control unit 110. The detection circuit 50 is configured to output a signal P2 based on the current of the light receiving element 10 in response to the signal CK2. The detection circuit 50 is configured to sample and output a data signal in synchronization with the signal CK2, which is a pulse signal, for example.

[0053] 2, the detection circuit 50 receives a signal P1 from the output circuit 40. The detection circuit 50 samples the signal P1 as a data signal in response to a signal CK2 as a clock signal (or an enable signal), and outputs a signal P2 based on the signal P1. The detection circuit 50 can capture and hold the signal P1 in synchronization with the signal CK2, and output a signal P2 corresponding to the signal P1.

[0054] The pixel control unit 110 supplies signals CK1 and CK2 to the pixel P and controls the operation of the pixel P. The pixel control unit 110 is configured to be able to change the output timing of the signals CK1 and CK2, for example. The pixel control unit 110 repeatedly outputs the signal CK1, which serves as a pulse signal, to the connection circuit 30 and can recharge the light receiving element 10 at predetermined cycles (time intervals).

[0055] The pixel control unit 110 sets the generation and output timing of the signal P2 by the detection circuit 50, for example, by adjusting the output timing of the signal CK2, which is a pulse signal. The pixel control unit 110 is configured to be able to change the period from the transition timing of the signal CK1 to the transition timing of the signal CK2. The detection circuit 50 can output the signal P2 based on the signal P1 in the period from the transition timing of the signal CK1 (i.e., the recharge timing) to the transition timing of the signal CK2.

[0056] In the pixel P of the photodetector 1, for example, the period from the transition timing of the signal CK1 (for example, the falling edge of the signal CK1) to the transition timing of the signal CK2 (for example, the rising edge of the signal CK2) is the detection period in the pixel P, i.e., the period during which light is detected by the light receiving element 10. By controlling the signals CK1 and CK2, the detection period (i.e., BIN) can be changed.

[0057] 3 is a timing chart showing an example of operation of the light detection system according to the embodiment. The timing chart in FIG. 3 shows signals CK1, CK2, and BIN (detection period) with time on the horizontal axis. It also shows an example of light irradiated onto the measurement object and light reflected from the measurement object. In FIG. 3, when signal CK1 is set to a low level, the connection circuit 30 is turned on, and the light receiving element 10 is recharged.

[0058] 3 , in the photodetector 1, a pulse signal CK1 is periodically input from the pixel control unit 110 to the connection circuit 30, and periodic recharging is performed. The detection circuit 50 generates and outputs a signal P2 indicating the presence or absence of light reception during the detection period in response to the rising edge of the signal CK2. The pixel control unit 110 can change the length of the detection period (BIN width) by adjusting the rising timing of the signal CK2.

[0059] As an example, the pixel control unit 110 detects a short detection period t ｓｈｏｒｔｂｉｎ and a long detection period t ｌｏｎｇｂｉｎ The detection period t ｓｈｏｒｔｂｉｎis a detection period used for short-distance measurement, for example, and is suitable for measurement when the arrival timing of reflected light is early, that is, when the distance to the measurement target is relatively short. ｌｏｎｇｂｉｎ is a detection period used for measuring, for example, medium to long distances, and is suitable for measurements when the arrival timing of reflected light is late, that is, when the distance to the measurement target is relatively long.

[0060] The pixel control unit 110 adjusts the rising timing of the signal CK2, for example, during the detection period t ｓｈｏｒｔｂｉｎ and the detection period t ｓｈｏｒｔｂｉｎ A detection period t ｌｏｎｇｂｉｎ In the example shown in FIG. ｓｈｏｒｔｂｉｎ Thereafter, multiple detection periods t ｌｏｎｇｂｉｎ As shown by the dashed line in FIG. 3, the pixel control unit 110 sets the detection period t ｓｈｏｒｔｂｉｎ The length can be adjusted as needed.

[0061] The pixel P of the photodetector 1 detects, for example, a detection period t ｓｈｏｒｔｂｉｎ signal P2a, which is a signal P2 indicating whether or not reflected light is received during the detection period t ｌｏｎｇｂｉｎ The signal processing unit 112 sequentially outputs a signal P2a and a signal P2b that are signals P2 indicating whether or not reflected light has been received at each pixel P. The signal processing unit 112 acquires the signals P2a and P2b output from each pixel P, and can calculate the distance to the measurement target.

[0062] The signal processing unit 112 determines whether the distance to the measurement target is short or medium to long, for example, using a signal (e.g., signal P2a, signal P2b) output for each detection period from each pixel P. Furthermore, the signal processing unit 112 can calculate the arrival timing of the reflected light by calculating the center of gravity or the like, depending on the result of the determination, and thereby determine the distance to the measurement target.

[0063] 4 is a diagram illustrating another example of the configuration of a pixel of a photodetector according to an embodiment. As shown in the example of FIG. 4, the readout circuit 20 of the pixel P may include an AND circuit 55 and a counter 60. The AND circuit 55 receives a signal P2 from the detection circuit 50 and a signal CK2 from the pixel control unit 110.

[0064] The counter 60 is configured to be able to count a signal based on the current of the light receiving element 10. In the example shown in Fig. 4, the counter 60 receives the signal Pout, which is the output signal of the AND circuit 55. Based on the signal Pout, the counter 60 counts the signal P2 during the period when the signal CK2 is at a high level. The counter 60 counts the number of pulses of the signal Pout, which is based on the current of the light receiving element 10, and can output a signal indicating the count value.

[0065] 5 is a timing chart showing an example of the operation of the photodetection system according to the embodiment. In FIG. 5, signals S1, CK1, P1, CK2, P2, and Pout are shown on the same time axis, along with the count value of the counter 60. In FIG. 5, the timing of incidence of photons (Photons) on the light-receiving element 10 is schematically shown by dashed arrows.

[0066] 5, in the photodetector 1, the signal CK1 is periodically switched from high to low by the pixel control unit 110 to set a recharge period. The period from the falling edge of the signal CK1 to the rising edge of the signal CK2 is the detection period.

[0067] The detection circuit 50 outputs a signal P2 corresponding to the reception of photons by the light receiving element 10 as a signal Pout to the counter 60 via the AND circuit 55. The counter 60 may, for example, count the number of pulses of the signal Pout as a count value and output a digital signal indicating the count value to the signal processing unit 112 (see FIG. 1 ).

[0068] As described above, the pixel control unit 110 of the photodetector 1 is configured to be able to control the signal CK1 supplied to the connection circuit 30 and to execute periodic recharging of the light receiving element 10. The pixel control unit 110 is also configured to be able to control the signal CK2 supplied to the detection circuit 50 and to change the detection period. In this embodiment, it is not necessary to take dead time into consideration, and it is possible to accurately generate a histogram showing the count value for each detection period (BIN).

[0069] When performing short-distance ranging, the pixel control unit 110 can appropriately adjust the ranging range and improve the accuracy of ranging by, for example, setting a short BIN width (the length of the detection period). Furthermore, when performing medium- to long-distance ranging, the pixel control unit 110 can expand the ranging range by, for example, setting a long BIN width. This makes it possible to perform accurate short-distance ranging while ensuring the long-distance ranging range.

[0070] [Actions and Effects] The photodetection device (photodetection device 1) according to this embodiment includes a light-receiving element (light-receiving element 10) that can receive light and output a current, a control circuit (pixel control unit 110) that can output a first signal and a second signal (e.g., signals CK1 and CK2), a connection circuit (connection circuit 30) that is provided between the light-receiving element and a first potential line (potential line L1) and is controlled by the first signal, and a detection circuit (detection circuit 50) that can output a third signal (signal P2) that is based on the current of the light-receiving element in response to the second signal.

[0071] The photodetector 1 according to this embodiment includes a pixel control unit 110 capable of outputting signals CK1 and CK2, a connection circuit 30 controlled by signal CK1, and a detection circuit 50 capable of outputting signal P2 in response to signal CK2. In this embodiment, it is possible to control the recharge and detection periods, and it is possible to realize a photodetector with good performance.

[0072] Next, a modified example of the present disclosure will be described. In the following, the same components as those in the above embodiment will be denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0073] 2. Modifications (2-1. Modification 1) FIG. 6 is a diagram illustrating an example configuration of a pixel of a photodetector according to modification 1 of the present disclosure. As shown in FIG. 6, a pixel P of the photodetector 1 includes a transistor Tr1. The photodetector 1 may also include a voltage generator 140. The transistor Tr1 is a transistor for limiting voltage and is referred to as a clamp transistor. The transistor Tr1 may be configured as part of the readout circuit 20.

[0074] The voltage generation unit 140 is a voltage generation circuit capable of generating a voltage, and is configured to output a predetermined voltage (potential) to the transistor Tr1. The voltage generation unit 140 is provided, for example, in common with a plurality of pixels P. The voltage generation unit 140 may be provided separately from the pixel control unit 110, or may be provided within the pixel control unit 110.

[0075] The voltage generating unit 140 is configured to generate a bias voltage and supply the generated bias voltage to the gate of the transistor Tr1. The voltage generating unit 140 is configured, for example, by a voltage step-up circuit, a voltage step-down circuit, etc. The voltage generating unit 140 can also be called a bias generating circuit (bias generating unit) capable of generating a bias voltage.

[0076] The transistor Tr1 is electrically connected between the light receiving element 10 and the connection circuit 30. The transistor Tr1 is configured as a PMOS transistor, for example, and is electrically connected in series between the light receiving element 10 and a node N1 connected to the connection circuit 30. The transistor Tr1 has, for example, a thick gate insulating film and is configured as a high-voltage transistor.

[0077] One of the source and drain of the transistor Tr1, for example, the source of the transistor Tr1, is electrically connected to the connection circuit 30 and the output circuit 40. The other of the source and drain of the transistor Tr1, for example, the drain of the transistor Tr1, is electrically connected to the light receiving element 10. A bias voltage, for example, a constant voltage, is applied to the gate of the transistor Tr1 by the voltage generation unit 140.

[0078] In this modification, the transistor Tr1 is provided between the light receiving element 10 and the connection circuit 30, so that the transistor connected to the source side of the transistor Tr1 can be configured using a low-voltage transistor. For example, the transistors that make up the connection circuit 30, the transistors that make up the output circuit 40, the transistors that make up the detection circuit 50, etc. can each be configured using transistors with thin gate insulating films.

[0079] The gate capacitance of the transistor to which the signal CK1 is input and the gate capacitance of the transistor to which the signal CK2 is input can be reduced, and the amplitude (voltage amplitude) of the signals CK1 and CK2 can be reduced, which enables the speed of the signals CK1 and CK2 to be increased, thereby enabling high-speed operation.

[0080] 7 is a diagram illustrating another example of the configuration of a pixel of the photodetector according to Modification 1. As shown in FIG. 7 , the photodetector 1 may include a supply unit 145. The supply unit 145 is configured to be able to supply a predetermined voltage. As an example, the supply unit 145 is electrically connected to the drain of the transistor Tr1 and the light receiving element 10.

[0081] 7, the supply unit 145 is electrically connected to a potential line L3 (power supply line) to which a voltage VRL is applied, and is configured to be able to supply the voltage VRL to the drain side of the transistor Tr1, i.e., the cathode side of the light receiving element 10. The voltage VRL has a voltage value between the power supply voltage VDD and the voltage VSP, for example.

[0082] For example, when the cathode voltage of the light-receiving element 10 drops in response to the incidence of photons on the light-receiving element 10, the supply unit 145 supplies the voltage VRL to the cathode of the light-receiving element 10. In this case, the potential difference across the light-receiving element 10 becomes smaller than the breakdown voltage, and the light-receiving element 10 can be brought into a state in which avalanche multiplication does not occur.

[0083] By applying the voltage VRL to the light receiving element 10, it is possible to prevent avalanche multiplication from occurring again during the detection period, thereby reducing power consumption, which makes it possible to achieve more power savings than when a current flows from the potential line L1, to which the power supply voltage VDD is applied, to the anode side of the light receiving element 10, to which the voltage VSP is applied.

[0084] 8 and 9 are diagrams for explaining a configuration example of a photodetector according to Modification 2. The pixel P of the photodetector 1 may have the configuration shown in FIG. 8. As shown in FIG. 9, the photodetector 1 has a processing unit 70. The readout circuit 20 of the pixel P is configured to output a signal Pout to the processing unit 70.

[0085] The processing unit 70 (processing circuit) is configured to include, for example, a plurality of counters 60 (counters 60a to 60n in FIG. 9) and a selection unit 65. The processing unit 70 is provided, for example, for each pixel P or for each plurality of pixels P. As an example, the processing unit 70 has a plurality of counters 60 corresponding to the set number of BINs (detection periods).

[0086] The selection unit 65 is configured to output the signal Pout from the pixel P to a selected counter 60 from among the plurality of counters 60. The selection unit 65 can be configured to switch the output destination of the signal Pout. The selection unit 65 is a selection circuit and is configured to include, for example, a shift register. As an example, the selection unit 65 is configured using a plurality of flip-flops and a plurality of AND circuits, as shown in the example of FIG.

[0087] The selection unit 65 outputs a signal Pout to a counter 60 selected in accordance with, for example, a signal BIN_CLK serving as a clock signal. The signal Pout is input to the counter 60 selected by the selection unit 65, and a counting operation is performed in accordance with the signal Pout. Note that the readout circuit 20 and the processing unit 70 of the pixel P may be partially or entirely configured as an integrated unit. For example, the readout circuit 20 may include the processing unit 70.

[0088] 10A is a diagram illustrating another example configuration of a photodetector according to Modification 2. The photodetector 1 may have an output circuit 66. The output circuit 66 is provided for, for example, a plurality of pixels P, and is configured to be able to output a signal Poutx based on a plurality of signals Pout. The output circuit 66 is configured, for example, by an OR circuit. The output circuit 66 may be configured to output a signal Poutx obtained by adding together a plurality of signals Pout.

[0089] 10A , the output circuit 66 is provided for four pixels P and is electrically connected to the four pixels P. The signal Pout of each of the four pixels P is input to the output circuit 66. The output circuit 66 can output a signal Poutx, which is a signal obtained by bundling the four signals Pout, to the processing unit 70.

[0090] In the processing unit 70, the signal Poutx is input to the counter 60 selected by the selection unit 65, and the counter 60 performs a counting operation in response to the signal Poutx. For example, when any of the plurality of pixels P (four pixels P in FIG. 10A ) detects light, the counter 60 counts up, thereby making it possible to improve the probability of detecting reflected light.

[0091] 10B, the output circuit 66 may be provided in a processing circuit (processing circuit) 70. In the example shown in Fig. 10B, the processing circuit 70 includes the output circuit 66, a selection unit 65, a counter 60, etc.

[0092] (2-3. Modification 3) FIG. 11 is a diagram illustrating an example of the configuration of a photodetector according to Modification 3. The processing unit 70 may be configured to be able to count the number of pixels that receive light based on the signals Pout from the plurality of pixels P. The processing unit 70 may be configured to perform two or more counts in response to a single pulse signal of the signal CLK, for example. As an example, the processing unit 70 may perform multi-value counts (for example, "0" to "2") in response to a single pulse of the signal CLK.

[0093] The processing unit 70 includes an output circuit 66, a selection unit 65, and a plurality of counters 60. The output circuit 66 includes, for example, a shift register, a selector, an AND circuit, an EXOR circuit, etc. The output circuit 66 includes, for example, a shift register 67 a and a shift register 67 b.

[0094] The shift register 67a and the shift register 67b are each configured to include flip-flops in a number corresponding to half the predetermined number of pixels P. The signal Pout of each of the plurality of pixels P, including pixel Pa, is input to the shift register 67a, and the signal Pout of each of the plurality of pixels P, including pixel Pb, is input to the shift register 67b.

[0095] The shift register 67a stores the signals Pout input from the pixels P connected to the shift register 67a in response to a signal CLK, which is a clock signal, for example. The shift register 67a also sequentially outputs the stored signals Pout from the pixels P as signals SR1 in response to the signal CLK.

[0096] The shift register 67b stores the signals Pout input from the pixels P connected to the shift register 67b in response to a signal CLK, which is a clock signal, for example. The shift register 67b also sequentially outputs the stored signals Pout from the pixels P as signals SR2 in response to the signal CLK.

[0097] The output circuit 66 is configured to generate signals c and s based on the signal SR1 from the shift register 67a and the signal SR2 from the shift register 67b, and output the signals c and s to the selection unit 65. For example, as in the example shown in Fig. 11, the output circuit 66 can output the signals c and s indicating the sum of the signals SR1 and SR2 by an AND circuit and an EXOR circuit.

[0098] The selection unit 65 is configured to output the signals c and s input from the output circuit 66 as signals c_bin and s_bin to a counter 60 selected from the plurality of counters 60. The selection unit 65 (selection circuit) outputs the signals c_bin and s_bin to a counter 60 selected in accordance with, for example, a signal BIN_CLK that serves as a clock signal.

[0099] In the processing unit 70, the signals c_bin and s_bin are input to the counter 60 selected by the selection unit 65, and a count operation is performed in accordance with the signals c_bin and s_bin. For example, when the signal c_bin is at a low level (i.e., the value of the signal c_bin is "0") and the signal s_bin is at a high level (i.e., the value of the signal s_bin is "1"), the signal CLK is input as the signal s_cnt to a flip-flop that holds the value of the LSB, thereby counting up by "+1".

[0100] Furthermore, when signal c_bin is at a high level (i.e., the value of signal c_bin is "1") and signal s_bin is at a low level (the value of signal s_bin is "0"), signal CLK is input as signal c_cnt to a flip-flop that holds the value of (LSB+1), thereby counting up by "+2".

[0101] In this way, the photodetector 1 according to this modification can add up the signals of a plurality of pixels P and count up by the added value. For example, the photodetector 1 can count "0," "1," or "2" in response to a single pulse signal from the signal CLK. The photodetector 1 can count (count) the number of responsive pixels, i.e., the number of pixels that receive light, thereby improving the S / N ratio.

[0102] The configuration of the photodetector 1 is not limited to the above example and can be modified as appropriate. For example, the photodetector 1 may be configured to add signals from three or more pixels and count each added value. For example, the processing unit 70 may be configured to count up using a signal that combines signals from four or more pixels.

[0103] 12 is a diagram illustrating another example configuration of the photodetector according to Modification 3. As an example, the output circuit 66 has shift registers 67a, 67b, 67c, and 67d. Each of the shift registers 67a to 67d is configured to include flip-flops the number of which corresponds to one-fourth of the predetermined number of pixels P. The processing unit 70 may have a bit selection unit 68 (bit selection circuit).

[0104] The shift register 67a, for example, receives the signal Pout input from each pixel P connected to the shift register 67a and sequentially outputs the signal Pout of each pixel P as a signal SR1. The shift register 67b receives the signal Pout input from each pixel P connected to the shift register 67b and sequentially outputs the signal Pout of each pixel P as a signal SR2.

[0105] The shift register 67c also receives the signal Pout input from each pixel P connected to the shift register 67c, and sequentially outputs the signal Pout of each pixel P as a signal SR3. The shift register 67d also receives the signal Pout input from each pixel P connected to the shift register 67d, and sequentially outputs the signal Pout of each pixel P as a signal SR4.

[0106] The output circuit 66 is configured to generate signals c3, c2, and c1 based on the signals SR1 to SR4 from the shift registers 67a to 67d, and output the signals c3, c2, and c1 to the selection unit 65. The output circuit 66 is configured to include, for example, a four-input adder, and can output signals c3, c2, and c1 that indicate the sum of the signals SR1 to SR4.

[0107] The selection unit 65 is configured to be able to output the signals c3, c2, and c1 input from the output circuit 66 as signals c3_bin, c2_bin, and c1_bin to a counter 60 selected from the plurality of counters 60. The selection unit 65 outputs signals c3_bin to c1_bin to the counter 60 selected in accordance with the signal BIN_CLK, for example.

[0108] In the processing unit 70, the signals c3_bin to c1_bin are input to the counter 60 selected by the selection unit 65, and a counting operation is performed in accordance with the signals c3_bin to c1_bin. The bit selection unit 68 controls the signals sel0, sel1a, sel1b, and sel2 supplied to the counter 60 based on the signal values ​​of the signals c3_bin to c1_bin.

[0109] For example, when signal c3_bin is low, signal c2_bin is low, and signal c1_bin is high, the bit selection unit 68 sets signal sel0 to high and signal sel1b to high. The bit selection unit 68 also sets signals sel1a and sel2 to low. In this case, signal CLK is input as signal clk0 to the flip-flop that holds the value of the LSB, thereby counting up by "+1."

[0110] When signal c3_bin is low, signal c2_bin is high, and signal c1_bin is low, the bit selection unit 68 sets signals sel1a and sel1b to high. The bit selection unit 68 also sets signals sel0 and sel2 to low. In this case, signal CLK is input as signal clk1 to a flip-flop that holds the value of (LSB+1), resulting in a count-up of "+2."

[0111] When the signals c3_bin are low, c2_bin are high, and c1_bin are high, and the signal s_lsb, which is the LSB data, is low, the bit selection unit 68 sets the signals sel0, sela, and sel1b to high levels and the signal sel2 to low level.

[0112] In this case, the signal CLK is input as signal clk0 to a flip-flop that holds the value of the LSB. Also, the signal CLK is input as signal clk1 to a flip-flop that holds the value of (LSB+1). The value of the LSB is inverted (+1 in this case), and the value of (LSB+1) is incremented by "+1," causing the counter 60 to count up by "+3."

[0113] When the signal c3_bin is low, the signal c2_bin is high, the signal c1_bin is high, and the signal s_lsb is high, the bit selection unit 68 sets the signals sel0 and sel2 to high and the signals sel1a and sel1b to low.

[0114] In this case, the signal CLK is input as signal clk0 to a flip-flop that holds the value of the LSB. The signal CLK is also input as signal clk2 to a flip-flop that holds the value of (LSB+2). The value of the LSB is inverted (-1 in this case) and the value of (LSB+2) is incremented by +1, causing the counter 60 to count up by +3.

[0115] Furthermore, when the signal c3_bin is at a high level, the signal c2_bin is at a low level, and the signal c1_bin is at a low level, the bit selection unit 68 sets the signal sel2 to a high level and the signals sel0 and sel1a to a low level. In this case, the signal CLK is input as the signal clk2 to the flip-flop that holds the value of (LSB+2), thereby counting up by "+4".

[0116] (2-4. Modification 4) FIG. 13 is a diagram illustrating an example of the configuration of a photodetector according to modification 4. The photodetector 1 has a plurality of operation modes. For example, the photodetector 1 has a first mode and a second mode as operation modes. In the first mode, the photodetector 1 performs processing to count the output signals of each pixel P. In the second mode, the photodetector 1 can perform processing to add up the output signals of a plurality of pixels P and count the added signals.

[0117] 13 , the photodetector 1 may include a switching circuit 69 in addition to the output circuit 66 and the selection unit 65. The switching circuit 69 may be configured to be able to switch signal paths, for example.

[0118] The selection unit 65 outputs the signal Poutx to, for example, a selector in the switching circuit 69 that is connected to the counter 60 selected by the selection unit 65. As described above, the signal Poutx is a signal based on the signals Pout of a plurality of pixels, and is a signal obtained by adding, for example, four signals Pout.

[0119] The selector of the switching circuit 69 is configured to output, for example, the signal Pout input from the pixel P or the signal Pout input from the selection unit 65 to the counter 60. In the example shown in Fig. 13 , the switching circuit 69 can output the signal Pout or the signal Poutx to the counter 60 based on the signal s_mode.

[0120] In the first mode, for example, when the signal s_mode goes high, the switching circuit 69 outputs the signal Pout of each pixel P to a separate counter 60. The separate counters 60 count the signal Pout of each of the multiple pixels P (four pixels P in FIG. 13 ). In the photodetector 1, one pixel P is associated with one counter 60, and the output signals of all the pixels P can be counted.

[0121] In the second mode, for example, when the signal s_mode becomes low level, the switching circuit 69 outputs the signal Poutx to the counter 60 selected by the selection unit 65. In the photodetector 1, for example, counting can be performed by the counter 60 selected for each detection period (BIN), and the count value for each detection period can be obtained.

[0122] (2-5. Modification 5) FIG. 14 is a diagram illustrating a configuration example of a photodetector according to Modification 5. As shown in the example of FIG. 14, the photodetector 1 has a switch SW1 and a switch SW2. The switch SW1 and the switch SW2 are provided for each pixel P (or each counter 60). The switches SW1 and SW2 are electrically connected between the counter 60 and a signal line Ls connected to a signal processing unit 112 including a calculation unit 120 and a memory unit 130, for example.

[0123] Each of the switches SW1 and SW2 is configured using, for example, a transistor. The switches SW1 and SW2 are each controlled to be turned on and off by a signal input from the pixel control unit 110. The pixel control unit 110 can perform processing to read out a signal indicating the count value held in the counter 60 to a signal line Ls.

[0124] The pixel control unit 110 controls, for example, the switch SW1 to cause the counter 60 to output a signal indicating the value of the MSB (Most Significant Bit) to the calculation unit 120. Furthermore, for example, the pixel control unit 110 controls the switch SW2 to cause the counter 60 to output a signal indicating the values ​​of the remaining bits other than the MSB to the calculation unit 120.

[0125] Fig. 15 is a timing chart showing an example of the operation of the photodetector according to Modification 5. Fig. 15 schematically shows, on the same time axis, the count value by the counter 60, the MSB of the count value, the MSB to be read (Read MSB), all bit data to be read, and the MSB value stored in the frame memory. In Fig. 15, the timing of reading the MSB from the counter 60 is indicated by a dotted line.

[0126] 15 , the pixel control unit 110 may read only the value of the MSB from the counter 60 during the exposure period and store it in the memory unit 130 (frame memory), and may read the value of all bits of the counter 60, "Ndata," after the exposure period. The counter 60 is configured to not be reset even when the count value reaches "Nmax (maximum value)," for example, but to start counting again from "0." The memory unit 130 stores, as an example, the number of times the count value of the counter 60 has reached Nmax.

[0127] The pixel control unit 110 can calculate the total count value based on, for example, the number of times n (n=3 in the example shown in FIG. 15 ) that the count value reaches Nmax, the value of all bits “Ndata,” and the following equation (1): Total count value=Ndata+n×Nmax (1)

[0128] By configuring the photodetector 1 as described above, it is possible to reduce the number of bits required for the counter 60, and to reduce the area of ​​the counter 60. It is also possible to reduce power consumption. In this modification, it is possible to reduce power consumption and circuit area.

[0129] 16A to 16D are diagrams illustrating an example of the arrangement of pixels in a photodetector according to Modification 6. The plurality of pixels P provided in the pixel section 100 of the photodetector 1 include, for example, pixels that receive infrared light (IR pixels) and pixels that receive visible light. The IR pixels have light receiving elements 10 and are configured to receive infrared light and perform photoelectric conversion.

[0130] Examples of pixels that receive visible light include pixels (R pixels) provided with filters that transmit red (R) light, pixels (G pixels) provided with filters that transmit green (G) light, and pixels (B pixels) provided with filters that transmit blue (B) light. Each of the R, G, and B pixels has, for example, a light receiving element 10 and is configured to photoelectrically convert incident light.

[0131] The filters provided in the pixels P are not limited to primary color (RGB) filters, but may be complementary color filters such as Cy (cyan), Mg (magenta), and Ye (yellow). The IR pixels may have filters that transmit infrared light. Furthermore, some or all of the pixels may not have filters, as needed.

[0132] In the pixel unit 100, for example, as shown in the examples of Figures 16A to 16C, a plurality of IR pixels, a plurality of R pixels, a plurality of G pixels, and a plurality of B pixels are arranged repeatedly. As an example, the IR pixels may be arranged by replacing some of the RGB pixels arranged in a Bayer array. Note that the arrangement of the pixels P is not limited to the example shown in the figures and can be set arbitrarily.

[0133] In the photodetector 1, for example, the IR pixel is configured to be able to generate a pixel signal of an IR component and can be used for distance measurement using the TOF method, and the R pixel, G pixel, and B pixel are configured to be able to generate a pixel signal of an R component, a pixel signal of a G component, and a pixel signal of a B component, respectively.

[0134] The provision of IR pixels and RGB pixels in the photodetector 1 enables simultaneous acquisition of visible light gradation values ​​and distance measurement. The photodetector 1 can obtain an image (e.g., an RGB image) showing the subject image and a distance image using the pixel signals of each pixel.

[0135] 16D , the photodetector 1 may have IRG pixels disposed across the entire pixel section 100. By disposing IR pixels across the entire pixel section 100, it is possible to improve the spatial resolution of the distance measurement sensor.

[0136] (2-7. Modification 7) FIGS. 17, 18A, and 18B are diagrams for explaining a configuration example of a photodetector according to Modification 7. The photodetector 1 may have a layered structure in which a plurality of semiconductor layers are stacked. In the example shown in FIGS. 17, 18A, and 18B, the photodetector 1 has a first layer 101 and a second layer 102. The photodetector 1 has a configuration in which the first layer 101 and the second layer 102 are stacked. The first layer 101 and the second layer 102 are stacked on top of each other.

[0137] The plurality of substrates (e.g., a first layer 101 and a second layer 102) of the photodetector 1 are configured by semiconductor substrates (e.g., a silicon substrate, an SOI substrate, etc.). The first layer 101 (first hierarchical layer) is provided with, for example, the light receiving elements 10 of each pixel P of the pixel section 100. In the first layer 101, the plurality of light receiving elements 10 can be arranged in the horizontal direction (row direction) and the vertical direction (column direction), as in the example shown in FIG. 18A or 18B .

[0138] The second layer 102 is provided with, for example, a readout circuit 20 for each pixel P, a pixel control unit 110, etc. The readout circuit 20 is provided for the region of one pixel P, as in the example shown in Fig. 18A or 18B . The pixel control unit 110 is arranged in a peripheral region of the plurality of readout circuits 20 arranged in a matrix, for example.

[0139] By arranging the light receiving element 10 of each pixel P on the first layer 101 and the readout circuit 20 and the like on the second layer 102, it is possible to ensure the area of ​​the light receiving element 10 and enable high integration. The pixel control unit 110 may be provided along the long side of the pixel unit 100 (pixel array), for example, as in the example shown in FIG.

[0140] By arranging the pixel control unit 110 on the long side of the pixel unit 100, it is possible to reduce the wiring impedance (load capacitance, load resistance, etc.) of the wiring that transmits the signal CK1, the wiring that transmits the signal CK2, etc. This makes it possible to set the detection period of each pixel P with high precision.

[0141] 18B , the pixel control unit 110 may be provided along a short side of the pixel unit 100. The signal processing unit 112, the control unit 113, and the like described above may be provided in the second layer 102, or may be provided in a layer separate from the second layer 102.

[0142] 19A to 19D are diagrams illustrating another example of the configuration of a photodetector according to Modification 7. The photodetector 1 may have a first layer 101, a second layer 102, and a third layer 103. The second layer 102 is provided, for example, between the first layer 101 and the third layer 103. The photodetector 1 may have a structure in which the first layer 101, the second layer 102, and the third layer 103 are stacked.

[0143] 19A , the second layer 102 is provided with a transistor Tr1 (clamp transistor) and a voltage generation unit 140. The third layer 103 is provided with a readout circuit 20 for each pixel P and a pixel control unit 110. By disposing the transistor Tr1, which is a high-voltage transistor, on the second layer 102 and disposing the transistors of the readout circuit 20, which are low-voltage transistors, on the third layer 103, it is possible to improve area efficiency.

[0144] 19B , the voltage generating unit 140 may be disposed on the third layer 103. The supplying unit 145 described above may be configured using a high-voltage transistor, similar to the transistor Tr1. Therefore, the supplying unit 145 including the high-voltage transistor may be disposed on the second layer 102, similar to the transistor Tr1. In this case, it is possible to improve area efficiency.

[0145] The readout circuit 20 may be provided separately in the second layer 102 and the third layer 103, as in the examples shown in Figure 19C or 19D. For example, as shown in Figure 19C, the connection circuit 30 and the output circuit 40 may be arranged on the second layer 102. Furthermore, for example, as shown in Figure 19D, the connection circuit 30, the output circuit 40, the detection circuit 50, and the AND circuit 55 may be arranged on the second layer 102.

[0146] 19C or 19D, the capacitance between the second layer 102 and the third layer 103, for example the capacitance added to the node N1, can be reduced, and power consumption can be reduced, compared to when the connection circuit 30 and the output circuit 40 are arranged on the third layer 103. This makes it possible to suppress the generation of unnecessary parasitic capacitance and prevent timing adjustment from becoming difficult.

[0147] (2-8. Modification 8) Fig. 20 is a diagram illustrating an example of the configuration of a pixel of a photodetector according to Modification 8. In the example shown in Fig. 20, the cathode of the light receiving element 10 is electrically connected to the potential line L1. Furthermore, the anode of the light receiving element 10 is electrically connected to the connection circuit 30 and the output circuit 40.

[0148] The connection circuit 30 is configured, for example, by an NMOS transistor, and is electrically connected in series between the light receiving element 10 and the potential line L2. The output circuit 40 can be configured, for example, by a buffer. In this modified example, the same effects as those of the above-described embodiment can be obtained.

[0149] 3. Usage Examples The above-described light detection device 1 and light detection system 200 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as televisions, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0150] 4. Application Examples (Application Examples to Mobile Bodies) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0151] FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0152] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 21 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0153] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0154] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0155] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0156] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0157] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0159] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0160] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0161] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 21, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0162] FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.

[0163] In FIG. 22 , a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0164] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0165] 22 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0166] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0167] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0168] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0169] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0170] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, for example, the light detection device 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, a high-resolution captured image can be obtained, and high-precision control using the captured image can be performed in the mobile object control system.

[0171] Although the present disclosure has been described above by giving embodiments, modifications, use examples, and application examples, the present technology is not limited to the above-described embodiments, etc., and various modifications are possible. For example, although the modifications described above have been described as modifications of the above-described embodiments, the configurations of the modifications can be combined as appropriate.

[0172] According to an embodiment of the present disclosure, a photodetector includes a light-receiving element capable of receiving light and outputting a current, a control circuit capable of outputting a first signal and a second signal, a connection circuit provided between the light-receiving element and a first potential line and controlled by the first signal, and a detection circuit capable of outputting a third signal based on the current of the light-receiving element in response to the second signal, thereby enabling a photodetector with good performance to be realized.

[0173] Note that the effects described in this specification are merely examples and are not limited to those described above, and other effects may be present. The present disclosure may also have the following configurations. (1) A photodetector comprising: a light-receiving element capable of receiving light and outputting a current; a control circuit capable of outputting a first signal and a second signal; a connection circuit provided between the light-receiving element and a first potential line and controlled by the first signal; and a detection circuit capable of outputting a third signal based on the current of the light-receiving element in response to the second signal. (2) The photodetector described in (1) above, wherein the control circuit outputs the first signal that controls the connection circuit and is capable of controlling recharging of the light-receiving element. (3) The photodetector described in (1) or (2) above, wherein the control circuit is capable of outputting the first signal as a pulse signal. (4) The photodetector described in any one of (1) to (3) above, wherein the control circuit is capable of outputting the second signal as a pulse signal. (5) The photodetector described in any one of (1) to (4) above, wherein the control circuit is capable of changing the output timing of the second signal. (6) The photodetector according to any one of (1) to (5), wherein the control circuit is capable of changing a period from a transition timing of the first signal to a transition timing of the second signal. (7) The photodetector according to any one of (1) to (6), wherein the control circuit is capable of repeatedly outputting the first signal, which is a pulse signal, and the control circuit is capable of repeatedly outputting the second signal, which is a pulse signal. (8) The photodetector according to any one of (1) to (7), wherein the control circuit is capable of executing control to change a period from a transition timing of the first signal to a transition timing of the second signal. (9) The photodetector according to any one of (1) to (8), wherein the detection circuit is capable of outputting the third signal in synchronization with the second signal. (10) The photodetector according to any one of (1) to (9), wherein the first potential line is a power supply line, and the connection circuit has a switch electrically connected in series between the light receiving element and the first potential line.(11) The photodetector according to any one of (1) to (10), wherein the detection circuit has a flip-flop. (12) The photodetector according to any one of (1) to (11), further comprising an output circuit capable of outputting a voltage signal based on a current of the light-receiving element to the detection circuit. (13) The photodetector according to (12), wherein the detection circuit is capable of outputting the third signal based on the voltage signal in a period from a transition timing of the first signal to a transition timing of the second signal. (14) The photodetector according to (12) or (13), wherein the output circuit has an inverter. (15) The photodetector according to any one of (1) to (14), further comprising a counter capable of counting the third signal. (16) The photodetector according to any one of (1) to (15), further comprising a processing circuit capable of counting the number of pixels that have received light based on the third signal for each pixel. (17) The photodetector according to (16), wherein the processing circuit is capable of performing two or more counts in response to a pulse signal. (18) The photodetector according to any one of (1) to (17), further comprising a transistor electrically connected between the light-receiving element and the connection circuit and having a gate to which a predetermined voltage is applied. (19) The photodetector according to any one of (1) to (18), further comprising: a first layer having a plurality of the light-receiving elements; and a second layer having at least one of the control circuit, the connection circuit, and the detection circuit, and stacked on the first layer. (20) The photodetector according to any one of (1) to (19), further comprising: a first pixel that photoelectrically converts infrared light; and a second pixel that photoelectrically converts visible light. (21) The photodetector according to any one of (1) to (20), wherein the light-receiving element is an avalanche photodiode.(22) An optical detection system comprising: a light source capable of irradiating light onto an object; and an optical detection device that receives light from the object, wherein the optical detection device has: a light receiving element that can receive light and output a current; a control circuit that can output a first signal and a second signal; a connection circuit that is provided between the light receiving element and a first potential line and controlled by the first signal; and a detection circuit that can output a third signal based on the current of the light receiving element in response to the second signal.

[0174] This application claims priority based on Japanese Patent Application No. 2024-023460, filed on February 20, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0175] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A photodetector comprising: a light-receiving element capable of receiving light and outputting a current; a control circuit capable of outputting a first signal and a second signal; a connection circuit provided between the light-receiving element and a first potential line and controlled by the first signal; and a detection circuit capable of outputting a third signal based on the current of the light-receiving element in response to the second signal.

2. The photodetector according to claim 1, wherein the control circuit outputs the first signal that controls the connection circuit and is capable of controlling recharging of the light receiving element.

3. The photodetector according to claim 1, wherein the control circuit is capable of outputting the first signal as a pulse signal.

4. The photodetector according to claim 1, wherein the control circuit is capable of outputting the second signal as a pulse signal.

5. The photodetector according to claim 4, wherein the control circuit is capable of changing the output timing of the second signal.

6. The photodetector according to claim 1, wherein the control circuit is capable of changing the period from the transition timing of the first signal to the transition timing of the second signal.

7. The photodetector according to claim 1, wherein the control circuit is capable of repeatedly outputting the first signal, which is a pulse signal, and the control circuit is capable of repeatedly outputting the second signal, which is a pulse signal.

8. The photodetector according to claim 1, wherein the control circuit is capable of executing control to change the period from the transition timing of the first signal to the transition timing of the second signal.

9. The photodetector according to claim 1, wherein the detection circuit is capable of outputting the third signal in synchronization with the second signal.

10. The photodetector according to claim 1, wherein the first potential line is a power supply line, and the connection circuit has a switch electrically connected in series between the light receiving element and the first potential line.

11. The photodetector device according to claim 1, wherein the detection circuit comprises a flip-flop.

12. The photodetector according to claim 1, further comprising an output circuit capable of outputting a voltage signal based on the current of said light receiving element to said detection circuit.

13. The photodetector according to claim 12, wherein the detection circuit is capable of outputting the third signal based on the voltage signal during the period from the transition timing of the first signal to the transition timing of the second signal.

14. The photodetector device according to claim 12, wherein the output circuit includes an inverter.

15. The photodetector according to claim 1, further comprising a counter capable of counting the third signal.

16. The photodetector according to claim 1, further comprising a processing circuit capable of counting the number of pixels that have received light based on the third signal for each pixel.

17. The photodetector device according to claim 16, wherein the processing circuit is capable of performing two or more counts in response to a pulse signal.

18. The photodetector according to claim 1, further comprising a transistor electrically connected between the light-receiving element and the connection circuit, the transistor having a gate to which a predetermined voltage is applied.

19. The photodetector device according to claim 1, further comprising: a first layer having a plurality of said photodetectors; and a second layer having at least one of said control circuit, said connection circuit, and said detection circuit, said second layer being stacked on said first layer.

20. The photodetector according to claim 1, further comprising: a first pixel that performs photoelectric conversion on infrared light; and a second pixel that performs photoelectric conversion on visible light.

21. The photodetector according to claim 1, wherein the light receiving element is an avalanche photodiode.

22. An optical detection system comprising: a light source capable of irradiating light onto an object; and an optical detection device that receives light from the object, wherein the optical detection device has: a light receiving element that can receive light and output a current; a control circuit that can output a first signal and a second signal; a connection circuit that is provided between the light receiving element and a first potential line and controlled by the first signal; and a detection circuit that can output a third signal based on the current of the light receiving element in response to the second signal.

Images