Driving signal-based reduction of gate switching instability for semiconductor power switch

Abstract

An electrical circuit (21) is usable as part of an electric drive system having a direct current (DC) voltage supply (18), a DC link capacitor (17), and an inverter circuit (11) for powering an electric machine (12). The electrical circuit (21) includes a driver circuit (15) connected to a gate terminal of a power switch (20), e.g., a silicon carbide power metal-oxide semiconductor field effect transistor (SiC power MOSFET). The power switch (20) has a gate-to-source voltage responsive to a driving voltage (VDR), and a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level below a threshold voltage toward a relatively high voltage level above the threshold voltage. The driver circuit (15) is operable to shape a trajectory of the driving voltage (VDR) over the degradation interval such that the driving voltage (VDR) is non-linear across over a full duration of the degradation interval.

Description

DRIVING SIGNAL-BASED REDUCTION OF GATE SWITCHINGINSTABILITY FOR SEMICONDUCTOR POWER SWITCHCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of priority to United States Provisional Application No. 63 / 555,563 filed on February 20, 2024, which is hereby incorporated by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to the switching control of a voltage-controlled semiconductor power switch, and in particular to a gate drive circuit and associated methodology for controlling a conductive state of the power switch.BACKGROUND

[0003] High-voltage electric drive systems typically include a direct current (DC) voltage bus connected to a DC power supply, for instance a lithium-ion or nickel- metal hydride battery pack. One or more single-phase or polyphase electric motors may be driven by inverter circuitry connected to the DC voltage bus. Resident semiconductor power switches of the inverter circuitry, as well as of other circuits of the electric drive system such as voltage rectifiers and DC-DC converters, employ voltage-controlled semiconductor switches to generate a desired voltage or current waveform.

[0004] Voltage-controlled power switches are available in various constructions for use in a wide range of power electronic applications. For instance, switching circuits of an electric drive system typically use metal-oxide semiconductor field effect transistors (MOSFETs) as high-frequency switching devices having drain, source, and gate terminals, with the gate terminal acting as a control terminal when operating the power switch. That is, a gate-to-source voltage is determined via provision of a driving voltage to the gate terminal by a driver circuit. This action alters a drain-to-source resistance level of the power switch and changes its ON / OFF conductive state.Attorney Docket No.: ONS04981USPCT PATENT APPLICATIONSUMMARY

[0005] The solutions described herein are intended to reduce gate switching instability (GSI) of a semiconductor power switch in an electrical circuit. According to JEDEC® Publication No. JEP195, “Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion”, published on February 1, 2023 by the JEDEC® Solid State Technology Association, GSI refers to the undesirable phenomenon of a “threshold instability of a MOS device operating in a gate switching mode between a voltage much above the threshold voltage and below the flatband voltage”, and thus “describes the degradation in the conduction path of the device driven by the switching event.” This phenomenon is referred to in the art by different terms, including “alternating current (AC) gate-bias stress” and “gate-switching stress”, with the term “GSI” used herein for illustrative consistency. Reduction of GSI is accomplished in various maimers using the solutions as described below.

[0006] In particular, an electrical circuit is described herein that includes a semiconductor power switch and an associated driver circuit. The power switch, which may be optionally constructed as a metal-oxide semiconductor field-effect transistor (MOSFET), for instance a silicon carbide (SiC) power MOSFET, has a threshold voltage (VTH), a gate-to-source voltage (VGS) responsive to a driving voltage (VDR), and a degradation interval (tdeg). During the degradation internal, the gate-to-source voltage increases from a relatively low voltage level (VGS L) that has a lower magnitude than / is below the threshold voltage. In response to the driving voltage, the gate-to-source voltage increases toward a relatively high voltage level (VGS_H) having a magnitude that exceeds the threshold voltage. The driver circuit, which is connected to a gate terminal of the power switch, is used to shape or generate a non-linear trajectory of the driving voltage over a full duration of the degradation interval.

[0007] The driver circuit may be optionally constructed as a multi-level driver circuit, e.g., one having three or more driver circuits.

[0008] The non-linear trajectory of the driving voltage over the full duration of the degradation interval may include multiple ramped or stepped segments, or the trajectory may be constructed as a periodic oscillating trajectory. The latterAttorney Docket No.: ONS04981USPCT PATENT APPLICATION implementation may be accomplished using a resonant tank in one or more embodiments.

[0009] The electrical circuit may also include a reducing circuit configured to reduce a rate of change (-^) of the above-noted gate-to-source voltage during the degradation interval. A possible implementation of the reducing circuit includes a bleeding resistor (RB) coupled to a gate terminal of an N-type MOSFET, a diode connected to a drain terminal of the N-type MOSFET, and a capacitance divider connected to the bleeding resistor and the N-type MOSFET.

[0010] Also disclosed herein is an electric drive system. The electric drive system may include a direct current (DC) power supply connected in parallel with a DC link capacitor, an inverter circuit connected to the DC link capacitor, a polyphase electric machine connected to the inverter circuit, a rotary output member coupled to the polyphase electric machine, and a load coupled to the rotary output member.

[0011] In a possible embodiment, the inverter circuit includes a plurality of silicon carbide (SiC) power MOSFETs. Each respective one of the SiC power MOSFETs has a threshold voltage, a gate-to-source voltage responsive to a driving voltage, and a degradation interval during which the gate-to-source voltage increases from the relatively low voltage level toward the relatively high voltage level as summarized above. In this particular implementation, a plurality of driver circuits are connected to a respective gate terminal of a different one of the SiC power MOSFETs. The driver circuits are collectively operable to shape or generate a non-linear trajectory of the driving voltage over the full duration of the degradation interval.

[0012] The above summary is not intended to represent every embodiment or aspect of the present disclosure. Rather, the foregoing summary exemplifies certain novel aspects and features as set forth herein. The above noted and other features and advantages of the present disclosure will be readily apparent from the following detailed description of representative embodiments and modes for carrying out the present disclosure when taken in connection with the accompanying drawings and the appended claims.BRIEF DESCRIPTION OF THE DRAWINGSAttorney Docket No.: ONS04981USPCT PATENT APPLICATION

[0013] The drawings described herein are for illustrative purposes only, are schematic in nature, and are intended to be exemplary rather than to limit the scope of the disclosure.

[0014] FIG. 1 illustrates an exemplary inverter circuit for energizing a polyphase electric machine, with the inverter circuit using voltage-controlled power switches controlled in accordance with the present disclosure to reduce gate switching instability (GSI).

[0015] FIG. 2 is a time plot of a gate-to-source voltage (VGS) and a gate current (IG) describing degradation intervals as used herein.

[0016] FIG. 3 illustrates a baseline driving voltage (VR) and gate-to-source voltage as it might appear absent the present teachings.

[0017] FIGS. 3A, 3B, and 3C illustrate an exemplary driving signal, driver circuit, and voltage pulses for reducing GSI in accordance with an aspect of the disclosure.

[0018] FIGS. 4A, 4B, and 4C illustrate an exemplary driving signal, driver circuit, and voltage pulses for reducing GSI via one or more ramped segments in accordance with another aspect of the disclosure.

[0019] FIGS. 5A, 5B, and 5C illustrate an exemplary driving signal, driver circuit, and voltage pulse for reducing GSI via a succession of stepped segments in accordance with another aspect of the disclosure.10020| FIG. 6 illustrates an exemplary driving signal and driver circuit for reducing GSI via a periodic oscillatory signal.

[0021] FIGS. 7A and 7B are a respective half-bridge circuit diagram and pulse train in accordance with an aspect of the disclosure.

[0022] The present disclosure may be modified or embodied in alternative forms, with representative embodiments shown in the drawings and described in detail below. Inventive aspects of the present disclosure are not limited to the disclosed embodiments. Rather, the present disclosure is intended to cover alternatives falling within the scope of the disclosure as defined by the appended claims.DETAILED DESCRIPTION

[0023] With reference to the drawings, wherein like reference numbers refer to the same or similar components throughout the several views, an electric drive system 10 is illustrated in FIG. 1 having an exemplary polyphase rotary electric machine (ME)Attorney Docket No.: ONS04981USPCT PATENT APPLICATION12. The electric drive system 10 may include semiconductor power switches 20 each driven by gate-to-source voltage (VGS) from a corresponding driver circuit 15 as set forth herein, with the driver circuits (DR) 15 and power switches 20 together forming an electrical circuit 21 (e.g., FIG. 3B). For simplicity, the power switch 20 labeled S3 is shown driven by a driver circuit 15. In an actual implementation, each of the power switches 20 will be driven by a corresponding driver circuit 15, as appreciated in the art. Also, although the power switches 20 are shown as part of an exemplary alternating current (AC)-to-direct current (DC) inverter circuit 11 in FIG. 1 , those skilled in the art will appreciate that other power electronic devices may benefit from use of the power switches 20, including for instance voltage rectifiers, DC-DC converters, and the like, and therefore the present teachings are not limited to the representative use illustrated in FIG. 1.

[0024] The power switches 20 may be embodied as any voltage-controlled switch that is susceptible, absent the present teachings, to undesirable effects of gate switching instability (GSI). The power switches 20 as contemplated herein may be embodied as wide bandgap (WBG) switches, for instance silicon carbide (SiC) power MOSFETs. Other voltage-controlled power switches that may benefit from the present teachings include, by way of example and not of limitation, gallium nitride (GaN) switches, insulated gate bipolar transistors (IGBTs), and silicon-controlled rectifiers (SCRs). For illustrative consistency, the power switches 20 will be described hereinbelow in a representative embodiment as SiC power MOSFETs without limiting the power switches 20 to any particular construction unless otherwise specified.

[0025] The rotary electric machine 12 may be embodied as an electric traction motor for powering a load in a stationary or mobile system in one or more embodiments, includes the phase leads 14, with each of the phase leads 14 being connectable to the inverter circuit 11. For example, a typical three-phase embodiment of the electric machine 12 includes three phase leads 14, which in turn are individually labeled “a”, “b”, and “c” to indicate nominal a, b, and c phases. The electric drive system 10 also includes a positive voltage rail 16+, a negative voltage rail 16" (electrical ground), and a DC link capacitor 17. The DC link capacitor 17 is connected to the respective positive and negative voltage rails (16 , 16 ) and configured to receive a DC voltage waveform from a DC voltage supply 18, forAttorney Docket No.: ONS04981USPCT PATENT APPLICATION instance a multi-cell electrochemical battery pack of an application-suitable battery chemistry such as lithium-ion, lithium-metal, nickel-metal hydride, etc.

[0026] Within the inverter circuit 1 1 of FIG. 1, a plurality of the power switches 20, also individually labeled SI, S2, S3, S4, S5, and S6, are arranged in multiple switching pairs SP1, SP2, and SP3, i.e., power switches (SI, S2), (S3, S4), and (S5, S6), respectively. Each respective switching pair SP1, SP2, and SP3 is connected to the DC link capacitor 17 and a corresponding one of the phase leads 14 of the electric machine 12. That is, the switching pairs SP1, SP2, and SP3 are respectively connected to the nominal a, b, and c phase leads 14 at nodes Ni, N2, and N3. Each power switch 20 is voltage-controlled by a corresponding gate drive circuit, one of which is schematically illustrated in FIG. 1 for simplicity.

[0027] During normal switching operations, the phase leads 14 are energized by switching control operation of the inverter circuit 11 to generate motor output torque (To) on a rotary output member 120. Being voltage-controlled devices, however, the power switches 20 may experience GSI during operation. Such a condition may be more prevalent in certain constructions of the power switches 20, with trench gate SiC MOSFETs in particular being susceptible to the effects of GSI. However, GSI appears to at least some extent in all voltage-controlled power switches, and therefore the present teachings are not limited to SiC MOSFETs in general or trench gate SiC MOSFETs in particular.

[0028] Referring briefly to FIG. 2, in which time in seconds (s) is illustrated on the horizontal axis and voltage and current magnitude in volts (V) and amps (A) are illustrated on the vertical axis, gate switching instability (GSI) is a significant degradation mechanism for long term operation of voltage-controlled power switches. GSI as contemplated herein is a dynamic effect occurring during regular gate driving, when the gate-to-source voltage (VGS) has fast ramp times of less than about 200 nanoseconds (ns), aof about 0. 1 volts / ns (V / ns) to 0.3 V / ns, and a peak gatecurrent (IPK) of about 1 ampere or more. Among other potential issues, GSI can cause permanent shifts in threshold voltage (VTH) and drain-source ON state resistance (Rdson) (not depicted in FIG. 2) with operational time, with the shift being recoverable only at annealing temperatures exceeding about 400° Celsius (C). Practically speaking, however, a junction temperature of 400° C will never be reached during real applications, and thus degradation is non-recoverable.Attorney Docket No.: ONS04981USPCT PATENT APPLICATION100291 Degradation occurs in the turn-on, and is defined by the interval (tdeg) where the gate-to-source voltage VGS (trace 24) ramps from a relatively low voltage level (VGS_L) to the threshold voltage VTH, i.e., the particular value of VGS that is needed to turn on the power switch 20 for linear and saturation regions of operation as appreciated in the art, and continues toward a relatively high voltage level (VGS_H). Threshold voltages (VTH) of about 3V to about 6V are typical. The relatively high voltage level, VGS H, lies between the relatively low voltage level (VGS L) and the threshold voltage (VTH). During the degradation interval (tdeg), a more negative valueof VGS L and a larger value of ~~ enhances the above-noted degradation. Gate current IG (trace 25) is likewise shown in FIG. 2, with peak gate current ( I I>K ) and minimum gate current (IMIN) also illustrated. Solutions to reducingsuch asincreasing gate resistance, tend to penalize transient power loss and are therefore suboptimal. In contrast, the present solutions incorporate a new driving method to reducewithout impacting switching losses, thereby reducing GSI in thecontrolled power switches 20 illustrated in FIG. 1.

[0030] Referring briefly to FIG. 3, which illustrates a driving voltage (VDR) signal as trace 31 and a gate-to-source voltage (VGS) signal (trace 33) at gate and source terminals of a controlled power switch when not connected to a load, the driving voltage (VDR) is shown rising linearly from a relatively low voltage level (VDR L), e.g., about -3V to about -8V, toward a relatively high voltage level (VDR H), typically about 15V to about 20V. This rise occurs over a rising ramp interval (tr). The driving voltage (VDR) is sustained at the relatively high voltage level (VDR_H) for a calibrated duration before returning to the relatively low voltage level (VDR L), with the trajectory occurring over a falling ramp interval (tf).

[0031] The corresponding gate-to-source voltage (VGS) is illustrated as rising parabolically from the relatively low voltage level (VGS L) through the defined threshold voltage (VTH) over the above-noted degradation interval (tdeg), with VGS_L being about -3V to about -8V (as with VDR L as noted above), continuing in this manner until reaching the relatively high voltage level (VGS_H), e.g., about 15V to about 20V. The gate-to-source voltage (VGS) thereafter drops rapidly back to the relatively low voltage level (VGS_L) when the power switch 20 is commanded OFF, i.e., with the start of the falling ramp interval (tr) of the driving voltage signal (VDR).Attorney Docket No.: ONS04981USPCT PATENT APPLICATION

[0032] In contrast, trace 30 of FIG. 3A represents an alternative driving voltage (VDR) signal from the driver circuit 15 of FIG. 1 to a gate contact of a corresponding power switch 20. The driving voltage (VDR) rises from the level of the relatively low voltage (VDR L) to that of the relatively high voltage (VDR H) over the above noted degradation interval (tdeg), i.e., the turn-on interval of the power switch 20. In accordance with the disclosure, the ramp from VDR_L to VDR H is non-linear over the full duration of the degradation interval (tdeg), and thus is not constant. That is, while portions or segments of the generated trajectory may increase linearly during the degradation interval (tdeg), the trajectory as a whole - taken over the full duration of the degradation interval (tdeg) - is non-linear. Instead, the degradation interval (tdeg) is separated into several intervals tri, treiax, and te as shown, with r in this instance indicating a rising trajectory. The relatively high voltage level (VDR H ) is then maintained for a predetermined duration until the driving voltage (VDR) indicated by trace 30 ramps back down to the level of the relatively low voltage (VDR L), which occurs over the falling duration tf, with / here representing a falling trajectory.

[0033] Trace 32 of FIG. 3 A represents the gate-to-source voltage (VGS), likewise with representative low and high voltages VGS_L and VGS_H, respectively. The threshold voltage (VTH) is also illustrated as the minimum voltage required to turn on the power switch 20 and thereby cause a current to flow between source and drain terminals. The non-linear trajectory of trace 30 over the full duration of the degradation interval (tdeg) may include a plateau segment 34, with a pair of ramped segments (Rl, R2) are connected by the plateau segment 34. Relative to trace 33 of FIG. 3, therefore, the resulting trajectory of trace 32 provides a reduced level of GSI.

[0034] Implementation of traces 30 and 32 of FIG. 3A may proceed by adding a relax time interval (treiax) to a scheme in which VTH > VDR _R > VDR _L. The time to ramp the driving voltage VDR from VDR L to VD (i.e., tri) added to the VDR-R plateau time (treiax), is longer than the time normally taken to ramp directly from VDR L to VDR H, i.e., tri + treiax > tr, with the actual extent of the increase being application dependent and customizable. The time to ramp the driving voltage (VDR) from VDR_R to VDR H, i.e., te, is typically not longer than tr, i.e., te < tr. Moreover, the time to ramp VGS from VGS_L IO VTH, i.e., tdeg, is longer relative to that of FIG. 3, thus reducing GSI. The time to ramp the driving voltage (VDR) from VTH to VGS H is also equal to or less than the baseline level of FIG. 3, which ensures that switching lossesAttorney Docket No.: ONS04981USPCT PATENT APPLICATION are not increased when the power switches 20 of FIG. 1 operate on a load. In general terms, tr~ tf ~~ 1 -20ns, while tri ~ treiax ~ 10-200ns.

[0035] A representative embodiment of the driver circuit 15 suitable for providing the trajectories of FIG. 3A is shown in FIG. 3B. In lieu of a single driver, in this embodiment the driver circuit 15 is constructed as respective first and second driver circuits 150 and 250 (DR1 and D2). For the power switch 20 having a gate terminal (G), a source terminal (S), and a drain terminal (D), the respective first and second driver circuits 150 and 250 are connected to the respective gate terminal (G) and source terminal (S), with the connection to the gate terminal (G) being through a gate resistor (RG) 35 of the electrical circuit 21 (see FIG. 3B), possibly as part of the driver circuit 15.

[0036] The first and second driver circuits 150 and 250 each have a corresponding local voltage source 180 or 280. For example, VDR R of FIG. 3A may be provided by the local voltage source 280, with the low voltage (VDR L) provided by another local voltage source 380. Voltage source 180 has a corresponding voltage level of VDR H- VDR_R. Input pulses (VIM and V1N2) are provided to the respective driver circuits 150 and 250 to generate the pulses 36A and 36B of FIG. 3C. Note that pulse 36A, i.e., VINI, lags pulse VIN2 by the duration of treiax shown in FIG. 3A and described above. An optional resonant tank 46 may be added to the driver circuit 15 to produce an oscillatory signal as described below with reference to FIG. 6.

[0037] The approach of FIGS. 3A-C may be modified in other embodiments within the scope of the disclosure. For instance, as shown by trajectories of traces 300 and 320 (VDR and VGS, respectively) in FIG. 4A one may implement the approach of FIG. 3 A with the interval treiax tending to zero, such that there is a resulting lack of a plateau in the trajectories of VDR and VGS. In other words, the interval tri forms most of the degradation interval tdcg, with the remainder of t<icgbeing the duration te.

[0038] A representative driver circuit 15A suitable for providing the trajectories of FIG. 4A is shown in FIG. 4B. The driver circuit 15A is constructed as the first driver circuit 150 as shown. For the power switch 20 having a gate terminal (G), a source terminal (S), and a drain terminal (D), the first driver circuit 150 is connected to the gate terminal (G) through the gate resistor (RG) 35. Voltage source 480 provides the relatively high voltage (VDR_H ) to the first driver circuit 150, with the low voltageAttorney Docket No.: ONS04981USPCT PATENT APPLICATION(VDR L ) provided via the voltage source 380. In this single-driver implementation, a — — reducing circuit 38 is included to reduce— — when VGS < VTH. at at

[0039] As shown in FIG. 4C, the reducing circuit 38 of FIG. 4B for reducingmay be implemented as a reducing circuit 380 having various circuit components. For example, the reducing circuit 380 may include a MOSFET 200, e.g., a low- voltage N-type MOSFET, configured to interrupt the VGS ramp rate to the power switch 20 for a short interval, thus generating treiax. A low-voltage diode 40 may be used to help avoid current to the first driver circuit 150 of FIG. 4B, with the low- voltage diode 40 acting as a parasitic element when the driver signal is negative. A capacitance divider 42, shown as capacitors Ci and C2, are used to adapt the amplitude of the driver signal to activate the power switch 20. A bleeding resistor (RB) 44 may be connected to the gate (G) as shown to ensure the power switch 20 is only in an ON state for a short time interval. Other implementations of the reducing circuit 38 of FIG. 4B may be contemplated within the scope of the disclosure, and therefore the approach of FIG. 4C is exemplary and non-limiting of the present teachings.

[0040] Referring now to FIG. 5A, traces 300A and 320A represent yet another alternative implementation for shaping trajectories of the driving voltage (VDR) and the gate-to-source voltage (VGS). In this approach, the rise in the driving voltage (VDR) occurs over the degradation interval (tdeg) as a series of steps and ramps. That is, for trace 300A, i.e., the low-to-high voltage transition from VDR L to VDR_H, intermediate voltage levels VD _RI may be attained over duration tri , with the interval treiax being used to complete multiple step increases, possibly at different voltage levels and different time intervals, i.e., to levels VDR R2 and VDR R3. Trace 300A may then be ramped to the relatively high voltage, VDR H, over the interval te, with the driving voltage (VDR) thereafter plateauing until the power switch 20 is turned off over falling interval tf. The corresponding effect on trace 320A over the degradation interval (tdeg) is a series of lobes or curved steps as the gate-to-source voltage (VGS) increases from the relatively low voltage (VGS_L) to the threshold voltage (VTH).

[0041] Any driving voltage levels (VDR Ri) used to execute the series of steps should fulfill the condition VTH > VDR Ri> VD L. The sum of the times needed toAttorney Docket No. : ONS04981USPCT PATENT APPLICATION ramp between such steps and the plateau times for each VDR R, may be defined as follows:

[0042] A possible hardware implementation usable for achieving the trajectories of traces 300A and 320A of FIG. 5A is shown in FIG. 5B. Here, the driver circuit 15B may be constructed as multiple driver circuits 150, 250. ... , 250n. i.e., DR1, DR2, ... , DRn. As explained above, the first driver circuit 150 is connected to the power switch 20 via the gate resistor 35. Individual voltage sources 480 and 580 may be connected to respective driver circuits 150, 250, ... , 250n as shown, with the voltage sources 480 and 580 having the indicated voltage values, i.e., VDR Ri (for voltage sources 480) and VDR H - . . . -VDR Ri-i - VDR Ri. Use of the driver circuit 15B will result in pulses 36A, 36B, and 36n of FIG. 5C, i.e., VINI, VI -I, and VIM, for a nonlimiting embodiment using three drivers. The pulses 36A, 36B, . . . , 36n initiate at different times to provide the desired trajectories of FIG. 5 A, for instance with pulse 36A commencing after ax, and pulse 36B commencing earlier than pulse 36A, i.e., after a duration Wa i after initiation of pulse 36n.

[0043] Referring now to traces 300B and 320B of FIG. 6, the present teachings may be implemented as a periodic oscillatory signal in lieu of the above-described stepped and / or ramped profiles of FIGS. 3A, 4A, and 5A. That is, rather than using a driving voltage (VDR) and gate-to-source voltage (VGS) with linear trajectories over the full duration of the degradation interval (tdeg), it is possible to generate the periodic oscillatory signal with a medium driving voltage, i.e., VDR R.

[0044] By w ay of an example and not of limitation, and referring briefly again to FIG. 3B, the driver circuit 15B may be used to produce the oscillatory signal of FIG.6 by adding the resonant tank 46 to its topology. The output of the second driver circuit 250 may be connected to the resonant tank 46 in this embodiment, such that the resonant tank 46 is connected to the second driver circuit 250 and to the source terminal (S) of the power switch 20. Gain control of the resonant tank 46 may be used to generate the oscillatory' signal of FIG. 6, as appreciated in the art, by filtering out harmonics and outputting a sine wave.

[0045] As appreciated in the art, the resonant tank 46 (also referred to in the art as a resonant circuit or tuned circuit) is an inductor-capacitor (LC) circuit that can determine the oscillation frequency and sustain oscillation via positive feedback. TheAttorney Docket No. : ONS04981USPCT PATENT APPLICATION resonant tank 46 may be constructed, for example, from a capacitor, a resonant inductor, a magnetizing inductor, and a transformer. The resonant inductor in a possible implementation is arranged in series with the resonant capacitor and transformer, while the magnetizing inductor is connected in parallel with the resonant capacitor and transformer. The resonant tank 46 has the ability to resonate at a resonant frequency fres= At the resonant frequency, the inductive andcapacitive reactance are equal in magnitude and opposite in sign, thus canceling each other out. As a result, the impedance of the resonant tank 46 is purely resistive and determined solely by losses in the inductors and capacitor.

[0046] Referring now to FIG. 7A, a half-bridge 50 may be used to implement a DC-DC converter in lieu of the inverter circuit 11 of FIG. I, with the half-bridge circuit 50 controlled via any of the present driving signal methodologies described above. A signal may be generated as the driving voltage (VDRI, VDR2) for each of the power switches 20 used in the half-bridge 50, in this instance the power switches 20A and 20B. Driver circuits 15-1 and 15-2 may be used to provide a driving voltage (VDRI, VDR2) to the respective power switches 20A and 20B. A load resistance (RL) 135 represents the resistance of a coupled load. Other components of the representative half-bridge 50 include an inductor (L) 37 and the voltage source 18.

[0047] The half-bridge 50 of FIG. 7A may therefore be used to generate the pulse trains 35D and 35E of FIG. 7B. Here, tri and treiax are embedded within the deadtime (DT), i.e., the period during which neither of the power switches 20A and 20B of the half-bridge circuit 50 conducts. As noted above, representative values for tri and treiax are about 10 ns to about 200 ns. By comparison, deadtime (DT) may be on the order of about 300 ns to about 800 ns. Thus, FIG. 7B is not drawn to scale, but rather is exaggerated for clarity.

[0048] The solutions set forth above are therefore usable for reducing GSI in SiC power MOSFETs and other voltage-controlled power switches 20. By implementing the various drive methodologies of FIGS. 3 A, 4A. 5 A, and 6, e.g., in a half-bridge 50 as shown in FIG. 7A, aboard the electric drive system 10 of FIG. 1, or in other electrical systems, one can avoid permanent shifts in threshold voltage (VTH) and on- state resistance (Rdson). This is accomplished by reducingwithout impactingAttorney Docket No. : ONS04981USPCT PATENT APPLICATION switching losses. These and other attendant benefits will be appreciated by those skilled in the art having the benefit of the present teachings.

[0049] While several modes for carry ing out the many aspects of the present teachings have been described in detail, those familiar with the art to which these teachings relate will recognize various alternative aspects for practicing the present teachings that are within the scope of the appended claims. The above description and accompanying drawings are illustrative and exemplary of the entire range of alternative embodiments that an ordinarily skilled artisan would recognize as implied by, structurally and / or functionally equivalent to, or otherwise rendered obvious based upon the included content, and not as limited solely to those explicitly depicted and / or described embodiments.

[0050] Moreover, the present concepts expressly include combinations and subcombinations of the described elements and features. The detailed description and the drawings are supportive and descriptive of the present teachings, with the scope of the present teachings defined solely by the claims. Words of approximation, such as ■‘about,’’ ‘'almost,” '‘substantially,” “generally,” '‘approximately,” and the like, may each be used herein to denote “at, near, or nearly at,” or “within 0-5% of,” or “within acceptable manufacturing tolerances,” or any logical combination thereof, for example.

Claims

Attorney Docket No. : ONS04981USPCT PATENT APPLICATIONCLAIMSWhat is Claimed Is:

1. An electrical circuit (21) comprising: a power switch (20) having a threshold voltage (VTH), a gate-to-source voltage (VGS) that is responsive to a driving voltage (VDR) to the power switch (20), and a degradation interval (tdeg) during which the gate-to-source voltage (VGS) increases from a relatively low voltage level (VGS L) below the threshold voltage (VTH) toward a relatively high voltage level (VGS H) above the threshold voltage (VTH); and a driver circuit (15) connected to a gate terminal of the power switch (20), wherein the driver circuit (15) is operable to generate a non-linear trajectory of the driving voltage (VDR) over a full duration of the degradation interval (tdeg).

2. The electrical circuit (21) of claim 1, wherein the driver circuit (15) is constructed as a multi-level driver circuit (15).

3. The electrical circuit (21) of claim 2, wherein the multi-level driver circuit (15) includes a three or more driver circuits (15).

4. The electrical circuit (21) of claim 1, wherein the power switch (20) includes a metal -oxide semiconductor field-effect transistor (MOSFET).

5. The electrical circuit (21) of claim 4. wherein the MOSFET is a silicon carbide (SiC) power MOSFET.

6. The electrical circuit (21) of claim 1, wherein the trajectory of the driving voltage (VDR) over the full duration of the degradation interval (tdeg) includes multiple ramped segments (Rl, R2).

7. The electrical circuit (21) of claim 6, wherein a pair of the multiple ramped segments (Rl, R2) are connected by a plateau segment (34).Attorney Docket No. : ONS04981USPCT PATENT APPLICATION8. The electrical circuit (21) of claim 1, wherein the trajectory of the driving voltage (VDR) over the full duration of the degradation interval (tdeg) includes multiple stepped segments.

9. The electrical circuit (21) of claim 1, wherein the driver circuit (15) includes a reducing circuit (38) configured to reduce a rate of change (-^) of the gate-to-source voltage (VGS) during the degradation interval (tdeg).

10. The electrical circuit (21) of claim 9. wherein the reducing circuit (38) includes an N-type metal-oxide semiconductor field-effect transistor (MOSFET) (200), a bleeding resistor (RB) (44) coupled to a gate terminal of the N-type MOSFET, a diode (40) connected to a drain terminal of the N-type MOSFET, and a capacitance divider (42) that is connected to the bleeding resistor (44) and the N-type MOSFET.

11. The electrical circuit (21) of claim 1. wherein the driver circuit (15) includes a resonant tank (46), and is operable to shape the trajectory of the driving voltage (VDR) via the resonant tank (46) such that the driving voltage (VDR) has a periodic oscillating trajectory over the full duration of the degradation interval (tdeg).

12. An electric drive system (10), comprising: a direct current (DC) voltage supply (18); a DC link capacitor (17) connected in parallel with the DC voltage supply (18); an inverter circuit (11) connected to the DC link capacitor (17) and having: a plurality of silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) (20), each respective one of the SiC power MOSFETs (20) having a threshold voltage (VTH), a gate-to- source voltage (VGS) that is responsive to a driving voltage (VDR), and a degradation interval (tdeg) during which the gate-to-source voltage (VGS) increases from a relatively low voltage level (VGS L) below theAttorney Docket No. : ONS04981USPCT PATENT APPLICATION threshold voltage (VTH) toward a relatively high voltage level (VGS _L) above the threshold voltage (VTH); and a plurality of driver circuits (15), each driver circuit (15) of the plurality of driver circuits (15) being connected to a respective gate terminal of a different one of the SiC power MOSFETs (20), wherein the driver circuits (15) are collectively operable to generate a non- linear trajectory of the driving voltage (VDR) over a full duration of the degradation interval (tdeg); a polyphase electric machine (12) connected to the inverter circuit (11); a rotary output member (120) coupled to the polyphase electric machine (11); and a load (i.e., load resistance 135) coupled to the rotary output member (120).

13. The electric drive system (10) of claim 12, wherein the plurality of driver circuits (15) are coupled to the respective gate terminal via a gate resistor.

14. The electric drive system of claim 12, wherein the trajectory of the driving voltage (VDR) over the full duration of the degradation interval (tdeg) includes multiple ramped segments.

15. The electric drive system of claim 12, wherein the trajectory of the driving voltage (VDR) over the full duration of the degradation interval (tdeg) includes multiple stepped segments.

16. The electric drive system of claim 12, wherein the plurality of driver circuits (15) include a reducing circuit (38) configured to reduce a rate of change (-^■) of the gate-to-source voltage (VGS) during the degradation interval (tdeg).

17. The electric drive system of claim 12, wherein at least one of the driver circuits (15) includes a resonant tank (46) that operable to generate the trajectory of the driving voltage (VDR) as a periodic oscillating trajectory over the full duration of the degradation interval (tdeg).Attorney Docket No. : ONS04981USPCT PATENT APPLICATION18. An electrical circuit (21) for use with a silicon carbide (SiC) power metal-oxide semiconductor field-effect transistor (MOSFET), comprising: a gate resistor (35); and a plurality' of driver circuits (15) coupled to a gate terminal of the SiC power MOSFET via the gate resistor (35), wherein the driver circuits (15) are collectively operable to generate a driving voltage (VDR) to the SiC power MOSFET over a degradation interval (tdeg) during which a gate-to-source voltage (VGS) increases from a relatively low voltage level (VGS L) below a threshold voltage (VTH) of the SiC power MOSFET toward a relatively high voltage level (VGS H) above the threshold voltage (VTH) of the SiC power MOSFET. such that a trajectory of the driving voltage (VDR) is non-linear across over a full duration of the degradation interval (tdeg) and includes multiple ramped segments or multiple stepped segments.

19. The electrical circuit (21) of claim 18, wherein the electrical circuit (21) includes a reducing circuit (38) configured to reduce a rate of change (““) of the gate-to-source voltage (VGS) during the degradation interval (tdeg), and wherein the reducing circuit (38) includes an N-type MOSFET (200), a bleeding resistor (RB) (44) coupled to a gate terminal of the N-type MOSFET (200), a diode (40) connected to a drain terminal of the N-type MOSFET (200), and a capacitance divider (42) that is connected to the bleeding resistor (44) and the N-type MOSFET (200).

20. The electrical circuit (21) of claim 18, further comprising: a resonant tank (46), wherein the plurality of driver circuits (15) is operable to output the driving voltage (VDR) with a periodic oscillating trajectory over the full duration of the degradation interval (tdeg) via the resonant tank (46).

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