Imaging device

Abstract

An imaging device 1 includes a first semiconductor substrate 100, pixels 10, an electrostatic protection circuit 500, and wiring. The first semiconductor substrate 100 includes a first impurity region and a second impurity region. Each of the pixels 10 includes a photoelectric conversion unit 310 and the first impurity region. The photoelectric conversion unit 310 converts incoming light into electric charges. The electrostatic protection circuit 500 includes the second impurity region. The wiring connects the pixels 10 and the electrostatic protection circuit 500. The impurity concentration of the second impurity region is identical to the impurity concentration of the first impurity region.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] Configurations for protecting an imaging device are known. For example, the imaging device disclosed in Japanese Patent Application Laid-Open No. 2003-144999 is provided with a protection diode circuit.

[0003] Patent No. 5693060 JP 2020-162117 A

[0004] The present disclosure provides techniques suitable for preventing damage to components of an imaging device.

[0005] The present disclosure provides an imaging device comprising: a first semiconductor substrate including a first impurity region and a second impurity region; pixels including the first impurity region and a photoelectric conversion unit that converts incident light into an electric charge; an electrostatic protection circuit including the second impurity region; and wiring that connects the pixels and the electrostatic protection circuit, wherein the impurity concentration of the second impurity region is the same as the impurity concentration of the first impurity region.

[0006] The technology according to the present disclosure is suitable for preventing damage to components of an imaging device.

[0007] FIG. 1 shows an exemplary configuration of an imaging device according to a first embodiment. FIG. 2A is a cross-sectional view showing a layered structure of the imaging device according to the first embodiment. FIG. 2B is an exploded explanatory view of the layered structure of the imaging device according to the first embodiment. FIG. 3 is a simplified circuit diagram of the imaging device according to the first embodiment. FIG. 4 is a detailed circuit diagram of the imaging device according to the first embodiment. FIG. 5A is a plan view for explaining electrostatic discharge protection circuits according to Examples 1-1, 1-2, and 1-3. FIG. 5B is a cross-sectional view for explaining the electrostatic discharge protection circuit according to Example 1-1. FIG. 5C is a plan view for explaining a plurality of unit pixels. FIG. 6 is a cross-sectional view for explaining the electrostatic discharge protection circuit according to Example 1-2. FIG. 7 is a cross-sectional view for explaining the electrostatic discharge protection circuit according to Example 1-3. FIG. 8A is a plan view for explaining electrostatic discharge protection circuits according to Examples 2-1, 2-2, and 2-3. FIG. 8B is a cross-sectional view for explaining the electrostatic discharge protection circuit according to Example 2-1. FIG. 9 is a cross-sectional view for explaining the electrostatic discharge protection circuit according to Example 2-2. FIG. 10 is a cross-sectional view for explaining the electrostatic discharge protection circuit according to Example 2-3. FIG. 11A is a plan view illustrating electrostatic protection circuits according to Examples 3-1, 3-2, and 3-3. FIG. 11B is a cross-sectional view illustrating the electrostatic protection circuit according to Example 3-1. FIG. 12 is a cross-sectional view illustrating the electrostatic protection circuit according to Example 3-2. FIG. 13 is a cross-sectional view illustrating the electrostatic protection circuit according to Example 3-3. FIG. 14A is a plan view illustrating the electrostatic protection circuits according to Examples 4-1, 4-2, and 4-3. FIG. 14B is a cross-sectional view illustrating the electrostatic protection circuit according to Example 4-1. FIG. 15A is a cross-sectional view illustrating the electrostatic protection circuit according to Example 4-2. FIG. 15B is a plan layout of signal pixels and dummy pixels according to a specific example of Example 4-2. FIG. 16 is a cross-sectional view illustrating the electrostatic protection circuit according to Example 4-3. FIG. 17A is a plan view illustrating the electrostatic protection circuits according to Examples 5-1, 5-2, and 5-3. FIG. 17B is a cross-sectional view illustrating the electrostatic protection circuit according to Example 5-1. Fig. 18 is a cross-sectional view for explaining an electrostatic protection circuit according to Example 5-2. Fig. 19 is a cross-sectional view for explaining an electrostatic protection circuit according to Example 5-3. Fig. 20 is an explanatory diagram of a diode-type electrostatic protection circuit that serves as a countermeasure against negative charges.FIG. 21 is an explanatory diagram of a diode-type electrostatic protection circuit according to Example 1-1, Example 2-1, Example 3-1, Example 4-1, and Example 5-1, which provides protection against both positive and negative charges. FIG. 22 is an explanatory diagram of a MOSFET-type electrostatic protection circuit according to Example 1-2, Example 2-2, Example 3-2, Example 4-2, and Example 5-2, which provides protection against both positive and negative charges. FIG. 24 is an explanatory diagram of a bipolar transistor-type electrostatic protection circuit according to Example 1-3, Example 2-3, Example 3-3, Example 4-3, and Example 5-3, which provides protection against both positive and negative charges. FIG. 25B is an explanatory diagram of a modified example of a bipolar transistor-type electrostatic protection circuit according to Example 2, which provides protection against both positive and negative charges. FIG. 26 is a detailed circuit diagram of an imaging device according to Embodiment 2. Fig. 27A is a circuit diagram showing first and second dummy pixels according to embodiment 2. Fig. 27B is a planar layout of the first and second dummy pixels according to embodiment 2. Fig. 28 is a detailed circuit diagram of an imaging device according to embodiment 3. Fig. 29 is a schematic diagram of a configuration example of a camera system according to embodiment 5.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component positions and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in the embodiments can be combined with each other unless a contradiction occurs. Furthermore, the components in the following embodiments are merely illustrative. In each drawing, components having substantially the same function are designated by the same reference numerals, and redundant explanations may be omitted or simplified.

[0009] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from those of the actual objects.

[0010] In the embodiments, terms such as "upper" and "lower" are used merely to specify the relative positions of components, and are not intended to limit the orientation of the imaging device when in use. In the embodiments, "planar view" refers to a view from the thickness direction of the first semiconductor substrate.

[0011] In the embodiments, a "via" refers to a wiring that connects wiring layers. Unless otherwise specified, "connection" and "electrical connection" may be interpreted interchangeably. An impurity region may also be referred to as a diffusion region. A gate may also be referred to as a gate electrode. A substrate may also be referred to as a wafer.

[0012] In the embodiments, the terms p-type and n-type are used, and unless otherwise contradictory, p-type elements may be replaced with n-type elements, and n-type elements may be replaced with p-type elements.

[0013] (Embodiment 1) Fig. 1 shows an exemplary configuration of an imaging device according to embodiment 1. The imaging device 1 shown in Fig. 1 has a pixel array 470 including a plurality of pixels 10, and a peripheral circuit 490. Each pixel 10 has a photoelectric conversion unit that converts incident light into an electric charge, and the plurality of pixels 10 are arranged two-dimensionally on a semiconductor substrate, for example, to form an imaging region. Note that dummy pixels 15 are not shown in Fig. 1.

[0014] 1, the pixels 10 are arranged in a matrix of m rows and n columns, with the center of each pixel 10 located on a lattice point of a square lattice. Of course, the arrangement of the pixels 10 is not limited to the example shown in the figure, and for example, multiple pixels 10 may be arranged so that each center is located on a lattice point of a triangular lattice, hexagonal lattice, or the like. Furthermore, for example, the pixels 10 may be arranged one-dimensionally, in which case the imaging device 1 may be used as a line sensor.

[0015] In this way, in the imaging device 1, the plurality of pixels 10 are arranged one-dimensionally or two-dimensionally in a plan view, thereby forming a repeating structure in which the plurality of pixels 10 are arranged one-dimensionally or two-dimensionally in a plan view.

[0016] In the configuration illustrated in FIG. 1, the peripheral circuit 490 includes a row scanning circuit 80 , a signal processing circuit 82 , an output circuit 84 , and a control circuit 86 .

[0017] The row scanning circuit 80 is also called a vertical scanning circuit, and includes row control lines R0, R1, . . . , R1 provided corresponding to each row of the plurality of pixels 10. i , ..., R m-1 For example, when the i-th row of the plurality of pixels 10 is taken into consideration, the plurality of pixels 10 belonging to the i-th row are connected to a row control line R i are connected, and therefore the row scanning circuit 80 controls the row control lines R i The row scanning circuit 80 selects the pixels 10 row by row, and performs operations such as reading out the signal voltage and resetting the photoelectric conversion units in the pixels.

[0018] 1 only schematically illustrates the connection between each pixel 10 and the row scanning circuit 80, and the number of control lines arranged for each row of the pixels 10 is not limited to one. As will be described later, the imaging device 1 may have two or more control lines for each row. For example, the row scanning circuit 80 may have connections to address control lines 351, reset control lines 352, and the like, which are provided corresponding to each row of the pixels 10 (see FIG. 4 ).

[0019] The signal processing circuit 82 outputs signal lines S0, S1, . . . , S1 provided in correspondence with each column of the plurality of pixels 10. j , ..., S n-1 For example, the pixels 10 in the j-th column have a connection to the output signal line S j The outputs of the pixels 10 are selected row by row by the row scanning circuit 80, and are connected to the output signal lines S0 to S10. n-1 The output signals read out from the pixels 10 are read out to a signal processing circuit 82 via an output circuit 84. The signal processing circuit 82 performs noise suppression signal processing, typically correlated double sampling, analog-to-digital conversion, and the like on the output signals read out from the pixels 10. The output of the signal processing circuit 82 is read out to the outside of the imaging device 1 via an output circuit 84.

[0020] The control circuit 86 receives, for example, command data, a clock, and the like provided from outside the imaging device 1, and controls the entire imaging device 1. The control circuit 86 typically has a timing generator, and supplies drive signals to the row scanning circuit 80, the signal processing circuit 82, and the like.

[0021] Fig. 2A is a cross-sectional view showing the layered structure of the imaging device 1 according to embodiment 1. Fig. 2B is an exploded explanatory view of the layered structure of the imaging device 1 according to embodiment 1.

[0022] 2A , in the imaging device 1, a second semiconductor substrate 200, a wiring layer 250, a first semiconductor substrate 100, a wiring layer 150, a photoelectric conversion unit 310, a color filter 320, and a microlens 325 are stacked in this order. A pixel array 470 is provided on the first semiconductor substrate 100. A peripheral circuit 490 is provided on the second semiconductor substrate 200. In the first embodiment, the first semiconductor substrate 100 and the second semiconductor substrate 200 contain silicon.

[0023] The pixel array 470 and the peripheral circuit 490 are connected by through electrodes 300. Specifically, the wiring layer 150 and the wiring layer 250 are connected by the through electrodes 300. The pixel array 470 and the peripheral circuit 490 transmit and / or receive signals via the through electrodes 300. The through electrodes 300 penetrate the first semiconductor substrate 100 and connect the wiring layer 250 and the wiring layer 150. In the first embodiment, the through electrodes 300 are TSVs (Through-Silicon Vias).

[0024] 2A, one through electrode 300 is representatively depicted. However, the number of through electrodes 300 may be one or more. In the first embodiment, the number of through electrodes 300 is more than one.

[0025] 2B (a) shows a configuration provided on the first semiconductor substrate 100. In a plan view, a plurality of through electrodes 300 and a plurality of pads 105 are provided on the first semiconductor substrate 100 outside the pixel array 470.

[0026] An electrostatic protection circuit 500 is provided on the first semiconductor substrate 100. The electrostatic protection circuit 500 prevents electrostatic damage to the wiring layer 150 and its connected destinations. The electrostatic protection circuit 500 prevents electrostatic damage during the manufacture of the imaging device 1.

[0027] 2B (b) shows a configuration provided on the second semiconductor substrate 200. In a plan view, the second semiconductor substrate 200 is provided with a plurality of through electrodes 300, a plurality of pads 205, and a plurality of electrostatic protection circuits 220 outside the peripheral circuit 490.

[0028] The pads 205 and the electrostatic discharge protection circuits 220 are in one-to-one correspondence. Each pad 205 is connected to a corresponding electrostatic discharge protection circuit 220. The electrostatic discharge protection circuit 220 has an electrostatic discharge protection function. In the first embodiment, the electrostatic discharge protection circuit 220 includes a protection diode.

[0029] Fig. 3 is a simplified circuit diagram of the imaging device 1 according to embodiment 1. Fig. 4 is a detailed circuit diagram of the imaging device 1 according to embodiment 1.

[0030] 2B and 3 , a pad group 207 including a plurality of pads 205 is configured on the second semiconductor substrate 200. An electrostatic protection circuit group 210 including a plurality of electrostatic protection circuits 220 is configured. The pad group 207 and the row scanning circuit 80 are connected via the electrostatic protection circuit group 210.

[0031] Specifically, the row scanning circuit 80 includes a plurality of drivers 280. The plurality of drivers 280 and the plurality of electrostatic discharge protection circuits 220 are in one-to-one correspondence. Each driver 280 is connected to a corresponding electrostatic discharge protection circuit 220. The plurality of drivers 280 include a plurality of address drivers 281 and a plurality of reset drivers 282. In the first embodiment, the driver 280 includes a complementary metal oxide semiconductor (CMOS).

[0032] 4, the pixel 10 includes a photoelectric conversion unit 310, an amplification transistor 311, a selection transistor 312, a reset transistor 313, and a wiring layer 150. The wiring layer 150 includes an address control line 351 and a reset control line 352. Although not shown in FIG. 4, the pixel 10 also includes a color filter 320 and a microlens 325 (see FIG. 2A). The pixel 10 is provided on the first semiconductor substrate 100.

[0033] The pixel 10 includes a charge storage node 330. The charge storage node 330 stores the charge generated in the photoelectric conversion unit 310. The charge storage node 330 includes a charge storage unit 335, a pixel electrode 310b, a gate of the amplification transistor 311, and the like. The charge storage unit 335 is an impurity region provided in the first semiconductor substrate 100 (see FIG. 2A ).

[0034] The photoelectric conversion unit 310 includes a photoelectric conversion film 310a, a pixel electrode 310b, and a counter electrode 310c. The photoelectric conversion film 310a is disposed between the pixel electrode 310b and the counter electrode 310c. The photoelectric conversion film 310a is located above the first semiconductor substrate 100. In this embodiment, the photoelectric conversion film 310a includes an organic material. In other words, the photoelectric conversion film 310a is an organic film. The photoelectric conversion film 310a may also include an inorganic material.

[0035] The microlens 325 has a light-condensing function of collecting light onto the photoelectric conversion unit 310. The color filter 320 separates colors.

[0036] The photoelectric conversion unit 310 is connected to one of the source and drain of the reset transistor 313 and the gate of the amplification transistor 311. Specifically, the pixel electrode 310b is connected to these. In the first embodiment, one of the source and drain of the reset transistor 313 is the charge accumulation unit 335. One of the source and drain of the amplification transistor 311 and one of the source and drain of the selection transistor 312 are formed by a common impurity region.

[0037] The photoelectric conversion unit 310 converts light into electric charges. Specifically, when a voltage is applied between the pixel electrode 310b and the counter electrode 310c, the photoelectric conversion film 310a converts light into electric charges, and the pixel electrode 310b collects the electric charges.

[0038] The charge is accumulated in a charge accumulation node 330. A power supply voltage is supplied to the other of the source and drain of the amplification transistor 311 through a voltage line 321. The amplification transistor 311 outputs a signal according to the potential of the charge accumulation node 330 to a signal line 322 via a selection transistor 312. The selection transistor 312 determines the timing at which the signal is output from the amplification transistor 311.

[0039] Specifically, the address driver 281 is connected to the gate of the selection transistor 312 via an address control line 351. A voltage is supplied from the address driver 281 to the gate of the selection transistor 312 in the pixel 10 selected by the row scanning circuit 80 via the address control line 351. This turns on the selection transistor 312, and a signal is output from the other of its source and drain.

[0040] A reset voltage is supplied to the other of the source and drain of the reset transistor 313 through a voltage line 323. In this way, the reset transistor 313 resets the charge stored in the charge storage node 330.

[0041] Specifically, the reset driver 282 is connected to the gate of the reset transistor 313 via a reset control line 352. A voltage is supplied from the reset driver 282 to the gate of the reset transistor 313 in the pixel 10 selected by the row scanning circuit 80 via the reset control line 352. This turns on the reset transistor 313, supplies the reset voltage to the charge storage node 330, and initializes the charge in the charge storage node 330.

[0042] In the first embodiment, the amplification transistor 311, the selection transistor 312, and the reset transistor 313 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0043] A plurality of impurity regions 230 are provided in the second semiconductor substrate 200. The impurity regions 230 are included in the driver 280. Specifically, the CMOS in the driver 280 includes a pMOS and an nMOS. The pMOS and nMOS share the impurity region 230.

[0044] The impurity region 230 of the address driver 281 is connected to an address control line 351. The impurity region 230 of the reset driver 282 is connected to a reset control line 352.

[0045] Here, let us assume that the electrostatic protection circuit 500 is not provided on the first semiconductor substrate 100. In this case, electrostatic breakdown may occur during the manufacture of the imaging device 1. For example, a conductive structure is processed into the wiring layer 150 by etching using ions. During this etching, the wiring layer 150 may be damaged by plasma. Furthermore, the plasma may cause an antenna effect. The antenna effect may destroy the gate insulating film of the selection transistor 312 connected to the address control line 351 of the wiring layer 150. The antenna effect may also destroy the gate insulating film of the reset transistor 313 connected to the reset control line 352 of the wiring layer 150.

[0046] The above problem is likely to become apparent during the manufacture of an imaging device 1 having a stacked structure including a first semiconductor substrate 100 and a second semiconductor substrate 200. Specifically, suppose that a pixel array 470 and a peripheral circuit 490 are provided on the first semiconductor substrate 100. In this case, electrostatic protection of the address control line 351 and the reset control line 352 can be achieved even without the electrostatic protection circuit 500. This is because the impurity region 230 connected to the address control line 351 and the impurity region 230 connected to the reset control line 352 can provide electrostatic protection. However, during the manufacture of an imaging device 1 having a stacked structure including the first semiconductor substrate 100 and the second semiconductor substrate 200, the first semiconductor substrate 100 and the second semiconductor substrate 200 may not be bonded together during the above-described etching. In this case, the address control line 351 is not connected to the impurity region 230, and the reset control line 352 is not connected to the impurity region 230.

[0047] However, in the first embodiment, the electrostatic protection circuit 500 is provided on the first semiconductor substrate 100. Therefore, even if the first semiconductor substrate 100 and the second semiconductor substrate 200 are not bonded together during the etching, electrostatic protection can be achieved by the electrostatic protection circuit 500. Electrostatic protection can improve the manufacturing yield of the imaging device 1. Furthermore, in the completed imaging device 1, the electrostatic protection provided by the electrostatic protection circuit 500 can prevent dielectric breakdown caused by exposure of the pads 105 and the like to static electricity. In this way, the electrostatic protection circuit 500 can prevent damage to the components of the imaging device 1.

[0048] In the first embodiment, as shown in Fig. 4, a protection circuit 500 may be provided for both the address control line 351 and the reset control line 352. In the first embodiment, a protection circuit 500 may be provided for only one of the address control line 351 and the reset control line 352. In the first embodiment, as shown in Fig. 4, an electrostatic protection circuit that provides protection against both positive and negative charges may be provided. In the first embodiment, an electrostatic protection circuit that provides protection against either positive or negative charges may be provided.

[0049] The electrostatic discharge protection circuit 500 will be further described below.

[0050] [Example 1-1] Fig. 5A is a plan view illustrating an electrostatic protection circuit 500 according to Example 1-1 of Embodiment 1. Fig. 5B is a cross-sectional view illustrating the electrostatic protection circuit 500 according to Example 1-1 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 1-1 may be referred to as an electrostatic protection circuit 511. Note that Fig. 5A is also a plan view illustrating the electrostatic protection circuits 500 according to Examples 1-2 and 1-3.

[0051] In Example 1-1, the imaging device 1 includes a through-electrode region 410, a protective circuit region 420, a guard ring 430, and a pixel array 470. Wiring 450 extends in the through-electrode region 410, the protective circuit region 420, the guard ring 430, and the pixel array 470. The imaging device 1 also includes a dummy pixel region 440 and an optical black region (hereinafter, OB region) 480.

[0052] 5A , in a plan view, the guard ring 430 is provided outside the pixel array 470. Specifically, in a plan view, the guard ring 430 is provided between the through-electrode region 410 and the pixel array 470.

[0053] The through electrode region 410 is provided with the through electrode 300. The through electrode 300 is not shown in Figures 5A and 5B.

[0054] 5B , in the through-electrode region 410, the first semiconductor substrate 100 includes a support substrate 111, a semiconductor region 112, and a well 121p. The semiconductor region 112 is provided above the support substrate 111. The well 121p is provided above the semiconductor region 112.

[0055] In plan view, the protective circuit region 420 is provided outside the guard ring 430. Specifically, in plan view, the protective circuit region 420 is provided between the through-electrode region 410 and the guard ring 430.

[0056] In Example 1-1, an electrostatic discharge protection circuit 511 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 511 includes a positive charge discharge circuit 511p and a negative charge discharge circuit 511n. The charge discharge circuits 511p and 511n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0057] 5B , in the protection circuit region 420, the first semiconductor substrate 100 includes a support substrate 111, a semiconductor region 112, a well 121n, a well 122p, an impurity region 141n, an impurity region 141p, an impurity region 142p, and an impurity region 142n. The semiconductor region 112 is provided above the support substrate 111. The well 121n and the well 122p are provided above the semiconductor region 112.

[0058] Between the well 121p and the well 121n, an isolation 171 is provided. Between the well 121n and the well 122p, an isolation 172 is provided. The isolations 171 and 172 are structures formed in the first semiconductor substrate 100 by, for example, an STI (shallow trench isolation) process.

[0059] An impurity region 141n and an impurity region 141p are provided in the well 121n. The well 121n is an n-type well. The impurity region 141n is an n-type impurity region. The impurity region 141p is a p-type impurity region. The concentration of n-type impurities in the impurity region 141n is higher than the concentration of n-type impurities in the well 121n. The impurity region 141p is connected to a wiring 450. The impurity region 141n is connected to a power supply 451.

[0060] An impurity region 142p and an impurity region 142n are provided in the well 122p. The well 122p is a p-type well. The impurity region 142n is an n-type impurity region. The impurity region 142p is a p-type impurity region. The concentration of the p-type impurity in the impurity region 142p is higher than the concentration of the p-type impurity in the well 122p. The impurity region 142n is connected to a wiring 450. The impurity region 142p is connected to a ground 452.

[0061] A positive charge discharging circuit 511p including a well 121n, an impurity region 141n, and an impurity region 141p is formed in the protection circuit region 420. A negative charge discharging circuit 511n including a well 122p, an impurity region 142p, and an impurity region 142n is formed. The electrostatic protection function of the charge discharging circuits 511p and 511n will be described later.

[0062] The guard ring 430 prevents noise from entering the plurality of pixels 10 in the pixel array 470 from the outside of the guard ring 430 in a plan view. As shown in FIG. 5A , in Example 1-1, the guard ring 430 has a closed frame shape in a plan view so as to surround the pixel array 470. The guard ring 430 will be specifically described below with reference to the configuration of the first semiconductor substrate 100.

[0063] As shown in FIG. 5B, in guard ring 430, first semiconductor substrate 100 includes support substrate 111, semiconductor region 112, well 122p, well 122n, well 123p, impurity region 143p1, impurity region 143n, and impurity region 143p2.

[0064] A semiconductor region 112 is provided above the support substrate 111. A well 122p, a well 122n, and a well 123p are provided above the semiconductor region 112.

[0065] An isolation 173 is provided between a portion of well 122p on the protection circuit region 420 side and a portion of well 122n side. An isolation 174 is provided between well 122p and well 122n. An isolation 175 is provided between well 122n and well 123p. An isolation 176 is provided between a portion of well 123p on the well 122n side and a portion of well 123p on the pixel array 470 side. The isolations 173, 174, 175, and 176 are structures formed in the first semiconductor substrate 100 by, for example, an STI process.

[0066] An impurity region 143p1 is provided in the well 122p. The well 122p is a p-type well. The impurity region 143p1 is a p-type impurity region. The concentration of the p-type impurity in the impurity region 143p1 is higher than the concentration of the p-type impurity in the well 122p. The impurity region 143p1 is connected to a wiring 453.

[0067] An impurity region 143n is provided in the well 122n. The well 122n is an n-type well. The impurity region 143n is an n-type impurity region. The concentration of n-type impurities in the impurity region 143n is higher than the concentration of n-type impurities in the well 122n. The impurity region 143n is connected to a wiring 454.

[0068] An impurity region 143p2 is provided in the well 123p. The well 123p is a p-type well. The impurity region 143p2 is a p-type impurity region. The concentration of the p-type impurity in the impurity region 143p2 is higher than the concentration of the p-type impurity in the well 123p. The impurity region 143p2 is connected to a wiring 455.

[0069] A voltage is applied to well 122p via interconnect 453 and impurity region 143p1 in this order, a voltage is applied to well 122n via interconnect 454 and impurity region 143n in this order, and a voltage is applied to well 123p via interconnect 455 and impurity region 143p2 in this order.

[0070] A plurality of unit pixels 20 are provided in the pixel array 470. Fig. 5C is a plan view illustrating the plurality of unit pixels 20. Hereinafter, the pixel 10 may be referred to as a signal pixel 10. The pixel electrode 310b may be referred to as a signal pixel electrode 310b.

[0071] The plurality of unit pixels 20 are arranged one-dimensionally or two-dimensionally, thereby forming a repeating structure in which the plurality of unit pixels 20 are arranged one-dimensionally or two-dimensionally in a plan view.

[0072] The plurality of unit pixels 20 include one or more dummy pixels 15 and a plurality of signal pixels 10. The plurality of signal pixels 10 and the one or more dummy pixels 15 are included in a pixel array 470. In the example of Fig. 5C, the plurality of unit pixels 20 include a plurality of dummy pixels 15. As will be described later, the plurality of signal pixels 10 include effective pixels 11 and OB pixels 12.

[0073] In a plan view, one or more dummy pixels 15 are located outside an array formed by a plurality of signal pixels 10. Typically, in a repeating structure in which unit pixels 20 are arranged one-dimensionally or two-dimensionally, the plurality of dummy pixels 15 are located at the end in the one-dimensional or two-dimensional direction.

[0074] 5B , each unit pixel 20 includes a unit electrode 465. In the pixel array 470, the unit electrodes 465 are arranged one-dimensionally or two-dimensionally, thereby forming a repeating structure in which the unit electrodes 465 are arranged one-dimensionally or two-dimensionally in a plan view.

[0075] 5C, the plurality of unit electrodes 465 includes one or more dummy electrodes 445 and a plurality of signal pixel electrodes 310b.

[0076] In a plan view, one or more dummy electrodes 445 are located outside the array formed by the plurality of signal pixel electrodes 310 b. Typically, in a repeating structure in which unit electrodes 465 are arranged one-dimensionally or two-dimensionally, the plurality of dummy electrodes 445 are located at the end in the one-dimensional or two-dimensional direction.

[0077] During the manufacture of the imaging device 1, the multiple unit electrodes 465 are formed by a common process. Specifically, a conductive film is etched into the multiple unit electrodes 465. The etching rate differs between the central portion of the conductive film and the edges of the conductive film. Therefore, the shape and / or dimensions of the unit electrodes 465 in the central portion of the conductive film may differ from the shape and / or dimensions of the unit electrodes 465 at the edges of the conductive film. Here, the central portion of the conductive film is the portion that is located at the central portion of the pixel array 470 in a planar view when the pixel array 470 is formed. The edges of the conductive film are the portions that are located at the edges of the pixel array 470 in a planar view when the pixel array 470 is formed.

[0078] Therefore, in the first embodiment, the unit pixels 20 are divided into signal pixels 10 and dummy pixels 15. In a plan view, a plurality of signal pixels 10 form an array. The array of the signal pixels 10 forms a plurality of rows and a plurality of columns. In a plan view, the dummy pixels 15 are located outside the array of the signal pixels 10.

[0079] The signals output from the signal pixels 10 are used to form an image. In contrast, no signal for image formation is output from one or more dummy pixels 15. The dummy pixels 15 act to compensate for the shape and / or dimensions of the signal pixel electrodes 310b. This action can contribute to the formation of a high-quality image.

[0080] 5B , each unit pixel 20 includes a unit transistor 461. In the pixel array 470, the unit transistors 461 are arranged one-dimensionally or two-dimensionally, forming a repeating structure in which the unit transistors 461 are arranged one-dimensionally or two-dimensionally in a plan view.

[0081] The plurality of unit transistors 461 includes one or more dummy transistors 441 and a plurality of signal transistors 471. In the example of FIG.

[0082] In a plan view, one or more dummy transistors 441 are located outside the array formed by the multiple signal transistors 471. Typically, in a repeating structure in which unit transistors 461 are arranged one-dimensionally or two-dimensionally, the multiple dummy transistors 441 are located at the ends in the one-dimensional or two-dimensional direction.

[0083] The unit transistors 461 have the same shape and size. Here, "same shape and size" is an expression intended to allow for errors in shape and size that are unavoidable in mass production of the imaging device 1.

[0084] The gates of the unit transistors 461 are arranged at equal center-to-center distances. "Equal center-to-center distances" is an expression intended to allow for errors in center-to-center distances that are unavoidable in mass production of the imaging device 1.

[0085] In the first embodiment, as shown in Fig. 5C , in a plan view, a plurality of signal pixels 10 are arranged two-dimensionally in a row direction 401 and a column direction 402 to form a plurality of rows and a plurality of columns. A plurality of dummy pixels 15 are distributed in a dummy pixel region 440. The dummy pixel region 440 is located outside the array formed by the plurality of signal pixels 10. The dummy pixel region 440 includes an outer region 403, an outer region 404, an outer region 405, and an outer region 406. Here, the external region 403 is a region on one side in the row direction 401 when viewed from the array configured by the plurality of signal pixels 10, the external region 404 is a region on the other side in the row direction 401 when viewed from the array configured by the plurality of signal pixels 10, the external region 405 is a region on one side in the column direction 402 when viewed from the array configured by the plurality of signal pixels 10, and the external region 406 is a region on the other side in the column direction 402 when viewed from the array configured by the plurality of signal pixels 10. In these descriptions, the "signal pixel 10" and the "dummy pixel 15" can be replaced with the "signal pixel electrode 310b" and the "dummy electrode 445." The "signal pixel 10" and the "dummy pixel 15" in these descriptions can be replaced with the "signal transistor 471" and the "dummy transistor 441."

[0086] In the following description, the central row 408 of the multiple rows formed by signal pixels 10 is the (m+1) / 2-th row counting along the column direction 402 when the number of rows (m) is odd, the central row 408 of the multiple rows formed by signal pixels 10 is the (m) / 2-th or (m+2) / 2-th row counting along the column direction 402 when the number of rows (m) is even, the central column 407 of the multiple columns formed by signal pixels 10 is the (n+1) / 2-th column counting along the row direction 401 when the number of columns (n) is odd, and the central column 407 of the multiple columns formed by signal pixels 10 is the (n) / 2-th or (n+2) / 2-th column counting along the row direction 401 when the number of columns (n) is even. In these descriptions, the "signal pixel 10" and the "dummy pixel 15" can be replaced with the "signal pixel electrode 310b" and the "dummy electrode 445." In these descriptions, the "signal pixel 10" and the "dummy pixel 15" can be replaced with the "signal transistor 471" and the "dummy transistor 441."

[0087] The ratio of the pitch at which the dummy electrodes 445 are arranged in the column direction 402 to the pitch at which the signal pixel electrodes 310b are arranged in the column direction 402 in the central column 407 is, for example, 80% or more and 120% or less. This explanation regarding the ratio can be applied to the dummy electrodes 445 located in the outer regions 403 and 404 in Fig. 5C. Here, the pitch of the elements is the arithmetic mean of the center-to-center distances of adjacent elements.

[0088] The ratio of the pitch at which dummy electrodes 445 are arranged in row direction 401 to the pitch at which signal pixel electrodes 310b are arranged in row direction 401 in central row 408 is, for example, 80% or more and 120% or less. The explanation regarding this ratio can be applied to dummy electrodes 445 located in outer region 405 and outer region 406 in FIG. 5C .

[0089] The ratio of the pitch at which the gates of the dummy transistors 441 are arranged in the column direction 402 to the pitch at which the gates of the signal transistors 471 are arranged in the column direction 402 in the central column 407 is, for example, 80% or more and 120% or less. This explanation regarding the ratio can be applied to the dummy transistors 441 located in the outer regions 403 and 404 in FIG. 5C .

[0090] The ratio of the pitch at which the gates of the dummy transistors 441 are arranged in the row direction 401 to the pitch at which the gates of the signal transistors 471 are arranged in the row direction 401 in the central row 408 is, for example, 80% or more and 120% or less. This explanation regarding the ratio can be applied to the dummy transistors 441 located in the outer regions 405 and 406 in FIG. 5C .

[0091] The ratio of the gate area of ​​the dummy transistor 441 to the gate area of ​​the signal transistor 471 located in the center column 407 and the center row 408 is, for example, 80% or more and 120% or less. This explanation regarding the ratio can be applied to the dummy transistors 441 located in the outer regions 403, 404, 405, and 406 in FIG. 5C .

[0092] 5C , the plurality of pixels 10 in the pixel array 470 includes a plurality of effective pixels 11 and one or more optical black pixels (hereinafter, referred to as OB pixels) 12. In the example of FIG.

[0093] A light-shielding film 360 is provided in the OB region 480. The effective pixels 11 are pixels 10 that do not overlap with the light-shielding film 360 in a planar view. The OB pixels 12 are pixels 10 that overlap with the light-shielding film 360 in a planar view. Dark noise can be suppressed by subtracting the signal level from the OB pixels 12 from the signal level from the effective pixels 11.

[0094] In one example of the first embodiment, the signal transistor 471 is the selection transistor 312. The wiring 450 is the address control line 351.

[0095] In one example of the first embodiment, the signal transistor 471 is the reset transistor 313. The wiring 450 is the reset control line 352.

[0096] In the imaging device 1 configured as above, a diode is configured in the electrostatic protection circuit 511 according to Example 1-1. The diode provides electrostatic protection against both positive and negative charges.

[0097] 5B, in the positive charge discharging circuit 511p, the impurity region 141p and the well 121n form a diode 610pn. The impurity region 141p is a p-type region of the diode 610pn. The well 121n is an n-type region of the diode 610pn.

[0098] The positive charges in the wiring 450 flow into the well 121n via the impurity region 141p. Then, the positive charges flow out from the well 121n to the power supply 451 via the impurity region 141n. In this way, the positive charge discharge circuit 511p forms an escape route for the positive charges in the wiring 450 to escape. This makes it possible to prevent electrostatic breakdown caused by the positive charges. This electrostatic breakdown prevention mechanism also applies to the positive charge discharge circuit 521p of Example 2-1, the positive charge discharge circuit 531p of Example 3-1, the positive charge discharge circuit 541p of Example 4-1, and the positive charge discharge circuit 551p of Example 5-1.

[0099] In the negative charge discharging circuit 511n, the impurity region 142n and the well 122p form a diode 610np. The impurity region 142n is an n-type region of the diode 610np. The well 122p is a p-type region of the diode 610np.

[0100] The negative charge in the interconnect 450 flows into the well 122p via the impurity region 142n. The negative charge then flows out from the well 122p to the ground 452 via the impurity region 142p. In this way, the negative charge discharging circuit 511n provides an escape route for the negative charge in the interconnect 450 to escape. This makes it possible to prevent electrostatic breakdown due to the negative charge. This electrostatic breakdown prevention mechanism also applies to the negative charge discharging circuit 521n of Example 2-1, the negative charge discharging circuit 531n of Example 3-1, the negative charge discharging circuit 541n of Example 4-1, and the negative charge discharging circuit 551n of Example 5-1.

[0101] In Example 1-1, a diode 610pn that discharges positive charges is configured in the positive charge discharge circuit 511p, and a diode 610np that discharges negative charges is configured in the negative charge discharge circuit 511n. Therefore, the electrostatic protection circuit 511 according to Example 1-1 can discharge both positive and negative charges.

[0102] 21 shows an explanatory diagram of a diode-type electrostatic protection circuit 500 according to Example 1-1, which provides protection against both positive and negative charges. Specifically, (a) of FIG. 21 shows an equivalent circuit of diodes 610pn and 610np configured in charge drain circuits 511p and 511n. (b) of FIG. 21 shows a schematic diagram of diodes 610pn and 610np. Note that (a) in Figure 21 is also an equivalent circuit of the diodes 610pn and 610np configured in the charge discharge circuits 521p and 521n according to Example 2-1, an equivalent circuit of the diodes 610pn and 610np configured in the charge discharge circuits 531p and 531n according to Example 3-1, an equivalent circuit of the diodes 610pn and 610np configured in the charge discharge circuits 541p and 541n according to Example 4-1, and an equivalent circuit of the diodes 610pn and 610np configured in the charge discharge circuits 551p and 551n according to Example 5-1.

[0103] The electrostatic protection circuit 511 does not necessarily have to be configured to allow both positive and negative charges to escape, and may instead be configured to provide electrostatic protection against either positive or negative charges based on a diode.

[0104] It is also possible to adopt a configuration in which the positive charge discharge circuit 511p and the negative charge discharge circuit 511n are omitted and only the negative charge discharge circuit 511n is left as the electrostatic protection circuit 511. The electrostatic protection circuit 511 according to this configuration is a diode-type electrostatic protection circuit that acts as a countermeasure against negative charges.

[0105] FIG. 20 is an explanatory diagram of a diode-type electrostatic protection circuit 500 that serves as a countermeasure against negative charge. Specifically, (a) of FIG. 20 shows an equivalent circuit of the diode 610np configured in the negative charge discharge circuit 511n. (b) of FIG. 20 is a schematic diagram of the diode 610np. Note that (a) of FIG. 20 is also: an equivalent circuit of the diode 610np configured in the negative charge discharge circuit 521n according to Example 2-1; an equivalent circuit of the diode 610np configured in the negative charge discharge circuit 531n according to Example 3-1; an equivalent circuit of the diode 610np configured in the negative charge discharge circuit 541n according to Example 4-1; and an equivalent circuit of the diode 610np configured in the negative charge discharge circuit 551n according to Example 5-1.

[0106] It is also possible to adopt a configuration in which the negative charge discharge circuit 511n is omitted from the positive charge discharge circuit 511p and the negative charge discharge circuit 511n and only the positive charge discharge circuit 511p is left as the electrostatic protection circuit 511. The electrostatic protection circuit 511 according to this configuration is a diode-type electrostatic protection circuit that acts as a countermeasure against positive charges.

[0107] The same applies to Examples 2-1, 3-1, 4-1, and 5-1, in that either the electrostatic protection circuit including the diode 610pn that releases positive charges or the electrostatic protection circuit including the diode 610np that releases negative charges can be omitted.

[0108] The diode-type electrostatic protection circuit 500 has the advantage of being easy to fabricate, which is advantageous from the viewpoint of fabricating the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the imaging device 1.

[0109] Other examples and embodiments will be described below. In the following, elements common to an example or embodiment already described and an example or embodiment to be described later will be given the same reference numerals, and their description may be omitted. The descriptions of each example and embodiment may be mutually applicable unless technically inconsistent. Unless technically inconsistent, each example and embodiment may be combined with each other.

[0110] 6 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 1-2 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 1-2 may be referred to as an electrostatic protection circuit 512.

[0111] It should be noted that the dummy electrodes 445, the signal pixel electrodes 310b, the photoelectric conversion film 310a, and the counter electrodes 310c are not shown in Fig. 6. This also applies to Figs. 7, 8B, 9, 10, 11B, 12, 13, 14B, 15A, 16, 17B, 18, and 19.

[0112] In Example 1-2, in plan view, the protective circuit region 420 is provided outside the guard ring 430. Specifically, in plan view, the protective circuit region 420 is provided between the through-electrode region 410 and the guard ring 430.

[0113] In Example 1-2, an electrostatic protection circuit 512 is provided in the protection circuit region 420. The electrostatic protection circuit 512 includes a positive charge discharge circuit 512p and a negative charge discharge circuit 512n. The charge discharge circuits 512p and 512n will be specifically described below with reference to the first semiconductor substrate 100 and the configuration of its periphery.

[0114] 6 , in the protection circuit region 420, the first semiconductor substrate 100 includes an impurity region 144p and an impurity region 144n. The impurity region 144p and the impurity region 141p are provided in the well 121n. The impurity region 144n and the impurity region 142n are provided in the well 122p. In the protection circuit region 420, an insulating film 191 and an insulating film 192 are provided on the first semiconductor substrate 100. The insulating films 191 and 192 are, for example, oxide films. Specifically, the insulating film 191 is provided on the well 121n. The insulating film 192 is provided on the well 122p. An electrode 195 is provided on the insulating film 191. An electrode 196 is provided on the insulating film 192.

[0115] The impurity region 144p and the electrode 195 are connected to a power supply 451. The impurity region 144n and the electrode 196 are connected to a ground 452.

[0116] In the protection circuit region 420, a positive charge discharging circuit 512p is formed, which includes a well 121n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. A negative charge discharging circuit 512n is formed, which includes a well 122p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196.

[0117] In the imaging device 1 configured as above, the electrostatic protection circuit 512 according to Example 1-2 is configured with a MOSFET. The MOSFET provides electrostatic protection against both positive and negative charges.

[0118] The positive charge discharging circuit 512p includes a p-type MOSFET 620p including a well 121n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. The impurity region 141p is a source 621s. The impurity region 144p is a drain 621d. The insulating film 191 is a gate insulating film, which may be an oxide film as described above. The electrode 195 is a gate 621g.

[0119] As the accumulation of positive charge in the wiring 450 progresses, the voltage between the gate 621g and source 621s of the p-type MOSFET 620p decreases, turning on the p-type MOSFET 620p. As a result, the positive charge in the wiring 450 flows out to the power supply 451 via the p-type MOSFET 620p. In this way, the positive charge discharge circuit 512p provides an escape route for the positive charge in the wiring 450 to escape. This makes it possible to prevent electrostatic breakdown due to positive charge. This electrostatic breakdown prevention mechanism also applies to the positive charge discharge circuit 522p of Example 2-2, the positive charge discharge circuit 532p of Example 3-2, the positive charge discharge circuit 542p of Example 4-2, and the positive charge discharge circuit 552p of Example 5-2.

[0120] The negative charge discharging circuit 512n includes an n-type MOSFET 620n including a well 122p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196. The impurity region 142n is a source 622s. The impurity region 144n is a drain 622d. The insulating film 192 is a gate insulating film, which may be an oxide film as described above. The electrode 196 is a gate 622g.

[0121] As the accumulation of negative charge in the interconnect 450 progresses, the voltage between the gate 622g and source 622s of the n-type MOSFET 620n increases, turning on the n-type MOSFET 620n. This causes the negative charge in the interconnect 450 to flow to ground 452 via the n-type MOSFET 620n. In this way, the negative charge discharge circuit 512n provides an escape route for the negative charge in the interconnect 450 to escape. This makes it possible to prevent electrostatic breakdown due to negative charge. This electrostatic breakdown prevention mechanism also applies to the negative charge discharge circuit 522n of Example 2-2, the negative charge discharge circuit 532n of Example 3-2, the negative charge discharge circuit 542n of Example 4-2, and the negative charge discharge circuit 552n of Example 5-2.

[0122] In Example 1-2, a p-type MOSFET 620p that releases positive charges is configured in the positive charge discharge circuit 512p, and an n-type MOSFET 620n that releases negative charges is configured in the negative charge discharge circuit 512n. Therefore, the electrostatic protection circuit 512 according to Example 1-2 can release both positive and negative charges.

[0123] 23 is an explanatory diagram of a MOSFET-type electrostatic protection circuit 500 according to Example 1-2, which provides protection against both positive and negative charges. Specifically, FIG. 23(a) shows an equivalent circuit of MOSFETs 620p and 620n configured in charge drain circuits 512p and 512n. FIG. 23(b) shows a schematic diagram of MOSFETs 620p and 620n. Note that (a) in Figure 23 is: - an equivalent circuit of MOSFETs 620p and 620n configured in charge discharge circuits 522p and 522n according to Example 2-2; - an equivalent circuit of MOSFETs 620p and 620n configured in charge discharge circuits 532p and 532n according to Example 3-2; - an equivalent circuit of MOSFETs 620p and 620n configured in charge discharge circuits 542p and 542n according to Example 4-2; and - an equivalent circuit of MOSFETs 620p and 620n configured in charge discharge circuits 552p and 552n according to Example 5-2.

[0124] The electrostatic protection circuit 512 does not necessarily have to be configured to dissipate both positive and negative charges, and may be configured to provide electrostatic protection against either positive or negative charges based on a MOSFET.

[0125] It is also possible to adopt a configuration in which the positive charge discharge circuit 512p and the negative charge discharge circuit 512n are omitted and only the negative charge discharge circuit 512n is left as the electrostatic protection circuit 512. The electrostatic protection circuit 512 according to this configuration is a MOSFET-type electrostatic protection circuit that acts as a countermeasure against negative charges.

[0126] FIG. 22 is an explanatory diagram of a MOSFET-type electrostatic protection circuit 500 that provides a countermeasure against negative charge. Specifically, FIG. 22(a) shows an equivalent circuit of an n-type MOSFET 620n configured in a negative charge discharge circuit 512n. FIG. 22(b) shows a schematic diagram of the n-type MOSFET 620n. Note that FIG. 22(a) is also: an equivalent circuit of the n-type MOSFET 620n configured in a negative charge discharge circuit 522n according to Example 2-2; an equivalent circuit of the n-type MOSFET 620n configured in a negative charge discharge circuit 532n according to Example 3-2; an equivalent circuit of the n-type MOSFET 620n configured in a negative charge discharge circuit 542n according to Example 4-2; and an equivalent circuit of the n-type MOSFET 620n configured in a negative charge discharge circuit 552n according to Example 5-2.

[0127] It is also possible to adopt a configuration in which the negative charge discharge circuit 512n is omitted and only the positive charge discharge circuit 512p is left as the electrostatic protection circuit 512. The electrostatic protection circuit 512 according to this configuration is a MOSFET-type electrostatic protection circuit that acts as a countermeasure against positive charges.

[0128] The same applies to Example 2-2, Example 3-2, Example 4-2, and Example 5-2, where either the electrostatic protection circuit configured with a p-type MOSFET that releases positive charges or the electrostatic protection circuit configured with an n-type MOSFET that releases negative charges can be omitted.

[0129] The MOSFET-type electrostatic protection circuit 500 has the advantage of being able to easily release electric charges, which is advantageous from the viewpoint of improving the electrostatic protection effect of the electrostatic protection circuit 500.

[0130] 7 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 1-3 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 1-3 may be referred to as an electrostatic protection circuit 513.

[0131] In Example 1-3, in plan view, the protective circuit region 420 is provided outside the guard ring 430. Specifically, in plan view, the protective circuit region 420 is provided between the through-electrode region 410 and the guard ring 430.

[0132] In Example 1-3, an electrostatic discharge protection circuit 513 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 513 includes a positive charge discharge circuit 513p and a negative charge discharge circuit 513n. The charge discharge circuits 513p and 513n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0133] 7, the impurity region 144p and the well 121n are connected to a power supply 451. The impurity region 144n and the well 122p are connected to a ground 452.

[0134] In the protection circuit region 420, a positive charge discharging circuit 513p including a well 121n, an impurity region 144p, and an impurity region 141p is formed. A negative charge discharging circuit 513n including a well 122p, an impurity region 144n, and an impurity region 142n is formed.

[0135] In the imaging device 1 configured as above, a bipolar transistor is configured in the electrostatic protection circuit 513 according to Example 1-3. The bipolar transistor provides electrostatic protection against both positive and negative charges.

[0136] The positive charge discharging circuit 513p includes a pnp bipolar transistor 630p including a well 121n, an impurity region 144p, and an impurity region 141p. The well 121n serves as a base 631b. The impurity region 141p serves as an emitter 631e. The impurity region 144p serves as a collector 631c.

[0137] As the accumulation of positive charge in the wiring 450 progresses, the voltage between the base 631b and the emitter 631e of the PNP bipolar transistor 630p decreases, turning on the PNP bipolar transistor 630p. As a result, the positive charge in the wiring 450 flows out to the power supply 451 via the PNP bipolar transistor 630p. In this way, the positive charge discharge circuit 513p provides an escape route for the positive charge in the wiring 450 to escape. This can prevent electrostatic breakdown due to positive charge. This electrostatic breakdown prevention mechanism also applies to the positive charge discharge circuit 523p of Example 2-3, the positive charge discharge circuit 533p of Example 3-3, the positive charge discharge circuit 543p of Example 4-3, and the positive charge discharge circuit 553p of Example 5-3.

[0138] The negative charge discharging circuit 513n includes an npn bipolar transistor 630n including a well 122p, an impurity region 144n, and an impurity region 142n. The well 122p serves as a base 632b. The impurity region 142n serves as a collector 632c. The impurity region 144n serves as an emitter 632e.

[0139] As negative charge accumulation in the wiring 450 progresses, the voltage between the base 632b and collector 632c of the npn bipolar transistor 630n increases, turning on the npn bipolar transistor 630n. This causes the negative charge in the wiring 450 to flow to ground 452 via the npn bipolar transistor 630n. In this way, the negative charge discharge circuit 513n provides an escape route for the negative charge in the wiring 450 to escape. This can prevent electrostatic discharge damage caused by negative charge. This electrostatic discharge damage prevention mechanism also applies to the negative charge discharge circuit 523n of Example 2-3, the negative charge discharge circuit 533n of Example 3-3, the negative charge discharge circuit 543n of Example 4-3, and the negative charge discharge circuit 553n of Example 5-3.

[0140] In Example 1-3, a pnp bipolar transistor 630p that releases positive charges is configured in the positive charge discharge circuit 513p, and an npn bipolar transistor 630n that releases negative charges is configured in the negative charge discharge circuit 513n. Therefore, the electrostatic protection circuit 513 according to Example 1-3 can release both positive and negative charges.

[0141] 25A is an explanatory diagram of a bipolar transistor-type electrostatic discharge protection circuit 500 according to Examples 1-3, which provides protection against both positive and negative charges. Specifically, (a) of FIG. 25A shows an equivalent circuit of bipolar transistors 630p and 630n configured in charge drain circuits 513p and 513n. (b) of FIG. 25A shows a schematic diagram of bipolar transistors 630p and 630n. Note that (a) of Figure 25A is: - an equivalent circuit of the bipolar transistors 630p and 630n configured in the charge discharge circuits 523p and 523n according to Example 2-3; - an equivalent circuit of the bipolar transistors 630p and 630n configured in the charge discharge circuits 533p and 533n according to Example 3-3; - an equivalent circuit of the bipolar transistors 630p and 630n configured in the charge discharge circuits 543p and 543n according to Example 4-3; and - an equivalent circuit of the bipolar transistors 630p and 630n configured in the charge discharge circuits 553p and 553n according to Example 5-3.

[0142] The electrostatic protection circuit 513 does not necessarily have to be configured to release both positive and negative charges, and may be configured to provide electrostatic protection against either positive or negative charges based on a bipolar transistor.

[0143] As the electrostatic protection circuit 513, it is also possible to adopt a configuration in which the positive charge discharging circuit 513p and the negative charge discharging circuit 513n are omitted and the negative charge discharging circuit 513n is left.

[0144] FIG. 24 is an explanatory diagram of a bipolar transistor-type electrostatic protection circuit 500 that serves as a countermeasure against negative charge. Specifically, FIG. 24(a) shows an equivalent circuit of an npn bipolar transistor 630n configured in a negative charge discharge circuit 513n. FIG. 24(b) shows a schematic diagram of the npn bipolar transistor 630n. Note that FIG. 24(a) is also: an equivalent circuit of the npn bipolar transistor 630n configured in a negative charge discharge circuit 523n according to Example 2-3; an equivalent circuit of the npn bipolar transistor 630n configured in a negative charge discharge circuit 533n according to Example 3-3; an equivalent circuit of the npn bipolar transistor 630n configured in a negative charge discharge circuit 543n according to Example 4-3; and an equivalent circuit of the npn bipolar transistor 630n configured in a negative charge discharge circuit 553n according to Example 5-3.

[0145] It is also possible to adopt a configuration in which the negative charge discharge circuit 513n is omitted and only the positive charge discharge circuit 513p is left as the electrostatic protection circuit 513. The electrostatic protection circuit 513 according to this configuration is a bipolar transistor type electrostatic protection circuit that acts as a countermeasure against positive charges.

[0146] The same is true for Examples 2-3, 3-3, 4-3, and 5-3, where either the electrostatic protection circuit configured with a pnp bipolar transistor that releases positive charges or the electrostatic protection circuit configured with an npn bipolar transistor that releases negative charges can be omitted.

[0147] The bipolar transistor type electrostatic protection circuit 500 has the advantage of being easy to fabricate, which is advantageous from the viewpoint of fabricating the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the imaging device 1.

[0148] [Example 2-1] Fig. 8A is a plan view illustrating an electrostatic protection circuit 500 according to Example 2-1 of Embodiment 1. Fig. 8B is a cross-sectional view illustrating the electrostatic protection circuit 500 according to Example 2-1 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 2-1 may be referred to as an electrostatic protection circuit 521. Note that Fig. 8A is also a plan view illustrating the electrostatic protection circuits 500 according to Examples 2-2 and 2-3.

[0149] In Example 2-1, the protective circuit region 420 is provided in the guard ring 430 in plan view.

[0150] An isolation 177 is provided between a portion of the well 121p on the side of the through electrode region 410 and a portion on the side of the guard ring 430. The isolation 177 is a structure formed in the first semiconductor substrate 100 by, for example, an STI process.

[0151] In Example 2-1, an electrostatic protection circuit 521 is provided in the protection circuit region 420. The electrostatic protection circuit 521 includes a positive charge discharge circuit 521p and a negative charge discharge circuit 521n. The charge discharge circuits 521p and 521n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0152] 8B , impurity region 141n and impurity region 141p are provided in well 122n. Impurity region 141n is an n-type impurity region. Impurity region 141p is a p-type impurity region. The concentration of n-type impurity in impurity region 141n is higher than the concentration of n-type impurity in well 122n. Impurity region 141p is connected to wiring 450. Impurity region 141n is connected to a power supply 451.

[0153] In the protection circuit region 420, a positive charge discharging circuit 521p including a well 122n, an impurity region 141n, and an impurity region 141p is formed. A negative charge discharging circuit 521n including a well 121p, an impurity region 142p, and an impurity region 142n is formed.

[0154] In the imaging device 1 configured as above, a diode is configured in the electrostatic protection circuit 521 according to Example 2-1. The diode provides electrostatic protection against both positive and negative charges.

[0155] In the positive charge discharging circuit 521p, the impurity region 141p and the well 122n form a diode 610pn. The impurity region 141p is a p-type region of the diode 610pn. The well 122n is an n-type region of the diode 610pn.

[0156] In the negative charge discharging circuit 521n, the impurity region 142n and the well 121p form a diode 610np. The impurity region 142n is an n-type region of the diode 610np. The well 121p is a p-type region of the diode 610np.

[0157] In Example 2-1, a diode 610pn that discharges positive charges is configured in the positive charge discharge circuit 521p, and a diode 610np that discharges negative charges is configured in the negative charge discharge circuit 521n. Therefore, the electrostatic protection circuit 521 according to Example 2-1 can discharge both positive and negative charges.

[0158] 9 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 2-2 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 2-2 may be referred to as an electrostatic protection circuit 522.

[0159] In Example 2-2, the protective circuit region 420 is provided in the guard ring 430 in plan view.

[0160] In Example 2-2, an electrostatic discharge protection circuit 522 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 522 includes a positive charge discharge circuit 522p and a negative charge discharge circuit 522n. The charge discharge circuits 522p and 522n will be specifically described below with reference to the first semiconductor substrate 100 and the configuration of its periphery.

[0161] 9 , an impurity region 144p and an impurity region 141p are provided in a well 122n. An impurity region 144n and an impurity region 142n are provided in a well 121p. In the protection circuit region 420, an insulating film 191 and an insulating film 192 are provided on a first semiconductor substrate 100. Specifically, the insulating film 191 is provided on the well 122n. The insulating film 192 is provided on the well 121p. An electrode 195 is provided on the insulating film 191. An electrode 196 is provided on the insulating film 192.

[0162] The impurity region 144p and the electrode 195 are connected to a power supply 451. The impurity region 144n and the electrode 196 are connected to a ground 452.

[0163] In the protection circuit region 420, a positive charge discharging circuit 522p is formed, which includes a well 122n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. A negative charge discharging circuit 522n is formed, which includes a well 121p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196.

[0164] In the imaging device 1 configured as described above, the electrostatic protection circuit 522 according to Example 2-2 is configured with a MOSFET. The MOSFET provides electrostatic protection against both positive and negative charges.

[0165] The positive charge discharging circuit 522p includes a p-type MOSFET 620p including a well 122n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. The impurity region 141p is a source 621s. The impurity region 144p is a drain 621d. The insulating film 191 is a gate oxide film. The electrode 195 is a gate 621g.

[0166] The negative charge discharging circuit 522n includes an n-type MOSFET 620n including a well 121p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196. The impurity region 142n is a source 622s. The impurity region 144n is a drain 622d. The insulating film 192 is a gate oxide film. The electrode 196 is a gate 622g.

[0167] In Example 2-2, a p-type MOSFET 620p that releases positive charges is configured in the positive charge discharge circuit 522p, and an n-type MOSFET 620n that releases negative charges is configured in the negative charge discharge circuit 522n. Therefore, the electrostatic protection circuit 522 according to Example 2-2 can release both positive and negative charges.

[0168] 10 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 2-3 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 2-3 may be referred to as an electrostatic protection circuit 523.

[0169] In Example 2-3, the protective circuit region 420 is provided in the guard ring 430 in plan view.

[0170] In Example 2-3, an electrostatic protection circuit 523 is provided in the protection circuit region 420. The electrostatic protection circuit 523 includes a positive charge discharge circuit 523p and a negative charge discharge circuit 523n. The charge discharge circuits 523p and 523n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0171] 10, the impurity region 144p and the well 122n are connected to a power supply 451. The impurity region 144n and the well 121p are connected to a ground 452.

[0172] In the protection circuit region 420, a positive charge discharging circuit 523p including the well 122n, the impurity region 144p, and the impurity region 141p is formed. A negative charge discharging circuit 523n including the well 121p, the impurity region 144n, and the impurity region 142n is formed.

[0173] In the imaging device 1 configured as above, a bipolar transistor is configured in the electrostatic protection circuit 523 according to Example 2-3. The bipolar transistor provides electrostatic protection against both positive and negative charges.

[0174] The positive charge discharging circuit 523p includes a pnp bipolar transistor 630p including a well 122n, an impurity region 144p, and an impurity region 141p. The well 122n serves as a base 631b. The impurity region 141p serves as an emitter 631e. The impurity region 144p serves as a collector 631c.

[0175] The negative charge discharging circuit 523n includes an npn bipolar transistor 630n including a well 121p, an impurity region 144n, and an impurity region 142n. The well 121p serves as a base 632b. The impurity region 142n serves as a collector 632c. The impurity region 144n serves as an emitter 632e.

[0176] In Example 2-3, a pnp bipolar transistor 630p that releases positive charges is configured in the positive charge discharge circuit 523p, and an npn bipolar transistor 630n that releases negative charges is configured in the negative charge discharge circuit 523n. Therefore, the electrostatic protection circuit 523 according to Example 2-3 can release both positive and negative charges.

[0177] [Example 3-1] Fig. 11A is a plan view illustrating an electrostatic protection circuit 500 according to Example 3-1 of Embodiment 1. Fig. 11B is a cross-sectional view illustrating the electrostatic protection circuit 500 according to Example 3-1 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 3-1 may be referred to as an electrostatic protection circuit 531. Note that Fig. 11A is also a plan view illustrating the electrostatic protection circuits 500 according to Examples 3-2 and 3-3.

[0178] In Example 3-1, in plan view, the protective circuit region 420 is provided inside the guard ring 430. Specifically, in plan view, the protective circuit region 420 is provided between the guard ring 430 and the pixel array 470.

[0179] As shown in FIG. 11B, in guard ring 430, first semiconductor substrate 100 includes support substrate 111, semiconductor region 112, well 121p, well 124n, well 124p, impurity region 143p1, impurity region 143n, and impurity region 143p2.

[0180] A semiconductor region 112 is provided above the support substrate 111. A well 121p, a well 124n, and a well 124p are provided above the semiconductor region 112.

[0181] An isolation 178 is provided between a portion of well 121p on the through-electrode region 410 side and a portion of well 124n side. An isolation 179 is provided between well 121p and well 124n. An isolation 180 is provided between well 124n and well 124p. An isolation 181 is provided between a portion of well 124p on the well 124n side and a portion of well 124p on the protection circuit region 420 side. The isolations 178, 179, 180, 181, and 182 are structures formed in first semiconductor substrate 100 by, for example, an STI process.

[0182] An impurity region 143p1 is provided in the well 121p. The well 121p is a p-type well. The impurity region 143p1 is a p-type impurity region. The concentration of the p-type impurity in the impurity region 143p1 is higher than the concentration of the p-type impurity in the well 121p. The impurity region 143p1 is connected to a wiring 453.

[0183] An impurity region 143n is provided in the well 124n. The well 124n is an n-type well. The impurity region 143n is an n-type impurity region. The concentration of n-type impurities in the impurity region 143n is higher than the concentration of n-type impurities in the well 124n. The impurity region 143n is connected to a wiring 454.

[0184] An impurity region 143p2 is provided in the well 124p. The well 124p is a p-type well. The impurity region 143p2 is a p-type impurity region. The concentration of the p-type impurity in the impurity region 143p2 is higher than the concentration of the p-type impurity in the well 124p. The impurity region 143p2 is connected to a wiring 455.

[0185] A voltage is applied to well 121p via interconnect 453 and impurity region 143p1 in this order, a voltage is applied to well 124n via interconnect 454 and impurity region 143n in this order, and a voltage is applied to well 124p via interconnect 455 and impurity region 143p2 in this order.

[0186] In Example 3-1, an electrostatic discharge protection circuit 531 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 531 includes a positive charge discharge circuit 531p and a negative charge discharge circuit 531n. The charge discharge circuits 531p and 531n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0187] 11B , in the protection circuit region 420, the first semiconductor substrate 100 includes a support substrate 111, a semiconductor region 112, a well 125n, a well 123p, an impurity region 141n, an impurity region 141p, an impurity region 142p, and an impurity region 142n. The semiconductor region 112 is provided above the support substrate 111. The well 125n and the well 123p are provided above the semiconductor region 112.

[0188] Between the well 124p and the well 125n, an isolation 182 is provided. Between the well 125n and the well 123p, an isolation 183 is provided. The isolations 182 and 183 are structures formed in the first semiconductor substrate 100 by, for example, an STI process.

[0189] An impurity region 141n and an impurity region 141p are provided in the well 125n. The well 125n is an n-type well. The impurity region 141n is an n-type impurity region. The impurity region 141p is a p-type impurity region. The concentration of the n-type impurity in the impurity region 141n is higher than the concentration of the n-type impurity in the well 125n. The impurity region 141p is connected to an interconnect 450. The impurity region 141n is connected to a power supply 451.

[0190] An impurity region 142p and an impurity region 142n are provided in the well 123p. The well 123p is a p-type well. The impurity region 142n is an n-type impurity region. The impurity region 142p is a p-type impurity region. The concentration of the p-type impurity in the impurity region 142p is higher than the concentration of the p-type impurity in the well 123p. The impurity region 142n is connected to a wiring 450. The impurity region 142p is connected to a ground 452.

[0191] In the protection circuit region 420, a positive charge discharging circuit 531p is formed including a well 125n, an impurity region 141n, and an impurity region 141p. A negative charge discharging circuit 531n is formed including a well 123p, an impurity region 142p, and an impurity region 142n.

[0192] In the imaging device 1 configured as above, a diode is configured in the electrostatic protection circuit 531 according to Example 3-1. The diode provides electrostatic protection against both positive and negative charges.

[0193] In the positive charge discharging circuit 531p, the impurity region 141p and the well 125n form a diode 610pn. The impurity region 141p is a p-type region of the diode 610pn. The well 125n is an n-type region of the diode 610pn.

[0194] In the negative charge discharging circuit 531n, the impurity region 142n and the well 123p form a diode 610np. The impurity region 142n is an n-type region of the diode 610np. The well 123p is a p-type region of the diode 610np.

[0195] In Example 3-1, a diode 610pn that discharges positive charges is configured in the positive charge discharge circuit 531p, and a diode 610np that discharges negative charges is configured in the negative charge discharge circuit 531n. Therefore, the electrostatic protection circuit 531 according to Example 3-1 can discharge both positive and negative charges.

[0196] 12 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 3-2 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 3-2 may be referred to as an electrostatic protection circuit 532.

[0197] In Example 3-2, in plan view, the protective circuit region 420 is provided inside the guard ring 430. Specifically, in plan view, the protective circuit region 420 is provided between the guard ring 430 and the pixel array 470.

[0198] In Example 3-2, an electrostatic discharge protection circuit 532 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 532 includes a positive charge discharge circuit 532p and a negative charge discharge circuit 532n. The charge discharge circuits 532p and 532n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0199] 12 , impurity regions 144p and 141p are provided in well 125n. Impurity regions 144n and 142n are provided in well 123p. Insulating films 191 and 192 are provided on first semiconductor substrate 100 in protection circuit region 420. Specifically, insulating film 191 is provided on well 125n. Insulating film 192 is provided on well 123p. An electrode 195 is provided on insulating film 191. An electrode 196 is provided on insulating film 192.

[0200] The impurity region 144p and the electrode 195 are connected to a power supply 451. The impurity region 144n and the electrode 196 are connected to a ground 452.

[0201] In the protection circuit region 420, a positive charge discharging circuit 532p is formed, which includes a well 125n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. A negative charge discharging circuit 532n is formed, which includes a well 123p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196.

[0202] In the imaging device 1 configured as above, the electrostatic protection circuit 532 according to Example 3-2 is configured with a MOSFET. The MOSFET provides electrostatic protection against both positive and negative charges.

[0203] The positive charge discharging circuit 532p includes a p-type MOSFET 620p including a well 125n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. The impurity region 141p is a source 621s. The impurity region 144p is a drain 621d. The insulating film 191 is a gate oxide film. The electrode 195 is a gate 621g.

[0204] The negative charge discharging circuit 532n includes an n-type MOSFET 620n including a well 123p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196. The impurity region 142n is a source 622s. The impurity region 144n is a drain 622d. The insulating film 192 is a gate oxide film. The electrode 196 is a gate 622g.

[0205] In Example 3-2, a p-type MOSFET 620p that releases positive charges is configured in the positive charge discharge circuit 532p, and an n-type MOSFET 620n that releases negative charges is configured in the negative charge discharge circuit 532n. Therefore, the electrostatic protection circuit 532 according to Example 3-2 can release both positive and negative charges.

[0206] 13 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 3-3 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 3-3 may be referred to as an electrostatic protection circuit 533.

[0207] In Example 3-3, in plan view, the protective circuit region 420 is provided inside the guard ring 430. Specifically, in plan view, the protective circuit region 420 is provided between the guard ring 430 and the pixel array 470.

[0208] In Example 3-3, an electrostatic protection circuit 533 is provided in the protection circuit region 420. The electrostatic protection circuit 533 includes a positive charge discharge circuit 533p and a negative charge discharge circuit 533n. The charge discharge circuits 533p and 533n will be specifically described below with reference to the first semiconductor substrate 100 and the configuration of its periphery.

[0209] 13, the impurity region 144p and the well 125n are connected to a power supply 451. The impurity region 144n and the well 123p are connected to a ground 452.

[0210] In the protection circuit region 420, a positive charge discharging circuit 533p including a well 125n, an impurity region 144p, and an impurity region 141p is formed. A negative charge discharging circuit 533n including a well 123p, an impurity region 144n, and an impurity region 142n is formed.

[0211] In the imaging device 1 configured as described above, a bipolar transistor is configured in the electrostatic protection circuit 533 according to Example 3-3. The bipolar transistor provides electrostatic protection against both positive and negative charges.

[0212] The positive charge discharging circuit 533p includes a pnp bipolar transistor 630p including a well 125n, an impurity region 144p, and an impurity region 141p. The well 125n serves as a base 631b. The impurity region 141p serves as an emitter 631e. The impurity region 144p serves as a collector 631c.

[0213] The negative charge exhaust circuit 533n includes an npn bipolar transistor 630n including a well 123p, an impurity region 144n, and an impurity region 142n. The well 123p serves as a base 632b. The impurity region 142n serves as a collector 632c. The impurity region 144n serves as an emitter 632e.

[0214] In Example 3-3, a pnp bipolar transistor 630p that releases positive charges is configured in the positive charge discharge circuit 533p, and an npn bipolar transistor 630n that releases negative charges is configured in the negative charge discharge circuit 533n. Therefore, the electrostatic protection circuit 533 according to Example 3-3 can release both positive and negative charges.

[0215] [Example 4-1] Fig. 14A is a plan view illustrating an electrostatic protection circuit 500 according to Example 4-1 of Embodiment 1. Fig. 14B is a cross-sectional view illustrating the electrostatic protection circuit 500 according to Example 4-1 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 4-1 may be referred to as an electrostatic protection circuit 541. Note that Fig. 14A is also a plan view illustrating the electrostatic protection circuits 500 according to Examples 4-2 and 4-3.

[0216] In Example 4-1, the protection circuit region 420 is provided in the dummy pixel 15 .

[0217] As shown in FIG. 14B, in the dummy pixel region 440, the first semiconductor substrate 100 includes a support substrate 111, a semiconductor region 112, a well 126n, a well 123p, an impurity region 141n, an impurity region 141p, an impurity region 142p, and an impurity region 142n.

[0218] A semiconductor region 112 is provided above the support substrate 111. A well 126n and a well 123p are provided above the semiconductor region 112.

[0219] Between the well 124p and the well 126n, an isolation 184 is provided. Between the well 126n and the well 123p, an isolation 185 is provided. The isolations 184 and 185 are structures formed in the first semiconductor substrate 100 by, for example, an STI process.

[0220] An impurity region 141n and an impurity region 141p are provided in the well 126n. The well 126n is an n-type well. The impurity region 141n is an n-type impurity region. The impurity region 141p is a p-type impurity region. The concentration of the n-type impurity in the impurity region 141n is higher than the concentration of the n-type impurity in the well 126n. The impurity region 141p is connected to a wiring 450. The impurity region 141n is connected to a power supply 451.

[0221] An impurity region 142p and an impurity region 142n are provided in the well 123p. The well 123p is a p-type well. The impurity region 142n is an n-type impurity region. The impurity region 142p is a p-type impurity region. The concentration of the p-type impurity in the impurity region 142p is higher than the concentration of the p-type impurity in the well 123p. The impurity region 142n is connected to a wiring 450. The impurity region 142p is connected to a ground 452.

[0222] In Example 4-1, an electrostatic discharge protection circuit 541 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 541 includes a positive charge discharge circuit 541p and a negative charge discharge circuit 541n. The charge discharge circuits 541p and 541n will be specifically described below with reference to the first semiconductor substrate 100 and the configuration of its periphery.

[0223] In the protection circuit region 420, a positive charge discharging circuit 541p is formed including a well 126n, an impurity region 141n, and an impurity region 141p. A negative charge discharging circuit 541n is formed including a well 123p, an impurity region 142p, and an impurity region 142n.

[0224] In the imaging device 1 configured as above, a diode is configured in the electrostatic protection circuit 541 according to Example 4-1. The diode provides electrostatic protection against both positive and negative charges.

[0225] In the positive charge discharging circuit 541p, the impurity region 141p and the well 126n form a diode 610pn. The impurity region 141p is a p-type region of the diode 610pn. The well 126n is an n-type region of the diode 610pn.

[0226] In the negative charge discharging circuit 541n, the impurity region 142n and the well 123p form a diode 610np. The impurity region 142n is an n-type region of the diode 610np. The well 123p is a p-type region of the diode 610np.

[0227] In Example 4-1, a diode 610pn that discharges positive charges is configured in the positive charge discharge circuit 541p, and a diode 610np that discharges negative charges is configured in the negative charge discharge circuit 541n. Therefore, the electrostatic protection circuit 541 according to Example 4-1 can discharge both positive and negative charges.

[0228] In Example 4-1, the electrostatic protection circuit 500 is provided in the dummy pixel 15. This is advantageous from the viewpoint of preventing an increase in the area of ​​the imaging device 1 in plan view due to the provision of the electrostatic protection circuit 500.

[0229] 15A is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 4-2 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 4-2 may be referred to as an electrostatic protection circuit 542.

[0230] In Example 4-2, the protection circuit region 420 is provided in the dummy pixel 15 .

[0231] In Example 4-2, an electrostatic protection circuit 542 is provided in the protection circuit region 420. The electrostatic protection circuit 542 includes a positive charge discharge circuit 542p and a negative charge discharge circuit 542n. The charge discharge circuits 542p and 542n will be specifically described below with reference to the first semiconductor substrate 100 and the configuration of its periphery.

[0232] 15A , impurity regions 144p and 141p are provided in well 126n. Impurity regions 144n and 142n are provided in well 123p. Insulating films 191 and 192 are provided on first semiconductor substrate 100 in protection circuit region 420. Specifically, insulating film 191 is provided on well 126n. Insulating film 192 is provided on well 123p. An electrode 195 is provided on insulating film 191. An electrode 196 is provided on insulating film 192.

[0233] The impurity region 144p and the electrode 195 are connected to a power supply 451. The impurity region 144n and the electrode 196 are connected to a ground 452.

[0234] In the protection circuit region 420, a positive charge discharging circuit 542p is formed, which includes a well 126n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. A negative charge discharging circuit 542n is formed, which includes a well 123p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196.

[0235] In the imaging device 1 configured as above, the electrostatic protection circuit 542 according to Example 4-2 is configured with a MOSFET. The MOSFET provides electrostatic protection against both positive and negative charges.

[0236] The positive charge discharging circuit 542p includes a p-type MOSFET 620p including a well 126n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. The impurity region 141p is a source 621s. The impurity region 144p is a drain 621d. The insulating film 191 is a gate oxide film. The electrode 195 is a gate 621g.

[0237] The negative charge discharging circuit 542n includes an n-type MOSFET 620n including a well 123p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196. The impurity region 142n is a source 622s. The impurity region 144n is a drain 622d. The insulating film 192 is a gate oxide film. The electrode 196 is a gate 622g.

[0238] In Example 4-2, a p-type MOSFET 620p that releases positive charges is configured in the positive charge discharge circuit 542p, and an n-type MOSFET 620n that releases negative charges is configured in the negative charge discharge circuit 542n. Therefore, the electrostatic protection circuit 542 according to Example 4-2 can release both positive and negative charges.

[0239] 15B is a planar layout of the signal pixels 10 and the dummy pixels 15 according to a specific example of Example 4-2. Specifically, FIG. 15B shows an example of configuring an electrostatic protection circuit 500 including an n-type MOSFET 620 n in the first embodiment.

[0240] 15B , the gate 311 e of the amplification transistor 311 is connected to the charge storage unit 335. The gate 312 e of the selection transistor 312 is connected to the address control line 351. The gate 313 e of the reset transistor 313 is connected to the reset control line 352.

[0241] 15B, the source 313s of the reset transistor 313 is connected to the reset control line 352. The gate 313e and the drain 313d of the reset transistor 313 are connected to the ground 370. With such connections, the reset transistor 313 functions as an n-type MOSFET 620n.

[0242] Specifically, as the accumulation of negative charge in the reset control line 352 progresses, the voltage between the gate 313e and the source 313s of the reset transistor 313 rises, turning on the reset transistor 313. As a result, the negative charge in the reset control line 352 flows out to the ground 370 via the source 313s, the channel region under the gate 312e, and the drain 313d in this order. In this way, the negative charge in the reset control line 352 flows out to the ground 370 via the reset transistor 313.

[0243] In the dummy pixel 15, the source 312s of the selection transistor 312 is connected to the address control line 351. One impurity region serves as both the drain 312d of the selection transistor 312 and the source 311s of the amplification transistor 311. The gate 312e of the selection transistor 312, the gate 311e of the amplification transistor 311, and the drain 311d of the amplification transistor 311 are connected to ground 370. With this connection, the combination of the selection transistor 312 and the amplification transistor 311 constitutes a series-connected n-type MOSFET, and behaves as if it were an n-type MOSFET 620n.

[0244] Specifically, as the accumulation of negative charge in the address control line 351 progresses, the voltage between the gate 312e and the source 312s of the selection transistor 312 rises, turning on the selection transistor 312. As a result, the negative charge in the address control line 351 flows into the drain 312d, i.e., the source 311s, via the source 312s and the channel region below the gate 312e, in that order. As the flow of negative charge into the source 311s progresses, the voltage between the gate 311e and the source 311s of the amplification transistor 311 rises, turning on the amplification transistor 311. As a result, the negative charge in the source 311s flows out to the ground 370 via the channel region below the gate 311e and the drain 311d, in that order. In this way, the combination of the selection transistor 312 and the amplification transistor 311 constitutes a series-connected n-type MOSFET, and behaves as if it were an n-type MOSFET 620n. In this way, the negative charge on the address control line 351 is bled off to ground 370 through the combination of the select transistor 312 and the amplifying transistor 311 .

[0245] 16 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 4-3 of Embodiment 1. Hereinafter, the electrostatic protection circuit 500 according to Example 4-3 may be referred to as an electrostatic protection circuit 543.

[0246] In Example 4-3, the protection circuit region 420 is provided in the dummy pixel 15 .

[0247] In Example 4-3, an electrostatic discharge protection circuit 543 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 543 includes a positive charge discharge circuit 543p and a negative charge discharge circuit 543n. The charge discharge circuits 543p and 543n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0248] 16, the impurity region 144p and the well 126n are connected to a power supply 451. The impurity region 144n and the well 123p are connected to a ground 452.

[0249] In the protection circuit region 420, a positive charge discharging circuit 543p including a well 126n, an impurity region 144p, and an impurity region 141p is formed. A negative charge discharging circuit 543n including a well 123p, an impurity region 144n, and an impurity region 142n is formed.

[0250] In the imaging device 1 configured as above, a bipolar transistor is configured in the electrostatic protection circuit 543 according to Example 4-3. The bipolar transistor provides electrostatic protection against both positive and negative charges.

[0251] The positive charge discharging circuit 543p includes a pnp bipolar transistor 630p including a well 126n, an impurity region 144p, and an impurity region 141p. The well 126n serves as a base 631b. The impurity region 141p serves as an emitter 631e. The impurity region 144p serves as a collector 631c.

[0252] The negative charge discharging circuit 543n includes an npn bipolar transistor 630n including a well 123p, an impurity region 144n, and an impurity region 142n. The well 123p serves as a base 632b. The impurity region 142n serves as a collector 632c. The impurity region 144n serves as an emitter 632e.

[0253] In Example 4-3, a pnp bipolar transistor 630p that releases positive charges is configured in the positive charge discharge circuit 543p, and an npn bipolar transistor 630n that releases negative charges is configured in the negative charge discharge circuit 543n. Therefore, the electrostatic protection circuit 543 according to Example 4-3 can release both positive and negative charges.

[0254] [Example 5-1] FIG. 17A is a plan view illustrating an electrostatic protection circuit 500 according to Example 5-1 of Embodiment 1. FIG. 17B is a cross-sectional view illustrating the electrostatic protection circuit 500 according to Example 5-1 of Embodiment 1. In FIG. 17B, the dummy pixels 15 are omitted from the illustration. Hereinafter, the electrostatic protection circuit 500 according to Example 5-1 may be referred to as an electrostatic protection circuit 551. Note that FIG. 17A is also a plan view illustrating the electrostatic protection circuits 500 according to Examples 5-2 and 5-3.

[0255] In Example 5-1, the protective circuit region 420 is provided in the OB region 480. The protective circuit region 420 is located below the light-shielding film 360 so as to overlap with the light-shielding film 360 in a plan view.

[0256] As shown in FIG. 17B, in the OB region 480, the first semiconductor substrate 100 includes a support substrate 111, a semiconductor region 112, a well 124p, a well 127n, a well 123p, an impurity region 141n, an impurity region 141p, an impurity region 142p, and an impurity region 142n.

[0257] A semiconductor region 112 is provided above the support substrate 111. A well 124p, a well 127n, and a well 123p are provided above the semiconductor region 112.

[0258] Between the well 124p and the well 127n, an isolation 186 is provided. Between the well 127n and the well 123p, an isolation 187 is provided. The isolations 186 and 187 are structures formed in the first semiconductor substrate 100 by, for example, an STI process.

[0259] In the OB region 480, a transistor 472 is provided on the first semiconductor substrate 100. Specifically, the transistor 472 is provided in the well 124p. The transistor 472 is included in the OB pixel 12. In the first embodiment, the transistor 472 is a MOSFET.

[0260] An impurity region 141n and an impurity region 141p are provided in the well 127n. The well 127n is an n-type well. The impurity region 141n is an n-type impurity region. The impurity region 141p is a p-type impurity region. The concentration of the n-type impurity in the impurity region 141n is higher than the concentration of the n-type impurity in the well 127n. The impurity region 141p is connected to an interconnect 450. The impurity region 141n is connected to a power supply 451.

[0261] An impurity region 142p and an impurity region 142n are provided in the well 123p. The well 123p is a p-type well. The impurity region 142n is an n-type impurity region. The impurity region 142p is a p-type impurity region. The concentration of the p-type impurity in the impurity region 142p is higher than the concentration of the p-type impurity in the well 123p. The impurity region 142n is connected to a wiring 450. The impurity region 142p is connected to a ground 452.

[0262] In the protection circuit region 420, a positive charge discharging circuit 551p is formed including a well 127n, an impurity region 141n, and an impurity region 141p. A negative charge discharging circuit 551n is formed including a well 123p, an impurity region 142p, and an impurity region 142n.

[0263] In the imaging device 1 configured as above, a diode is configured in the electrostatic protection circuit 551 according to Example 5-1. The diode provides electrostatic protection against both positive and negative charges.

[0264] In the positive charge discharging circuit 551p, the impurity region 141p and the well 127n form a diode 610pn. The impurity region 141p is a p-type region of the diode 610pn. The well 127n is an n-type region of the diode 610pn.

[0265] In the negative charge discharging circuit 551n, the impurity region 142n and the well 123p form a diode 610np. The impurity region 142n is an n-type region of the diode 610np. The well 123p is a p-type region of the diode 610np.

[0266] In Example 5-1, a diode 610pn that releases positive charges is configured in the positive charge discharge circuit 551p, and a diode 610np that releases negative charges is configured in the negative charge discharge circuit 551n. Therefore, the electrostatic protection circuit 551 according to Example 5-1 can release both positive and negative charges.

[0267] As described above, in Example 5-1, the electrostatic protection circuit 500 is provided in the OB region 480. In one example, the electrostatic protection circuit 500 is provided in the space for the OB pixels 12 in the OB region 480, instead of the OB pixels 12. Doing so is advantageous from the viewpoint of preventing an increase in the planar area of ​​the imaging device 1 due to the provision of the electrostatic protection circuit 500.

[0268] [Example 5-2] Fig. 18 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 5-2 of Embodiment 1. In Fig. 18, the dummy pixels 15 are omitted from the illustration. Hereinafter, the electrostatic protection circuit 500 according to Example 5-2 may be referred to as an electrostatic protection circuit 552.

[0269] In Example 5-2, the protective circuit region 420 is provided in the OB region 480. The protective circuit region 420 is located below the light-shielding film 360 so as to overlap with the light-shielding film 360 in a plan view.

[0270] In Example 5-2, an electrostatic protection circuit 552 is provided in the protection circuit region 420. The electrostatic protection circuit 552 includes a positive charge discharge circuit 552p and a negative charge discharge circuit 552n. The charge discharge circuits 552p and 552n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0271] 18 , impurity regions 144p and 141p are provided in well 127n. Impurity regions 144n and 142n are provided in well 123p. Insulating films 191 and 192 are provided on first semiconductor substrate 100 in protection circuit region 420. Specifically, insulating film 191 is provided on well 127n. Insulating film 192 is provided on well 123p. An electrode 195 is provided on insulating film 191. An electrode 196 is provided on insulating film 192.

[0272] The impurity region 144p and the electrode 195 are connected to a power supply 451. The impurity region 144n and the electrode 196 are connected to a ground 452.

[0273] In the protection circuit region 420, a positive charge discharging circuit 552p is formed, which includes a well 127n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. A negative charge discharging circuit 552n is formed, which includes a well 123p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196.

[0274] In the imaging device 1 configured as above, the electrostatic protection circuit 552 according to Example 5-2 is configured with a MOSFET. The MOSFET provides electrostatic protection against both positive and negative charges.

[0275] The positive charge discharging circuit 552p includes a p-type MOSFET 620p including a well 127n, an impurity region 144p, an impurity region 141p, an insulating film 191, and an electrode 195. The impurity region 141p is a source 621s. The impurity region 144p is a drain 621d. The insulating film 191 is a gate oxide film. The electrode 195 is a gate 621g.

[0276] The negative charge discharging circuit 552n includes an n-type MOSFET 620n including a well 123p, an impurity region 144n, an impurity region 142n, an insulating film 192, and an electrode 196. The impurity region 142n is a source 622s. The impurity region 144n is a drain 622d. The insulating film 192 is a gate oxide film. The electrode 196 is a gate 622g.

[0277] In Example 5-2, a p-type MOSFET 620p that releases positive charges is configured in a positive charge discharge circuit 552p, and an n-type MOSFET 620n that releases negative charges is configured in a negative charge discharge circuit 552n. Therefore, the electrostatic protection circuit 552 according to Example 5-2 can release both positive and negative charges.

[0278] [Example 5-3] Fig. 19 is a cross-sectional view for explaining an electrostatic protection circuit 500 according to Example 5-3 of Embodiment 1. In Fig. 19, the dummy pixels 15 are omitted from the illustration. Hereinafter, the electrostatic protection circuit 500 according to Example 5-3 may be referred to as an electrostatic protection circuit 553.

[0279] In Example 5-3, the protective circuit region 420 is provided in the OB region 480. The protective circuit region 420 is located below the light-shielding film 360 so as to overlap with the light-shielding film 360 in a plan view.

[0280] In Example 5-3, an electrostatic discharge protection circuit 553 is provided in the protection circuit region 420. The electrostatic discharge protection circuit 553 includes a positive charge discharge circuit 553p and a negative charge discharge circuit 553n. The charge discharge circuits 553p and 553n will be specifically described below with reference to the configuration of the first semiconductor substrate 100 and its periphery.

[0281] 19, in the protection circuit region 420, the impurity region 144p and the well 127n are connected to a power supply 451. The impurity region 144n and the well 123p are connected to a ground 452.

[0282] In the protection circuit region 420, a positive charge discharging circuit 553p including a well 127n, an impurity region 144p, and an impurity region 141p is formed. A negative charge discharging circuit 553n including a well 123p, an impurity region 144n, and an impurity region 142n is formed.

[0283] In the imaging device 1 configured as above, a bipolar transistor is configured in the electrostatic protection circuit 553 according to Example 5-3. The bipolar transistor provides electrostatic protection against both positive and negative charges.

[0284] The positive charge discharging circuit 553p includes a pnp bipolar transistor 630p including a well 127n, an impurity region 144p, and an impurity region 141p. The well 127n serves as a base 631b. The impurity region 141p serves as an emitter 631e. The impurity region 144p serves as a collector 631c.

[0285] The negative charge exhaust circuit 553n includes an npn bipolar transistor 630n including a well 123p, an impurity region 144n, and an impurity region 142n. The well 123p serves as a base 632b. The impurity region 142n serves as a collector 632c. The impurity region 144n serves as an emitter 632e.

[0286] In Example 5-3, a pnp bipolar transistor 630p that releases positive charges is configured in the positive charge discharge circuit 553p, and an npn bipolar transistor 630n that releases negative charges is configured in the negative charge discharge circuit 553n. Therefore, the electrostatic protection circuit 553 according to Example 5-3 can release both positive and negative charges.

[0287] In Examples 1-1 to 5-3, at least one step for fabricating the electrostatic protection circuit 500 and at least one step for fabricating the effective pixels 11 may be a common step. Specifically, common steps may include a step for forming a well in the electrostatic protection circuit 500 and the effective pixels 11, a step for forming an impurity region in the electrostatic protection circuit 500 and the effective pixels 11, a step for forming a gate oxide film in the electrostatic protection circuit 500 and the effective pixels 11, and a step for forming a gate (gate electrode) in the electrostatic protection circuit 500 and the effective pixels 11. This is advantageous from the viewpoint of fabricating the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the imaging device 1.

[0288] If the electrostatic protection circuit 500 and the effective pixel 11 share a common process for forming wells, the impurity concentrations of the wells can be the same in the electrostatic protection circuit 500 and the effective pixel 11. If the electrostatic protection circuit 500 and the effective pixel 11 share a common process for forming impurity regions, the impurity concentrations of the impurity regions can be the same in the electrostatic protection circuit 500 and the effective pixel 11. If the electrostatic protection circuit 500 and the effective pixel 11 share a common process for forming gate oxide films, the thicknesses of the gate oxide films can be the same in the electrostatic protection circuit 500 and the effective pixel 11. If the electrostatic protection circuit 500 and the effective pixel 11 share a common process for forming gates, the thicknesses of the gates can be the same in the electrostatic protection circuit 500 and the effective pixel 11.

[0289] 26 is a detailed circuit diagram of an image pickup device 1 according to embodiment 2. In the image pickup device 1 of embodiment 2, the pixel 10 includes an overflow transistor 314. In embodiment 2, the overflow transistor 314 is a MOSFET.

[0290] One of the source and drain of the reset transistor 313 constitutes the charge storage unit 335. Also, one of the source and drain of the overflow transistor 314 constitutes the charge storage unit 335. In other words, the charge storage unit 335 is shared by the reset transistor 313 and the overflow transistor 314.

[0291] The photoelectric conversion unit 310 is connected to the charge accumulation unit 335, the gate of the overflow transistor 314, and the gate of the amplification transistor 311. Specifically, the pixel electrode 310b is connected to these.

[0292] A voltage is applied to the other of the source and drain of the overflow transistor 314 via the voltage line 324. As described above, the gate of the overflow transistor 314 is connected to the charge accumulation unit 335. When strong light is incident on the photoelectric conversion unit 310, the charge in the charge accumulation unit 335 increases, and the overflow transistor 314 is turned on. As a result, excess charge accumulated in the charge accumulation unit 335 is discharged via the overflow transistor 314. This protects the various transistors and ensures the safety of the imaging device 1.

[0293] Like the signal pixel 10 , the dummy pixel 15 according to the second embodiment includes an amplifier transistor 311 , a selection transistor 312 , a reset transistor 313 , and an overflow transistor 314 .

[0294] In the second embodiment, as shown in FIG. 26 , a protection circuit 500 may be provided for both the address control line 351 and the reset control line 352. In the second embodiment, a protection circuit 500 may be provided for only one of the address control line 351 and the reset control line 352. In the second embodiment, as shown in FIG. 26 , an electrostatic protection circuit that provides protection against both positive and negative charges may be provided. In the second embodiment, an electrostatic protection circuit that provides protection against either positive or negative charges may be provided.

[0295] In the second embodiment, a plurality of dummy pixels 15 are provided in the pixel array 470. The plurality of dummy pixels 15 include a first dummy pixel 15a and a second dummy pixel 15b. In the first dummy pixel 15a, various transistors are connected in a manner similar to that of the signal pixel 10. In the second dummy pixel 15b, various transistors are connected in a manner different from that of the first dummy pixel 15a. In the second dummy pixel 15b, an n-type MOSFET 620n is configured.

[0296] Fig. 27A is a circuit diagram showing a first dummy pixel 15a and a second dummy pixel 15b according to embodiment 2. Fig. 27B is a planar layout of the first dummy pixel 15a and the second dummy pixel 15b according to embodiment 2. Specifically, Fig. 27A and Fig. 27B show an example of configuring an electrostatic protection circuit 500 including an n-type MOSFET 620n in embodiment 2.

[0297] 27A (a) and 27B (a) show the first dummy pixel 15a. In the first dummy pixel 15a, the gate 311e of the amplification transistor 311, the gate 314e of the overflow transistor 314, and the charge storage unit 335 are connected. The gate 312e of the selection transistor 312 is connected to an address control line 351. The gate 313e of the reset transistor 313 is connected to a reset control line 352. As described above, the charge storage unit 335 is shared by the reset transistor 313 and the overflow transistor 314.

[0298] 27A (b) and 27B (b) show a second dummy pixel 15b. An n-type MOSFET 620n is configured in the second dummy pixel 15b. In the examples of FIGS. 27A (b) and 27B (b), the wiring 450 is one of the address control line 351 and the reset control line 352. When the wiring 450 is the address control line 351, electrostatic protection for the address control line 351 can be achieved. When the wiring 450 is the reset control line 352, electrostatic protection for the reset control line 352 can be achieved. One impurity region is shared by the reset transistor 313 and the overflow transistor 314. This impurity region also serves as the source 313s of the reset transistor 313 and the source 314s of the overflow transistor 314.

[0299] 27A(b) and 27B(b), the source 313s of the reset transistor 313 is connected to a wiring 450. The gate 313e and drain 313d of the reset transistor 313 are connected to a ground 370. With such connections, the reset transistor 313 functions as an n-type MOSFET 620n as shown within the dotted line in FIG.

[0300] Specifically, as the accumulation of negative charges in the wiring 450 progresses, the voltage between the gate 313e and the source 313s of the reset transistor 313 rises, turning on the reset transistor 313. As a result, the negative charges in the wiring 450 flow out to the ground 370 via the source 313s, the channel region under the gate 312e, and the drain 313d in this order. In this way, the negative charges in the wiring 450 flow out to the ground 370 via the reset transistor 313.

[0301] 27A(b) and 27B(b), the source 314s of the overflow transistor 314 is connected to the wiring 450. The gate 314e and the drain 314d of the overflow transistor 314 are connected to the ground 370. With such connections, the overflow transistor 314 functions as an n-type MOSFET 620n as shown within the dotted line in FIG.

[0302] Specifically, as the accumulation of negative charge in wiring 450 progresses, the voltage between gate 314e and source 314s of overflow transistor 314 rises, turning on overflow transistor 314. As a result, the negative charge in wiring 450 flows out to ground 370 via source 314s, the channel region below gate 314e, and drain 314d, in that order. In this way, the negative charge in wiring 450 flows out to ground 370 via overflow transistor 314.

[0303] 27A(b) and 27B(b), the source 312s of the selection transistor 312 is connected to the wiring 450. One impurity region serves as both the drain 312d of the selection transistor 312 and the source 311s of the amplification transistor 311. The gate 312e of the selection transistor 312, the gate 311e of the amplification transistor 311, and the drain 311d of the amplification transistor 311 are connected to ground 370. With this connection, the combination of the selection transistor 312 and the amplification transistor 311 constitutes a series-connected n-type MOSFET, and behaves as if it were an n-type MOSFET 620n as shown within the dotted line in FIG. 27A(b).

[0304] Specifically, as the accumulation of negative charge in the wiring 450 progresses, the voltage between the gate 312e and the source 312s of the selection transistor 312 increases, and the selection transistor 312 turns on. As a result, the negative charge in the wiring 450 flows into the drain 312d, i.e., the source 311s, via the source 312s and the channel region below the gate 312e, in that order. As the flow of negative charge into the source 311s progresses, the voltage between the gate 311e and the source 311s of the amplification transistor 311 increases, and the amplification transistor 311 turns on. As a result, the negative charge in the source 311s flows out to the ground 370 via the channel region below the gate 311e and the drain 311d, in that order. In this way, the combination of the selection transistor 312 and the amplification transistor 311 constitutes a series-connected n-type MOSFET, and behaves as if it were an n-type MOSFET 620n. In this way, the negative charge in the wiring 450 flows out to the ground 370 via the combination of the selection transistor 312 and the amplification transistor 311 .

[0305] 28 is a detailed circuit diagram of an image pickup device 1 according to a third embodiment. In the image pickup device 1 of the third embodiment, the photoelectric conversion unit 310 includes a photodiode 710. Furthermore, the pixel 10 includes a transfer transistor 315. In the third embodiment, the transfer transistor 315 is a MOSFET.

[0306] The photodiode 710 is connected to one of the source and drain of the transfer transistor 315. The other of the source and drain of the transfer transistor 315 constitutes the charge accumulation unit 335. In addition, one of the source and drain of the reset transistor 313 constitutes the charge accumulation unit 335. In other words, the charge accumulation unit 335 is shared by the reset transistor 313 and the transfer transistor 315. The charge accumulation unit 335 is connected to the gate of the amplification transistor 311.

[0307] The photodiode 710 converts light into an electric charge, and the transfer transistor 315 transfers the electric charge from the photodiode 710 to the charge storage unit 335.

[0308] The plurality of drivers 280 includes a plurality of transfer drivers 283. The wiring layer 150 includes a transfer control line 353.

[0309] The transfer driver 283 is connected to the gate of the transfer transistor 315 via a transfer control line 353. A voltage is supplied from the transfer driver 283 to the gate of the transfer transistor 315 in the pixel 10 selected by the row scanning circuit 80 via the transfer control line 353. This turns on the transfer transistor 315. This causes charge to be transferred from the photodiode 710 to the charge accumulation unit 335 via the transfer transistor 315.

[0310] In the third embodiment, the wiring 450 can be the transfer control line 353. In this way, the electrostatic protection circuit 500 can protect the transfer control line 353 and the transfer transistor 315.

[0311] In the third embodiment, as shown in FIG. 28 , a protection circuit 500 may be provided for all of the transfer transistor 315, the address control line 351, and the reset control line 352. In the third embodiment, a protection circuit 500 may be provided for one or two of the transfer transistor 315, the address control line 351, and the reset control line 352. In the third embodiment, as shown in FIG. 28 , an electrostatic protection circuit that serves as a measure against both positive and negative charges may be provided. In the third embodiment, an electrostatic protection circuit that serves as a measure against either positive or negative charges may be provided.

[0312] In one example of the third embodiment, the signal transistor 471 is the selection transistor 312. The wiring 450 is the address control line 351.

[0313] In one example of the third embodiment, the signal transistor 471 is the reset transistor 313. The wiring 450 is the reset control line 352.

[0314] In one example of the third embodiment, the signal transistor 471 is the transfer transistor 315. The wiring 450 is the transfer control line 353.

[0315] Fourth Embodiment In a fourth embodiment, the pixel 10 includes a feedback transistor. The wiring 450 includes a feedback control line. The plurality of transfer drivers 283 includes a plurality of feedback drivers. As the feedback transistor, for example, one described in Patent Document 2 can be adopted. In the fourth embodiment, the feedback transistor is a MOSFET.

[0316] In the fourth embodiment, the feedback driver is connected to the gate of the feedback transistor via a feedback control line. A voltage is supplied from the feedback driver via the feedback control line to the gate of the feedback transistor in the pixel 10 selected by the row scanning circuit 80. This controls the feedback transistor.

[0317] In the fourth embodiment, the wiring 450 may be a feedback control line. In this way, the ESD protection circuit 500 can protect the feedback control line and the feedback transistor.

[0318] In the fourth embodiment, the protection circuit 500 may be provided for all of the address control line 351, the reset control line 352, and the feedback control line. In the fourth embodiment, the protection circuit 500 may be provided for one or two of the address control line 351, the reset control line 352, and the feedback control line. In the fourth embodiment, an electrostatic protection circuit that provides protection against both positive and negative charges may be provided. In the fourth embodiment, an electrostatic protection circuit that provides protection against either positive or negative charges may be provided.

[0319] In one example of the fourth embodiment, the signal transistor 471 is the selection transistor 312. The wiring 450 is the address control line 351.

[0320] In one example of the fourth embodiment, the signal transistor 471 is the reset transistor 313. The wiring 450 is the reset control line 352.

[0321] In one example of the fourth embodiment, the signal transistor 471 is a feedback transistor, and the wiring 450 is a feedback control line.

[0322] Fifth Embodiment A camera system 1000 according to this embodiment will be described with reference to FIG.

[0323] 29 schematically shows an example configuration of a camera system 1000 according to this embodiment. The camera system 1000 includes a lens optical system 1100, an imaging device 1200, a system controller 1300, and a camera signal processing circuit 1400. The camera system 1000 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0324] The lens optical system 1100 may include a lens group including, for example, an autofocus lens and a zoom lens, and an aperture. The lens optical system 1100 focuses light onto the imaging plane of the imaging device 1200. The imaging device 1200 can be any of the imaging devices 1 according to the first to fourth embodiments described above.

[0325] The system controller 1300 controls the entire camera system 1000. The system controller 1300 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0326] The camera signal processing circuit 1400 has a function of processing an output signal from the image capture device 1200. The camera signal processing circuit 1400 receives output data from the image capture device 1200 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The image capture device 1200 and the camera signal processing circuit 1400 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 1200 as a part thereof. The camera signal processing circuit 1400 is, for example, a DSP (Digital Signal Processor).

[0327] Various modifications can be applied to the first to fifth embodiments.

[0328] 2A, the image pickup device 1 is a front side illumination (FSI) type, but may be a back side illumination (BSI) type.

[0329] In the first to fifth embodiments, a plurality of dummy pixels 15 are arranged outside the array of signal pixels 10 in a plan view. In the example of Fig. 5C , one column is formed by the dummy pixels 15 on one side of the array in the row direction 401. One column is formed by the dummy pixels 15 on the other side of the array in the row direction 401. One row is formed by the dummy pixels 15 on one side of the array in the column direction 402. One row is formed by the dummy pixels 15 on the other side of the array in the column direction 402. Here, the row direction 401 is the direction in which the rows extend, which is the left-right direction in Fig. 5C . The column direction 402 is the direction in which the columns extend, which is the up-down direction in Fig. 5C .

[0330] However, two or more columns may be formed by dummy pixels 15 on one side of the array of signal pixels 10 in the row direction 401. Two or more columns may be formed by dummy pixels 15 on the other side of the array in the row direction 401. Two or more rows may be formed by dummy pixels 15 on one side of the array in the column direction 402. Two or more rows may be formed by dummy pixels 15 on the other side of the array in the column direction 402.

[0331] In the second embodiment, the pixel array 470 has both the first dummy pixel 15 a and the second dummy pixel 15 b. The pixel array 470 may have only one of the first dummy pixel 15 a and the second dummy pixel 15 b. Even if the pixel array 470 has only the second dummy pixel 15 b out of the first dummy pixel 15 a and the second dummy pixel 15 b, electrostatic protection is still achieved.

[0332] In the first to fifth embodiments, in a plan view, a plurality of OB pixels 12 are arranged outside the array of effective pixels 11. In the example of Fig. 5C, the light-shielding film 360 extends on one side of the array in a row direction 401, and one column is formed by the OB pixels 12. The light-shielding film 360 extends on one side of the array in a column direction 402, and one row is formed by the OB pixels 12.

[0333] The light-shielding film 360 may extend on the other side of the array in the row direction 401, and one column may be formed by the OB pixels 12. The light-shielding film 360 may extend on the other side of the array of effective pixels 11 in the column direction 402, and one row may be formed by the OB pixels 12.

[0334] On one side of the array of effective pixels 11 in the column direction 402, the light-shielding film 360 may extend, and multiple rows may be formed by the OB pixels 12. On the other side of the array in the column direction 402, the light-shielding film 360 may extend, and multiple rows may be formed by the OB pixels 12. On one side of the array in the row direction 401, the light-shielding film 360 may extend, and multiple columns may be formed by the OB pixels 12. On the other side of the array in the row direction 401, the light-shielding film 360 may extend, and multiple columns may be formed by the OB pixels 12.

[0335] In the first to fifth embodiments, the guard ring 430 has a closed frame shape in plan view so as to surround the pixel array 470. However, in plan view, there may be a portion in the closed frame-shaped region surrounding the pixel array 470 where the guard ring 430 is not present. For example, in plan view, the guard ring 430 may have an L-shape.

[0336] As described above, in the first to fifth embodiments, the electrostatic discharge protection circuit 500 can be configured using a diode, a MOSFET, and a bipolar transistor. The electrostatic discharge protection circuit 500 may also be configured using a thyristor. As in the case of using a diode, a MOSFET, and a bipolar transistor, when a thyristor is used, electrostatic discharge protection can be achieved by connecting the wiring 450 to the impurity region of the thyristor.

[0337] In the first to fifth embodiments, the first semiconductor substrate 100 and the second semiconductor substrate 200 are stacked on top of each other. The first semiconductor substrate 100 is provided with pixels 10. The second semiconductor substrate 200 is provided with a peripheral circuit 490. The peripheral circuit 490 controls the pixels 10. As can be understood from the above description, in this configuration, the components of the first semiconductor substrate 100 are likely to benefit from the electrostatic discharge protection effect provided by the electrostatic discharge protection circuit 500.

[0338] In the modified example, the pixels 10, the electrostatic protection circuit 500, and the peripheral circuit 490 are provided on the first semiconductor substrate 100. Even in the modified example, the electrostatic protection effect based on the electrostatic protection circuit 500 can be utilized. For example, in manufacturing the imaging device 1, in addition to the electrostatic protection effect based on the impurity region 230 of the peripheral circuit 490, the electrostatic protection effect based on the electrostatic protection circuit 500 can be utilized. These electrostatic protection effects work together to provide a high electrostatic protection effect in the pixels 10.

[0339] 25B is an explanatory diagram of a modified example of a bipolar transistor-type electrostatic discharge protection circuit 500 that provides a countermeasure against both positive and negative charges. The electrostatic discharge protection circuit 500 shown in FIG. 25B can be employed in Examples 1-3, 2-3, 3-3, 4-3, and 5-3. Furthermore, in Examples 1-3, 2-3, 3-3, 4-3, and 5-3, it is also possible to employ an electrostatic discharge protection circuit of a type in which one of the pnp bipolar transistor 630p and the npn bipolar transistor 630n is omitted from the configuration of FIG. 25B.

[0340] In the example of FIG. 4 , the electrostatic protection circuit 500 is a MOSFET-type electrostatic protection circuit shown in FIG. 23 . However, the electrostatic protection circuit 500 in the example of FIG. 4 may be changed to an electrostatic protection circuit of the type shown in FIG. 20 , FIG. 21 , FIG. 22 , FIG. 24 , FIG. 25A , or FIG. 25B . Furthermore, the electrostatic protection circuit 500 in the example of FIG. 4 may be changed to an electrostatic protection circuit of the type in which one of the pnp bipolar transistor 630 p and the npn bipolar transistor 630 n is omitted from the configuration of FIG. 25B . This possibility of change also applies to the electrostatic protection circuit 500 in the example of FIG. 26 and the protection circuit 500 in the example of FIG. 28 . In this way, various electrostatic protection circuits can be adopted in the embodiments.

[0341] Hereinafter, for convenience of explanation, the terms "first charge" and "second charge" may be used. However, the "first" in "first charge" and the "second" in "second charge" are not intended to limit the interpretation of the charges. The same applies to the first wiring and the first gate.

[0342] As can be understood from the above description, the imaging device 1 according to an example of the present disclosure includes a first semiconductor substrate 100, pixels 10, an electrostatic protection circuit 500, and first wiring. The first semiconductor substrate 100 includes a first impurity region and a second impurity region. The pixels 10 include a photoelectric conversion unit 310 and the first impurity region. The photoelectric conversion unit 310 converts incident light into a first charge. The electrostatic protection circuit 500 includes a second impurity region.

[0343] The first impurity region is, for example, the source or drain of the amplifier transistor 311, the selection transistor 312, the reset transistor 313, the overflow transistor 314, the transfer transistor 315, the feedback transistor, etc. The second impurity region is, for example, an impurity region included in the diode 610pn, the diode 610np, the MOSFET 620p, the MOSFET 620n, the bipolar transistor 630p, the bipolar transistor 630n, the thyristor, etc. configured in the electrostatic protection circuit 500.

[0344] The impurity concentration of the second impurity region is the same as the impurity concentration of the first impurity region. This configuration appears, for example, when the first impurity region and the second impurity region are fabricated using a common process. This configuration is advantageous from the perspective of fabricating the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the imaging device 1. Furthermore, this configuration makes it easy to prevent the impurity concentration of the second impurity region from being excessively high relative to the impurity concentration of the first impurity region. This can be advantageous from the perspective of suppressing dark current.

[0345] Here, the expression "the impurity concentration of the second impurity region is the same as the impurity concentration of the first impurity region" will be explained. Hereinafter, the impurity concentration at the position with the highest impurity concentration in the first impurity region will be referred to as the first peak concentration. The impurity concentration at the position with the highest impurity concentration in the second impurity region will be referred to as the second peak concentration. In this case, the above expression means that the ratio of the second peak concentration to the first peak concentration is 80% or more and 120% or less.

[0346] The first wiring is, for example, an address control line 351, a reset control line 352, a transfer control line 353, a feedback control line, and the like.

[0347] The first wiring connects the pixel 10 and the electrostatic protection circuit 500. With this configuration, the electrostatic protection circuit 500 can prevent electrostatic damage to the components of the pixel 10 and / or the first wiring. Therefore, this configuration is suitable for preventing damage to the components of the imaging device 1.

[0348] In one example, the electrostatic protection circuit 500 includes a third impurity region included in the first semiconductor substrate 100. The first wiring is connected to the second impurity region. A fixed potential is applied to the third impurity region. The second charge in the first wiring is discharged through the second impurity region and the third impurity region in this order. In one specific example, the electrostatic protection circuit 500 includes a transistor. As the accumulation of the second charge in the first wiring progresses, the transistor is turned on, and the discharge is performed.

[0349] The third impurity region is, for example, an impurity region included in the diode 610pn, the diode 610np, the MOSFET 620p, the MOSFET 620n, the bipolar transistor 630p, the bipolar transistor 630n, the thyristor, etc., which are configured in the electrostatic protection circuit 500. The fixed potential is, for example, the potential of the power supply 451, the potential of the ground 452, etc.

[0350] In one example, the imaging device 1 includes a peripheral circuit 490. The peripheral circuit 490 controls the pixel 10. The second impurity region is provided at a position different from that of the peripheral circuit 490.

[0351] In one example, the second impurity region is provided in, for example, the dummy pixel 15. This configuration is advantageous from the viewpoint of preventing an increase in the area of ​​the imaging device 1 in plan view due to the provision of the second impurity region.

[0352] In one example, the imaging device 1 includes a plurality of unit pixels 20 arranged one-dimensionally or two-dimensionally to form a repeating structure. The plurality of unit pixels 20 includes a plurality of signal pixels 10 and one or more dummy pixels 15. The signal pixels 10 output signals used to form an image. In a plan view, the one or more dummy pixels 15 are located outside the array of signal pixels 10. No signal for image formation is output from the one or more dummy pixels 15. Details of the dummy pixels 15 are as described in embodiment 1, etc.

[0353] In one example, in a plan view, a guard ring 430 is arranged outside the pixel array 470. The plurality of pixels 10 in the pixel array 470 includes one or more OB pixels 12. In a plan view, the OB pixels 12 are provided so as to overlap with the light-shielding film 360 in a plan view.

[0354] In one example, in a plan view, the second impurity region is provided outside the pixel array 470. Specifically, in a plan view, the second impurity region is provided between the guard ring 430 and the pixel array 470.

[0355] The second impurity region may be provided in the guard ring 430. In plan view, the second impurity region may be provided outside the guard ring 430. The second impurity region may be provided so as to overlap with the light-shielding film 360 in plan view.

[0356] In the following description, the first conductivity type and the second conductivity type are conductivity types of opposite polarity. Specifically, one of the first conductivity type and the second conductivity type is n-type, and the other of the first conductivity type and the second conductivity type is p-type.

[0357] In one example, the first semiconductor substrate 100 is of a first conductivity type. The first impurity region and the second impurity region are of a second conductivity type. In this configuration, the conductivity type of the first impurity region included in the pixel 10 and the conductivity type of the second impurity region included in the electrostatic discharge protection circuit 500 are of the same polarity. This can make the imaging device 1 easier to manufacture.

[0358] In one example, the electrostatic discharge protection circuit 500 includes a second impurity region and a third impurity region. The conductivity type of the second impurity region is the second conductivity type. The conductivity type of the third impurity region is the first conductivity type. The electrostatic discharge protection circuit 500 having this configuration can prevent both electrostatic discharge damage caused by positive charge and electrostatic discharge damage caused by negative charge.

[0359] The impurity concentration of the third impurity region may be the same as the impurity concentration of the first impurity region. The impurity concentration of the third impurity region may be the same as the impurity concentration of the second impurity region.

[0360] The third impurity region is, for example, an impurity region included in the diode 610pn, diode 610np, MOSFET 620p, MOSFET 620n, bipolar transistor 630p, bipolar transistor 630n, thyristor, etc., which are configured in the electrostatic protection circuit 500.

[0361] Here, the expression "the impurity concentration of the third impurity region is the same as the impurity concentration of the first impurity region" will be explained. Hereinafter, the impurity concentration at the position with the highest impurity concentration in the third impurity region will be referred to as the "third peak concentration." In this case, the above expression means that the ratio of the third peak concentration to the first peak concentration is 80% or more and 120% or less.

[0362] Here, the expression "the impurity concentration of the third impurity region is the same as the impurity concentration of the second impurity region" will be explained. This expression means that the ratio of the third peak concentration to the second peak concentration is 80% or more and 120% or less.

[0363] In one example, the pixel 10 includes a first transistor, one of the source and drain of which is a first impurity region, and the electrostatic discharge protection circuit 500 includes a second transistor, one of the source and drain of which is a second impurity region.

[0364] The first transistors are, for example, an amplifier transistor 311, a selection transistor 312, a reset transistor 313, an overflow transistor 314, a transfer transistor 315, a feedback transistor, etc. The second transistors are, for example, a MOSFET 620p, a MOSFET 620n, etc.

[0365] In one example, the thickness of the gate oxide film of the second transistor is the same as the thickness of the gate oxide film of the first transistor. This configuration appears, for example, when the gate oxide films of the first transistor and the second transistor are fabricated using a common process. This configuration is advantageous from the viewpoint of fabricating the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the image pickup device 1.

[0366] Here, the expression "the thickness of the gate oxide film of the second transistor is the same as the thickness of the gate oxide film of the first transistor" will be explained. Hereinafter, the thickness of the gate oxide film of the second transistor will be referred to as the second thickness. The thickness of the gate oxide film of the first transistor will be referred to as the first thickness. In this case, the above expression means that the ratio of the second thickness to the first thickness is 90% or more and 110% or less.

[0367] In one example, the electrostatic protection circuit 500 includes a third impurity region and a third transistor. The conductivity type of the third impurity region is the first conductivity type. One of the source and drain of the third transistor is the third impurity region. The electrostatic protection circuit 500 having this configuration can prevent both electrostatic breakdown due to positive charge and electrostatic breakdown due to negative charge.

[0368] In one example, the thickness of the gate oxide film of the third transistor is the same as the thickness of the gate oxide film of the first transistor. This configuration appears, for example, when the gate oxide films of the first transistor and the third transistor are fabricated using a common process. This configuration is advantageous from the viewpoint of fabricating the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the image pickup device 1.

[0369] The third transistor is, for example, a MOSFET 620p, a MOSFET 620n, or the like.

[0370] Here, the expression "the thickness of the gate oxide film of the third transistor is the same as the thickness of the gate oxide film of the first transistor" will be explained. Hereinafter, the thickness of the gate oxide film of the third transistor will be referred to as the "third thickness." In this case, the expression means that the ratio of the third thickness to the first thickness is 90% or more and 110% or less.

[0371] In one example, the pixel 10 includes a charge storage unit 335 and a reset transistor 313. The charge storage unit 335 stores a first charge. The reset transistor 313 initializes the first charge stored in the charge storage unit 335.

[0372] In one example, the first wiring is connected to the gate 313e of the reset transistor 313. This configuration enables electrostatic protection of the first wiring and the reset transistor 313. In this configuration, the first wiring can be the reset control line 352.

[0373] In one example, the pixel 10 includes a charge storage unit 335 and a selection transistor 312. The charge storage unit 335 stores a first charge. The selection transistor 312 determines the timing at which a signal corresponding to the first charge stored in the charge storage unit 335 is output from the pixel 10.

[0374] In one example, the first wiring is connected to the gate 312e of the selection transistor 312. This configuration enables electrostatic protection of the first wiring and the selection transistor 312. In this configuration, the first wiring can be the address control line 351.

[0375] In one example, the imaging device 1 includes a first semiconductor substrate 100, a plurality of signal pixels 10, dummy pixels 15, and a first wiring. In a plan view, the dummy pixels 15 are provided outside the array of the signal pixels 10. The imaging device 1 includes a repeating structure in which unit structures are arranged. Each unit structure includes a plurality of transistors provided on the first semiconductor substrate 100. Each signal pixel 10 includes a photoelectric conversion unit 310, a first circuit, and a first gate. The first circuit includes a plurality of transistors. The first circuit outputs a signal corresponding to a first charge. The first gate is included in one of the plurality of transistors. The first gate is connected to the first wiring. In the dummy pixel 15, the first wiring is connected to the source of at least one of the plurality of transistors. The dummy pixel 15 includes a second circuit that discharges charge in the first wiring via at least one transistor.

[0376] In the above example, the first and second circuits have in common the fact that they include multiple transistors, but they are not electrically equivalent because their wiring is different. The first circuit operates as a circuit that generates a signal in response to incident light. The second circuit operates as a circuit that drains electric charge.

[0377] In the above example, the plurality of transistors are, for example, at least two transistors selected from the group consisting of the amplification transistor 311, the selection transistor 312, the reset transistor 313, the overflow transistor 314, the transfer transistor 315, and the feedback transistor. The one transistor is, for example, the selection transistor 312, the reset transistor 313, the transfer transistor 315, or the feedback transistor.

[0378] The first circuit includes, for example, an amplifier transistor 311, a selection transistor 312, and a reset transistor 313. The first circuit may further include an overflow transistor 314, a transfer transistor 315, a feedback transistor, and the like.

[0379] The second circuit is, for example, an electrostatic discharge protection circuit 500. The electrostatic discharge protection circuit 500 includes, for example, a positive charge discharge circuit 512p, a positive charge discharge circuit 522p, a positive charge discharge circuit 532p, a positive charge discharge circuit 542p, a positive charge discharge circuit 552p, a negative charge discharge circuit 512n, a negative charge discharge circuit 522n, a negative charge discharge circuit 532n, a negative charge discharge circuit 542n, and a negative charge discharge circuit 552n.

[0380] In one example, the manufacturing method of the image pickup device 1 includes forming the first impurity region and the second impurity region by a common process of implanting impurities into the first semiconductor substrate 100. This configuration is advantageous from the viewpoint of producing the electrostatic protection circuit 500 while reducing the manufacturing time and manufacturing costs of the image pickup device 1.

[0381] In one example, the manufacturing method of the imaging device 1 includes processing a conductive structure connected to the electrostatic protection circuit 500 including the second impurity region into the first wiring by etching using ions.

[0382] (Additional Note) The present disclosure discloses the following techniques.

[0383] (Technology 1) An imaging device comprising: a first semiconductor substrate including a first impurity region and a second impurity region; pixels including the first impurity region and a photoelectric conversion unit that converts incident light into electric charges; an electrostatic protection circuit including the second impurity region; and wiring that connects the pixels and the electrostatic protection circuit, wherein the impurity concentration of the second impurity region is the same as the impurity concentration of the first impurity region.

[0384] (Technology 2) The imaging device according to Technology 1, wherein the second impurity region is provided in a dummy pixel.

[0385] (Technology 3) The imaging device according to Technology 1, wherein the second impurity region is provided outside a pixel array.

[0386] (Technology 4) The imaging device according to Technology 1, wherein the second impurity region is provided in a guard ring.

[0387] (Technology 5) The imaging device according to Technology 1, wherein the second impurity region is provided outside a guard ring.

[0388] (Technology 6) The imaging device according to any one of Technologies 1 to 5, wherein the first semiconductor substrate is of a first conductivity type, and the first impurity region and the second impurity region are of a second conductivity type.

[0389] (Technology 7) The imaging device according to Technology 6, wherein the electrostatic protection circuit includes a third impurity region of the first conductivity type.

[0390] (Technology 8) The imaging device according to any one of technologies 1 to 7, wherein the pixel includes a first transistor, one of a source and a drain of which is the first impurity region; the electrostatic protection circuit includes a second transistor, one of a source and a drain of which is the second impurity region; and a thickness of a gate oxide film of the second transistor is the same as a thickness of a gate oxide film of the first transistor.

[0391] (Technology 9) The imaging device according to Technology 8, wherein the first semiconductor substrate is of a first conductivity type, and the first impurity region and the second impurity region are of a second conductivity type.

[0392] (Technology 10) The imaging device according to Technology 9, wherein the electrostatic protection circuit includes: a third impurity region of the first conductivity type; and a third transistor having a source and a drain that are the third impurity region; and a thickness of a gate oxide film of the third transistor is the same as a thickness of a gate oxide film of the first transistor.

[0393] (Technology 11) The imaging device according to any one of Techniques 1 to 10, further comprising: a second semiconductor substrate on which a peripheral circuit for controlling the pixels is provided; and the first semiconductor substrate and the second semiconductor substrate are stacked on each other.

[0394] (Technology 12) The imaging device according to any one of Technologies 1 to 11, wherein the pixel further includes: a charge accumulation unit that accumulates the charge; and a reset transistor that initializes the charge accumulated in the charge accumulation unit, and the wiring is connected to a gate of the reset transistor.

[0395] (Technology 13) The imaging device according to any one of Technologies 1 to 11, wherein the pixel comprises: a charge accumulation section that accumulates the charge; and a selection transistor that determines a timing at which a signal corresponding to the charge accumulated in the charge accumulation section is output from the pixel; and the wiring is connected to a gate of the selection transistor.

[0396] (Technology 14) The imaging device according to any one of Techniques 1 to 13, wherein the photoelectric conversion unit includes a photoelectric conversion film.

[0397] (Technology 15) The imaging device according to Technology 14, wherein the photoelectric conversion film is an organic film.

[0398] (Technology 16) The imaging device according to any one of Techniques 1 to 13, wherein the photoelectric conversion unit includes a photodiode.

[0399] (Technology 17) The imaging device according to any one of Technologies 1 to 16, wherein the electrostatic protection circuit includes a third impurity region included in the first semiconductor substrate, the wiring is connected to the second impurity region, a fixed potential is applied to the third impurity region, and charges in the wiring are discharged passing through the second impurity region and the third impurity region in this order. Note that charges obtained by conversion of incident light in a photoelectric conversion unit may be referred to as first charges, and charges in the wiring may be referred to as second charges.

[0400] (Technology 18) An imaging device comprising: a first semiconductor substrate; pixels; dummy pixels; and wiring; wherein a repeating structure is formed in which unit structures are arranged, and each unit structure includes a plurality of transistors provided on the first semiconductor substrate; the pixel includes: a photoelectric conversion unit that converts incident light into a first charge; a circuit that includes the plurality of transistors and outputs a signal corresponding to the first charge; and a gate that is included in any one of the plurality of transistors and is connected to the wiring; and in the dummy pixel, the wiring is connected to a source of at least one transistor of the plurality of transistors, and the charge in the wiring is discharged via the at least one transistor.

[0401] (Technology 19) A method for manufacturing an imaging device comprising: a first semiconductor substrate including a first impurity region and a second impurity region; pixels including the first impurity region and a photoelectric conversion unit that converts incident light into electric charges; an electrostatic protection circuit including the second impurity region; and wiring that connects the pixels and the electrostatic protection circuit, the method comprising forming the first impurity region and the second impurity region by a common process of implanting impurities into the first semiconductor substrate.

[0402] (Technology 20) The manufacturing method according to Technology 19, further comprising processing a conductive structure connected to an electrostatic protection circuit including the second impurity region into the wiring by etching using ions.

[0403] The imaging device according to the present disclosure can be employed in a variety of applications, for example.

[0404] REFERENCE SIGNS LIST 1 imaging device 10 pixel (signal pixel) 11 effective pixel 12 OB pixel 15, 15a, 15b dummy pixel 20 unit pixel 80 row scanning circuit 82 signal processing circuit 84 output circuit 86 control circuit 100, 200 semiconductor substrate 105, 205 pad 111 support substrate 112 semiconductor region 121n, 121p, 122n, 122p, 123p, 124n, 124p, 125n, 126n, 127n well 141n, 141p, 142n, 142p, 143n, 143p1, 143p2, 144n, 144p, 230 impurity region 150, 250 wiring layer 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187 Element isolation 191, 192 Insulating film 195, 196 Electrode 207 Pad group 210 Electrostatic protection circuit group 220, 500, 511, 512, 513, 521, 522, 523, 531, 532, 533, 541, 542, 543, 551, 552, 553 Electrostatic protection circuit 280 Driver 281 Address driver 282 Reset driver 283 Transfer driver 300 Through electrode 310 Photoelectric conversion unit 310a Photoelectric conversion film 310b Pixel electrode (signal pixel electrode) 310b Pixel electrode 310c Counter electrode 311 Amplifying transistor 311d, 312d, 313d, 314d, 621d, 622d Drain 311e, 312e, 313e, 314e, 621g, 622g Gate 311s, 312s, 313s, 314s, 621s, 622s Source 312 Select transistor 313 Reset transistor 314 Overflow transistor 315 Transfer transistor 320 Color filter 321, 323, 324 Voltage line322 Signal line 325 Microlens 330 Charge storage node 335 Charge storage section 351 Address control line 352 Reset control line 353 Transfer control line 360 ​​Light-shielding film 370, 452 Ground 401 Row direction 402 Column direction 403, 404, 405, 406 External region 407 Column 408 Row 410 Through electrode region 420 Protection circuit region 430 Guard ring 440 Dummy pixel region 441 Dummy transistor 445 Dummy electrode 450, 453, 454, 455 Wiring 451 Power supply 461 Unit transistor 465 Unit electrode 470 Pixel array 471 Signal transistor 472 Transistor 480 OB region 490 Peripheral circuit 511n, 511p, 512n, 512p, 513n, 513p, 521n, 521p, 522n, 522p, 523n, 523p, 531n, 531p, 532n, 532p, 533n, 533p, 541n, 541p, 542n, 542p, 543n, 543p, 551n, 551p, 552n, 552p, 553n, 553p Charge drain circuit 610np, 610pn Diode 620n, 620p MOSFET 630n, 630p Bipolar transistor 631b, 632b Base 631c, 632c Collector 631e, 632e Emitter 710 Photodiode 1000 Camera system 1100: Lens optical system 1200: Image pickup device 1300: System controller 1400: Camera signal processing circuit

Claims

1. An imaging device comprising: a first semiconductor substrate including a first impurity region and a second impurity region; pixels including the first impurity region and a photoelectric conversion unit that converts incident light into electric charges; an electrostatic protection circuit including the second impurity region; and wiring connecting the pixels and the electrostatic protection circuit, wherein the impurity concentration of the second impurity region is the same as the impurity concentration of the first impurity region.

2. The imaging device according to claim 1, wherein the second impurity region is provided in a dummy pixel.

3. The imaging device according to claim 1, wherein the second impurity region is provided outside the pixel array.

4. The imaging device according to claim 1, wherein the second impurity region is provided in a guard ring.

5. The imaging device according to claim 1, wherein the second impurity region is provided outside a guard ring.

6. The imaging device according to claim 1, wherein the first semiconductor substrate is of a first conductivity type, and the first impurity region and the second impurity region are of a second conductivity type.

7. The imaging device according to claim 6, wherein the electrostatic protection circuit includes a third impurity region of the first conductivity type.

8. The imaging device according to claim 1, wherein the pixel includes a first transistor, one of whose source and drain is the first impurity region; the electrostatic protection circuit includes a second transistor, one of whose source and drain is the second impurity region; and the thickness of the gate oxide film of the second transistor is the same as the thickness of the gate oxide film of the first transistor.

9. The imaging device according to claim 8, wherein the first semiconductor substrate is of a first conductivity type, and the first impurity region and the second impurity region are of a second conductivity type.

10. The imaging device described in claim 9, wherein the electrostatic protection circuit includes: a third impurity region of the first conductivity type; and a third transistor having a source or a drain that is the third impurity region; and the thickness of the gate oxide film of the third transistor is the same as the thickness of the gate oxide film of the first transistor.

11. The imaging device according to claim 1, further comprising a second semiconductor substrate on which peripheral circuits for controlling the pixels are provided, the first semiconductor substrate and the second semiconductor substrate being stacked on top of each other.

12. The imaging device according to claim 1, wherein the pixel further comprises: a charge storage section that stores the charge; and a reset transistor that initializes the charge stored in the charge storage section; and the wiring is connected to the gate of the reset transistor.

13. The imaging device according to claim 1, wherein the pixel comprises: a charge storage section that stores the charge; and a selection transistor that determines the timing at which a signal corresponding to the charge stored in the charge storage section is output from the pixel; and the wiring is connected to the gate of the selection transistor.

14. The imaging device according to claim 1, wherein the photoelectric conversion section includes a photoelectric conversion film.

15. The imaging device according to claim 14, wherein the photoelectric conversion film is an organic film.

16. The imaging device according to claim 1, wherein the photoelectric conversion section includes a photodiode.

Images