Three-dimensional chip and three-dimensional chip detection method

Abstract

The present application relates to a three-dimensional chip and a three-dimensional chip detection method. The three-dimensional chip comprises a plurality of fusion-bonded chiplets, and further comprises detection circuits; the detection circuits are distributed to the chiplets; the detection circuits of at least two of the chiplets are connected in series to form a detection line; and the detection line leads out a detection port on the outer side of the three-dimensional chip. The detection port is led to the outer side of the three-dimensional chip to achieve the detection of the chiplets located inside the three-dimensional chip, so that the chiplets in the three-dimensional chip are all covered during the detection of the three-dimensional chip; in addition, the detection circuits of at least two chiplets are connected in series to form a detection line, thereby reducing the occupation of the positions of pins of the three-dimensional chip.

Description

Three-dimensional chip and three-dimensional chip detection method Technical Field

[0001] The present application relates to the field of chips, and in particular to a three-dimensional chip and a three-dimensional chip detection method. Background Art

[0002] As chips become increasingly complex, the contradiction between chip area, yield, and complex processes becomes increasingly difficult to reconcile. 3D packaging research and development aims to reduce costs by breaking large chips into several smaller ones. These chips can be produced using mature processes without requiring the most advanced processes. Fusion bonding (Fusion Bonding) is then used to assemble these small chips (chiplets) into a single large chip.

[0003] Because 3D chips are assembled from multiple cores, the probability of short circuits and open circuits after the packaging process is higher than that of a single chip. Therefore, after the packaging process, the 3D chip needs to be inspected; and the inspection process for 3D chips requires that all cores in the chip be covered. Summary of the Invention

[0004] In order to facilitate the detection of three-dimensional chips, the present application provides a three-dimensional chip and a three-dimensional chip detection method.

[0005] In a first aspect, the present application provides a three-dimensional chip comprising a plurality of bonded core particles and a detection circuit, wherein the detection circuit is distributed on the core particles, and the detection circuits of at least two of the core particles are connected in series to form a detection circuit, and the detection circuit leads to a detection port on the outside of the three-dimensional chip.

[0006] By adopting the above technical solution, the detection port is led to the outside of the three-dimensional chip, so as to realize the detection of the core particles located inside the three-dimensional chip, so that all the core particles in the three-dimensional chip can be covered during the detection process of the three-dimensional chip; at the same time, the detection circuits of at least two core particles are connected in series to form a detection circuit, so as to reduce the occupation of the pin position of the three-dimensional chip.

[0007] Preferably, the core particle includes a logic chip or a memory chip.

[0008] Preferably, the detection port includes an SPI port or a JTAG port.

[0009] Preferably, the detection circuits of all the core particles are connected in series to form the detection circuit.

[0010] By adopting the above technical solution, during the detection process of the three-dimensional chip, all the core particles in the three-dimensional chip can be covered; at the same time, there is only one detection port on the outside of the three-dimensional chip, which minimizes the occupation of the three-dimensional chip pin position, especially when the number of core particles reaches dozens, hundreds or more.

[0011] In a second aspect, the present application provides a three-dimensional chip detection method for detecting the above-mentioned three-dimensional chip, including: inputting a detection signal into the detection port; receiving a feedback signal from the detection port; and judging whether the three-dimensional chip has a short circuit and / or open circuit based on the feedback signal.

[0012] Preferably, inputting a detection signal to the detection port includes: inputting a first signal to the current pin of the core particle; receiving a feedback signal from the detection port includes: receiving a signal received by a specific pin, wherein the specific pin is located on the peripheral side of the current pin; judging whether there is a short circuit and / or open circuit in the three-dimensional chip based on the feedback signal, including: when a specific pin receives the first signal, judging that there is a short circuit between the specific pin and the current pin.

[0013] Preferably, inputting the detection signal to the detection port further includes: inputting a second signal to a specific pin.

[0014] By adopting the above technical solution, the interference of the outside world on the specific pins is reduced, and the accuracy of the detection results is guaranteed.

[0015] Preferably, inputting a detection signal to the detection port includes: inputting a pulse signal of a preset frequency to the current pin of the core particle; receiving a feedback signal from the detection port includes: receiving a signal received by a setting pin, wherein the setting pin is used to connect to the current pin; judging whether there is a short circuit and / or a break in the three-dimensional chip based on the feedback signal, including: when the setting pin does not receive a pulse signal, or the setting pin receives a pulse signal with a frequency lower than the preset frequency, judging that there is a break between the setting pin and the current pin.

[0016] By adopting the above technical solution, in qualified three-dimensional chips, the set pin and the current pin are connected by welding; during the welding process, there is a possibility of a cold weld (for example, there is a small gap between the metal connected to the set pin and the metal connected to the current pin, thus forming a capacitor-like structure). At this time, the high-frequency pulse can still pass through the cold weld, and then by setting a preset frequency, the welding point is detected using a low-frequency pulse to realize the circuit break detection of the welding point.

[0017] In summary, this application includes at least one of the following beneficial technical effects:

[0018] 1. The detection port is led to the outside of the 3D chip to detect the chiplets inside the 3D chip, so that all the chiplets in the 3D chip can be covered during the 3D chip detection process. At the same time, the detection circuits of at least two chiplets are connected in series to form a detection circuit, thereby reducing the occupation of the 3D chip pin position.

[0019] 2. The detection circuits of all the chiplets are connected in series to form a detection circuit, so that all the chiplets in the three-dimensional chip can be covered during the detection process of the three-dimensional chip; at the same time, there is only one detection port on the outside of the three-dimensional chip, which minimizes the occupation of the three-dimensional chip pin position, especially when the number of chiplets reaches dozens, hundreds or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic diagram of the structure of a three-dimensional chip.

[0021] FIG2 is a flow chart of the detection method.

[0022] Explanation of the accompanying reference numerals: 1. chip; 2. detection circuit; 3. detection port. DETAILED DESCRIPTION

[0023] The present application is further described in detail below with reference to Figures 1-2.

[0024] 1 , an embodiment of the present application discloses a three-dimensional chip, including a core particle 1 and a detection circuit 2 .

[0025] A plurality of core particles 1 are provided, and the core particles 1 are stacked and bonded to each other.

[0026] The core particle 1 is a logic chip or a memory chip. In one embodiment, the three-dimensional chip includes at least one logic chip.

[0027] There are multiple detection circuits 2. The detection circuits 2 are distributed in the core particles 1 and correspond one to one.

[0028] The detection circuits 2 of at least two chiplets 1 are connected in series to form a detection circuit. In one embodiment, the detection circuits 2 of all chiplets 1 are connected in series to form a detection circuit.

[0029] The detection circuit leads to the detection port 3 outside the three-dimensional chip. In one embodiment, the detection port 3 is an SPI port, which implements communication based on the SPI protocol. In another embodiment, the detection port 3 is a JTAG port, which implements communication based on the JTAG protocol.

[0030] The implementation principle of a three-dimensional chip in an embodiment of the present application is: the detection circuits 2 of all core particles 1 are connected in series to form a detection circuit, and the detection port 3 is led out from the outside of the three-dimensional chip, so that during the detection process of the three-dimensional chip, all the core particles 1 in the three-dimensional chip can be covered and the occupation of the three-dimensional chip pin position can be reduced.

[0031] The embodiment of the present application also discloses a three-dimensional chip detection method for detecting the above-mentioned three-dimensional chip.

[0032] Referring to FIG2 , the detection method includes:

[0033] S10, input a detection signal to the detection port 3;

[0034] S20, receiving a feedback signal from detection port 3;

[0035] S30: Based on the feedback signal, determine whether the three-dimensional chip has a short circuit and / or a break circuit.

[0036] Based on detection port 3, it is possible to input detection signals and receive feedback signals.

[0037] Step S10 includes:

[0038] S111, input a first signal to the current pin of chiplet 1;

[0039] S112, inputting a second signal to a specific pin; wherein the specific pin is located around the current pin.

[0040] In one embodiment, the first signal is a high-level signal, the second signal is a low-level signal, and a pull-down resistor is provided at a specific pin.

[0041] The specific pins are mainly the pins adjacent to the current pin. For example, if the pins of chip 1 are arranged in a rectangular array, the specific pins include the eight pins located around the current pin.

[0042] Step S20 includes:

[0043] S211, receiving a signal received by a specific pin.

[0044] Step S30 includes:

[0045] S311, when the specific pin receives the first signal, determining whether there is a short circuit between the specific pin and the current pin;

[0046] S312: When no first signal is detected at the specific pin, determine that there is no short circuit between the specific pin and the current pin.

[0047] Step S10 also includes:

[0048] S121, input a pulse signal of a preset frequency to the current pin of chip 1;

[0049] S122, setting a pull-down resistor at a pin, wherein the setting pin is used to be connected to the current pin.

[0050] In the three-dimensional chip packaging process, the set pin and the current pin should be soldered and connected.

[0051] Step S20 also includes:

[0052] S221, receiving a signal received by a specific pin.

[0053] Step S30 also includes:

[0054] S321, when the setting pin does not receive a pulse signal, or the setting pin receives a pulse signal with a frequency lower than a preset frequency, determining that there is a circuit break between the setting pin and the current pin;

[0055] S322: When the setting pin receives a pulse signal of a preset frequency, it is determined that there is no open circuit between the setting pin and the current pin.

[0056] The implementation principle of the detection method of a three-dimensional chip in the embodiment of the present application is: detection of all core particles 1 in the three-dimensional chip is achieved through a detection port 3 located outside the three-dimensional chip.

[0057] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A three-dimensional chip comprising a plurality of bonded core particles (1), characterized in that: The invention also includes a detection circuit (2), wherein the detection circuit (2) is distributed on the core particle (1), and the detection circuits (2) of at least two core particles (1) are connected in series to form a detection circuit, and the detection circuit leads to a detection port (3) outside the three-dimensional chip.

2. The three-dimensional chip according to claim 1, wherein: The core particle (1) includes a logic chip or a memory chip.

3. The three-dimensional chip according to claim 1, wherein: The detection port (3) includes an SPI port or a JTAG port.

4. The three-dimensional chip according to claim 1, wherein: The detection circuits (2) of all the core particles (1) are connected in series to form the detection circuit.

5. A three-dimensional chip detection method for detecting the three-dimensional chip according to any one of claims 1 to 4, characterized in that: include: Inputting a detection signal into the detection port (3); receiving a feedback signal from the detection port (3); Based on the feedback signal, it is determined whether the three-dimensional chip has a short circuit and / or a break circuit.

6. The three-dimensional chip detection method according to claim 5, characterized in that: Inputting a detection signal to the detection port (3) includes: inputting a first signal to the current pin of the core particle (1); Receiving a feedback signal from the detection port (3), comprising: receiving a signal received by a specific pin, wherein the specific pin is located on the peripheral side of the current pin; Determining whether the three-dimensional chip has a short circuit and / or an open circuit based on the feedback signal includes: when a specific pin receives a first signal, determining whether a short circuit exists between the specific pin and the current pin.

7. The three-dimensional chip detection method according to claim 6, characterized in that: Inputting a detection signal to the detection port (3) also includes: inputting a second signal to a specific pin.

8. The three-dimensional chip detection method according to claim 5, characterized in that: Inputting a detection signal to the detection port (3) includes: inputting a pulse signal of a preset frequency to the current pin of the core particle (1); Receiving a feedback signal from the detection port (3), comprising: receiving a signal received by a setting pin, wherein the setting pin is used to connect to the current pin; Based on the feedback signal, it is determined whether the three-dimensional chip has a short circuit and / or a break, including: when the set pin does not receive a pulse signal, or the set pin receives a pulse signal with a frequency lower than the preset frequency, it is determined that there is a break between the set pin and the current pin.

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