Bus circuit and electronic device

Abstract

The present application relates to the technical field of electronic products, and discloses a bus circuit and an electronic device. The bus circuit comprises a bus master device and a bus slave device; the bus master device is connected to the bus slave device by means of a clock bus; at least one of a clock input port of the bus master device and a clock input port of the bus slave device is connected to a noise suppression circuit; and the noise suppression circuit is used for filtering out noise in an initial clock signal received by the connected clock input port.

Description

Bus circuits and electronic devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202410251759.0 filed in China on March 6, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of electronic products, and in particular to a bus circuit and electronic equipment. Background Art

[0004] The bus protocol is a standard protocol used by the system to manage communication, data transmission and control signals between various hardware devices. It specifies the communication method, data format, transmission protocol and timing characteristics of each hardware device on the bus system.

[0005] Different bus protocols are suitable for a variety of hardware devices and application scenarios, and can be categorized as serial and parallel bus protocols. These protocols are primarily used in mobile or portable devices, such as smartphones, tablets, and smartwatches, to manage each device's operating mode, information transmission, system power supply, and other functions, thereby improving device efficiency and lifespan. The master device in each bus regularly sends read and write commands to the slave device to retrieve the required data. When reading data, timing accuracy and reliability must be ensured, otherwise communication anomalies may occur. As mobile system design becomes increasingly complex, the environment in which master and slave devices communicate via the bus is becoming increasingly harsh, making bus clock interference more common. Minor anomalies manifest as bit errors, but if the interference is significant, or if a bit error occurs during the reading or writing of critical bus information, it can easily lead to serious problems such as device downtime and system crashes and reboots. Consequently, buses in related technologies suffer from poor interference resistance. Summary of the Invention

[0006] The present application provides a bus circuit and an electronic device, which can solve the problem of poor anti-interference capability of bus circuits in related technologies.

[0007] In a first aspect, an embodiment of the present application provides a bus circuit, comprising a bus master device and a bus slave device, wherein the bus master device and the bus slave device are connected via a clock bus, and at least one of the clock input port of the bus master device and the clock input port of the bus slave device is connected to a noise suppression circuit; and the noise suppression circuit is used to filter out noise in an initial clock signal received by the connected clock input port.

[0008] In a second aspect, an embodiment of the present application provides an electronic device, comprising the bus circuit described in the first aspect.

[0009] In an embodiment of the present application, at least one of the clock input port of the bus master device and the clock input port of the bus slave device is connected to a noise suppression circuit. Since the noise suppression circuit can filter out noise in the clock signal received by the connected clock input port, it is beneficial to improve the anti-interference capability of the bus circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a schematic diagram of a bus circuit according to an embodiment of the present invention;

[0011] FIG2 is a schematic diagram of the structure of a noise suppression circuit in an embodiment of the present application;

[0012] FIG3 is a partial enlarged view of 410 in FIG2 ;

[0013] FIG4 is a partial enlarged view of 420 in FIG2 ;

[0014] FIG5 is a partial enlarged view of 450 in FIG2 ;

[0015] FIG6 is a second structural diagram of a bus circuit according to an embodiment of the present application;

[0016] FIG7 is a third structural diagram of a bus circuit according to an embodiment of the present application;

[0017] FIG8 is a schematic diagram of noise suppression performed on a bus circuit according to an embodiment of the present application;

[0018] FIG9 is a second schematic diagram of noise suppression based on the bus circuit provided in an embodiment of the present application;

[0019] FIG10 is a schematic diagram of reading and writing data to a shift register based on a bus circuit in the related art in the presence of pulse interference;

[0020] FIG11 is a schematic diagram of a bus circuit according to an embodiment of the present application performing data reading and writing on a shift register in the presence of pulse interference;

[0021] FIG12 is a schematic diagram of a process of processing an initial clock signal based on a bus circuit in an embodiment of the present application when the value of the first delay time is too small;

[0022] FIG13 is a schematic diagram of a process of processing an initial clock signal based on a bus circuit in an embodiment of the present application when the value of the first delay time is too large;

[0023] FIG14 is a schematic diagram of reading and writing data to a shift register based on a bus circuit in the related art in the presence of edge interference;

[0024] FIG15 is a schematic diagram of reading and writing data to a shift register using a bus circuit according to an embodiment of the present application in the presence of edge interference. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0026] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0027] The bus circuit and electronic device provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0028] Please refer to Figures 1 and 2, where Figure 1 is one of the structural schematic diagrams of a bus circuit provided in an embodiment of the present application; Figure 2 is a structural schematic diagram of a noise suppression circuit in an embodiment of the present application; the bus circuit includes a bus master device 100 and a bus slave device 200, the bus master device 100 and the bus slave device 200 are connected via a clock bus 300 (BUS CLK), and at least one of the clock input port 110 of the bus master device 100 and the clock input port 210 of the bus slave device 200 is connected to a noise suppression circuit 400 (Noise Stopper Circuit); and the noise suppression circuit 400 is used to filter out noise in the initial clock signal received by the connected clock input port.

[0029] The bus master 100 and bus slave 200 can be any two devices in a bus circuit that communicate via a bus. For example, when the bus circuit is a bus circuit in an electronic device, the bus master 100 can be a system-on-chip (SOC) in the electronic device, and the bus slave 200 can be various other chips in the electronic device other than the SoC, such as an image acquisition chip, a power management chip, or a touch screen controller chip in a camera. Please refer to Figure 6. In some embodiments of the present application, the bus master device 100 is a master device SOC (Master SOC), and the bus slave device 200 is a slave device chip (Slaver Integrated Circuit, Slaver IC), wherein the Master SOC includes a first bus module 140, and the Slaver IC includes a second bus module 230. The first bus module 140 includes the clock input port 110 of the above-mentioned bus master device 100, and the second bus module 230 includes the clock input port 210 of the above-mentioned bus slave device 200, and the first bus module 140 and the second bus module 230 are respectively connected through a clock bus 300 and a data bus 500.

[0030] It is understandable that the bus circuit can be connected to multiple devices, and the multiple devices may include at least one bus master device 100, see Figure 1. Among the multiple devices, the other devices 600 except the bus master device 100 are all bus slave devices. For example, see Figure 7. In some embodiments of the present application, the bus circuit includes 4 bus masters and 3 bus slaves, and each bus master is connected to each main line slave device via a clock bus and a data bus. The embodiment of the present application only uses a bus master device 100 and a bus slave device 200 in the bus circuit as an example to illustrate the structure and principle of the bus circuit in the embodiment of the present application. In fact, each bus slave device 200 in the bus circuit can perform noise filtering according to the noise filtering method of the bus slave device 200 in the embodiment of the present application.

[0031] The noise suppression circuit 400 can be any type of noise suppression circuit 400 capable of filtering noise from a clock signal. Referring to FIG. 1 , noise can be represented by the arrows denoted by reference numeral 700. FIG. 1 illustrates that, during operation of the bus circuit, both the bus master 100 and the bus slave 200 may be subject to noise interference. Therefore, in some embodiments of the present application, a noise suppression circuit 400 can be connected to each of the clock input ports 110 of the bus master 100 and 210 of the bus slave 200. This allows for filtering noise at various locations within the bus circuit, thereby improving the bus circuit's anti-interference capability.

[0032] 1 , the bus master device 100 may include a clock output port 120 in addition to a clock input port. The clock output port 120 of the bus master device 100 and the bus slave device 200 connected via the clock bus 300 may include: the clock output port 120 of the bus master device 100 is connected to the clock input port 210 of the bus slave device 200 via the clock bus 300. In this way, the bus master device 100 can send a clock signal to the bus slave device 200 via the clock output port 120. Furthermore, since the bus master device 100 itself also has some control logic associated with clock signals, the clock output port 120 of the bus master device 100 may also be connected to the clock input port 110 of the bus master device 100 via the clock bus 300. In this way, the bus master device 100 can send a clock signal to its own clock input port via the clock output port 120.

[0033] Please further refer to Figure 1. In some embodiments of the present application, the bus master device 100 may further include a first amplifier 160, wherein the first amplifier 160 may be arranged between the clock output port 120 and the clock bus 300. Specifically, the input end of the first amplifier 160 is connected to the clock output port 120, the output end of the first amplifier 160 is connected to the input end of the clock bus 300, and the enable end of the first amplifier 160 may be connected to the control circuit inside the bus master device 100. The control circuit inside the bus master device 100 may send an enable signal SCLK OUT EN to the enable end of the first amplifier 160 to control the first amplifier 160 to enter an enabled state.

[0034] The clock input port being connected to a noise suppression circuit may mean that the noise suppression circuit is integrated into the clock input port, or that the noise suppression circuit is connected to the input-side circuit of the clock input port, or that the noise suppression circuit is connected to the output-side circuit of the clock input port. To facilitate understanding, the following further explains the configuration of the noise suppression circuit using some specific embodiments:

[0035] In some embodiments of the present application, only the clock input port 110 of the bus master device 100 may be connected to the noise suppression circuit 400, thereby improving the anti-interference capability of the bus master device 100. Specifically, the noise suppression circuit 400 may be integrated into the clock input port 110 of the bus master device 100, or the noise suppression circuit 400 may be connected between the clock input port 110 and the internal circuit of the bus master device 100, or the noise suppression circuit 400 may be connected between the clock input port 110 and the clock bus.

[0036] In some embodiments of the present application, only the clock input port 210 of the bus slave device 200 may be connected to the noise suppression circuit 400, thereby improving the anti-interference capability of the bus master device 100. Specifically, the noise suppression circuit 400 may be integrated into the clock input port 210 of the bus slave device 200, or the noise suppression circuit 400 may be connected between the clock input port 210 and the circuit inside the bus slave device 200, or the noise suppression circuit 400 may be connected between the clock input port 210 and the clock bus.

[0037] In some embodiments of the present application, the clock input port 110 of the bus master device 100 and the clock input ports 210 of each bus slave device 200 in the bus circuit can be connected to a noise suppression circuit 400. This can improve the overall anti-interference capability of the bus circuit. The connection method between the noise suppression circuit 400 and the clock input port is similar to that in the above embodiment and will not be described again to avoid repetition.

[0038] In some embodiments of the present application, the bus master device 100 is provided with a first shift register, the input end of which is electrically connected to the output end of the noise suppression circuit 400 in the clock input port 110 of the bus master device 100. The bus slave device 200 is provided with a second shift register, the input end of which is electrically connected to the output end of the noise suppression circuit 400 in the clock input port 210 of the bus slave device 200. Thus, by providing the noise suppression circuit 400 in the upstream stage of the shift register, the problem of read and write confusion caused by interference can be effectively suppressed.

[0039] The bus slave device 200 is provided with a first shift register, and an input end of the first shift register is electrically connected to an output end of the noise suppression circuit 400 .

[0040] In this embodiment, at least one of the clock input port 110 of the bus master device 100 and the clock input port 210 of the bus slave device 200 is connected to the noise suppression circuit 400. Since the noise suppression circuit 400 can filter out noise in the clock signal received by the connected clock input port, it is beneficial to improve the anti-interference ability of the bus circuit.

[0041] Optionally, the noise suppression circuit 400 includes a first sampling circuit 410, a second sampling circuit 420, a two-input OR gate circuit 430, a delay circuit 440 and a frequency division circuit 450;

[0042] The output end of the first sampling circuit 410 and the output end of the second sampling circuit 420 are respectively connected to the input end of the two-input OR gate circuit 430, and the input end of the frequency divider circuit 450 and the input end of the delay circuit 440 are respectively connected to the output end of the two-input OR gate circuit 430; the output end of the delay circuit 440 is electrically connected to the first sampling circuit 410, and the output end of the delay circuit 440 is electrically connected to the second sampling circuit 420;

[0043] Among them, the first sampling circuit 410 is used to sample the rising edge signal in the received initial clock signal, and the second sampling circuit 420 is used to sample the falling edge signal in the received initial clock signal; the two-input OR gate circuit 430 is used to perform clock recovery based on the received rising edge signal and falling edge signal to obtain a first clock signal; the delay circuit 440 is used to control the sampling process of the first sampling circuit 410 and the sampling process of the second sampling circuit 420 according to the received first clock signal; the frequency division circuit 450 is used to perform frequency division processing on the received first clock signal to obtain a second clock signal.

[0044] The initial clock signal may be a clock signal received by a clock input terminal of the noise suppression circuit 400. The clock input terminal may transmit the received initial clock signal to the first sampling circuit 410 and the second sampling circuit 420, respectively. Thus, the first sampling circuit 410 and the second sampling circuit 420 may simultaneously sample the initial clock signal, thereby obtaining rising edge signals and falling edge signals for each clock cycle of the initial clock signal. Specifically, upon identifying a rising edge signal in the initial clock signal, the first sampling circuit 410 may output a high level. Simultaneously, the first sampling circuit 410 may output a low level for non-rising edge positions in the initial clock signal. Accordingly, upon identifying a falling edge signal in the initial clock signal, the second sampling circuit 420 may output a high level. Simultaneously, the second sampling circuit 420 may output a low level for non-falling edge positions in the initial clock signal.

[0045] One input of the two-input OR gate circuit 430 can be connected to the output of the first sampling circuit 410, and the other input of the two-input OR gate circuit 430 can be connected to the output of the second sampling circuit 420. Thus, when either the first sampling circuit 410 or the second sampling circuit 420 outputs a high level, the two-input OR gate circuit 430 can also output a high level. Based on the output of the two-input OR gate circuit 430, the positions of each rising edge and falling edge in the initial clock signal can be determined, thereby recovering the initial clock signal to obtain a first clock signal. Since each rising edge and falling edge in the initial clock signal generates a corresponding pulse waveform in the first clock signal, the first clock signal is twice the frequency of the initial clock signal. Thus, by transmitting the first clock signal to the frequency divider circuit 450 for frequency division, a second clock signal can be obtained, wherein the second clock signal is the clock signal after the noise signal in the initial clock signal has been filtered out.

[0046] It is understood that when the two-input OR gate circuit 430 receives a rising edge signal or a falling edge signal, it transmits it to the delay circuit 440 and the frequency divider circuit 450. In this way, the frequency divider circuit 450 can determine the clock period of the initial clock signal and the time of the rising edge signal currently sampled by the first sampling circuit 410. In this way, when the first sampling circuit 410 next samples a rising edge signal, the frequency divider circuit 450 can determine whether the time difference between two adjacent rising edge signals matches the clock period of the initial clock signal. If not, the next sampled rising edge signal may be a rising edge caused by an interference pulse. Therefore, the frequency divider circuit 450 can send a reset signal to the first sampling circuit 410 to use this reset signal to cover the noise pulse in the first clock signal, thus causing the first sampling circuit 410 to discard the next sampled rising edge signal. As a result, the output terminal of the first sampling circuit 410 will not output a high level for the sampled noise pulse, thereby filtering the noise pulse. It is understandable that when the frequency dividing circuit 450 determines that the time difference between two adjacent rising edge signals matches the clock period of the initial clock signal, the first sampling circuit 410 can normally sample the next sampled rising edge signal and output the corresponding high level.

[0047] Accordingly, the frequency divider circuit 450 can also determine the time of the falling edge signal currently sampled by the second sampling circuit 420. Thus, when the second sampling circuit 420 next samples a falling edge signal, the frequency divider circuit 450 can determine whether the time difference between two adjacent falling edge signals matches the clock period of the initial clock signal. If not, the next sampled falling edge signal may be a falling edge caused by an interference pulse. Therefore, the frequency divider circuit 450 can send a reset signal to the second sampling circuit 420 to cover the noise pulse in the second clock signal through the reset signal, thereby causing the second sampling circuit 420 to discard the next sampled falling edge signal. Consequently, the output terminal of the second sampling circuit 420 will not output a high level for the sampled noise pulse, thereby filtering the noise pulse. It can be understood that when the frequency divider circuit 450 determines that the time difference between two adjacent falling edge signals matches the clock period of the initial clock signal, the second sampling circuit 420 can normally sample the next sampled falling edge signal and output a corresponding high level.

[0048] In this embodiment, since the delay circuit 440 can control the first sampling circuit 410 and the second sampling circuit 420 to filter the noise signal during the sampling process, the first clock signal obtained by resetting the two-input OR gate circuit 430 is a clock signal from which the noise signal has been filtered. In this way, the second clock signal after the frequency division processing of the first clock signal is a clock signal obtained after filtering the noise signal in the initial clock signal, thereby realizing the process of filtering the noise signal in the initial clock signal.

[0049] Optionally, the delay circuit 440 is used to send a first reset signal to the first sampling circuit 410 according to the received first clock signal, and the delay circuit 440 is used to send a second reset signal to the second sampling circuit 420 according to the received first clock signal, wherein the first reset signal is used to control the first sampling circuit 410 to filter out noise within a first time period, and the first time period includes: a time period from a time point of the sampled rising edge signal to a time point less than the first delay time length; the second reset signal is used to control the second sampling circuit 420 to filter out noise within a second time period, and the second time period includes: a time period from a time point of the sampled falling edge signal to a time point less than the first delay time length.

[0050] The value of the first delay time can be set according to actual needs. For example, the first delay time (Program Delay) satisfies 0<Program Delay<0.25UI, wherein the UI is the length of one clock cycle of the initial clock signal.

[0051] In some embodiments of the present application, the first reset signal is used to control the first sampling circuit 410 to filter out noise within a first time period, specifically including: after the first sampling circuit 410 currently samples a rising edge signal, determining a corresponding first time period based on the time point of the sampling of the rising edge signal, the first time period being a time period formed by a first delay period before and after the time point of the currently sampled rising edge signal; if, within the first time period, rising edge signals other than the currently sampled rising edge signal are sampled, the sampled other rising edge signals are considered noise signals and filtered out. The second reset signal is used to control the second sampling circuit 420 to filter out noise within a second time period, specifically including: after the second sampling circuit 420 currently samples a falling edge signal, determining a corresponding second time period based on the time point of the sampling of the falling edge signal, the second time period being a time period formed by a first delay period before and after the time point of the currently sampled falling edge signal; if, within the second time period, falling edge signals other than the currently sampled falling edge signal are sampled, the sampled other falling edge signals are considered noise signals and filtered out. It is understandable that each rising edge signal output by the first sampling circuit 410 may correspond to a first time period, and each falling edge signal output by the second sampling circuit 420 may correspond to a second time period.

[0052] In other embodiments of the present application, the first reset signal is used to control the first sampling circuit 410 to filter out noise within the first time period, specifically including: within the first delay period after the first sampling circuit 410 currently samples a rising edge signal, if a rising edge signal is sampled again, it is considered a noise signal, and the sampled signal is filtered out. Correspondingly, the second reset signal is used to control the second sampling circuit 420 to filter out noise within the first delay period after the first falling edge signal is sampled, specifically including: within the first delay period after the second sampling circuit 420 currently samples a falling edge signal, if a falling edge signal is sampled again, it is considered a noise signal, and the sampled signal is filtered out.

[0053] In this embodiment, by sending a first reset signal to the first sampling circuit 410 and a second reset signal to the second sampling circuit 420 , noise signals can be filtered out during the sampling process of the first sampling circuit 410 and the second sampling circuit 420 .

[0054] Optionally, when the initial clock signal is a periodic clock signal, the first delay duration ranges from 0.5T to UI / 4, wherein T is: the absolute value of the time difference with the largest absolute value among the time differences between the noise location and the adjacent clock edges in the initial clock signal, and the clock edges include: the position corresponding to the rising edge signal and the position corresponding to the falling edge signal; and UI is the duration of one clock cycle of the initial clock signal.

[0055] The absolute value of the time difference with the largest absolute value among the time differences between the location of the noise and the adjacent clock edges in the initial clock signal specifically refers to the absolute value of the time difference with the largest absolute value among the time differences between the location of all noise and the adjacent clock edges in the initial clock signal. Specifically, in the process of determining T, the clock cycle in which each noise is located can be determined separately, and then the time difference between the location of each noise and the clock edge of the clock cycle is calculated. Each calculated time difference is used as a candidate time difference, thereby obtaining at least two candidate time differences. Then, the candidate time difference with the largest absolute value among the at least two candidate time differences is used as T.

[0056] Specifically, the value of T can be determined in advance based on experience, or can also be obtained by analyzing the initial clock signal. It is understandable that when there is no noise interference in the initial clock signal, the value of T is 0.

[0057] As shown in Figure 12, it is a schematic diagram of the process of processing the initial clock signal based on the bus circuit in the embodiment of the present application when the value of the first delay duration is too small. In Figure 12, the first row is the initial clock signal, the second row simulates pulse group noise such as DC to DC converter (DCDC) switching noise coupled to the initial clock signal, and the third row is the second clock signal recovered after noise suppression by the bus circuit in the embodiment of the present application. It can be seen that when the value of the above-mentioned first delay duration is too small, certain types of interference will not be completely filtered out, and the ultimately recovered clock will still have abnormal pulse waveforms.

[0058] Figure 13 shows a schematic diagram of the process of processing the initial clock signal using the bus circuit in an embodiment of the present application when the first delay duration is set too large. The first row in Figure 13 represents the initial clock signal, the second row simulates pulse train noise, such as DC-DC switching noise, coupled to the initial clock signal, and the third row represents the recovered second clock signal after noise suppression by the bus circuit in an embodiment of the present application. As can be seen, when the first delay duration is set too large, it can overwrite the original signal edges, resulting in an incorrect recovered clock frequency and potentially incomplete interference filtering.

[0059] Based on this, in the embodiment of the present application, by making the value range of the first delay time (Program Delay) satisfy: 0.5T<Program Delay<0.25UI, it is helpful to avoid the above-mentioned problems caused by the value of the first delay time being too large or too small.

[0060] In this embodiment, by making the value range of the first delay time be between 0.5T and UI / 4, the reset signal can cover as many positions where the noise signal may appear as possible, thereby improving the effect of filtering the noise signal.

[0061] Optionally, the bus master device 100 further includes a delay control circuit 150, and the delay control circuit 150 is electrically connected to the delay circuit 440; the bus master device 100 and the bus slave device 200 are further connected via a data bus 500 (BUSDATS);

[0062] The delay control circuit 150 is used to send an adjustment signal to the delay circuit 440 when the bus master device 100 receives a check code sent by the bus slave device 200 based on the data bus 500, and the check code does not match a preset value. The adjustment signal is used to control the delay circuit 440 to increase the first delay duration. The check code is a check code obtained from the transmission data after the bus slave device 200 receives the transmission data based on the data bus 500.

[0063] Please refer to FIG6 . The delay control circuit may be a programmable delay controller (PDC) in FIG6 . Please refer to FIG6 . The PDC may be electrically connected to the delay circuit in the noise suppression circuit 400 (Noise Stopper Circuit).

[0064] The fact that the check code does not match the preset value may specifically mean that the check code is not equal to the preset value.

[0065] Specifically, since each reading and writing of data on the data bus 500 carries a known check code, after the bus master 100 transmits the transmission data to the bus slave 200, the bus slave 200 can parse the check code in the received data and transmit the check code to the bus master 100 via the data bus 500. In this way, the bus master 100 can determine whether the data transmission process is normal by verifying whether the received check code is a preset value. Specifically, when the check code is not equal to the preset value, it is determined that the transmission process of the transmission data is abnormal. In this case, the abnormality may be caused by noise interference during the transmission process. Therefore, an adjustment signal can be sent to the delay circuit 440 to increase the size of the first delay time. When the first delay time increases, the range of noise filtering will also increase, which is conducive to filtering more noise signals that may affect the data transmission process.

[0066] It is understandable that the delay control circuit 150 may be any control chip capable of implementing the control logic corresponding to the delay control circuit 150 , and the present application does not limit the specific circuit structure of the delay control circuit 150 .

[0067] In this embodiment, whether the data transmission process of the bus circuit is interfered with by the noise signal is determined based on the check code, and when it is determined that the data transmission process of the bus circuit is interfered with by the noise signal, the filtering range of the noise signal is increased, thereby facilitating filtering of more noise signals that may affect the data transmission process.

[0068] Optionally, the adjustment signal is used to control the delay circuit 440 to gradually increase the first delay time until the check code received by the bus master device 100 matches the corresponding preset value.

[0069] Specifically, multiple first delay time levels can be pre-set. When the check code does not match the preset value, the first delay time level can be increased step by step until the check code received by the bus master device 100 matches the corresponding preset value. For example, referring to Table 1 below, the basic Program Delay can be pre-set to T0, ignoring interference, and the T0 range is: 0<T0<UI / 4. That is, before the first delay time is adjusted, the initial value of the first delay time is T0. If the check code is incorrect, the Program Delay is automatically increased step by step according to the previously predetermined level until the check code is normal, thereby achieving the effect of adaptive adjustment.

[0070] Table 1:

[0071] It should be clear that the above gear settings are only examples and are not fixed. Different buses can be set with fewer gears under different application conditions and taking into account design differences to meet the specific needs of different ICs.

[0072] In actual applications, there are also cases where the clock duty cycle of some buses is not fixed. By applying this design solution, after optimizing the Program Delay, the pulse noise on the edge can also be effectively optimized.

[0073] Assuming the minimum clock duty cycle is TD, in the case of such small-amplitude pulse noise, the Program Delay is required to be less than TD / 2, and the initial value T0 also needs to be set to a smaller value within this range. In this case, the specific preset gear examples can be adjusted as shown in Table 2 below:

[0074] Table 2:

[0075] It is understood that after each gear shift, a set of test data can be sent to the bus slave 200 via the bus master 100. After receiving the test data, the bus slave 200 sends a check code corresponding to the test data to the bus master 100. The delay control circuit 150 of the bus master 100 uses a preset value to verify whether the received check code is normal. If the check code is normal, the adjustment of the first delay duration is stopped. If the check code is abnormal, the first delay duration is increased by one gear until the check code is normal. The preset value corresponding to the check code received by the bus master 100 specifically matches: the check code received by the bus master 100 is equal to the corresponding preset value, at which point the check code is determined to be normal.

[0076] Please refer to Figures 14 and 15, where Figure 14 is a schematic diagram of reading and writing data to a shift register based on a bus circuit in the related art in the presence of edge interference, and Figure 15 is a schematic diagram of reading and writing data to a shift register based on a bus circuit in an embodiment of the present application in the presence of edge interference. As can be seen from Figures 14 and 15, Bit 1 in the solution of the related art is interfered with, causing the shift register to shift abnormally to the left. In the embodiment of the present application, after adjusting the first delay time according to the above-mentioned method of gradually increasing the first delay time, even when applied to certain buses with inconsistent clock duty cycles, the impact of edge back-grooving interference can be effectively filtered out, and the Bit 1 shift register operates normally.

[0077] In this embodiment, when the data transmitted by the bus circuit contains anomalies, the range of noise signal filtering is gradually increased, thereby improving the filtering effect of noise signals during the data transmission process. At the same time, the problem of excessive data volume required to be processed by the bus circuit due to the process of determining the first delay duration can be avoided.

[0078] Optionally, the first sampling circuit 410 includes a first D flip-flop 411 , and the second sampling circuit 420 includes a second D flip-flop 422 and a first inverter 421 ;

[0079] The first D flip-flop 411 includes a first input terminal 4111, a second input terminal 4113, a first output terminal 4114, and a first reset terminal 4112. The first input terminal 4111 is an input terminal of the first sampling circuit 410, the second input terminal 4113 is connected to VDD, the first output terminal 4114 is connected to the input terminal of the two-input OR gate circuit 430, and the first reset terminal 4112 is connected to the output terminal of the delay circuit 440.

[0080] The second D flip-flop 422 includes a third input terminal 4221, a fourth input terminal 4223, a second output terminal 4224 and a second reset terminal 4222. The input terminal of the first inverter 421 is the input terminal of the second sampling circuit 420, the output terminal of the first inverter 421 is connected to the third input terminal 4221, the fourth input terminal 4223 is connected to VDD, the second output terminal 4224 is connected to the input terminal of the two-input OR gate circuit 430, and the second reset terminal 4222 is connected to the output terminal of the delay circuit 440.

[0081] 3 , in some embodiments of the present application, the first input terminal 4111 may be a clock signal input terminal of the first D flip-flop 411, the second input terminal 4113 may be a D terminal of the first D flip-flop 411, the first output terminal 4114 may be a Q terminal of the first D flip-flop 411, the first reset terminal 4112 may be an RST terminal of the first D flip-flop 411, and the first D flip-flop 411 may further include end 4115 and PRE end 4116, wherein the Terminal 4115 is not connected to the bus circuit, and the PRE terminal 4116 is grounded.

[0082] 4 , in some embodiments of the present application, the third input terminal 4221 may be a clock signal input terminal of the second D flip-flop 422, the fourth input terminal 4223 may be a D terminal of the second D flip-flop 422, the second output terminal 4224 may be a Q terminal of the second D flip-flop 422, the second reset terminal 4222 may be an RST terminal of the second D flip-flop 422, and the second D flip-flop 422 may further include end 4225 and PRE end 4226, wherein the Terminal 4225 is not connected to the bus circuit, and the PRE terminal 4226 is grounded.

[0083] The first D flip-flop 411 and the second D flip-flop 422 may be various types of D flip-flops. The VDD is the power supply terminal for devices in the bus circuit. The first inverter 421 may be various types of inverters. The first inverter 421 may process rising edge signals in a received clock signal into falling edge signals, and may also process falling edge signals in a received clock signal into rising edge signals.

[0084] It is understood that both the first D flip-flop 411 and the second D flip-flop 422 are used to detect rising edges in the received clock signal. Since the clock signal received by the clock input port is directly transmitted to the clock signal input terminal of the first D flip-flop 411, the first D flip-flop 411 can detect rising edges in the clock signal received by the clock input port. Accordingly, the clock signal received by the clock input port is first inverted by the first inverter 421 before entering the clock signal input terminal of the second D flip-flop 422. Since the first inverter 421 can convert a falling edge signal into a rising edge signal, the rising edge signal detected by the second D flip-flop 422 is the falling edge signal in the clock signal received by the clock input port. In this way, the first D flip-flop 411 and the second D flip-flop 422 can detect both rising and falling edges in the clock signal received by the clock input port.

[0085] In some embodiments of the present application, the delay circuit 440 includes a programmable delay module 441, please refer to Figures 2 to 4, the first reset terminal 4112 and the second reset terminal 4222 are both reset terminals with an inverting function, that is, the reset signal will be inverted after passing through the first reset terminal 4112 and the second reset terminal 4222. Therefore, in order to ensure that the first reset signal received by the first D flip-flop 411 is consistent with the first reset signal output by the programmable delay module 441, and at the same time, ensure that the second reset signal received by the second D flip-flop 422 is consistent with the second reset signal output by the programmable delay module 441, the delay circuit 440 can also include a fourth inverter 442, the input end of the programmable delay module 441 is the input end of the delay circuit 440, the output end of the programmable delay module 441 is connected to the input end of the fourth inverter 442, and the output end of the fourth inverter 442 is the output end of the delay circuit 440. In this way, the reset signal can remain unchanged after being inverted twice by the fourth inverter 442 and the reset end during transmission to the D flip-flop, thereby making the first reset signal received by the first D flip-flop 411 consistent with the first reset signal output by the programmable delay module 441, and at the same time, making the second reset signal received by the second D flip-flop 422 consistent with the second reset signal output by the programmable delay module 441.

[0086] Among them, the programmable delay module 441 can be various control chips, and the programmable delay module 441 can generate the above-mentioned reset signal for controlling the first sampling circuit 410 and the second sampling circuit 420, and the fourth inverter 442 can be various inverters that can invert the received signal.

[0087] In addition, in other embodiments of the present application, when the first D flip-flop 411 and the second D flip-flop 422 are both D flip-flops with reset terminals that do not have an inverting function, the above-mentioned fourth inverter 442 can be cancelled, that is, the delay circuit 440 only includes a programmable delay module 441, but does not include the fourth inverter 442.

[0088] In this embodiment, by specifically configuring the structures of the first sampling circuit 410 and the second sampling circuit 420 , the rising edge and the falling edge detection process of the initial clock signal can be implemented.

[0089] Optionally, the two-input OR gate circuit 430 includes a two-input OR gate device 431, a second inverter 432 and a third inverter 433;

[0090] The input end of the two-input OR gate device 431 is the input end of the two-input OR gate circuit 430, the output end of the two-input OR gate device 431 is connected to the input end of the second inverter 432, the output end of the second inverter 432 is connected to the input end of the third inverter 433, and the output end of the third inverter 433 is the output end of the two-input OR gate circuit 430.

[0091] The two-input OR gate device 431 can be any two-input OR gate device 431 or chip. The two-input OR gate device 431 has two input terminals and one output terminal. When at least one of the two input terminals of the two-input OR gate device 431 is at a high level, the output terminal of the two-input OR gate device 431 outputs a high level. When both input terminals of the two-input OR gate device 431 are at a low level, the output terminal of the two-input OR gate device 431 outputs a low level.

[0092] It can be understood that the second inverter 432 and the third inverter 433 can be various inverters capable of performing inversion processing on the received signal.

[0093] In this embodiment, by configuring the structure of the two-input OR gate circuit 430 , the initial clock signal can be recovered based on the two-input OR gate circuit 430 .

[0094] Optionally, the frequency dividing circuit 450 includes a third D flip-flop 451, and the third D flip-flop 451 includes a fifth input terminal 4511, a sixth input terminal 4513, a third output terminal 4514, a fourth output terminal 4515 and a third reset terminal 4512. The fifth input terminal 4511 is the input terminal of the frequency dividing circuit 450, the sixth input terminal 4513 is connected to the fourth output terminal 4515, the third reset terminal 4512 is connected to VDD, and the third output terminal 4514 is the output terminal of the frequency dividing circuit 450.

[0095] 5 , in some embodiments of the present application, the fifth input terminal 4511 may be a clock signal input terminal of the third D flip-flop 451, the sixth input terminal 4513 may be a D terminal of the third D flip-flop 451, the third output terminal 4514 may be a Q terminal of the third D flip-flop 451, and the fourth output terminal 4515 may be a Q terminal of the third D flip-flop 451. The third reset terminal 4512 may be an RST terminal of the third D flip-flop 451. In addition, the third D flip-flop 451 further includes a third PRE terminal 4116, which is grounded.

[0096] Please refer to Figures 2 and 5. In some embodiments of the present application, the frequency division circuit 450 may further include a second amplifier 452. The third output terminal 4514 may be connected to the input terminal of the second amplifier 452. At this time, the output terminal of the second amplifier 452 is the output terminal of the frequency division circuit 450. In this way, the received clock signal can be amplified by the second amplifier 452.

[0097] In addition, in some other embodiments of the present application, the second amplifier 452 may also be eliminated. In this case, the third output terminal 4514 is the output terminal of the frequency dividing circuit 450 .

[0098] The third D flip-flop 451 may be any type of D flip-flop.

[0099] In this embodiment, by configuring the structure of the frequency dividing circuit 450 , the received first clock signal can be frequency-divided based on the frequency dividing circuit 450 to obtain a second clock signal.

[0100] Optionally, the bus circuit further includes a first Schmitt trigger 130 and a second Schmitt trigger 220, the clock bus 300 is connected to the clock input port 110 of the bus master device 100 through the first Schmitt trigger 130, and the clock bus 300 is connected to the clock input port 210 of the bus slave device 200 through the second Schmitt trigger 220.

[0101] The above-mentioned first Schmitt trigger 130 and second Schmitt trigger 220 are both Schmitt triggers. The Schmitt trigger has two stable states. However, unlike general triggers, the Schmitt trigger adopts a potential triggering method, and its state is maintained by the input signal potential; for input signals with two different change directions of negative decreasing and positive increasing, the Schmitt trigger has different threshold voltages.

[0102] Please refer to Figure 1. In some embodiments of the present application, the first Schmitt trigger 130 may further include an enable terminal. The control circuit inside the bus master device 100 may be connected to the enable terminal of the first Schmitt trigger 130, and the control circuit inside the bus master device 100 may send an enable signal SCLK IN EN to the enable terminal of the first Schmitt trigger 130 to control the first Schmitt trigger 130 to enter an enabled state.

[0103] In this embodiment, a first Schmitt trigger 130 is provided at the front stage of the clock input port 110 of the bus master device 100, and a second Schmitt trigger 220 is provided at the front stage of the clock input port 210 of the bus slave device 200. Thus, the clock signal is subjected to noise filtering by the Schmitt trigger before entering the corresponding clock input port, which is conducive to further improving the anti-interference capability of the bus circuit.

[0104] Please refer to Figure 2, which is a flowchart of how, in some embodiments of the present application, after the clock input port receives the initial clock signal BUS_SCLK_IN, the noise suppression circuit 400 performs noise filtering on BUS_SCLK_IN to obtain the second clock signal BUS_SCLK_OUT.

[0105] Please refer to Figure 8, which is a schematic diagram illustrating noise suppression using a bus circuit according to an embodiment of the present application. The first row in Figure 8 shows the initial clock signal, the second row simulates pulse train noise, such as DC-DC switching noise, coupled to the initial clock signal, and the third row shows the second clock signal recovered after noise suppression using the bus circuit according to an embodiment of the present application. The figure shows that the recovered second clock signal is essentially identical to the initial clock signal, effectively filtering out pulse train noise, such as switching noise.

[0106] Please refer to Figure 9, which is a second schematic diagram of noise suppression based on a bus circuit provided by an embodiment of the present application. The first row in Figure 9 shows the initial clock signal, the second row simulates carrier noise, such as from an RF antenna, coupled to the initial clock signal, and the third row shows the second clock signal recovered after noise suppression by the bus circuit provided by an embodiment of the present application. The figure shows that the recovered second clock signal is essentially identical to the initial clock signal and effectively filters out carrier-coupled noise, such as from the RF antenna.

[0107] Please refer to Figures 10 and 11. Figure 10 is a schematic diagram of a bus circuit in the related art reading and writing data to a shift register in the presence of pulse interference. Figure 11 is a schematic diagram of a bus circuit in the embodiment of the present application reading and writing data to a shift register in the presence of pulse interference. As shown in Figure 10, the chip circuit design in the related art is easily affected when it is subjected to the pulse group noise shown by the arrow. Bit 1, Bit 2, and Bit 5 in Figure 10 are all affected by the pulse interference, which in turn causes all subsequent data to be misaligned and communication to fail. Correspondingly, as shown in Figure 11, after the bus circuit in the embodiment of the present application is subjected to the same pulse group interference, due to the noise suppression circuit 400 integrated in the clock input port, that is, the noise suppression circuit 400 is provided in front of the shift register, it can make the data of each bit read and write normal, effectively suppressing the reading and writing confusion caused by the interference.

[0108] The bus circuit provided in the present application has at least the following beneficial effects: solving the increasingly serious problem of clock interference of various buses in complex application environments; the circuit is simple, low-cost, and easy to integrate into various ICs; it can be applied to various low-speed buses including the integrated circuit bus (Inter-Integrated Circuit, I2C), serial peripheral interface (Serial Peripheral Interface, SPI) bus, RF Front End Interface (RFFE) bus, sound bus (SOUNDWIRE), system power management interface (System Power Management Interface, SPMI) bus, as well as specially designed buses with non-fixed clock duty cycle, effectively preventing and solving the problem of clock interference of various buses.

[0109] An embodiment of the present application further provides an electronic device, which includes the bus circuit described in the above embodiment.

[0110] In this implementation, since the electronic device includes the bus circuit described in the above embodiment, the electronic device can implement each process of the bus circuit in the above embodiment and has the same beneficial effects. To avoid repetition, they will not be described here.

[0111] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A bus circuit, comprising a bus master device and a bus slave device, wherein the bus master device and the bus slave device are connected via a clock bus, and at least one of a clock input port of the bus master device and a clock input port of the bus slave device is connected to a noise suppression circuit; wherein the noise suppression circuit is configured to filter noise in an initial clock signal received by the connected clock input port.

2. The bus circuit according to claim 1, wherein: The noise suppression circuit includes a first sampling circuit, a second sampling circuit, a two-input OR gate circuit, a delay circuit and a frequency division circuit; The output end of the first sampling circuit and the output end of the second sampling circuit are respectively connected to the input end of the two-input OR gate circuit, and the input end of the frequency divider circuit and the input end of the delay circuit are respectively connected to the output end of the two-input OR gate circuit; the output end of the delay circuit is electrically connected to the first sampling circuit, and the output end of the delay circuit is electrically connected to the second sampling circuit.

3. The bus circuit according to claim 2, wherein: The first sampling circuit is used to sample a rising edge signal in the received initial clock signal, and the second sampling circuit is used to sample a falling edge signal in the received initial clock signal; the two-input OR gate circuit is used to perform clock recovery based on the received rising edge signal and falling edge signal to obtain a first clock signal; The frequency division circuit is used to perform frequency division processing on the received first clock signal to obtain a second clock signal; The delay circuit is used to send a first reset signal to the first sampling circuit according to the received first clock signal, and the delay circuit is used to send a second reset signal to the second sampling circuit according to the received first clock signal, wherein the first reset signal is used to control the first sampling circuit to filter out noise within a first time period, and the first time period includes: a time period from a time point of a sampled rising edge signal that is less than a first delay time; the second reset signal is used to control the second sampling circuit to filter out noise within a second time period, and the second time period includes: a time period from a time point of a sampled falling edge signal that is less than the first delay time.

4. The bus circuit according to claim 3, wherein: When the initial clock signal is a periodic clock signal, the first delay duration ranges from 0.5T to UI / 4, where T is the absolute value of the time difference with the largest absolute value among the time differences between the noise location and the adjacent clock edges in the initial clock signal, and the clock edges include the position corresponding to the rising edge signal and the position corresponding to the falling edge signal; and UI is the duration of one clock cycle of the initial clock signal.

5. The bus circuit according to claim 3, wherein: The bus master device further includes a delay control circuit, the delay control circuit being electrically connected to the delay circuit; the bus master device and the bus slave device are further connected via a data bus; The delay control circuit is used to send an adjustment signal to the delay circuit when the bus master device receives a check code sent by the bus slave device based on the data bus, and the check code does not match a preset value. The adjustment signal is used to control the delay circuit to increase the first delay duration. The check code is a check code obtained from the transmission data after the bus slave device receives the transmission data based on the data bus.

6. The bus circuit according to claim 5, wherein: The adjustment signal is used to control the delay circuit to gradually increase the first delay time until the check code received by the bus master device matches the corresponding preset value.

7. The bus circuit according to claim 2, wherein: The first sampling circuit includes a first D flip-flop, and the second sampling circuit includes a second D flip-flop and a first inverter; The first D flip-flop includes a first input terminal, a second input terminal, a first output terminal and a first reset terminal, the first input terminal is the input terminal of the first sampling circuit, the second input terminal is connected to VDD, the first output terminal is connected to the input terminal of the two-input OR gate circuit, and the first reset terminal is connected to the output terminal of the delay circuit; The second D flip-flop includes a third input terminal, a fourth input terminal, a second output terminal and a second reset terminal. The input terminal of the first inverter is the input terminal of the second sampling circuit. The output terminal of the first inverter is connected to the third input terminal. The fourth input terminal is connected to VDD. The second output terminal is connected to the input terminal of the two-input OR gate circuit. The second reset terminal is connected to the output terminal of the delay circuit.

8. The bus circuit according to claim 2, wherein: The two-input OR gate circuit includes a two-input OR gate device, a second inverter and a third inverter; The input end of the two-input OR gate device is the input end of the two-input OR gate circuit, the output end of the two-input OR gate device is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is the output end of the two-input OR gate circuit.

9. The bus circuit according to claim 2, wherein: The frequency dividing circuit includes a third D flip-flop, which includes a fifth input terminal, a sixth input terminal, a third output terminal, a fourth output terminal and a third reset terminal. The fifth input terminal is the input terminal of the frequency dividing circuit, the sixth input terminal is connected to the fourth output terminal, the third reset terminal is connected to VDD, and the third output terminal is the output terminal of the frequency dividing circuit.

10. The bus circuit according to claim 1, wherein The bus circuit also includes a first Schmitt trigger and a second Schmitt trigger. The clock bus is connected to the clock input port of the bus master device through the first Schmitt trigger, and the clock bus is connected to the clock input port of the bus slave device through the second Schmitt trigger.

11. An electronic device comprising the bus circuit according to any one of claims 1 to 10.

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