Interposer, structure, and electronic component module
Patent Information
- Application Number
- PCT/JP2025/004999
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-07
- Filing Date
- 2025-02-14
- Publication Date
- 2025-10-02
AI Technical Summary
The alignment margin between via conductors and electrodes in interposers is small, leading to a decrease in manufacturing yield.
The interposer design includes a dielectric layer with via conductors and electrodes of specific shapes and configurations, such as truncated cones, to increase alignment margins and improve manufacturing yield.
The improved alignment margins enhance manufacturing yield and mounting reliability by reducing stress and improving signal transmission efficiency.
Smart Images
Figure JP2025004999_02102025_PF_FP_ABST
Abstract
Description
Interposer, structure and electronic component module
[0001] The present disclosure relates to an interposer, a structure, and an electronic component module, and more particularly to an interposer having a via conductor portion, a structure having an interposer, and an electronic component module having an interposer.
[0002] Patent Document 1 discloses a wiring board with built-in electronic components. The wiring board disclosed in Patent Document 1 has a multilayer structure in which build-up insulating layers and build-up conductor layers are alternately stacked on the front and back surfaces of a core substrate. Two build-up conductor layers adjacent in the stacking direction are connected by a via conductor that penetrates the build-up insulating layer located between the two build-up conductor layers.
[0003] In an interposer, the margin for alignment between the via conductor portion connected to the first electrode and the second electrode connected to the IC chip is small, which may result in a decrease in manufacturing yield.
[0004] JP 2016-58472 A
[0005] An object of the present disclosure is to provide an interposer, a structure, and an electronic component module that can improve manufacturing yield.
[0006] An interposer according to one aspect of the present disclosure includes a dielectric layer, a via conductor, a first electrode, and a second electrode. The dielectric layer has a first main surface and a second main surface opposite the first main surface. The via conductor penetrates the dielectric layer. The first electrode is circular and located across the first main surface of the dielectric layer and the via conductor. The first electrode is connected to the via conductor. The second electrode is circular and located across the second main surface of the dielectric layer and the via conductor. The second electrode is connected to the via conductor. In a plan view from the thickness direction of the dielectric layer, the second electrode is smaller than the first electrode and located inside the outer edge of the first electrode. The second electrode has a first surface in contact with the via conductor and a second surface opposite the first surface. In the second electrode, a first outer diameter of the first surface is larger than a second outer diameter of the second surface.
[0007] A structure according to one aspect of the present disclosure includes the interposer according to the above aspect, a temporary adhesive layer, and a carrier substrate. The temporary adhesive layer covers the first main surface of the dielectric layer and the first electrode of the interposer. The temporary adhesive layer is releasable from the interposer. The carrier substrate is in contact with the temporary adhesive layer.
[0008] An electronic component module according to one aspect of the present disclosure includes the interposer according to the above aspect, and an IC chip, which is an electronic component, connected to the second electrode of the interposer.
[0009] An interposer according to one aspect of the present disclosure includes a dielectric layer, a via conductor, a first electrode, and a second electrode. The dielectric layer has a first main surface and a second main surface opposite the first main surface. The via conductor penetrates the dielectric layer. The first electrode is rectangular and is located across the first main surface of the dielectric layer and the via conductor. The first electrode is connected to the via conductor. The second electrode is rectangular and is located across the second main surface of the dielectric layer and the via conductor. The second electrode is connected to the via conductor. In a plan view from the thickness direction of the dielectric layer, the second electrode is smaller than the first electrode and is located inside the outer edge of the first electrode. The second electrode has a first surface in contact with the via conductor and a second surface opposite the first surface. In a plan view from the thickness direction of the dielectric layer, the outline of the first surface of the second electrode is located outside the outline of the second surface of the second electrode.
[0010] FIG. 1 is a cross-sectional view of an interposer according to the first embodiment. FIG. 2 is an enlarged cross-sectional view of a main portion of the interposer. FIG. 3 is a cross-sectional view of a structure including the interposer according to the first embodiment. FIGS. 4A to 4B are cross-sectional views illustrating steps in a method for manufacturing a structure including the interposer according to the first embodiment. FIGS. 5A to 5B are cross-sectional views illustrating steps in a method for manufacturing a structure including the interposer according to the first embodiment. FIGS. 6A to 6B are cross-sectional views illustrating steps in a method for manufacturing a structure including the interposer according to the first embodiment. FIGS. 7A to 7B are cross-sectional views illustrating steps in a method for manufacturing a structure including the interposer according to the first embodiment. FIGS. 8A to 8B are cross-sectional views illustrating steps in a method for manufacturing a structure including the interposer according to the first embodiment. FIGS. 9A to 9B are cross-sectional views illustrating steps in a method for manufacturing an interposer according to a modification of the first embodiment. FIGS. 10A to 10B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIG. 11 is a cross-sectional view of a structure including an interposer according to the second embodiment. FIG. 12 is a cross-sectional view of an electronic component module including an interposer according to the third embodiment. 13A and 13B are cross-sectional views illustrating steps in a method for manufacturing the electronic component module.
[0011] Hereinafter, embodiments 1 to 3 will be described with reference to the drawings. The drawings referred to in the following embodiments 1 to 3 are schematic diagrams, and the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensions, and the size ratios and thickness ratios between the components do not necessarily reflect the actual dimensional ratios.
[0012] (Embodiment 1) (1) Interposer and Structure Including the Interposer As shown in FIG. 1 , an interposer 1 according to embodiment 1 includes a dielectric layer 201, a plurality of via conductors 31, a plurality of first electrodes 4, and a plurality of second electrodes 32. The dielectric layer 201 has a first main surface 211 and a second main surface 212 opposite to the first main surface 211. The plurality of via conductors 31 penetrate the dielectric layer 201. Each of the plurality of first electrodes 4 is circular. The plurality of first electrodes 4 correspond one-to-one to the plurality of via conductors 31. The plurality of first electrodes 4 are positioned across the first main surface 211 of the dielectric layer 201 and a corresponding one of the plurality of via conductors 31. The plurality of second electrodes 32 correspond one-to-one to the plurality of via conductors 31. The plurality of second electrodes 32 are located across a corresponding one of the plurality of via conductors 31 and the second main surface 212 of the dielectric layer 201. Each of the plurality of second electrodes 32 has a circular shape. Each of the plurality of second electrodes 32 is connected to a corresponding one of the plurality of via conductors 31.
[0013] The interposer 1 according to the first embodiment further includes a second dielectric layer 202, a plurality of second via conductors 33, and a plurality of third electrodes 7. The second dielectric layer 202 is laminated on the first dielectric layer 201, which is the dielectric layer 201, and covers the plurality of second electrodes 32. The plurality of second via conductors 33 are different from the plurality of first via conductors 31, which are the plurality of via conductors 31. The plurality of second via conductors 33 penetrate the second dielectric layer 202. The plurality of second via conductors 33 correspond one-to-one to the plurality of second electrodes 32. The plurality of second via conductors 33 are connected to corresponding second electrodes 32 of the plurality of second electrodes 32. The plurality of third electrodes 7 correspond one-to-one to the plurality of second via conductors 33. The plurality of third electrodes 7 are located across the second dielectric layer 202 and corresponding second via conductors 33 of the plurality of second via conductors 33. Each of the plurality of third electrodes 7 is connected to a corresponding one of the plurality of second via conductors 33. The plurality of third electrodes 7 correspond one-to-one to the plurality of second electrodes 32. Each of the plurality of third electrodes 7 faces a corresponding one of the plurality of second electrodes 32. Each of the plurality of second via conductors 33 has a truncated cone shape. The diameter of each of the plurality of second via conductors 33 decreases as it approaches the corresponding one of the plurality of second electrodes 32 in the thickness direction D1 of the dielectric layer 201.
[0014] In the interposer 1 according to the first embodiment, the first dielectric layer 201 and the second dielectric layer 202 constitute the dielectric substrate 2. In addition, in the interposer 1 according to the first embodiment, the first via conductor 31, the second electrode 32, and the second via conductor 33, which overlap in the thickness direction D1 of the first dielectric layer 201, constitute a through wiring portion 3 that penetrates the dielectric substrate 2. Therefore, the interposer 1 according to the first embodiment includes a plurality of through wiring portions 3. The plurality of third electrodes 7 correspond one-to-one to the plurality of through wiring portions 3 and one-to-one to the plurality of first electrodes 4. The plurality of third electrodes 7 are connected to corresponding through wiring portions 3 among the plurality of through wiring portions 3. Furthermore, each of the plurality of third electrodes 7 is connected to a corresponding first electrode 4 among the plurality of first electrodes 4 via the through wiring portion 3.
[0015] In the interposer 1 according to the first embodiment, the plurality of first electrodes 4 constitute a plurality of first pad electrodes for BGA (Ball Grid Array) connection, and the plurality of third electrodes 7 constitute a plurality of second pad electrodes for IC chip connection.
[0016] Moreover, the interposer 1 according to the first embodiment further includes a plurality of wiring portions 6. The plurality of wiring portions 6 are arranged on the second main surface 212 of the dielectric layer 201. The plurality of wiring portions 6 correspond, for example, to the plurality of second electrodes 32 in a one-to-one relationship and are connected to the corresponding second electrodes 32.
[0017] 3, the structure 110 including the interposer 1 according to the first embodiment includes the interposer 1, a temporary adhesive layer 15, and a carrier substrate 16. When the interposer 1 is to be brought into a state in which the functions of the interposer 1 can be realized (see FIG. 12), the carrier substrate 16 is peeled off from the temporary adhesive layer 15, and the temporary adhesive layer 15 is peeled off from the interposer 1.
[0018] The interposer 1 according to the first embodiment is disposed between, for example, an IC chip and a package substrate of a SiP (System in Package). The IC chip includes, for example, a processor, a logic IC (Integrated Circuit), a memory (for example, an HBM: High Bandwidth Memory), etc.
[0019] (2) Components of the Interposer Each component of the interposer 1 according to the first embodiment will be described below with reference to FIG.
[0020] The dielectric substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21 .
[0021] The dielectric substrate 2 includes a first dielectric layer 201 and a second dielectric layer 202. The first dielectric layer 201 is laminated on the second dielectric layer 202. The thickness direction of the dielectric substrate 2 is the same as the thickness direction D1 of the first dielectric layer 201.
[0022] The first dielectric layer 201 has a first major surface 211 and a second major surface 212 opposite to the first major surface 211 .
[0023] The second dielectric layer 202 has a third main surface 221 in contact with the second main surface 212 of the first dielectric layer 201 and a fourth main surface 222 opposite to the third main surface 221. The second dielectric layer 202 covers the second electrode 32.
[0024] The material of the first dielectric layer 201 includes an organic material. More specifically, the material of the first dielectric layer 201 includes, as a main component, for example, an imide resin (e.g., polyimide, bismaleimide, etc.) or a fluorine resin (e.g., polytetrafluoroethylene, etc.). From the viewpoint of improving the high-frequency characteristics of the interposer 1, the material of the first dielectric layer 201 preferably has a low dielectric constant and a low dielectric loss tangent. "Improving the high-frequency characteristics" means reducing the transmission loss of signals transmitted through the through wiring portion 3.
[0025] The material of the second dielectric layer 202 includes an organic material. More specifically, the material of the second dielectric layer 202 includes, as a main component, for example, an imide-based resin (e.g., polyimide, bismaleimide, etc.), a fluorine-based resin (e.g., polytetrafluoroethylene, etc.), or an epoxy-based resin. The material of the second dielectric layer 202 may be the same as or different from the material of the first dielectric layer 201.
[0026] In the dielectric substrate 2, the second main surface 212 of the first dielectric layer 201 is in contact with the third main surface 221 of the second dielectric layer 202. The first main surface 21 of the dielectric substrate 2 is formed by the first main surface 211 of the first dielectric layer 201. The second main surface 22 of the dielectric substrate 2 is formed by the fourth main surface 222 of the second dielectric layer 202. When viewed from a plane in the thickness direction D1 of the first dielectric layer 201, the outer edge shape of the dielectric substrate 2 is rectangular, but may be a shape other than rectangular.
[0027] Each of the plurality of first electrodes 4 is located across a corresponding one of the plurality of through wiring portions 3 and the first main surface 21 of the dielectric substrate 2. More specifically, each of the plurality of first electrodes 4 is located across a first via conductor portion 31 of a corresponding one of the plurality of through wiring portions 3 and a part of the first main surface 211 of the first dielectric layer 201.
[0028] In a plan view from the thickness direction D1 of the first dielectric layer 201, each of the multiple first electrodes 4 has a circular shape. In a plan view from the thickness direction D1 of the first dielectric layer 201, each of the multiple first electrodes 4 is larger than each of the through wiring portions 3 and the third electrodes 7. In a plan view from the thickness direction D1 of the first dielectric layer 201, an outer edge 402 of each of the multiple first electrodes 4 encompasses an outer edge of a first via conductor 31 connected to the first electrode 4. In addition, in a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge 402 of each of the multiple first electrodes 4 encompasses an outer edge 323 of a second electrode 32 overlapping the first electrode 4. In addition, in a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge 402 of each of the multiple first electrodes 4 encompasses an outer edge 702 of a third electrode 7 overlapping the first electrode 4. The plurality of first electrodes 4 protrude from the first main surface 211 of the first dielectric layer 201. Each of the plurality of first electrodes 4 has a main surface 401 opposite to the first dielectric layer 201.
[0029] The material of each of the plurality of first electrodes 4 includes, for example, copper. The material of each of the plurality of first electrodes 4 is not limited to copper, and may be, for example, a copper alloy, aluminum, or titanium.
[0030] The thickness of each of the plurality of first electrodes 4 is, for example, but not limited to, 10 μm. The thickness of each of the plurality of first electrodes 4 is the thickness of the portion that overlaps the first main surface 211 of the first dielectric layer 201.
[0031] Each of the multiple first electrodes 4 includes a first portion 41 in contact with the first main surface 211 of the first dielectric layer 201 and a second portion 42 overlapping the first portion 41. In a plan view from the thickness direction D1 of the first dielectric layer 201, the first portion 41 of each of the multiple first electrodes 4 is circular, and the second portion 42 of each of the multiple first electrodes 4 is circular. The multiple first electrodes 4 are, for example, multiple pad electrodes for BGA. The outer diameter R0 (see FIG. 2 ) of the main surface 401 of each of the multiple first electrodes 4 is, for example, 200 μm, but is not limited to 200 μm. Furthermore, the distance L1 between the centers of two adjacent first electrodes 4 among the multiple first electrodes 4 is, for example, 400 μm, but is not limited to 400 μm.
[0032] Each of the plurality of through wiring portions 3 includes, for example, a first via conductor portion 31, a second electrode 32, and a second via conductor portion 33. The first via conductor portion 31 is composed of a first portion 311 seamlessly connected to the first portion 41 of the first electrode 4, and a second portion 312 seamlessly connected to the second portion 42 of the first electrode 4. In each through wiring portion 3, the first via conductor portion 31, the second electrode 32, and the second via conductor portion 33 are arranged in this order from the first main surface 21 side of the dielectric substrate 2. In each through wiring portion 3, the first via conductor portion 31 and the second electrode 32 are directly connected, and the second electrode 32 and the second via conductor portion 33 are directly connected, so that the first via conductor portion 31, the second electrode 32, and the second via conductor portion 33 are electrically connected. In each through wiring portion 3, the first via conductor portion 31 penetrates the first dielectric layer 201. In each through wiring portion 3, the second electrode 32 and the second via conductor portion 33 are embedded in the second dielectric layer 202.
[0033] When viewed in a plane from the thickness direction D1 of the first dielectric layer 201, each of the multiple second electrodes 32 is smaller than a corresponding first electrode 4 among the multiple first electrodes 4 and is located inside the outer edge 402 of the corresponding first electrode 4.
[0034] Each of the second electrodes 32 has a first surface 321 in contact with a corresponding one of the first via conductors 31 and a second surface 322 opposite to the first surface 321. In a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge shape of each of the second electrodes 32 is circular. Each of the second electrodes 32 has a truncated cone shape. In each of the second electrodes 32, a first outer diameter R1 (see FIG. 2 ) of the first surface 321 is larger than a second outer diameter R2 (see FIG. 2 ) of the second surface 322. The outer diameter of each of the second electrodes 32 gradually decreases with increasing distance from the first via conductor 31 in the thickness direction D1 of the first dielectric layer 201.
[0035] In addition, in a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge shape of each of the multiple first via conductors 31 is circular. Each of the multiple first via conductors 31 has a truncated cone shape. In each of the multiple first via conductors 31, a fourth outer diameter R4 (see FIG. 2 ) on the second main surface 212 of the first dielectric layer 201 is smaller than a third outer diameter R3 (see FIG. 2 ) on the first main surface 211 of the first dielectric layer 201. The outer diameter of each of the multiple first via conductors 31 gradually decreases in the thickness direction D1 of the first dielectric layer 201 as it moves away from the first electrode 4 and closer to the second electrode 32.
[0036] In the second electrode 32 of this embodiment, for example, the first outer diameter R1 is 25 μm and the second outer diameter R2 is 20 μm. In addition, in the first via conductor portion 31 of this embodiment, for example, the third outer diameter R3 is 15 μm and the fourth outer diameter R4 is 10 μm.
[0037] The plurality of second electrodes 32 are embedded in the second dielectric layer 202 and are exposed from the third main surface 221 of the second dielectric layer 202 .
[0038] In a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge shape of each of the multiple second via conductors 33 is circular. Each of the multiple second via conductors 33 is frustoconical. In each of the multiple second via conductors 33, a fifth outer diameter R5 (see FIG. 2 ) on the second surface 322 of the second electrode 32 is smaller than a sixth outer diameter R6 (see FIG. 2 ) on the fourth main surface 222 of the second dielectric layer 202. The outer diameter of each of the multiple second via conductors 33 gradually decreases as it moves away from the third electrode 7 and closer to the second electrode 32 in the thickness direction D1 of the first dielectric layer 201. The fifth outer diameter R5 of the second via conductor 33 is smaller than the second outer diameter R2 of the second electrode 32.
[0039] The material of each of the plurality of through wiring portions 3 includes, for example, copper. The material of each of the plurality of through wiring portions 3 is not limited to copper, but may be, for example, a copper alloy, aluminum, or titanium.
[0040] When viewed in a plane from the thickness direction D1 of the first dielectric layer 201, each of the multiple third electrodes 7 is smaller than a corresponding first electrode 4 among the multiple first electrodes 4 and is located inside the outer edge 402 of the corresponding first electrode 4.
[0041] In a plan view from the thickness direction D1 of the first dielectric layer 201, each of the multiple third electrodes 7 has a circular shape. In a plan view from the thickness direction D1 of the first dielectric layer 201, each of the multiple third electrodes 7 is smaller than each of the first electrodes 4. In a plan view from the thickness direction D1 of the first dielectric layer 201, an outer edge 702 of each of the multiple third electrodes 7 includes an outer edge of a second via conductor 33 connected to the third electrode 7. In addition, in a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge 702 of each of the multiple third electrodes 7 is included within an outer edge 323 of a corresponding second electrode 32 among the multiple second electrodes 32. In addition, in a plan view from the thickness direction D1 of the first dielectric layer 201, the outer edge 702 of each of the multiple third electrodes 7 is included within an outer edge 402 of a first electrode 4 connected to the third electrode 7. The multiple third electrodes 7 protrude from the fourth main surface 222 of the second dielectric layer 202. Each of the plurality of third electrodes 7 has a main surface 701 opposite to the second dielectric layer 202 .
[0042] The material of each of the third electrodes 7 includes, for example, copper. The material of each of the third electrodes 7 is not limited to copper, and may be, for example, a copper alloy, aluminum, or titanium.
[0043] The thickness of each of the third electrodes 7 is, for example, but not limited to, 5 μm. The thickness of each of the third electrodes 7 is the thickness of a portion that overlaps the fourth main surface 222 of the second dielectric layer 202.
[0044] The plurality of wiring portions 6 are arranged on the second main surface 212 of the first dielectric layer 201 and are connected to at least one of the plurality of second electrodes 32. The thickness of each of the plurality of wiring portions 6 is the same as the thickness of each of the plurality of second electrodes 32.
[0045] Each of the plurality of wiring portions 6 has a third surface 61 in contact with the second main surface 212 of the dielectric layer 201 and a fourth surface 62 opposite to the third surface 61. In each of the plurality of wiring portions 6, a first width H1 (see FIG. 2) of the third surface 61 is larger than a second width H2 (see FIG. 2) of the fourth surface 62. The first width H1 of each of the plurality of wiring portions 6 is smaller than a first outer diameter R1 (see FIG. 2) of a corresponding one of the plurality of second electrodes 32. The second width H2 of each of the plurality of wiring portions 6 is smaller than a second outer diameter R2 of a corresponding one of the plurality of second electrodes 32.
[0046] The plurality of wiring portions 6 are covered with the second dielectric layer 202. Therefore, the plurality of wiring portions 6 are embedded in the dielectric substrate 2.
[0047] The interposer 1 further includes a plurality of barrier layers 17 that correspond one-to-one to the plurality of third electrodes 7, and a plurality of solder bumps 18 that correspond one-to-one to the plurality of third electrodes 7. Each of the plurality of solder bumps 18 is disposed on the main surface 701 of the corresponding third electrode 7 among the plurality of third electrodes 7, with the barrier layer 17 interposed therebetween.
[0048] (3) Structure As shown in FIG. 3, the structure 110 includes an interposer 1, a temporary adhesive layer 15, and a carrier substrate 16.
[0049] The temporary adhesive layer 15 is laminated directly on the first main surface 211 of the first dielectric layer 201, and covers the first main surface 21 of the dielectric substrate 2. The temporary adhesive layer 15 covers the plurality of first electrodes 4 and the first main surface 211 of the first dielectric layer 201. The temporary adhesive layer 15 is peelable from the interposer 1. The material of the temporary adhesive layer 15 includes, for example, an acrylic resin. The thickness of the temporary adhesive layer 15 is, for example, 20 μm. The thickness of the temporary adhesive layer 15 is the thickness of the portion that overlaps the first main surface 211 of the first dielectric layer 201.
[0050] The carrier substrate 16 includes, for example, a glass substrate 161 and a release layer 162 laminated on the glass substrate 161. The carrier substrate 16 is temporarily fixed to the temporary adhesive layer 15 but can be peeled off from the temporary adhesive layer 15.
[0051] (4) Method for Manufacturing Interposer A method for manufacturing the interposer 1 according to the first embodiment will be described with reference to FIGS. 4A to 10B.
[0052] In the manufacturing method of the interposer 1, as shown in FIG. 4A, a laminate 10 is prepared in which a second dielectric layer 202 is laminated on a carrier substrate 9 (hereinafter referred to as the first carrier substrate 9), and then steps 1 to 15 are performed sequentially.
[0053] The first carrier substrate 9 has a first main surface 91 and a second main surface 92 opposite to the first main surface 91. The first carrier substrate 9 is, for example, a metal substrate. In this embodiment, the material of the metal substrate is stainless steel, but materials other than stainless steel may also be used. Note that, instead of a metal substrate, the first carrier substrate 9 may include, for example, an organic substrate, a silicon substrate, or a glass substrate. Examples of organic substrates that can be used include an LCP (Liquid Crystal Polymer) substrate, a PET (Polyethylene terephthalate) substrate, and a PTFE (Polytetrafluoroethylene) substrate. The second dielectric layer 202 is laminated on the first main surface 91 of the first carrier substrate 9.
[0054] In the first step, as shown in FIG. 4B, a plurality of second electrodes 32 and a plurality of wiring portions 6 are formed on the second dielectric layer 202 of the laminate 10.
[0055] 5A , in the second step, a first dielectric layer 201 is formed to cover the third main surface 221 of the second dielectric layer 202, the plurality of second electrodes 32, and the plurality of wiring portions 6. In the second step, a solution containing an organic material for the first dielectric layer 201 is applied onto the laminate 10 using a coater (e.g., a spin coater) or a dispenser, and pre-baked to form the first dielectric layer 201. Note that in the second step, the first dielectric layer 201 may also be formed by laminating a resin film that will become the first dielectric layer 201 onto the laminate 10.
[0056] 5B , in the third step, a plurality of first via holes 213 are formed in the first dielectric layer 201 by laser processing. In the third step, the plurality of first via holes 213 are formed in regions in the first dielectric layer 201 where the plurality of first via conductor portions 31 are to be formed. The plurality of first via holes 213 correspond one-to-one to the plurality of first via conductor portions 31.
[0057] In the manufacturing method of the interposer 1 of this embodiment, multiple first via conductor portions 31 are formed by performing steps 4 to 6, and multiple first electrodes 4 are formed by performing steps 4 to 7.
[0058] 6A , in the fourth step, a seed layer 11 is formed by, for example, electroless plating, covering the first main surface 211 of the first dielectric layer 201, the inner surfaces of the plurality of first via holes 213, and the exposed portions of the first surfaces 321 of the plurality of second electrodes 32. The material of the seed layer 11 is the same as the material of the first portions 41 of each first electrode 4. The material of the seed layer 11 is, for example, copper, but is not limited to this and may be, for example, a copper alloy. The method of forming the seed layer 11 is not limited to electroless plating and may also be a sputtering method.
[0059] 6B , in the fifth step, a resist layer 13 having a predetermined pattern is formed on the seed layer 11. The predetermined pattern of the resist layer 13 is a pattern that exposes regions in the seed layer 11 where the plurality of first via conductors 31 and the plurality of first electrodes 4 are to be formed.
[0060] 7A , in the sixth step, a plurality of first via conductors 31 and a plurality of first electrodes 4 are formed. In the sixth step, the plurality of first via conductors 31 and a plurality of first electrodes 4 are formed by, for example, electrolytic plating, and then the resist layer 13 is removed. The material of each of the plurality of plating layers 12 grown on the seed layer 11 in the sixth step is the same as the material of the second portion 42 of the first electrode 4. The material of the plating layer 12 is, for example, copper, but is not limited to this and may be, for example, a copper alloy.
[0061] 7B, in the seventh step, a part of the seed layer 11 is removed to expose the first main surface 211 of the first dielectric layer 201. In the seventh step, the seed layer 11 exposed in the state of FIG. 7A is removed by etching.
[0062] 8A , a temporary adhesive layer 15 is formed to cover the plurality of first electrodes 4 and the first main surface 211 of the first dielectric layer 201. In the eighth step, the temporary adhesive layer 15 is formed by applying and drying a varnish containing an organic material (e.g., acrylic resin) for the temporary adhesive layer 15. The thickness of the temporary adhesive layer 15 is, for example, 20 μm.
[0063] 8B , in the ninth step, a carrier substrate 16 (hereinafter also referred to as a second carrier substrate 16) is bonded to the temporary adhesive layer 15. The second carrier substrate 16 includes, for example, a glass substrate 161 and a release layer 162 laminated on the glass substrate 161. In the ninth step, the release layer 162 of the second carrier substrate 16 is bonded to the temporary adhesive layer 15.
[0064] In a tenth step, as shown in FIG. 9A, the first carrier substrate 9 is peeled off from the second dielectric layer 202.
[0065] 9B , in the eleventh step, a plurality of second via holes 223 are formed in the second dielectric layer 202. In the eleventh step, the plurality of second via holes 223 are formed in regions in the second dielectric layer 202 where the plurality of second via conductor portions 33 are to be formed, respectively.
[0066] In the twelfth step, as shown in FIG. 10A, a plurality of second via conductors 33, a plurality of third electrodes 7, and a plurality of barrier layers 17 are formed.
[0067] 10B, in the thirteenth step, a plurality of solder bumps 18 are formed on each of the plurality of barrier layers 17. By performing the first to thirteenth steps, a structure 110 including the interposer 1 can be manufactured.
[0068] In a fourteenth step, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15 .
[0069] In the fifteenth step, the temporary adhesive layer 15 is peeled off from the interposer 1 .
[0070] In the method for manufacturing the interposer 1 according to the first embodiment, the interposer 1 is formed by performing the first to fifteenth steps.
[0071] (5) Advantages The interposer 1 according to the first embodiment includes a dielectric layer 201, a via conductor 31, a first electrode 4, and a second electrode 32. The dielectric layer 201 has a first main surface 211 and a second main surface 212 opposite to the first main surface 211. The via conductor 31 penetrates the dielectric layer 201. The first electrode 4 is circular and located across the first main surface 211 of the dielectric layer 201 and the via conductor 31. The first electrode 4 is connected to the via conductor 31. The second electrode 32 is circular and located across the second main surface 212 of the dielectric layer 201 and the via conductor 31. The second electrode 32 is connected to the via conductor 31. In a plan view from the thickness direction D1 of the dielectric layer 201, the second electrode 32 is smaller than the first electrode 4 and is located inside the outer edge 402 of the first electrode 4. The second electrode 32 has a first surface 321 in contact with the via conductor portion 31 and a second surface 322 opposite to the first surface 321. In the second electrode 32, a first outer diameter R1 of the first surface 321 is larger than a second outer diameter R2 of the second surface 322.
[0072] According to the above configuration, it is possible to improve the manufacturing yield. According to the above configuration, the first outer diameter R1 of the first surface 321 of the second electrode 32 is larger than the second outer diameter R2 of the second surface 322, so that the margin for aligning the first surface 321 of the second electrode 32 with the via conductor portion 31 can be increased, thereby improving the manufacturing yield.
[0073] In addition, in the interposer 1 of embodiment 1, the via conductor portion 31 is truncated cone-shaped, and the fourth outer diameter R4 on the second main surface 212 of the dielectric layer 201 is smaller than the third outer diameter R3 on the first main surface 211 of the dielectric layer 201.
[0074] According to the above configuration, the margin for alignment between the first surface 321 of the second electrode 32 and the via conductor portion 31 can be further increased, and the manufacturing yield can be further improved.
[0075] The interposer 1 according to the first embodiment further includes a second dielectric layer 202, a second via conductor 33, and a third electrode 7. The second dielectric layer 202 has a third main surface 221 in contact with the second main surface 212 of the first dielectric layer 201, which is the dielectric layer 201, and a fourth main surface 222 opposite to the third main surface 221. The second dielectric layer 202 covers the second electrode 32. The second via conductor 33 is different from the first via conductor 31, which is the via conductor 31. The second via conductor 33 penetrates the second dielectric layer 202 and is connected to the second electrode 32. The third electrode 7 is located across the fourth main surface 222 of the second dielectric layer 202 and the second via conductor 33, and is connected to the second via conductor 33. The second via conductor portion 33 has a truncated cone shape, and a fifth outer diameter R5 on the second surface 322 of the second electrode 32 is smaller than a sixth outer diameter R6 on the fourth main surface 222 of the second dielectric layer 202 .
[0076] The above configuration can further improve manufacturing yield. Furthermore, the above configuration can improve mounting reliability. More specifically, the above configuration can reduce the maximum principal stress (tensile stress) generated in the second electrode 32 when an IC chip is mounted on the third electrode 7, compared to when the outer diameter of the first surface of the second electrode is smaller than the outer diameter of the second surface, thereby improving mounting reliability.
[0077] The interposer 1 according to the first embodiment further includes a wiring portion 6 disposed on the second main surface 212 of the dielectric layer 201 and connected to the second electrode 32. The wiring portion 6 has a third surface 61 in contact with the second main surface 212 of the dielectric layer 201 and a fourth surface 62 opposite the third surface 61. In the wiring portion 6, a first width H1 of the third surface 61 is larger than a second width H2 of the fourth surface 62. The first width H1 of the wiring portion 6 is smaller than a first outer diameter R1 of the second electrode 32, and the second width H2 of the wiring portion 6 is smaller than a second outer diameter R2 of the second electrode 32. The wiring portion 6 is covered with the second dielectric layer 202.
[0078] According to the above configuration, it is possible to improve the reliability of the wiring portion 6 while narrowing the width of the wiring portion 6 .
[0079] An interposer 1A and a structure 110A according to a second embodiment will be described with reference to Fig. 11. With respect to the interposer 1A according to the second embodiment, the same components as those of the interposer 1 according to the first embodiment (see Fig. 1) will be assigned the same reference numerals and descriptions thereof will be omitted. Furthermore, with respect to the structure 110A according to the second embodiment, the same components as those of the structure 110 according to the first embodiment (see Fig. 3) will be assigned the same reference numerals and descriptions thereof will be omitted.
[0080] (1) Configuration The interposer 1A of the second embodiment differs from the interposer 1 of the first embodiment in that each of the multiple through wiring portions 3 of the interposer 1 of the first embodiment is composed only of a first via conductor portion 31, and the multiple second electrodes 32 constitute multiple second pad electrodes for IC connection.
[0081] In the interposer 1A according to the second embodiment, the second electrodes 32 are connected to the first electrodes 4 in a one-to-one relationship.
[0082] The structure 110A according to the second embodiment includes an interposer 1A, a temporary adhesive layer 15, and a carrier substrate 16.
[0083] (2) Method of Manufacturing Interposer With regard to the method of manufacturing the interposer 1A according to the second embodiment, the same steps as those in the method of manufacturing the interposer 1 according to the first embodiment will not be described as appropriate.
[0084] In the method for manufacturing the interposer 1A according to the second embodiment, the structure shown in Fig. 9A is obtained by performing the first to tenth steps of the method for manufacturing the interposer 1 according to the first embodiment, and then the second dielectric layer 202 is subjected to CMP (Chemical Mechanical Polishing) to expose the plurality of second electrodes 32 and the plurality of wiring portions 6. By performing the steps up to the tenth step, the structure 110A shown in Fig. 11 is formed.
[0085] Thereafter, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15 in the same manner as in step 14 of the manufacturing method of the interposer 1 of embodiment 1, and then the temporary adhesive layer 15 is peeled off in the same manner as in step 15, thereby obtaining the interposer 1A.
[0086] (3) Advantages Like the interposer 1 according to the first embodiment, the interposer 1A according to the second embodiment makes it possible to improve the manufacturing yield.
[0087] Third Embodiment An electronic component module 100 according to a third embodiment will be described with reference to Fig. 12. The electronic component module 100 according to the third embodiment includes the interposer 1 according to the first embodiment (see Fig. 1).
[0088] (1) Configuration The electronic component module 100 according to the third embodiment includes an interposer 1 , an IC chip 19 which is an electronic component, and a resin layer 20 .
[0089] The IC chip 19 is mounted on the interposer 1. More specifically, the IC chip 19 is flip-chip mounted on the interposer 1. The IC chip 19 has a plurality of external connection electrodes (not shown), which are connected to the plurality of third electrodes 7 of the interposer 1 via solder bumps 18, respectively.
[0090] The resin layer 20 is disposed on the fourth main surface 222 side of the second dielectric layer 202 of the interposer 1 so as to cover the IC chip 19. The resin layer 20 includes, for example, a resin (e.g., an epoxy resin). The resin layer 20 may further include a filler.
[0091] (2) Manufacturing method of electronic component module The manufacturing method of electronic component module 100 is substantially the same as the manufacturing method of interposer 1 of embodiment 1, but differs from the manufacturing method of interposer 1 of embodiment 1 in that it includes a component mounting process and a molding process between the 13th and 14th processes in the manufacturing method of interposer 1 of embodiment 1.
[0092] After performing steps 1 to 13 in the manufacturing method of interposer 1 according to embodiment 1 to obtain a structure similar to structure 110 shown in Figure 10B, in the component mounting step, an IC chip 19, which is an electronic component, is mounted on interposer 1 as shown in Figure 13A.
[0093] 13A, in the molding process, a resin layer 20 is formed on the fourth main surface 222 side of the second dielectric layer 202 of the interposer 1 so as to cover the IC chip 19. In a fourteenth process, as shown in FIG. 13B, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15.
[0094] In a fifteenth step, temporary adhesive layer 15 is removed to obtain electronic component module 100 including interposer 1 .
[0095] (3) Advantages The electronic component module 100 according to the third embodiment includes the interposer 1, which makes it possible to improve the manufacturing yield.
[0096] Fourth Embodiment An interposer 1 according to a fourth embodiment has the same configuration as the interposer 1 according to the first embodiment (see FIGS. 1 and 2), and therefore illustrations and detailed descriptions thereof will be omitted.
[0097] (1) Configuration The interposer 1 of embodiment 4 differs from the interposer 1 of embodiment 1 in that the first electrode 4 is rectangular (rectangular or square) and the second electrode 32 is rectangular (rectangular or square).
[0098] In the present embodiment, in a plan view from the thickness direction D1 of the dielectric layer 201, the outline of the first surface 321 of the second electrode 32 is located outside the outline of the second surface 322 of the second electrode 32. In the second electrode 32, the length of the shortest straight line among the group of straight lines that pass through the center of the first surface 321 and connect any two points on the outline of the first surface 321 is longer than the length of the shortest straight line among the group of straight lines that pass through the center of the second surface 322 and connect any two points on the outline of the second surface 322.
[0099] (2) Advantages The interposer 1 according to the fourth embodiment includes a dielectric layer 201, a via conductor 31, a first electrode 4, and a second electrode 32. The dielectric layer 201 has a first main surface 211 and a second main surface 212 opposite to the first main surface 211. The via conductor 31 penetrates the dielectric layer 201. The first electrode 4 is rectangular and is located across the first main surface 211 of the dielectric layer 201 and the via conductor 31. The first electrode 4 is connected to the via conductor 31. The second electrode 32 is rectangular and is located across the second main surface 212 of the dielectric layer 201 and the via conductor 31. The second electrode 32 is connected to the via conductor 31. In a plan view from the thickness direction D1 of the dielectric layer 201, the second electrode 32 is smaller than the first electrode 4 and is located inside the outer edge 402 of the first electrode 4. The second electrode 32 has a first surface 321 in contact with the via conductor portion 31 and a second surface 322 opposite to the first surface 321. In a plan view from the thickness direction D1 of the dielectric layer 201, the outline of the first surface 321 of the second electrode 32 is located outside the outline of the second surface 322 of the second electrode 32.
[0100] According to the above configuration, it is possible to improve the manufacturing yield.
[0101] (Other) In interposers 1 and 1A, the organic material that is the material of each of dielectric layer 201 (first dielectric layer 201) and second dielectric layer 202 is an insulator, and dielectric layer 201 (first dielectric layer 201), second dielectric layer 202, and dielectric substrate 2 are, respectively, an insulator layer (first insulator layer), a second insulator layer, and an insulator substrate.
[0102] (Modifications) The above-described first to fourth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to fourth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.
[0103] For example, in the interposers 1 and 1A, the material of each of the first dielectric layer 201 and the second dielectric layer 202 is not limited to an organic material, and may be, for example, an inorganic material (e.g., ceramic, etc.). In the interposers 1 and 1A, when the material of each of the dielectric layer 201 (first dielectric layer 201) and the second dielectric layer 202 is an inorganic material, the inorganic material is an insulator, and the dielectric layer 201 (first dielectric layer 201), the second dielectric layer 202, and the dielectric substrate 2 are an insulator layer (first insulator layer), a second insulator layer, and an insulator substrate, respectively.
[0104] In the interposers 1 and 1A, the dielectric substrate 2 may have one or more dielectric layers in addition to the first dielectric layer 201 and the second dielectric layer 202 .
[0105] Furthermore, in the interposers 1 and 1A, the via conductor portion 31 is not limited to a truncated cone shape, but may be a cylindrical shape.
[0106] Furthermore, the interposer 1, 1A has multiple sets of a first electrode 4, a via conductor portion 31, and a second electrode 32, but the number of sets of a first electrode 4, a via conductor portion 31, and a second electrode 32 may be one.
[0107] Furthermore, the shape of the second electrodes 32 of the interposer 1A of the second embodiment may be the same as that of the second electrodes 32 of the fourth embodiment.
[0108] (Aspects) The following aspects are disclosed in this specification.
[0109] The interposer (1; 1A) according to the first aspect comprises a dielectric layer (201), a via conductor (31), a first electrode (4), and a second electrode (32). The dielectric layer (201) has a first main surface (211) and a second main surface (212) opposite the first main surface (211). The via conductor (31) penetrates the dielectric layer (201). The first electrode (4) is circular and is located across the first main surface (211) of the dielectric layer (201) and the via conductor (31). The first electrode (4) is connected to the via conductor (31). The second electrode (32) is circular and is located across the second main surface (212) of the dielectric layer (201) and the via conductor (31). The second electrode (32) is connected to the via conductor (31). In a plan view from the thickness direction (D1) of the dielectric layer (201), the second electrode (32) is smaller than the first electrode (4) and is located inside the outer edge (402) of the first electrode (4). The second electrode (32) has a first surface (321) in contact with the via conductor portion (31) and a second surface (322) opposite to the first surface (321). In the second electrode (32), a first outer diameter (R1) of the first surface (321) is larger than a second outer diameter (R2) of the second surface (322).
[0110] According to this aspect, it is possible to improve the manufacturing yield.
[0111] In the interposer (1; 1A) of the second aspect, in the first aspect, the via conductor portion (31) is truncated cone-shaped, and the fourth outer diameter (R4) at the second main surface (212) of the dielectric layer (201) is smaller than the third outer diameter (R3) at the first main surface (211) of the dielectric layer (201).
[0112] According to this aspect, it is possible to further improve the manufacturing yield.
[0113] The interposer (1; 1A) according to the third aspect is the same as that of the first or second aspect, and further includes a second dielectric layer (202), a second via conductor (33), and a third electrode (7). The second dielectric layer (202) has a third main surface (221) in contact with the second main surface (212) of the first dielectric layer (201), which is the dielectric layer (201), and a fourth main surface (222) opposite the third main surface (221). The second dielectric layer (202) covers the second electrode (32). The second via conductor (33) is different from the first via conductor (31), which is the via conductor (31). The second via conductor (33) penetrates the second dielectric layer (202) and is connected to the second electrode (32). The third electrode (7) is located across the fourth main surface (222) of the second dielectric layer (202) and the second via conductor portion (33), and is connected to the second via conductor portion (33). The second via conductor portion (33) has a truncated cone shape, and a fifth outer diameter (R5) on the second surface (322) of the second electrode (32) is smaller than a sixth outer diameter (R6) on the fourth main surface (222) of the second dielectric layer (202).
[0114] According to this aspect, it is possible to further improve the manufacturing yield.
[0115] In the interposer (1; 1A) of the fourth aspect, in the third aspect, when viewed in a plane from the thickness direction (D1) of the dielectric layer (201), the third electrode (7) is smaller than the first electrode (4) and is located inside the outer edge (402) of the first electrode (4).
[0116] The interposer (1; 1A) according to a fifth aspect is the third or fourth aspect, further comprising a wiring portion (6) disposed on the second main surface (212) of the dielectric layer (201) and connected to the second electrode (32). The wiring portion (6) has a third surface (61) in contact with the second main surface (212) of the dielectric layer (201) and a fourth surface (62) opposite the third surface (61). In the wiring portion (6), the first width (H1) of the third surface (61) is larger than the second width (H2) of the fourth surface (62). The first width (H1) of the wiring portion (6) is smaller than the first outer diameter (R1) of the second electrode (32), and the second width (H2) of the wiring portion (6) is smaller than the second outer diameter (R2) of the second electrode (32). The wiring portion (6) is covered by the second dielectric layer (202).
[0117] According to this aspect, it is possible to improve the reliability of the wiring portion (6).
[0118] In the interposer (1; 1A) according to the sixth aspect, in any one of the third to fifth aspects, the material of each of the first dielectric layer (201) and the second dielectric layer (202) includes an organic material.
[0119] According to this aspect, it is possible to improve high frequency characteristics.
[0120] In the interposer (1A) according to the seventh aspect, in the first or second aspect, the second electrode (32) is a pad electrode for connecting to an IC.
[0121] In the interposer (1A) according to the eighth aspect, in the first or second aspect, the material of the dielectric layer (201) includes an organic material.
[0122] According to this aspect, it is possible to improve high frequency characteristics.
[0123] A structure (110; 110A) according to a ninth aspect includes an interposer (1; 1A) according to any one of the first to eighth aspects, a temporary adhesive layer (15), and a carrier substrate (16). The temporary adhesive layer (15) covers the first main surface (211) of the dielectric layer (201) and the first electrode (4) in the interposer (1; 1A). The temporary adhesive layer (15) is releasable from the interposer (1; 1A). The carrier substrate (16) is in contact with the temporary adhesive layer (15).
[0124] According to this aspect, it is possible to improve the manufacturing yield.
[0125] The electronic component module (100) according to the tenth aspect comprises an interposer (1; 1A) according to any one of the first to eighth aspects, and an IC chip (19) which is an electronic component connected to the second electrode (32) of the interposer (1; 1A).
[0126] According to this aspect, it is possible to improve the manufacturing yield.
[0127] An interposer (1; 1A) according to an eleventh aspect includes a dielectric layer (201), a via conductor (31), a first electrode (4), and a second electrode (32). The dielectric layer (201) has a first main surface (211) and a second main surface (212) opposite the first main surface (211). The via conductor (31) penetrates the dielectric layer (201). The first electrode (4) is rectangular and is located across the first main surface (211) of the dielectric layer (201) and the via conductor (31). The first electrode (4) is connected to the via conductor (31). The second electrode (32) is rectangular and is located across the second main surface (212) of the dielectric layer (201) and the via conductor (31). The second electrode (32) is connected to the via conductor (31). In a plan view from the thickness direction (D1) of the dielectric layer (201), the second electrode (32) is smaller than the first electrode (4) and is located inside the outer edge (402) of the first electrode (4). The second electrode (32) has a first surface (321) in contact with the via conductor portion (31) and a second surface (322) opposite to the first surface (321). In a plan view from the thickness direction (D1) of the dielectric layer (201), the outline of the first surface (321) of the second electrode (32) is located outside the outline of the second surface (322) of the second electrode (32).
[0128] According to this aspect, it is possible to improve the manufacturing yield.
[0129] DESCRIPTION OF SYMBOLS 1, 1A Interposer 201 Dielectric layer (first dielectric layer) 211 First main surface 212 Second main surface 202 Second dielectric layer 221 Third main surface 222 Fourth main surface 31 Via conductor portion (first via conductor portion) 32 Second electrode 321 First surface 322 Second surface 33 Second via conductor portion 4 First electrode 6 Wiring portion 61 Third surface 62 Fourth surface 7 Third electrode 19 IC chip 20 Resin layer 100 Electronic component module 110, 110A Structure D1 Thickness direction H1 First width H2 Second width R1 First outer diameter R2 Second outer diameter R3 Third outer diameter R4 Fourth outer diameter R5 Fifth outer diameter R6 Sixth outer diameter
Claims
1. An interposer comprising: a dielectric layer having a first main surface and a second main surface opposite to the first main surface; a via conductor portion penetrating the dielectric layer; a circular first electrode located across the first main surface of the dielectric layer and the via conductor portion and connected to the via conductor portion; and a circular second electrode located across the second main surface of the dielectric layer and the via conductor portion and connected to the via conductor portion, wherein, in a plan view in the thickness direction of the dielectric layer, the second electrode is smaller than the first electrode and is located inside the outer edge of the first electrode, the second electrode has a first surface in contact with the via conductor portion and a second surface opposite to the first surface, and a first outer diameter of the first surface of the second electrode is larger than a second outer diameter of the second surface.
2. The interposer according to claim 1, wherein the via conductor portion is frustum-shaped and has a fourth outer diameter on the second main surface of the dielectric layer that is smaller than a third outer diameter on the first main surface of the dielectric layer.
3. The interposer according to claim 1 or 2, further comprising: a second dielectric layer having a third main surface in contact with the second main surface of the first dielectric layer, which is the dielectric layer, and a fourth main surface opposite to the third main surface, and covering the second electrode; a second via conductor portion different from the first via conductor portion, which is the via conductor portion, penetrating the second dielectric layer and connected to the second electrode; and a third electrode located across the fourth main surface of the second dielectric layer and the second via conductor portion and connected to the second via conductor portion, wherein the second via conductor portion is frustum-shaped, and a fifth outer diameter of the second electrode on the second surface is smaller than a sixth outer diameter on the fourth main surface of the second dielectric layer.
4. An interposer according to claim 3, wherein, in a plan view from the thickness direction of the dielectric layer, the third electrode is smaller than the first electrode and is located inside the outer edge of the first electrode.
5. An interposer as described in claim 3, further comprising a wiring portion disposed on the second main surface of the dielectric layer and connected to the second electrode, the wiring portion having a third surface in contact with the second main surface of the dielectric layer and a fourth surface opposite the third surface, the first width of the third surface of the wiring portion being larger than the second width of the fourth surface, the first width of the wiring portion being smaller than the first outer diameter of the second electrode, the second width of the wiring portion being smaller than the second outer diameter of the second electrode, and the wiring portion being covered by the second dielectric layer.
6. The interposer of claim 3, wherein the material of each of the first and second dielectric layers includes an organic material.
7. The interposer according to claim 1 or 2, wherein the second electrode is a pad electrode for connecting to an IC.
8. The interposer according to claim 1 or 2, wherein the material of the dielectric layer includes an organic material.
9. A structure comprising an interposer, comprising: an interposer according to claim 1 or 2; a temporary adhesive layer covering the first main surface of the dielectric layer and the first electrode in the interposer and peelable from the interposer; and a carrier substrate in contact with the temporary adhesive layer.
10. An electronic component module comprising: the interposer according to claim 1 or 2; and an IC chip, which is an electronic component, connected to the second electrode of the interposer.
11. An interposer comprising: a dielectric layer having a first main surface and a second main surface opposite to the first main surface; a via conductor portion penetrating the dielectric layer; a rectangular first electrode located across the first main surface of the dielectric layer and the via conductor portion and connected to the via conductor portion; and a rectangular second electrode located across the second main surface of the dielectric layer and the via conductor portion and connected to the via conductor portion, wherein, in a planar view from the thickness direction of the dielectric layer, the second electrode is smaller than the first electrode and is located inside the outer edge of the first electrode, the second electrode has a first surface in contact with the via conductor portion and a second surface opposite to the first surface, and, in a planar view from the thickness direction of the dielectric layer, the outline of the first surface of the second electrode is located outside the outline of the second surface of the second electrode.