Component built-in substrate

Abstract

A component built-in substrate 1A comprises: a plurality of unit substrates; a first electronic component 40a; and a second electronic component 40b. The plurality of unit substrates each comprise a second single-sided substrate 10b including a wiring layer 12 which includes a wiring 121c connected to the second electronic component. The first electronic component includes second opposite sides 402a, 402b that do not overlap with any of the four sides of the second electronic component. The second electronic component includes fourth opposite sides 404a, 404b that do not overlap with any of the four sides of the first electronic component and that are adjacent to a first side with an interval therebetween. A second wiring extends in a manner intersecting the second opposite sides and the fourth opposite sides in a plan view.

Description

Embedded component board

[0001] The present invention relates to a component-embedded substrate having multiple electronic components built in. For designated countries where incorporation by reference of literature is permitted, the content of Japanese Patent Application No. 2024-032315 filed in Japan on March 4, 2024 is incorporated herein by reference and made a part of the description of this specification.

[0002] A multi-layer component-embedded substrate is known in which a plurality of unit substrates are stacked and a plurality of electronic components are embedded in the stacking direction (see, for example, Patent Document 1). The unit substrates include a double-sided substrate, an intermediate substrate, and a single-sided substrate.

[0003] The double-sided board has a first wiring layer formed on both sides of a first insulating layer, a first interlayer conductive layer that penetrates the first insulating layer and is connected to the first wiring layer, and an opening that accommodates an electronic component.

[0004] The intermediate substrate has first adhesive layers provided on both sides of the second insulating layer, and second interlayer conductive layers that penetrate the second insulating layer together with the first adhesive layers. Double-sided substrates are disposed above and below the intermediate substrate, respectively.

[0005] The single-sided substrate has a second wiring layer formed on one side of the third insulating layer, a third interlayer conductive layer that penetrates the third insulating layer and is connected to the second wiring layer, and a second adhesive layer provided on the other side of the third insulating layer, and a part of the third interlayer conductive layer of this single-sided substrate is connected to an electronic component.

[0006] A component-embedded substrate is manufactured by laminating a plurality of such unit substrates together by thermocompression bonding.

[0007] JP 2014-187350 A

[0008] In the conventional technology described above, multiple electronic components are arranged so that they coincide in a planar view (see, for example, FIG. 1 of Patent Document 1), and the gap between the outer periphery of the electronic components and the inner wall of the opening coincides in a planar view.

[0009] However, if these gaps are aligned in a plan view, the second insulating layer of the intermediate substrate is less likely to deform in the stacking direction during thermocompression bonding. Therefore, when the adhesive layer flows into the gap, the third insulating layer of the single-sided substrate deforms significantly toward the gap. In this case, if the second wiring layer of the single-sided substrate intersects the gap in a plan view, the second wiring layer will deform together with the third insulating layer, potentially reducing the electrical reliability of the component-embedded substrate.

[0010] The problem to be solved by the present invention is to provide a component-embedded substrate that can improve electrical reliability.

[0011] [1] Aspect 1 of the present invention is a component-embedded substrate including a plurality of unit substrates stacked on top of each other, a first electronic component, and a second electronic component, wherein the plurality of unit substrates include: a first double-sided substrate including a first insulating layer having a first opening formed therein in which the first electronic component is disposed; a second double-sided substrate including a second insulating layer having a second opening formed therein in which the second electronic component is disposed; a third insulating layer provided between the first and second double-sided substrates; a first intermediate substrate including a first adhesive layer formed on one side of the third insulating layer and a second adhesive layer formed on the other side of the third insulating layer; a fourth insulating layer, a third adhesive layer formed on the fourth insulating layer so as to be adhered to the first double-sided substrate; and a first wiring layer including first wiring connected to the first electronic component; a fifth insulating layer and a fifth insulating layer adhered to the second double-sided substrate. and a second single-sided substrate including a fourth adhesive layer formed on the fifth insulating layer so as to form a fourth adhesive layer on the fifth insulating layer, and a second wiring layer including second wiring connected to the second electronic component, wherein the first electronic component and the second electronic component have a substantially rectangular planar shape, the first electronic component overlaps the second electronic component in a planar view, the first electronic component includes a first side that does not overlap any of the four sides of the second electronic component in a planar view, and a second side that is different from the first side, the second electronic component includes a third side that does not overlap any of the four sides of the first electronic component in a planar view and is adjacent to the first side with a gap therebetween, and a fourth side that substantially overlaps the second side in a planar view, and the second wiring extends to intersect with the first and third sides in a planar view.

[0012] [2] A second aspect of the present invention may be the component-embedded substrate of the first aspect, wherein the component-embedded substrate satisfies the following formula (1): D≧W (1) where D is the distance between the first side and the third side in a plan view, and W is the distance between the first electronic component and the inner wall of the first opening.

[0013] [3] A third aspect of the present invention may be a component-embedded substrate according to the second aspect, wherein the first electronic component includes a pair of first opposite sides extending generally parallel to each other along a first direction in a plan view, and a pair of second opposite sides connected to the first opposite sides in a plan view and extending generally parallel to each other along a second direction generally perpendicular to the first direction; the second electronic component includes a pair of third opposite sides generally parallel to the first opposite sides in a plan view, and a pair of fourth opposite sides connected to the third opposite sides in a plan view and generally parallel to the second opposite sides; and wherein a first center of gravity of the first electronic component and a second center of gravity of the second electronic component are misaligned in the first direction or the second direction when the following formulas (2) and (3) are satisfied: |X1-X2|<W ... (2) |Y1-Y2|<W ... (3) However, in the above formula (2), X1 is the length of the first opposite side in the first direction, X2 is the length of the third opposite side in the first direction, and in the above formula (3), Y1 is the length of the second opposite side in the second direction, and Y2 is the length of the fourth opposite side in the second direction.

[0014] [4] A fourth aspect of the present invention relates to the component-embedded substrate of the second aspect, wherein the first electronic component includes a pair of first opposite sides extending generally parallel to each other along a first direction in a plan view, and a pair of second opposite sides connected to the first opposite sides in a plan view and extending generally parallel to each other along a second direction generally perpendicular to the first direction; the second electronic component includes a pair of third opposite sides generally parallel to the first opposite sides in a plan view, and a pair of fourth opposite sides connected to the third opposite sides in a plan view and generally parallel to the second opposite sides; and the component-embedded substrate may be such that, when the following formulas (4) and (5) are satisfied, a first center of gravity of the first electronic component and a second center of gravity of the second electronic component substantially coincide with each other or the first center of gravity and the second center of gravity are misaligned in the second direction: |X1-X2|<W ... (4) |Y1-Y2|>W ... (5) However, in the above formula (4), X1 is the length of the first opposite side in the first direction, X2 is the length of the third opposite side in the first direction, and in the above formula (5), Y1 is the length of the second opposite side in the second direction, and Y2 is the length of the fourth opposite side in the second direction.

[0015] [5] A fifth aspect of the present invention relates to the component-embedded substrate of the second aspect, wherein the first electronic component includes a pair of first opposite sides extending generally parallel to each other along a first direction in a plan view, and a pair of second opposite sides connected to the first opposite sides in a plan view and extending generally parallel to each other along a second direction generally perpendicular to the first direction; the second electronic component includes a pair of third opposite sides generally parallel to the first opposite sides in a plan view, and a pair of fourth opposite sides connected to the third opposite sides in a plan view and generally parallel to the second opposite sides; and wherein a first center of gravity of the first electronic component and a second center of gravity of the second electronic component are misaligned in the first direction or the second direction when the following formulas (6) and (7) are satisfied: |X1-X2|>W ... (6) |Y1-Y2|>W ... (7) However, in the above formula (6), X1 is the length of the first opposite side in the first direction, X2 is the length of the third opposite side in the first direction, and in the above formula (7), Y1 is the length of the second opposite side in the second direction, and Y2 is the length of the fourth opposite side in the second direction.

[0016] [6] Aspect 6 of the present invention may be a component-embedded substrate in which, in the component-embedded substrate of any one of Aspects 1 to 5, the first wiring layer is formed on one side of the fourth insulating layer, the third adhesive layer is formed on the other side of the fourth insulating layer, the second wiring layer is formed on the other side of the fifth insulating layer, the fourth adhesive layer is formed on one side of the fifth insulating layer, the first adhesive layer of the first intermediate substrate is adhered to the other side of the first double-sided substrate, the second adhesive layer of the first intermediate substrate is adhered to one side of the second double-sided substrate, the third adhesive layer of the first single-sided substrate is adhered to one side of the first double-sided substrate, and the fourth adhesive layer of the second single-sided substrate is adhered to the other side of the second double-sided substrate.

[0017] [7] A seventh aspect of the present invention is the component-embedded substrate of any one of Aspects 1 to 5, wherein the plurality of unit substrates further include a third single-sided substrate including a sixth insulating layer and a fifth adhesive layer formed on the sixth insulating layer so as to adhere to the first double-sided substrate from the side opposite to the third adhesive layer, and the first wiring layer is formed on the other side of the fourth insulating layer, the third adhesive layer is formed on one side of the fourth insulating layer, the second wiring layer is formed on the other side of the fifth insulating layer, and the fourth adhesive layer is formed on the fifth insulating layer. the first adhesive layer of the first intermediate substrate is adhered to the other side of the first single-sided substrate, the third adhesive layer of the first single-sided substrate is adhered to the other side of the first double-sided substrate, the fifth adhesive layer of the third single-sided substrate is adhered to one side of the first double-sided substrate, the second adhesive layer of the first intermediate substrate is adhered to one side of the second double-sided substrate, and the fourth adhesive layer of the second single-sided substrate is adhered to the other side of the second double-sided substrate.

[0018] [8] Aspect 8 of the present invention is a component-embedded substrate according to any one of Aspects 1 to 7, wherein the component-embedded substrate further includes a third electronic component having a substantially rectangular planar shape and overlapping the first and second electronic components in a planar view; the plurality of unit substrates further include a third double-sided substrate including a sixth insulating layer having a third opening in which the third electronic component is disposed; and a second intermediate substrate including a seventh insulating layer provided between the second and third double-sided substrates, a fifth adhesive layer formed on one side of the seventh insulating layer, and a sixth adhesive layer formed on the other side of the seventh insulating layer; and the third electronic component may be in the component-embedded substrate substantially coincident with the first electronic component in a planar view.

[0019] [9] A ninth aspect of the present invention may be the component-embedded substrate of the sixth aspect, wherein the thicknesses of the third to fifth insulating layers are half or less of the thicknesses of the first to fourth adhesive layers.

[0020]

[10] A tenth aspect of the present invention may be the component-embedded substrate of the seventh aspect, wherein the thicknesses of the third to sixth insulating layers are half or less of the thicknesses of the second to fifth adhesive layers.

[0021]

[11] Aspect 11 of the present invention may be a component-embedded substrate according to any one of aspects 1 to 10, wherein the first and second electronic components include a plurality of combinations of the first side and the third side, the combinations including a first combination in which the distance D between the first side and the third side is the longest, and the second wiring extends so as to intersect with the first combination in a planar view.

[0022] According to the present invention, the first electronic component includes a first side that does not overlap any of the four sides of the second electronic component in a plan view, and the second electronic component includes a third side that does not overlap any of the four sides of the first electronic component in a plan view and is adjacent to the first side with a gap therebetween. The second wiring extends so as to intersect with the first and third sides in a plan view. This reduces stress generated in the second wiring and makes the second wiring less susceptible to deformation, thereby improving electrical reliability.

[0023] FIG. 1 is a cross-sectional view showing a component-embedded substrate according to a first embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of portion II in FIG. 1. FIG. 3(a) is a plan view showing a first electronic component and a second electronic component according to the first embodiment of the present invention. FIG. 3(b) is a perspective view showing the positional relationship between the first electronic component, the second electronic component, and the wiring layer of a second single-sided board according to the first embodiment of the present invention, as viewed from the -Z direction. FIG. 4(a) is a cross-sectional view illustrating deformation of the wiring of a component-embedded substrate according to a comparative example. FIG. 4(b) is a cross-sectional view illustrating deformation of the wiring of a component-embedded substrate according to the first embodiment of the present invention. FIGS. 5(a) to 5(f) are cross-sectional views illustrating a method for manufacturing a single-sided board according to an embodiment of the present invention. FIGS. 6(a) to 6(e) are cross-sectional views illustrating a method for manufacturing a double-sided board according to an embodiment of the present invention. FIGS. 7(a) to 7(e) are cross-sectional views illustrating a method for manufacturing an intermediate board according to an embodiment of the present invention. FIG. 8 is a cross-sectional view showing a component-embedded substrate according to a second embodiment of the present invention. 9(a) to 9(d) are plan views showing the positional relationship between the first electronic component and the second electronic component in the first to fourth modified examples of the present invention. 10(a) to 10(c) are plan views showing the positional relationship between the first electronic component and the second electronic component in the fifth to seventh modified examples of the present invention. 11(a) and 11(b) are schematic cross-sectional views showing the positional relationship between the first to third electronic components in the eighth and ninth modified examples of the present invention. 12(a) to 12(d) are schematic cross-sectional views showing the positional relationship between the first to fourth electronic components in the tenth to thirteenth modified examples of the present invention.

[0024] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the upper surface (the surface on the +Z side in the drawings) in the following embodiments corresponds to an example of "one surface" in the aspects of the present invention, and the lower surface (the surface on the -Z side in the drawings) corresponds to an example of "the other surface" in the aspects of the present invention. However, the lower surface (the surface on the -Z side in the drawings) in the following embodiments may also correspond to an example of "one surface" in the aspects of the present invention, and the upper surface (the surface on the +Z side in the drawings) may also correspond to an example of "the other surface" in the aspects of the present invention.

[0025] First Embodiment

[0026] FIG. 1 is a cross-sectional view showing a component-embedded substrate 1A according to the first embodiment. FIG. 2 is an enlarged cross-sectional view of portion II in FIG. 1. FIG. 3(a) is a plan view showing a first electronic component 40a and a second electronic component 40b according to the first embodiment, and FIG. 3(b) is a back view showing the first electronic component 40a, the second electronic component 40b, and the wiring layer 12 of the second single-sided substrate 10b according to the first embodiment. Note that in FIGS. 3(a) and 3(b), solid lines indicate the first electronic component 40a, and dashed lines indicate the second electronic component 40b. Also, in FIG. 3(a), the terminals 41 of the first electronic component 40a are not shown. Also, in FIG. 3(b), the wiring layer 12 of the second single-sided substrate 10b is indicated by a two-dot chain line.

[0027] The component-embedded substrate 1A of this embodiment is a multilayer wiring board that has a plurality of electronic components 40a to 40c built in. The electronic components 40a to 40c are not particularly limited, but may be, for example, IC chips.

[0028] Since this component-embedded substrate 1A can be made smaller and thinner, it can be used in medical equipment such as wearable devices and implantable devices. Note that the uses of the component-embedded substrate 1A are not particularly limited to the uses described above, and the component-embedded substrate 1A may also be used for purposes other than medical equipment.

[0029] 1, the component-embedded substrate 1A includes first to third single-sided substrates 10a to 10c, first to third double-sided substrates 20a to 20c, first and second intermediate substrates 30a and 30b, and first to third electronic components 40a to 40c. Note that the numbers of single-sided substrates, double-sided substrates, intermediate substrates, and electronic components are not limited to these and may be changed as appropriate depending on the design of the component-embedded substrate 1A.

[0030] In this embodiment, a first single-sided substrate 10a is provided on the uppermost layer of the component-embedded substrate 1A. This first single-sided substrate 10a includes a resin base material 11, a wiring layer 12, an adhesive layer 13, a plurality of vias 14, and a plurality of vias 15. The resin base material 11 of the first single-sided substrate 10a corresponds to an example of the "fourth insulating layer" in this aspect of the present invention, the wiring layer 12 corresponds to an example of the "first wiring layer" in this aspect of the present invention, and the adhesive layer 13 corresponds to an example of the "third adhesive layer" in this aspect of the present invention.

[0031] The resin substrate 11 is made of an electrically insulating material such as a resin material. Specific examples of the resin constituting the resin substrate 11 include polyimide, polyolefin, and liquid crystal polymer (LCP). As shown in FIG. 2 , the thickness T1 of the resin substrate 11 is equal to or less than half the thickness T2 of the adhesive layer 13 (T1≦T2×½). Although not particularly limited, the thickness T1 of the resin substrate 11 may be, for example, about 12 μm.

[0032] A wiring layer 12 is formed on one surface (the upper surface in this embodiment, the surface on the +Z direction side in the drawing) of the resin base material 11. The wiring layer 12 is made of a conductive material such as copper, and is patterned on one main surface of the resin base material 11. The pattern shape of the wiring layer 12 can be any shape.

[0033] In this embodiment, the wiring layer 12 of the first single-sided substrate 10a includes wiring 121a and wiring 121b. Wiring 121a is electrically connected to the first electronic component 40a, while wiring 121b is electrically connected to the wiring layer 22 of the first double-sided substrate 20a. Although not particularly limited, in this embodiment, wiring 121a is separated from wiring 121b and is not electrically connected to wiring 121b in the component-embedded substrate 1A. Note that wiring 121a may be electrically connected to wiring 121b. Furthermore, wiring 121a corresponds to an example of the "first wiring" in this aspect of the present invention.

[0034] An adhesive layer 13 is formed on the other surface (the lower surface in this embodiment, the surface on the −Z direction side in the drawing) of the resin substrate 11. The adhesive layer 13 is formed by curing an organic adhesive such as an epoxy or acrylic adhesive containing a volatile component.

[0035] The adhesive layer 13 is adhered to one surface of the first double-sided substrate 20 a so as to cover the first opening 25 a of the first double-sided substrate 20 a. As shown in Fig. 2, the thickness T2 of the adhesive layer 13 is not particularly limited, but may be, for example, about 25 µm.

[0036] Vias 15 are interlayer conductive paths that electrically connect wiring layer 12 of first single-sided substrate 10a and wiring layer 22 of first double-sided substrate 20a. On the other hand, vias 14 are interlayer conductive paths that electrically connect wiring layer 12 of first single-sided substrate 10a and terminals 41 of first electronic component 40a, and first electronic component 40a is mounted on the other surface of first single-sided substrate 10a via vias 14.

[0037] Although not particularly limited, the vias 14 and 15 are formed by hardening a conductive paste filled in through holes that penetrate the resin base material 11 and the adhesive layer 13. Although not particularly limited, the vias 14 and 15 electrically connect the wiring layers 12 and 22 and also electrically connect the wiring layer 12 and the terminal 41 by contacting or bonding the metal particles contained in the vias 14 and 15 with each other.

[0038] The conductive paste that forms the vias 14 and 15 contains, for example, at least one type of low electrical resistance metal particles selected from nickel, gold, silver, copper, aluminum, iron, etc., and at least one type of low melting point metal particles selected from tin, bismuth, indium, lead, etc. The conductive paste is made from a paste in which these metal particles are mixed with a binder component whose main component is epoxy, acrylic, urethane, etc.

[0039] The conductive paste thus configured has the characteristics of a metal sintering type, with a hardening temperature of approximately 150°C to 200°C and a melting point of 260°C or higher after hardening. For example, low-melting-point metal particles can melt at 200°C or lower to form an alloy, and can form intermetallic compounds with copper, silver, or the like, in particular. Therefore, the connection portions between the vias 14, 15 and the wiring layers 12, 22 are alloyed with intermetallic compounds during the batch thermocompression bonding described below.

[0040] The conductive paste may be a paste formed by mixing low-electrical-resistance metal particles, such as nickel, with the binder component. In this case, the conductive paste establishes electrical connection by contact between the metal particles. Alternatively, the conductive paste may be a nanopaste, in which a filler with nano-sized particles, such as gold, silver, copper, or nickel, is mixed with the binder component.

[0041] A first double-sided substrate 20a is bonded to the other surface of the first single-sided substrate 10a. As shown in Fig. 1, the first double-sided substrate 20a includes a resin base material 21, wiring layers 22 and 23, and a plurality of vias 24. The resin base material 21 of the first double-sided substrate 20a corresponds to an example of a "first insulating layer" in accordance with an aspect of the present invention.

[0042] The resin substrate 21 is made of an electrically insulating material such as a resin material. Specific examples of the resin that makes up the resin substrate 21 include polyimide, polyolefin, and liquid crystal polymer (LCP). As shown in Fig. 2, the thickness T3 of the resin substrate 21 is thicker than the thicknesses of the resin substrates and adhesive layers of the other substrates. Although not particularly limited, the thickness T3 of the resin substrate 21 may be, for example, about 50 µm.

[0043] The resin base material 21 has a first opening 25a formed therein, penetrating the resin base material 21 in its thickness direction. The first opening 25a accommodates a first electronic component 40a. The planar shape of the first opening 25a is a rectangle similar to the planar shape of the first electronic component 40a (described later). In addition, in a planar view, the center C1 of the first opening 25a (see FIG. 3A) and the first center of gravity G1 of the first electronic component 40a (see FIG. 3A) substantially coincide with each other.

[0044] In this embodiment, "the centers of gravity G1 and G2 substantially coincide" means that the distance between the centers of gravity G1 and G2 is equal to or greater than 0 and less than W / 2 (described later) in a plan view. In other words, this means that the centers of gravity overlap or the distance between the centers of gravity is less than W / 2.

[0045] 2, a gap 252a is formed between an inner wall 251 of the first opening 25a and an opposing side surface 401 of the first electronic component 40a that faces the inner wall 251. The planar shape of this gap 252a (the shape when viewed from above) is a frame shape that surrounds the periphery of the first electronic component 40a. This gap 252a is filled with the adhesive that constitutes the adhesive layer 13 of the first single-sided substrate 10a and the adhesive that constitutes the adhesive layer 32 of the first intermediate substrate 30a, which will be described later.

[0046] The width W of this gap 252a is determined based on the thickness of the first electronic component 40a, etc. The thickness of the first electronic component 40a is basically approximately the same as the thickness of the second and third electronic components 40b, 40c, and therefore the widths of gaps 252b and 252c, which will be described later, are also W. The width W is not particularly limited, but ideally, when thermocompression bonding is performed from above and below in the absence of other electronic components, it is a width that allows adhesive to flow into the gap to an extent that does not cause unevenness and that allows the gap to be sufficiently filled with adhesive.

[0047] 1, the wiring layers 22, 23 are made of a conductive material such as a metal material. Specific examples of the material making up the wiring layers 22, 23 include copper, as with the wiring layer 12. The wiring layer 22 is formed on one side of the resin base material 11, and the wiring layer 23 is formed on the other side of the resin base material 11. The wiring layers 22, 23 have a predetermined pattern shape. The pattern shape of the wiring layers 22, 23 can be any shape.

[0048] The vias 24 are interlayer conductive paths that electrically connect the wiring layers 22, 23 formed on both main surfaces of the resin base material 11. The vias 24 are formed by filling the interior of through holes that penetrate the resin base material 21 in its thickness direction with copper by plating. The configuration of the vias 24 is not particularly limited as long as they electrically connect the wiring layers 22, 23. For example, the vias 24 may be vias formed by forming a copper layer on the inner wall surface of the through holes in the resin base material 21. Alternatively, the vias 24 may be vias formed by hardening the above-mentioned conductive paste.

[0049] 3A, the first electronic component 40a in this embodiment has a rectangular planar shape. However, the planar shape of the first electronic component 40a may be a square. Alternatively, the planar shape of the first electronic component 40a may be a rounded rectangle in which the corners of a rectangle are replaced with curved lines.

[0050] In a plan view, the first electronic component 40a includes a pair of first opposite sides 401a, 401b and a pair of second opposite sides 402a, 402b. The first opposite sides 401a, 401b extend substantially parallel to each other in the X direction. On the other hand, unlike the pair of first opposite sides 401a, 401b, the second opposite sides 402a, 402b extend substantially parallel to each other in the Y direction.

[0051] Both ends of the second opposite sides 402a and 402b are connected to both ends of the first opposite sides 401a and 401b. The length Y1 of the second opposite sides 402a and 402b is shorter than the length X1 of the first opposite sides 401a and 401b (Y1<X1). The second opposite sides 402a and 402b correspond to an example of a "first side" in this aspect of the present invention, and the first opposite sides 401a and 401b correspond to an example of a "second side" in this aspect of the present invention. The X direction corresponds to an example of a "first direction" in this aspect of the present invention, and the Y direction corresponds to an example of a "second direction" in this aspect of the present invention.

[0052] 1, a first intermediate substrate 30a is adhered to the other surface of the first double-sided substrate 20a so as to cover the first opening 25a and the first electronic component 40a. The first intermediate substrate 30a includes a resin base material 31, an adhesive layer 32, an adhesive layer 33, and a plurality of vias 34. The resin base material 31 of the first intermediate substrate 30a corresponds to an example of a "third insulating layer" in this aspect of the present invention, the adhesive layer 32 corresponds to an example of a "first adhesive layer" in this aspect of the present invention, and the adhesive layer 33 corresponds to an example of a "second adhesive layer" in this aspect of the present invention.

[0053] The resin substrate 31 is made of an electrically insulating material such as a resin material. Specific examples of resins that make up the resin substrate 31 include polyimide, polyolefin, and liquid crystal polymer (LCP). As shown in FIG. 2, the thickness T4 of the resin substrate 31 is equal to or less than half the thicknesses T5 and T6 of the adhesive layers 32 and 33 of the first intermediate substrate 30a (T4≦T5×1 / 2, T4≦T6×1 / 2), and equal to or less than half the thickness T2 of the adhesive layers 13 of the first and second single-sided substrates 10a and 10b (T4≦T2×1 / 2). While not particularly limited, the thickness T4 of the resin substrate 31 may be, for example, approximately 12 μm.

[0054] 1, the adhesive layer 32 is provided on one surface of the resin substrate 31, and the adhesive layer 33 is provided on the other surface 212 of the resin substrate 31. The adhesive layers 32 and 33 are formed by curing an organic adhesive, such as an epoxy or acrylic adhesive, that contains a volatile component.

[0055] The adhesive layer 32 is adhered to the other surface of the first double-sided substrate 20 a so as to cover the first opening 25 a of the first double-sided substrate 20 a. As shown in Fig. 2, the thickness T5 of the adhesive layer 32 is not particularly limited, but may be, for example, about 25 µm.

[0056] The adhesive layer 33 is adhered to one surface of the second double-sided substrate 20b so as to cover the second opening 25b and the second electronic component 40b of the second double-sided substrate 20b. The thickness T6 of the adhesive layer 33 is not particularly limited, but may be approximately the same as the thickness T5 of the adhesive layer 32 (T6 = T5), for example, about 25 μm. The thickness T6 of the adhesive layer 33 may be different from the thickness T5 of the adhesive layer 32, but is preferably at least twice the thickness T4 of the resin base material 31 (T6 ≧ T4 × 2).

[0057] 1 , the vias 34 are interlayer conductive paths that electrically connect the wiring layer 23 of the first double-sided substrate 20 a and the wiring layer 22 of the second double-sided substrate 20 b. Although not particularly limited, the vias 34 are formed by hardening a conductive paste that is filled in through holes that penetrate the resin base material 31 and the adhesive layers 32, 33. Although not particularly limited, the vias 34 electrically connect the wiring layers 23, 22 by contacting or bonding the metal particles contained in the vias 34.

[0058] The second double-sided substrate 20b is adhered to the other surface of the first intermediate substrate 30a. The first intermediate substrate 30a covers one surface of the second double-sided substrate 20b so as to cover the second opening 25b of the second double-sided substrate 20b.

[0059] Similar to the first double-sided board 20a, the second double-sided board 20b in this embodiment also includes a resin base material 21, wiring layers 22 and 23, and a plurality of vias 24. The resin base material 21 of the second double-sided board 20b corresponds to an example of a "second insulating layer" in this aspect of the present invention.

[0060] This second double-sided substrate 20b basically has the same configuration as the first double-sided substrate 20a, but the position of the second opening 25b is shifted with respect to the position of the first opening 25a. That is, the second opening 25b formed in the resin base material 21 of the second double-sided substrate 20b is shifted in the −X direction in the figure when viewed from above.

[0061] 2 , a gap 252b is formed between the inner wall 151 of the second opening 25b and the opposing side surface 401 of the second electronic component 40b facing the inner wall 151, and the width of the gap 252b is W, similar to the width of the gap 252a. In this embodiment, the amount of deviation D1 of the second opening 25b from the first opening 25a is equal to or greater than the width W of the gap 252a (D1≧W). Note that, although not particularly limited, the amount of deviation D1 in this embodiment is the distance between the inner wall 251 of the first opening 25a and the inner wall 251 of the second opening 25b in a plan view, and the gap 252b is offset from the gap 252a by an amount of deviation D2.

[0062] The second opening 25b accommodates the second electronic component 40b. The planar shape of the second opening 25b is a rectangle similar to the planar shape of the second electronic component 40b. As shown in FIG. 3A, in plan view, the center C2 of the second opening 25b and the second center of gravity G2 of the second electronic component 40b substantially coincide with each other. As described above, in this embodiment, "the center and the center of gravity substantially coincide" means that the distance between the center and the center of gravity is equal to or greater than 0 and less than W / 2 in plan view.

[0063] Although not particularly limited, the planar shape of the second electronic component 40c in this embodiment is substantially the same rectangular shape as the first electronic component 40a. Therefore, like the first electronic component 40a, the second electronic component 40b also includes a pair of third opposite sides 403a, 403b and a pair of fourth opposite sides 404a, 404b in plan view. The fourth opposite sides 404a, 404b correspond to an example of the "third side" in this aspect of the present invention, and the third opposite sides 403a, 403b correspond to an example of the "fourth side" in this aspect of the present invention.

[0064] The third opposite sides 403a, 403b extend substantially parallel to the first opposite sides 401a, 401b. Meanwhile, the fourth opposite sides 404a, 404b extend substantially parallel to the second opposite sides 402a, 402b, and both ends of the fourth opposite sides 404a, 404b are connected to both ends of the third opposite sides 403a, 403b. The length X2 of the third opposite sides 403a, 403b is substantially the same as the length X1 of the first opposite sides 401a, 401b (X2 = X1), and the length Y2 of the fourth opposite sides 404a, 404b is substantially the same as the length Y1 of the second opposite sides 402a, 402b (Y2 = Y1). Therefore, in this embodiment, the absolute value of the difference between length X1 and length X2, |X1-X2|, is smaller than W (|X1-X2| = 0<W), and the absolute value of the difference between length Y1 and length Y2, |Y1-Y2|, is also smaller than W (|Y1-Y2| = 0<W).

[0065] In plan view, the second electronic component 40b overlaps with but does not coincide with the first electronic component 40. In this embodiment, the second opening 25b is shifted in the −X direction relative to the first opening 25a in plan view, and therefore the second electronic component 40b is also shifted in the −X direction relative to the first electronic component 40a in plan view.

[0066] 2, in this embodiment, the amount of deviation D2 of the second electronic component 40b from the first electronic component 40a is substantially the same as the amount of deviation D1 between the first and second openings 25a, 25b (D2=D1), and therefore the amount of deviation D2 is equal to or greater than the width W of the gap 252a (D2≧W). Note that, as shown in FIG. 3A, although not particularly limited, the amount of deviation D2 in this embodiment is the distance between the second opposite side 402a and the fourth opposite side 404a.

[0067] Due to this misalignment, the fourth opposite sides 404a, 404b do not overlap any of the four sides (the pair of first opposite sides 401a, 401b and the pair of second opposite sides 402a, 402b) of the first electronic component 40a in a plan view. The fourth opposite side 404a is adjacent to the second opposite side 402a with a gap therebetween, and the fourth opposite side 404b is adjacent to the second opposite side 402b with a gap therebetween. Meanwhile, a portion of the third opposite side 403a substantially overlaps a portion of the first opposite side 401a, and a portion of the third opposite side 403b substantially overlaps a portion of the first opposite side 401b.

[0068] In this embodiment, "sides substantially overlap" means that the distance between the sides is equal to or greater than 0 and less than W / 2 (described later) in plan view. In other words, it means that the sides (or a part of one side and another side) coincide with each other, or the distance between the sides is less than W / 2.

[0069] 1, a second single-sided substrate 10b is adhered to the other side of the second double-sided substrate 20b so as to cover the second opening 25b and the second electronic component 40b. The second electronic component 40b is mounted on one side of this second single-sided substrate 10b. Therefore, in this embodiment, the back surface of the first electronic component 40a (the surface opposite to the surface on which the terminals 41 are formed) and the back surface of the second electronic component 40b face each other via the first intermediate substrate 30a.

[0070] Similar to the first single-sided substrate 10a, the second single-sided substrate 10b includes a resin base material 11, a wiring layer 12, an adhesive layer 13, a plurality of vias 14, and a plurality of vias 15. The resin base material 11 of the second single-sided substrate 10b corresponds to an example of a "fifth insulating layer" in this aspect of the present invention, the wiring layer 12 corresponds to an example of a "second wiring layer" in this aspect of the present invention, and the adhesive layer 13 corresponds to an example of a "fourth adhesive layer" in this aspect of the present invention.

[0071] Unlike the first single-sided substrate 10a, the adhesive layer 13 of the second single-sided substrate 10b is formed on one side of the second single-sided substrate 10b. Although not particularly limited, the thickness of the adhesive layer 13 of the second single-sided substrate 10b is T2, the same as that of the first single-sided substrate 10a.

[0072] Furthermore, in this second single-sided substrate 10b, the wiring layer 12 is formed on the other side of the second single-sided substrate 10b. The wiring layer 12 also has wiring 121c and 121d that connect between the vias 14 and 15. The wiring 121c and 121d are also connected to the via 14, and are thereby electrically connected to the second electronic component 40b. The wiring 121c and 121d correspond to an example of the "second wiring" in this aspect of the present invention.

[0073] As shown in FIG. 3B, the wiring 121c extends so as to intersect with the second opposite side 402a and the fourth opposite side 404a in a plan view. Therefore, as shown in FIG. 2, the wiring 121c extends so as to intersect with the gap 252a and the gap 252b in a plan view. Also, as shown in FIG. 3B, the wiring 121d extends so as to intersect with the second opposite side 402b and the fourth opposite side 404b in a plan view. Therefore, as shown in FIG. 2, the wiring 121d also extends so as to intersect with the gap 252a and the gap 252b in a plan view. On the other hand, the wirings 121c and 121d do not intersect with the first opposite sides 401a and 401b and the third opposite sides 403a and 403b in a plan view.

[0074] 2, a second intermediate substrate 30b is bonded to the other surface of the second single-sided substrate 10b. Like the first intermediate substrate 30a, the second intermediate substrate 30b also includes a resin base material 31, an adhesive layer 32, an adhesive layer 33, and a plurality of vias 34. The second intermediate substrate 30b basically has the same configuration as the first intermediate substrate 30a. The resin base material 31 of the second intermediate substrate 30b corresponds to an example of the "seventh insulating layer" in this aspect of the present invention, the adhesive layer 32 corresponds to an example of the "fifth adhesive layer" in this aspect of the present invention, and the adhesive layer 33 corresponds to an example of the "sixth adhesive layer" in this aspect of the present invention.

[0075] The adhesive layer 32 of the second intermediate substrate 30b is adhered to the other surface of the second single-sided substrate 10b. The thickness T7 of the adhesive layer 32 is substantially the same as the thickness T4 of the resin base material 31 (T7 = T4). Although not particularly limited, the thickness T7 of the adhesive layer 32 may be, for example, about 12 μm.

[0076] The adhesive layer 33 of the second intermediate substrate 30b is adhered to one surface of the third double-sided substrate 20c so as to cover the third opening 25c and the third electronic component 40c of the third double-sided substrate 20c. The thickness of the adhesive layer 33 is approximately the same as the thickness T6 of the adhesive layer 33. Although not particularly limited, the thickness T6 of the adhesive layer 33 may be, for example, about 25 μm.

[0077] Also, vias 34 of second intermediate substrate 30b are interlayer connection paths that connect wiring 121c, 121d with wiring layer 22 of third double-sided substrate 20c.

[0078] Similar to the first double-sided board 20a, the third double-sided board 20c includes a resin base material 21, wiring layers 22 and 23, and a plurality of vias 24. The resin base material 21 of the third double-sided board 20c corresponds to an example of a "sixth insulating layer" in accordance with an aspect of the present invention.

[0079] The wiring layer 22 of this third double-sided substrate 20c is connected to the via 34 of the second intermediate substrate 30b, while the wiring layer 23 is connected to the via 15 of the third single-sided substrate 10c.

[0080] Furthermore, in the third double-sided substrate 20c, the third opening 25c formed in the resin base material 21 coincides with the first opening 25a of the first double-sided substrate 20a in plan view. Therefore, the third electronic component 40c also overlaps with the first electronic component 40a and the second electronic component 40b in plan view, but while it coincides with the first electronic component 40a, it is shifted in the X direction with respect to the second electronic component 40b.

[0081] A third single-sided substrate 10c is bonded to the other surface of the third double-sided substrate 20c so as to cover the third opening 25c. In other words, the third single-sided substrate 10c is provided as the bottom layer of the component-embedded substrate 1A.

[0082] The third single-sided substrate 10c includes a resin base material 11, a wiring layer 12, an adhesive layer 13, a plurality of vias 14, and a plurality of vias 15, similar to the first single-sided substrate 10a.

[0083] The wiring layer 12 of the third single-sided substrate 10c includes wiring 121a and wiring 121b, similar to that of the first single-sided substrate 10a. Wiring 121a is electrically connected to terminal 41 of third electronic component 40c through via 14. Meanwhile, wiring 121b is electrically connected to wiring layer 23 of third double-sided substrate 20c through via 15.

[0084] The adhesive layer 13 of the third single-sided substrate 10c is formed on one surface of the resin base material 11. The thickness of this adhesive layer 13 is approximately the same as the thickness T2 of the above-mentioned adhesive layer 13. Although not particularly limited, the thickness T2 of this adhesive layer 13 may be, for example, about 25 μm.

[0085] The effects of the component-embedded substrate 1A described above will be described with reference to Fig. 4. Fig. 4(a) is a cross-sectional view illustrating deformation of the wiring 121e of the component-embedded substrate 1C in the comparative example, and Fig. 4(b) is a cross-sectional view illustrating deformation of the wiring 121c of the component-embedded substrate 1A in the first embodiment.

[0086] 4A, in the component-embedded substrate 1C of the comparative example, the first electronic component 40d and the second electronic component 40e have the same shape, as in the component-embedded substrate 1A. Furthermore, in the vicinity of the first and second electronic components 40d, 40e, as in the component-embedded substrate 1A, the first double-sided substrate 20d, the first intermediate substrate 30c, the second double-sided substrate 20e, the second single-sided substrate 10e, and the second intermediate substrate 30d are stacked. On the other hand, the component-embedded substrate 1C of the comparative example differs from the component-embedded substrate 1A of the first embodiment in that the first electronic component 40d and the second electronic component 40e are aligned in a plan view, and the four sides of the first electronic component 40d and the four sides of the second electronic component 40e are aligned.

[0087] When the first electronic component 40d and the second electronic component 40e are aligned in a plan view, as in the component-embedded substrate 1C of this comparative example, the gap 252d in the first opening 25d and the gap 252e in the second opening 25e are aligned in a plan view. In this configuration, when the unit substrates of the component-embedded substrate 1C are thermocompression-bonded together, the resin base material 31 located between the gap 252d and the gap 252e is structurally balanced and therefore less likely to deform. Instead, the adhesive layer 13 flows into the gap 252e, causing the resin base material 11 of the second single-sided substrate 10e to deform significantly upward along with the wiring 121e. This results in uneven stress being applied to the connection between the wiring 121e and the vias 14e and 15e, reducing the connection reliability of the vias 14e and 15e. This, in turn, reduces the electrical reliability of the component-embedded substrate 1C.

[0088] On the other hand, in the component-embedded substrate 1A of the first embodiment, as shown in FIG. 3B, the wiring 121c extends in a plan view so as to intersect the second opposite side 402a and the adjacent fourth opposite side 404a, spaced apart by the second opposite side 402a. As a result, as shown in FIG. 4B, the gap 252a is misaligned with the gap 252b in a plan view. With this configuration, the resin base material 31 is structurally unbalanced, so that deformation of the resin base material 31 of the first intermediate substrate 30a is more likely to occur when the unit substrates of the component-embedded substrate 1A are thermocompression-bonded together. This makes it easier for the adhesive layer 33, in addition to the adhesive layer 13, to flow into the gap 252b, thereby reducing deformation of the resin base material 11 of the second single-sided substrate 10b. This reduces deformation of the wiring 121c and reduces stress applied to the connection portions with the vias 14 and 15, thereby improving the connection reliability of the vias 14 and 15. Therefore, the electrical reliability of the component-embedded substrate 1A can be improved.

[0089] Furthermore, in the component-embedded substrate 1A of the first embodiment, the first electronic component 40a overlaps with the second and third electronic components 40b, 40c in a planar view. Therefore, regardless of the shapes of the first to third electronic components 40a to 40c, the increase in size of the component-embedded substrate 1A in the planar direction (the X and Y directions in the figure) can be suppressed compared to a case in which the electronic components do not overlap in a planar view. In particular, in this embodiment, the first electronic component 40a coincides with the third electronic component 40c in a planar view, so the increase in size of the component-embedded substrate 1A can be suppressed.

[0090] 2, in the component-embedded substrate 1A of this embodiment, the thicknesses T1 and T4 of the resin base materials 11 and 31 and the thickness T7 of the adhesive layer 32 of the second intermediate substrate 30b are less than half the thicknesses T2, T5, and T6 of the adhesive layers 13, 32, and 33 covering the first to third openings 25a to 25c. This allows the component-embedded substrate 1A to be thinned. Furthermore, when attempting to thin the component-embedded substrate 1A, a sufficient amount of adhesive may not flow into the gaps 252a to 252c, resulting in voids (spaces unfilled with adhesive) in the gaps 252a to 252c and reduced moisture absorption reflow resistance. However, in this embodiment, the thicknesses T2, T5, and T6 of the adhesive layers 13 and 32 covering the first to third openings 25a to 25c are relatively thick, thereby suppressing the generation of voids and maintaining moisture absorption reflow resistance.

[0091] A method for manufacturing the component-embedded substrate 1A of the first embodiment will be described below. As will be described below, the component-embedded substrate 1A is formed by individually manufacturing each of the unit substrates 10, 20a to 20c, and 30, and then stacking and thermocompression bonding them together.

[0092] First, a description will be given of a method for manufacturing the single-sided substrate 10. Figures 5(a) to 5(f) are cross-sectional views illustrating each step of the method for manufacturing the single-sided substrate 10 according to the first embodiment of the present invention.

[0093] First, a single-sided CCL is prepared, in which a conductor layer 122 is formed on one side (the bottom side in this example) of a resin substrate 11 (FIG. 5(a)). The single-sided CCL used here is not particularly limited, but may be, for example, a resin substrate 11 having a thickness of about 12 μm bonded to a conductor layer 122 made of copper foil having a thickness of about 12 μm. This single-sided CCL may be prepared, for example, by applying a polyimide varnish to copper foil using a known casting method and then curing the varnish.

[0094] The single-sided CCL may be formed by forming a seed layer on a polyimide film by sputtering, and then growing copper by plating to form a conductor layer, or by bonding a rolled or electrolytic copper foil to a polyimide film with an adhesive, etc. The resin substrate 11 does not necessarily have to be made of polyimide, and may be made of a plastic film such as a liquid crystal polymer as described above.

[0095] Next, the conductor layer 122 is subjected to etching or the like to form the wirings 121a and 121b of the wiring layer 12 (FIG. 5B).

[0096] Next, the adhesive 13B and the resin film 16 are sequentially stacked on top of each other on the upper surface of the resin substrate 11 and bonded together by thermocompression ( FIG. 5( c) ). While not particularly limited, a specific example of the adhesive 13B is an epoxy-based thermosetting film. A specific example of the resin film 16 is a polyimide resin film. A vacuum laminator is used to bond the films together, and the adhesive 13B is heat-pressed in a reduced pressure atmosphere at a temperature equal to or lower than the curing temperature of the adhesive 13B, thereby bonding the adhesive 13B and the resin film 16 to the resin substrate 11. Note that instead of a film-like adhesive, a varnish-like adhesive may be used as the adhesive 13B. In this case, the adhesive 13B is applied to the upper surface of the resin substrate 11.

[0097] Next, through holes 101 and 102 are formed through the resin film 16, the adhesive 13B, and the resin base material 11 ( FIG. 5( d) ). Specifically, the through holes 101 and 102 are formed by irradiating the resin film 16 with laser light from the upper side in the figure. Note that the through holes 101 and 102 may be formed by drilling, chemical etching, or the like instead of laser processing. The through holes 101 and 102 may also be subjected to a desmear treatment.

[0098] This desmearing treatment is carried out by CF ４ and O ２ Although the desmearing can be performed using a mixed gas of (tetrafluoromethane + oxygen), an inert gas such as Ar (argon) may also be used. Furthermore, the desmearing may be a wet desmearing using a chemical solution, instead of a so-called dry desmearing.

[0099] Next, the through holes 101, 102 are filled with the conductive pastes 14B, 15B (FIG. 5(e)). Specific methods for filling the through holes 101, 102 with the conductive pastes 14B, 15B include, for example, a printing method such as screen printing, a spin coating method, a spray coating method, a dispensing method, and a lamination method.

[0100] Next, the resin film 16 is peeled off from the adhesive 13B (FIG. 5(f)). As a result, the tip portions of the conductive pastes 14B and 15B protrude from the surface of the adhesive 13B by an amount corresponding to the thickness of the resin film 16. Note that the conductive pastes 14B and 15B are thermally cured by the above-mentioned thermocompression bonding, and the vias 14 and 15 are formed. Similarly, the adhesive 13B is thermally cured by the thermocompression bonding, and the adhesive layer 13 is formed. In this manner, the first and third single-sided substrates 10a and 10c can be produced.

[0101] In the manufacturing method shown in Figure 5, the first and third single-sided substrates 10a and 10c are produced, but when producing the second single-sided substrate 10b, it is sufficient to form the wiring 121c in the etching process of Figure 5(b).

[0102] Next, a method for manufacturing the double-sided boards 20a and 20c will be described. Figures 6(a) to 6(d) are cross-sectional views illustrating each step of the method for manufacturing the double-sided boards 20a and 20c according to the first embodiment of the present invention.

[0103] First, a double-sided CCL is prepared, comprising a resin substrate 21 and conductor layers 221, 231 laminated on both sides of the resin substrate 21 ( FIG. 6( a) ). While not particularly limited, a specific example of this double-sided CCL is one fabricated by laminating copper foil of approximately 12 μm thickness on both sides of a polyimide film of approximately 50 μm thickness. The CCL may be fabricated by a so-called casting method, in which polyimide varnish is applied to copper foil and then cured. Alternatively, the CCL may be fabricated by forming a seed layer on a polyimide film and growing copper by plating.

[0104] Next, through holes 201 are formed that penetrate the resin substrate 21 and the conductor layer 221 ( FIG. 6B ). Specifically, first, the conductor layer 221 is subjected to an etching process to remove a portion of the conductor layer 221, and then the removed portion is irradiated with laser light using a UV-YAG laser device, thereby forming through holes 201 in the resin substrate 21. Note that the etching process of the conductor layer 221 before the laser light irradiation may be omitted. Instead of the UV-YAG laser device, the through holes 201 may be formed in the resin substrate 21 using a carbon dioxide laser (CO2 laser), an excimer laser, or the like. Alternatively, the through holes 201 may be formed in the resin substrate 21 by drilling, chemical etching, or the like. Note that the through holes 201 may be subjected to a desmear process.

[0105] Next, panel plating is performed on the double-sided CCL to grow copper plating in the through holes 201, thereby forming vias 24 in the through holes 201 (FIG. 6C).

[0106] Next, an etching resist is formed on the conductor layers 221, 231 by photolithography or the like, and then etching is performed to pattern the wiring layers 22, 23 (FIG. 6D). For this etching, an etchant containing ferric chloride, cupric chloride, or the like as a main component can be used. Note that the wiring layers 22, 23 may be formed on the resin substrate 21 by a semi-additive method without using double-sided CCL.

[0107] Next, a UV-YAG laser device is used to irradiate the resin substrate 21 with laser light, thereby forming a first opening 25a (or a third opening 25c) in the resin substrate 21 (FIG. 6(e)). The first opening 25a may also be formed by punching using a mold. In this manner, the first and third double-sided substrates 20a and 20c are formed.

[0108] In the manufacturing method shown in Figure 6, the first and third double-sided substrates 20a and 20c are produced. However, when producing the second double-sided substrate 20b, the second opening 25b can be formed in the drilling process shown in Figure 6(e).

[0109] Next, a description will be given of a method for manufacturing the intermediate substrate 30. Figures 7(a) to 7(e) are cross-sectional views illustrating each step of the method for manufacturing the intermediate substrate 30 according to the first embodiment of the present invention.

[0110] First, a resin base material 31 is prepared (FIG. 7A). As the resin base material 31, for example, a resin base material with a thickness of about 12 μm can be prepared.

[0111] Next, adhesive 32B and resin film 35 are sequentially stacked and bonded to the upper surface of resin substrate 31 by thermocompression bonding, and adhesive 33B and resin film 36 are sequentially stacked and bonded to the lower surface of resin substrate 31 by thermocompression bonding ( FIG. 7( b) ). The adhesive 32B and resin film 36 can be formed using the materials exemplified for adhesive 13B and resin film 16 shown in FIG. 5( c). The adhesive 32B and resin film 36 can be formed using the methods exemplified for forming adhesive 13B and resin film 16.

[0112] Next, a through hole 301 is formed through the resin films 35 and 36, the adhesives 32B and 33B, and the resin base material 31 (FIG. 7C). The through hole 301 can be formed by the method exemplified for forming the through holes 101 and 102 and the resin film 16 shown in FIG. 5D.

[0113] Next, the through-hole 301 is filled with the conductive paste 34B (FIG. 7D). Specific methods for filling the through-holes 301 and 102 with the conductive paste 34B include, for example, a printing method such as screen printing, a spin coating method, a spray coating method, a dispensing method, and a lamination method.

[0114] Next, the resin films 35, 36 are peeled off from the adhesives 32B, 33B (FIG. 7(e)). As a result, the tip portions of the conductive paste 34B protrude from the surfaces of the adhesives 32B, 33B by an amount corresponding to the thickness of the resin films 35, 36. Note that the above-described thermocompression bonding causes the conductive paste 34B to thermally harden, forming the vias 34. Similarly, the thermocompression bonding causes the adhesives 32B, 33B to thermally harden, forming the adhesive layers 32, 33. In this manner, the first and second intermediate substrates 30 can be fabricated.

[0115] The three double-sided boards 10 manufactured as described above, the three double-sided boards 20a to 20c, and the two intermediate boards 30 are stacked together.

[0116] Specifically, first, terminals 41 of first to third electronic components 40a to 40c, which have been manufactured separately, are mounted on conductive paste 15B of each single-sided substrate 10 before lamination. Electronic components 40a to 40c can be temporarily bonded and mounted by, for example, aligning them using an electronic component mounting machine and heating them at a temperature equal to or lower than the hardening temperature of adhesive 13B and conductive pastes 14B and 15B of each single-sided substrate 10.

[0117] Next, the single-sided board 10 with the third electronic component 40c mounted thereon, the third double-sided board 20c, the intermediate board 30, the single-sided board 10 with the second electronic component 40b mounted thereon, the second double-sided board 20b, the intermediate board 30, the first double-sided board 20a, and the single-sided board 10 with the first electronic component 40a mounted thereon are stacked in this order. The third electronic component 40c is housed in the third opening 25c of the third double-sided board 20c, the second electronic component 40b is housed in the second opening 25b of the second double-sided board 20b, and the first electronic component 40a is housed in the first opening 25a of the first double-sided board 20a.

[0118] Finally, the components are laminated together by thermocompression bonding using a vacuum press under reduced pressure of 1 kPa or less, thereby completing the component-embedded substrate 1A shown in Fig. 1. At this time, the adhesive layer fills the gaps 252a to 252c.

[0119] Second Embodiment

[0120] 8 is a cross-sectional view of a component-embedded substrate 1B according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in that the orientation of the first electronic component 40a is the same as the orientation of the second and third electronic components 40b, 40c. Therefore, the component-embedded substrate 1B according to the second embodiment further includes a fourth single-sided substrate 10d as a unit substrate. Apart from the above two points, the configuration of the second embodiment is the same as that of the first embodiment. Below, only the differences between the component-embedded substrate 1B according to the second embodiment and the first embodiment will be described, and parts having the same configuration as the first embodiment will be designated by the same reference numerals and will not be described again.

[0121] 8, in the second embodiment, the surface on which the terminals 41 of the first electronic component 40a built into the component-embedded substrate 1B are formed is located on the lower side, and the back surface is located on the upper side. Therefore, the unit substrate further includes a fourth single-sided substrate 10d that faces the terminals 41. In this case, the fourth single-sided substrate 10d corresponds to an example of the "first single-sided substrate" in this aspect of the present invention.

[0122] Similar to the first single-sided substrate 10a in the first embodiment, the fourth single-sided substrate 10d includes a resin base material 11, a wiring layer 12, an adhesive layer 13, a plurality of vias 14, and a plurality of vias 15. The resin base material 11 of the fourth single-sided substrate 10d corresponds to an example of a "fourth insulating layer" in this aspect of the present invention, the wiring layer 12 corresponds to an example of a "first wiring layer" in this aspect of the present invention, and the adhesive layer 13 corresponds to an example of a "third adhesive layer" in this aspect of the present invention.

[0123] The wiring layer 12 of the fourth single-sided substrate 10d is formed on the other surface of the resin base material 11. In this embodiment, the wiring layer 12 of the fourth single-sided substrate 10d includes wiring 121a and wiring 121b, similar to the first single-sided substrate 10a in the first embodiment. Wiring 121a is electrically connected to the first electronic component 40a, while wiring 121b is electrically connected to the wiring layer 22 of the second double-sided substrate 20b. Note that wiring 121b corresponds to an example of the "first wiring" in this aspect of the present invention.

[0124] Furthermore, the first single-sided substrate 10a in the second embodiment does not have the first electronic component 40a mounted thereon, and therefore does not have the wiring 121a or the via 15.

[0125] In the component-embedded substrate 1B of the second embodiment, similarly to the above-described first embodiment, the first electronic component 40a is shifted in the −X direction relative to the second electronic component 40b, and therefore the electrical reliability of the component-embedded substrate 1B can be improved.

[0126] It should be noted that the above-described embodiments have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments are intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0127] For example, in the first and second embodiments, the second electronic component 40b is offset in the X direction relative to the first electronic component 40a, but as shown in the following first modified example, the second electronic component 40b may be offset in the Y direction relative to the first electronic component 40a. Fig. 9A is a plan view showing the positional relationship between the first electronic component 40a and the second electronic component 40b in the first modified example.

[0128] 9A, in this first modified example, the second electronic component 40b is shifted in the −Y direction with respect to the first electronic component 40a by a shift amount D3 that is equal to or greater than the width W (D3≧W).

[0129] Therefore, the first opposite sides 401a and 401b do not overlap any of the four sides of the second electronic component 40b. Similarly, the third opposite sides 403a and 403b do not overlap any of the four sides of the first electronic component 40a. Furthermore, the first opposite side 401a is adjacent to the third opposite side 403a with a gap therebetween, and the first opposite side 401b is adjacent to the third opposite side 403b with a gap therebetween. Meanwhile, a portion of the second opposite side 402a substantially overlaps with a portion of the fourth opposite side 404a, and a portion of the second opposite side 402b substantially overlaps with a portion of the fourth opposite side 404b.

[0130] In this case, the wirings 121c and 121d intersect with the first opposite side 401a and the third opposite side 403a, or with the first opposite side 401b and the third opposite side 403b, in a plan view, while the wirings 121c and 121d do not intersect with the second opposite sides 402a and 402b and the fourth opposite sides 404a and 404b, in a plan view.

[0131] Furthermore, in the above embodiment, the planar shape of the first electronic component 40a is the same as the planar shape of the second electronic component 40b, but the planar shapes of the two may be different, as in the second to sixth modified examples below.

[0132] 9(b) to 9(d) are plan views showing the positional relationship between the first electronic component 40a and the second electronic component 40b in the second to fourth modified examples. In these second to fourth modified examples, the length of a pair of opposite sides of the first electronic component 40a is different from the length of a pair of opposite sides of the second electronic component 40b.

[0133] Specifically, the length Y1 of the second opposite sides 402a, 402b and the length Y2 of the fourth opposite sides 404a, 404b are different, and the absolute value of the difference between them, |Y1-Y2|, is greater than W (|Y1-Y2|>W). On the other hand, the length X1 of the first opposite sides 401a, 401b and the length X2 of the third opposite sides 403a, 403b are substantially the same, and the absolute value of the difference between them, |X1-X2|, is smaller than W (|X1-X2|=0<W).

[0134] As shown in FIG. 9B , in the second modification, the first center of gravity G1 of the first electronic component 40a and the second center of gravity G2 of the second electronic component 40b coincide with each other. Furthermore, because the length Y2 of the fourth opposite sides 404a, 404b of the second electronic component 40b is shorter than the length Y1 of the first opposite sides 401a, 401b of the first electronic component 40a (Y2<Y1), the entire fourth opposite sides 404a, 404b substantially overlap with the first opposite sides 401a, 401b. Meanwhile, the first opposite sides 401a, 401b do not overlap with any of the four sides of the second electronic component 40b. Similarly, the third opposite sides 403a, 403b substantially overlap with the first electronic component 40a but do not overlap with any of the four sides of the first electronic component 40a. The first opposite side 401a is adjacent to the third opposite side 403a with a gap therebetween, and the first opposite side 401b is adjacent to the third opposite side 403b with a gap therebetween.

[0135] In the second modified example, the first opposite sides 401a and 401b are shifted in the Y direction with respect to the third opposite sides 403a and 403b. The amount of shift D4 at this time is equal to or greater than the width W (D4≧W).

[0136] In this case, the wirings 121c and 121d intersect with the first opposite side 401a and the third opposite side 403a, or with the first opposite side 401b and the third opposite side 403b, in a plan view, while the wirings 121c and 121d do not intersect with the second opposite sides 402a and 402b and the fourth opposite sides 404a and 404b, in a plan view.

[0137] 9C, in the third modified example, the second electronic component 40b is moved in the −Y direction relative to the first electronic component 40a, thereby shifting the center of gravity G2 in the −Y direction with respect to the center of gravity G1, and aligning the first opposite side 401b with the third opposite side 403b. In this case, the amount of deviation D5 between the first opposite side 401a and the third opposite side 403a can be made larger than the amount of deviation D4 (D5>D4≧W).

[0138] In this case, the wirings 121c and 121d intersect with the first opposite side 401a and the third opposite side 403a in plan view. However, unlike the first and second modifications, the wirings 121c and 121d do not intersect with the first opposite side 401b and the third opposite side 403b. Furthermore, the wirings 121c and 121d do not intersect with the second opposite sides 402a and 402b and the fourth opposite sides 404a and 404b in plan view.

[0139] As shown in FIG. 9D , in the fourth modification, the second electronic component 40b of the third modification is further moved in the −Y direction relative to the first electronic component 40a, thereby separating the first opposite side 401b and the third opposite side 403b. In this case, the misalignment amount D6 between the first opposite side 401a and the third opposite side 403a can be made larger than the misalignment amount D5 (D6 > D5 > D4 ≧ W). Furthermore, in this fourth modification, the first opposite side 401b is misaligned in the Y direction with respect to the third opposite side 403b. The misalignment amount D7 at this time is equal to or greater than the width W (D7 ≧ W).

[0140] In this case, the wirings 121c and 121d intersect with the first opposite side 401a and the third opposite side 403a, or with the first opposite side 401b and the third opposite side 403b, in a plan view, while the wirings 121c and 121d do not intersect with the second opposite sides 402a and 402b and the fourth opposite sides 404a and 404b, in a plan view.

[0141] 10(a) to 10(c) are plan views showing the positional relationship between the first electronic component 40a and the second electronic component 40b in the fifth to seventh modified examples. In the fifth and sixth modified examples, the lengths of the four sides of the first electronic component 40a are different from the lengths of the four sides of the second electronic component 40b.

[0142] Specifically, the length X1 of the first opposite sides 401a, 401b is different from the length X2 of the third opposite sides 403a, 403b, and the absolute value of the difference between them, |X1-X2|, is greater than W (|X1-X2|>W). Furthermore, the length Y1 of the second opposite sides 402a, 402b is different from the length Y2 of the fourth opposite sides 404a, 404b, and the absolute value of the difference between them, |Y1-Y2|, is greater than W (|Y1-Y2|>W).

[0143] As shown in FIG. 10( a), in this fifth modified example, the first opposite side 401 b and the third opposite side 403 b are substantially entirely overlapped, so that the center of gravity G2 of the second electronic component 40 b is shifted in the −Y direction with respect to the center of gravity G1 of the first electronic component 40 a.

[0144] Additionally, the third opposite side 403a is offset by D8 in the -Y direction with respect to the first opposite side 401a, the fourth opposite side 404a is offset by D9 in the +X direction with respect to the second opposite side 402a, and the fourth opposite side 404b is offset by D10 in the -X direction with respect to the second opposite side 402b. All of these offset amounts D8 to D10 are equal to or greater than the width W (D8≧W, D9≧W, D10≧W).

[0145] In this case, the wirings 121c and 121d intersect with the first opposite side 401a and the third opposite side 403a, or with the second opposite side 402a and the fourth opposite side 404a, or with the second opposite side 402b and the fourth opposite side 404b in a plan view. On the other hand, the wirings 121c and 121d do not intersect with the first opposite side 401b and the third opposite side 403b in a plan view.

[0146] As shown in FIG. 10B, in the sixth modified example, the second electronic component 40b of the fifth modified example is moved in the −X direction relative to the first electronic component 40a, so that the second opposite side 402a and the entire fourth opposite side 404a are aligned with each other.

[0147] The fourth opposite side 404b is offset by D11 in the −X direction with respect to the second opposite side 402b, and this offset amount D11 is equal to or greater than the width W (D11≧W).

[0148] In this case, the wirings 121c and 121d intersect with the first opposite side 401a and the third opposite side 403a, or with the second opposite side 402b and the fourth opposite side 404b, in plan view. On the other hand, the wirings 121c and 121d do not intersect with the first opposite side 401b, the second opposite side 402a, the third opposite side 403b, or the fourth opposite side 404a, in plan view.

[0149] In the sixth modification, second electronic component 40b may be further moved in the −X direction relative to first electronic component 40a, so that fourth opposite side 404a is further shifted in the −X direction relative to second opposite side 402a while first opposite side 401b and third opposite side 403b remain overlapped. In the sixth modification, second electronic component 40b is moved along the X direction, but it may be moved along the Y direction so that first opposite side 401a or first opposite side 401b overlaps the entire third opposite side 403a or third opposite side 403b.

[0150] As shown in FIG. 10C, the seventh modification differs from the sixth modification in that the wiring 121c, in addition to the wiring 121d, also intersects with the second opposite side 402b and the fourth opposite side 404b.

[0151] As shown in FIG. 10( c), the first and second electronic components 40 a, 40 b include combinations of adjacent sides spaced apart in a plan view, such as a combination of a first opposite side 401 a and a third opposite side 403 a, and a combination of a second opposite side 402 b and a fourth opposite side 404 b.

[0152] Furthermore, the amount of deviation D11 between the second opposite side 402b and the fourth opposite side 404b is larger than the amount of deviation D8 between the first opposite side 401a and the third opposite side 403a, and the amount of deviation D11 is the largest among the amounts of deviation between adjacent sides in this modified example. Note that the combination of the second opposite side 402b and the fourth opposite side 404b in this embodiment corresponds to an example of the "first combination" in the present invention.

[0153] The wirings 121c and 121d extend so as to intersect with the combination of the second opposite side 402b and the fourth opposite side 404b that has the largest amount of misalignment in plan view. The greater the amount of misalignment, the smaller the stress generated in the second wiring. Therefore, by having the wirings 121c and 121d intersect with the combination that has the largest amount of misalignment, as in this modification, it is possible to further reduce the stress generated in the wirings 121c and 121d.

[0154] In this modified example, an example is shown in which there are two combinations of adjacent sides spaced apart in a planar view, but if there are three such combinations, the wiring may be extended so as to intersect with the above-mentioned "first combination" in a planar view.

[0155] In the above embodiment, the third electronic component 40c is aligned with the first electronic component 40a in a plan view, but as in the following eighth and ninth modified examples, the third electronic component 40c may be offset from the first electronic component 40a in a plan view. Figures 11(a) and 11(b) are schematic cross-sectional views showing the positional relationships of the first to third electronic components 40a to 40c in the eighth and ninth modified examples of the present invention.

[0156] In an eighth modified example shown in Fig. 11(a), the third electronic component 40c is shifted in the +X direction with respect to the first electronic component 40a, while in a ninth modified example shown in Fig. 11(b), the third electronic component 40c is shifted in the -X direction with respect to the first electronic component 40a.

[0157] In the above embodiment, the component-embedded substrates 1A, 1B have three built-in electronic components 40a to 40c, but the component-embedded substrates 1A, 1B may have four or more built-in electronic components, as in the following tenth to twelfth modified examples. In the tenth to twelfth modified examples, the positional relationships of the first to fourth electronic components will be described using the example in which the component-embedded substrates 1A, 1B have four built-in electronic components 40a to 40d.

[0158] 12(a) to 12(d) are schematic cross-sectional views showing the positional relationships of the first to fourth electronic components 40a to 40c in the tenth to thirteenth modified examples.

[0159] 12A, in the tenth modification, the fourth electronic component 40d is arranged to coincide with the second electronic component 40b in a plan view. By aligning the first electronic component 40a with the third electronic component 40c and the second electronic component 40b with the fourth electronic component 40d as in the tenth modification, it is possible to prevent the component-embedded substrate from becoming too large in the planar direction.

[0160] 12B, in the eleventh modification, the second electronic component 40b of the tenth modification is moved along the +X direction. In this way, the amount of misalignment between the first electronic component 40a and the second electronic component 40b and the amount of misalignment between the second electronic component 40b and the third electronic component 40c may be increased preferentially.

[0161] 12C, in the twelfth modification, the second electronic component 40b of the tenth modification is moved along the +X direction, and the third electronic component 40c is also moved toward the +X direction. In this manner, the amount of misalignment between the first electronic component 40a and the second electronic component 40b and the amount of misalignment between the fourth electronic component 40d and the third electronic component 40c may be increased preferentially.

[0162] 12(d), in the thirteenth modification, the second electronic component 40b of the tenth modification is moved along the +X direction, and the third electronic component 40c is moved in the −X direction. In this way, the amount of misalignment between the second electronic component 40b and the third electronic component 40c may be preferentially increased.

[0163] In the above embodiment and modified example, the case where the deviation amount D is equal to or greater than the width W (D≧W) is exemplified, but the present invention is not limited to this. As described above, in this embodiment, "sides substantially overlap" means that the distance between the sides is equal to or greater than 0 and less than W / 2 in plan view, and therefore even if the deviation amount D in the above embodiment and modified example is set to be equal to or greater than W / 2 and less than W (W>D≧W / 2), the effect of reducing stress on the wiring can be obtained.

[0164] In the above embodiment, the first to third electronic components 40a to 40c have substantially the same thickness, but the first to third electronic components 40a to 40c may have different thicknesses. Even in this case, the thickness of the first electronic component 40a and the thickness of the first double-sided board 20a are made substantially equal, the thickness of the second electronic component 40b and the thickness of the second double-sided board 20b are made substantially equal, and the thickness of the third electronic component 40c and the thickness of the third double-sided board 20c are made substantially equal.

[0165] DESCRIPTION OF SYMBOLS 1A, 1B... Substrate with built-in components 10a to 10d... First to fourth single-sided substrates 11... Resin base material 12... Wiring layer 121a to 121d... Wiring 13... Adhesive layer 14... Via 15... Via 20a to 20c... First to third double-sided substrates 21... Resin base material 22, 23... Wiring layer 24... Via 25a to 25c... First to third openings 251... Inner wall 252a to 252c... Gap 30a, 30b... First and second intermediate substrates 31... Resin base material 32, 33... Adhesive layer 34... Via 40a to 40d... First to fourth electronic components 41... Terminal 401a, 401b... First opposite side 402a, 402b... Second opposite side 403a, 403b... Third opposite side 404a, 404b...fourth opposite side

Claims

1. A component-embedded substrate comprising a plurality of unit substrates stacked on top of one another, a first electronic component, and a second electronic component, wherein the plurality of unit substrates comprise: a first double-sided substrate including a first insulating layer having a first opening formed therein in which the first electronic component is disposed; a second double-sided substrate including a second insulating layer having a second opening formed therein in which the second electronic component is disposed; a first intermediate substrate including a third insulating layer provided between the first and second double-sided substrates, a first adhesive layer formed on one side of the third insulating layer, and a second adhesive layer formed on the other side of the third insulating layer; a first single-sided substrate including a fourth insulating layer, a third adhesive layer formed on the fourth insulating layer so as to adhere to the first double-sided substrate, and a first wiring layer including first wiring connected to the first electronic component; a second single-sided substrate including a fifth insulating layer, a fourth adhesive layer formed on the fifth insulating layer so as to adhere to the second double-sided substrate, and a second wiring layer including second wiring connected to the second electronic component, wherein the first electronic component and the second electronic component have a substantially rectangular planar shape, the first electronic component overlaps with the second electronic component in a planar view, the first electronic component includes: a first side that does not overlap with any of the four sides of the second electronic component in a planar view, and a second side different from the first side, the second electronic component includes: a third side that does not overlap with any of the four sides of the first electronic component in a planar view and is adjacent to the first side with a gap therebetween, and a fourth side that substantially overlaps with the second side in a planar view, 2. A component-embedded substrate according to claim 1, which satisfies the following formula (1): D≧W ... (1) where D is the distance between the first side and the third side in a plan view, and W is the distance between the first electronic component and the inner wall of the first opening.

3. A component-embedded substrate according to claim 2, wherein the first electronic component includes: a pair of first opposite sides extending generally parallel to each other along a first direction in a plan view; and a pair of second opposite sides connected to the first opposite sides in a plan view and extending generally parallel to each other along a second direction generally perpendicular to the first direction; and the second electronic component includes: a pair of third opposite sides generally parallel to the first opposite sides in a plan view; and a pair of fourth opposite sides connected to the third opposite sides in a plan view and generally parallel to the second opposite sides; and wherein a first center of gravity of the first electronic component and a second center of gravity of the second electronic component are misaligned in the first direction or the second direction when the following formulas (2) and (3) are satisfied: |X1-X2|<W ... (2) |Y1-Y2|<W ... (3) However, in the above formula (2), X1 is the length of the first opposite side in the first direction, X2 is the length of the third opposite side in the first direction, and in the above formula (3), Y1 is the length of the second opposite side in the second direction, and Y2 is the length of the fourth opposite side in the second direction.

4. A component-embedded substrate according to claim 2, wherein the first electronic component includes: a pair of first opposite sides extending generally parallel to each other along a first direction in a plan view; and a pair of second opposite sides connected to the first opposite sides in a plan view and extending generally parallel to each other along a second direction generally perpendicular to the first direction; and the second electronic component includes: a pair of third opposite sides generally parallel to the first opposite sides in a plan view; and a pair of fourth opposite sides connected to the third opposite sides in a plan view and generally parallel to the second opposite sides; and wherein, when the following formulas (4) and (5) are satisfied, a first center of gravity of the first electronic component and a second center of gravity of the second electronic component substantially coincide with each other, or the first center of gravity and the second center of gravity are deviated in the second direction: |X1-X2|<W ... (4) |Y1-Y2|>W ... (5) However, in the above formula (4), X1 is the length of the first opposite side in the first direction, X2 is the length of the third opposite side in the first direction, and in the above formula (5), Y1 is the length of the second opposite side in the second direction, and Y2 is the length of the fourth opposite side in the second direction.

5. A component-embedded substrate according to claim 2, wherein the first electronic component includes: a pair of first opposite sides extending generally parallel to each other along a first direction in a plan view; and a pair of second opposite sides connected to the first opposite sides in a plan view and extending generally parallel to each other along a second direction generally perpendicular to the first direction; and the second electronic component includes: a pair of third opposite sides generally parallel to the first opposite sides in a plan view; and a pair of fourth opposite sides connected to the third opposite sides in a plan view and generally parallel to the second opposite sides; and wherein a first center of gravity of the first electronic component and a second center of gravity of the second electronic component are misaligned in the first direction or the second direction when the following formulas (6) and (7) are satisfied: |X1-X2|>W ... (6) |Y1-Y2|>W ... (7) However, in the above formula (6), X1 is the length of the first opposite side in the first direction, X2 is the length of the third opposite side in the first direction, and in the above formula (7), Y1 is the length of the second opposite side in the second direction, and Y2 is the length of the fourth opposite side in the second direction.

6. A component-embedded substrate according to any one of claims 1 to 5, wherein the first wiring layer is formed on one side of the fourth insulating layer, the third adhesive layer is formed on the other side of the fourth insulating layer, the second wiring layer is formed on the other side of the fifth insulating layer, the fourth adhesive layer is formed on one side of the fifth insulating layer, the first adhesive layer of the first intermediate substrate is adhered to the other side of the first double-sided substrate, the second adhesive layer of the first intermediate substrate is adhered to one side of the second double-sided substrate, the third adhesive layer of the first single-sided substrate is adhered to one side of the first double-sided substrate, and the fourth adhesive layer of the second single-sided substrate is adhered to the other side of the second double-sided substrate.

7. A component-embedded substrate according to any one of claims 1 to 5, wherein the plurality of unit substrates further comprise a third single-sided substrate including a sixth insulating layer and a fifth adhesive layer formed on the sixth insulating layer so as to adhere to the first double-sided substrate from the side opposite to the third adhesive layer, wherein the first wiring layer is formed on the other side of the fourth insulating layer, the third adhesive layer is formed on one side of the fourth insulating layer, the second wiring layer is formed on the other side of the fifth insulating layer, the fourth adhesive layer is formed on one side of the fifth insulating layer, the first adhesive layer of the first intermediate substrate is adhered to the other side of the first single-sided substrate, the third adhesive layer of the first single-sided substrate is adhered to the other side of the first double-sided substrate, the fifth adhesive layer of the third single-sided substrate is adhered to one side of the first double-sided substrate, and the second adhesive layer of the first intermediate substrate is adhered to one side of the second double-sided substrate. The fourth adhesive layer of the second single-sided substrate is adhered to the other surface of the second double-sided substrate.

8. A component-embedded substrate according to any one of claims 1 to 7, wherein the component-embedded substrate further comprises a third electronic component having a substantially rectangular planar shape and overlapping the first and second electronic components in a plan view, and the plurality of unit substrates further comprise: a third double-sided substrate including a seventh insulating layer having a third opening formed therein in which the third electronic component is to be disposed; and a second intermediate substrate including an eighth insulating layer provided between the second and third double-sided substrates, a sixth adhesive layer formed on one side of the eighth insulating layer, and a seventh adhesive layer formed on the other side of the eighth insulating layer, and the third electronic component substantially coincides with the first electronic component in a plan view.

9. A component-embedded substrate according to claim 6, wherein the thicknesses of the third to fifth insulating layers are equal to or less than half the thicknesses of the first to fourth adhesive layers.

10. A component-embedded substrate according to claim 7, wherein the thicknesses of the third to sixth insulating layers are equal to or less than half the thicknesses of the second to fifth adhesive layers.

11. A component-embedded substrate according to any one of claims 1 to 10, wherein the first and second electronic components include a plurality of combinations of the first side and the third side, the combinations include a first combination in which the distance D between the first side and the third side is the longest, and the second wiring extends so as to intersect with the first combination in a planar view.

Images