Semiconductor device and method for producing same

Abstract

The present invention comprises a semiconductor substrate (12) having a first impurity layer (40) of a first conductivity type, an upper layer portion (120) that is disposed on the first impurity layer (40) and includes second impurity layers (38, 37) of the first conductivity type, a body layer (34) of a second conductivity type formed on the surface layer part of the upper layer portion (120), and a third impurity layer (30) of a first conductivity type formed on the surface layer part of the body layer (34), the semiconductor substrate (12) being configured from a compound semiconductor, and the surface of the semiconductor substrate (12) on the opposite side from the first impurity layer (40) side being defined as one surface (12a). Ion implantation defects (50) are formed in the second impurity layers (37, 38) of the semiconductor substrate (12). The ion implantation defects (50) are such that, with reference to the one surface (12a) of the semiconductor substrate (12), defect positions are at 2 μm to 6 μm from the one surface (12a), and the defect density is 2.0 × 1016 / cm3 to 5.0 × 1016 / cm3.

Description

Semiconductor device and manufacturing method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-033124, filed on March 5, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] For example, Patent Document 1 proposes a method for efficiently capturing minority carriers by forming a diode on a semiconductor substrate made of silicon and performing ion implantation to form ion implantation defects. Specifically, in this semiconductor device, a diode is formed using an n-type layer and a p-type layer, and ion implantation defects are formed in the p-type layer.

[0004] JP 2013-77615 A

[0005] The present inventors have been studying the construction of a semiconductor device using a semiconductor substrate made of a compound semiconductor substrate. The compound semiconductor substrate is, for example, a substrate made of silicon carbide, gallium nitride, gallium oxide, or the like. Such a compound semiconductor substrate may suffer from crystal misalignment when energized, resulting in degradation of its characteristics. In other words, such a compound semiconductor substrate may be subject to degradation due to electrical conduction. For example, a semiconductor substrate made of silicon carbide may have basal plane dislocations. When holes recombine with electrons near the basal plane dislocations, the basal plane dislocations may expand into stacking faults due to the large recombination energy. When basal plane dislocations expand into stacking faults, the stacking faults occupy a larger area than the basal plane dislocations, resulting in degradation of the characteristics of the semiconductor substrate made of silicon carbide.

[0006] For this reason, the present inventors have been studying the suppression of electrical degradation in semiconductor devices using semiconductor substrates made of such compound semiconductor substrates by forming ion implantation defects. However, forming ion implantation defects in a compound semiconductor substrate is based on a different approach from forming ion implantation defects in a semiconductor substrate made of silicon as described above, and therefore it is difficult to directly apply the structure for forming ion implantation defects to a semiconductor substrate made of silicon.

[0007] An object of the present disclosure is to provide a semiconductor device using a compound semiconductor substrate that can suppress electrical degradation, and a method for manufacturing the same.

[0008] According to one aspect of the present disclosure, a semiconductor device includes: a first impurity layer of a first conductivity type or a second conductivity type; an upper layer portion disposed on the first impurity layer and including a second impurity layer of the first conductivity type; a body layer of the second conductivity type formed in a surface layer portion of the upper layer portion; and a third impurity layer of the first conductivity type formed in a surface layer portion of the body layer; a semiconductor substrate made of a compound semiconductor, the semiconductor substrate having a surface opposite to the first impurity layer; a gate insulating film disposed between the third impurity layer and the second impurity layer and in contact with the body layer; and a gate electrode disposed on the gate insulating film; and ion implantation defects are formed in the second impurity layer of the semiconductor substrate, and the ion implantation defects are located at a distance of 2 μm to 6 μm from the surface of the semiconductor substrate as a reference, and the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ It is stated as follows.

[0009] According to another aspect of the present disclosure, there is provided a semiconductor device comprising: a first impurity layer of a first conductivity type or a second conductivity type; an upper layer portion disposed on the first impurity layer and including a second impurity layer of the first conductivity type; a body layer of the second conductivity type formed in a surface layer portion of the upper layer portion; and a third impurity layer of the first conductivity type formed in the surface layer portion of the body layer; a semiconductor substrate made of a compound semiconductor, the semiconductor substrate having one surface opposite to the first impurity layer side; a gate insulating film disposed between the third impurity layer and the second impurity layer and in contact with the body layer; and a gate electrode disposed on the gate insulating film; and ion implantation defects formed in the second impurity layer of the semiconductor substrate, the ratio of the defect positions from the one surface of the semiconductor substrate of the ion implantation defects to the thickness of the upper layer portion being equal to or greater than 0.2 and equal to or less than 0.6, and the defect density being 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ It is stated as follows.

[0010] According to these, since the defect positions and defect density of ion implantation defects are specified as described above, deterioration due to current flow can be suppressed without increasing the on-resistance or the forward voltage of the parasitic diode.

[0011] According to another aspect of the present disclosure, in the method for manufacturing a semiconductor device, ion implantation defects can be formed by performing ion implantation.

[0012] 1 is a perspective cross-sectional view of a semiconductor device according to a first embodiment; FIG. 2 is a perspective cross-sectional view of the semiconductor device shown in FIG. 1 , omitting a source electrode and an interlayer insulating film; FIG. 3 is a cross-sectional view along the surface direction of a semiconductor substrate, showing a portion including a p-type trench lower layer, a p-type deep layer, and an n-type deep layer, and showing the positional relationship between the p-type trench lower layer, the p-type deep layer, and the n-type deep layer; FIG. 4 is a cross-sectional view along the surface direction of a semiconductor substrate, showing a portion including a trench, a p-type deep layer, and an n-type deep layer, and showing the positional relationship between the trench, the p-type deep layer, and the n-type deep layer; FIG. 5 is a cross-sectional view along the depth direction of a semiconductor substrate, showing a portion including a p-type deep layer and an n-type deep layer, and showing the positional relationship between the p-type deep layer and the n-type deep layer; FIG. 6 is a perspective cross-sectional view of a portion of a semiconductor device different from FIG. 1; FIG. 7 is a diagram showing the relationship between defect positions, defect density, and hole density at 200° C.; FIG. 8 is a diagram showing the relationship between defect positions, defect density, and hole density at 500° C.; and FIG. 9 is a diagram showing the relationship between defect positions, defect density, and hole density at 25° C. 1 is a diagram showing the relationship between defect position and defect density and hole density at 200° C. 2 is a diagram showing the relationship between defect position and defect density and on-resistance at 200° C. 3 is a diagram showing the relationship between defect position and defect density and DS leakage current at 200° C. 4 is a diagram showing the relationship between defect position and defect density and forward voltage at 200° C.

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0014] First Embodiment A semiconductor device 10 according to a first embodiment will be described with reference to the drawings. In this embodiment, a semiconductor device 10 including a MOSFET will be described. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0015] As shown in FIGS. 1 and 2 , the semiconductor device 10 includes a semiconductor substrate 12 having a first surface 12 a and a second surface 12 b. In the following description, the depth (i.e., thickness) direction of the semiconductor substrate 12 is referred to as the z-axis direction, a direction parallel to the first surface 12 a of the semiconductor substrate 12 (i.e., a direction perpendicular to the z-axis direction) is referred to as the x-axis direction, and a direction perpendicular to the x-axis and z-axis directions is referred to as the y-axis direction. In the following description, the first surface 12 a of the semiconductor substrate 12 is used as the reference, and the length in the z-axis direction from the first surface 12 a to the second surface 12 b is simply referred to as the position. In the following description, the portion of each part located on the first surface 12 a of the semiconductor substrate 12 is referred to as the upper surface or upper portion, and the portion located on the second surface 12 b of the semiconductor substrate 12 is referred to as the lower surface or lower portion. In the following description, the second surface 12 b of the semiconductor substrate 12 is also referred to as the lower side or lower side.

[0016] The semiconductor substrate 12 is made of a compound semiconductor, and in this embodiment is made of silicon carbide, but may be made of other compound semiconductors such as gallium nitride or gallium oxide.

[0017] A plurality of trenches 14 are formed in the semiconductor substrate 12 from the one surface 12a side. As shown in Fig. 2, the plurality of trenches 14 are formed with their longitudinal direction in the y-axis direction and are arranged at intervals in the x-axis direction.

[0018] 1 and 2, the wall surfaces (i.e., the side surfaces and bottom surfaces) of each trench 14 are covered with a gate insulating film 16. A gate electrode 18 is disposed on the gate insulating film 16 in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. Furthermore, as shown in FIG. 1, the top surface of each gate electrode 18 is covered with an interlayer insulating film 20.

[0019] A source electrode 22 serving as a first electrode is provided on the one surface 12a of the semiconductor substrate 12. The source electrode 22 is disposed so as to cover each interlayer insulating film 20, and is insulated from the gate electrode 18 by the interlayer insulating films 20. The source electrode 22 contacts the one surface 12a of the semiconductor substrate 12 in positions where the interlayer insulating films 20 are not present. A drain electrode 24 serving as a second electrode is disposed on the other surface 12b of the semiconductor substrate 12. The drain electrode 24 is disposed so as to contact the entire other surface 12b of the semiconductor substrate 12.

[0020] 1 and 2 , the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench lower layers 35, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, a drift layer 38, and a drain layer 40. In this embodiment, the drain layer 40 corresponds to a first impurity layer, the n-type deep layer 37 and the drift layer 38 correspond to a second impurity layer, and the source layer 30 corresponds to a third impurity layer.

[0021] Each source layer 30 has a high n-type impurity concentration. ＋ Each source layer 30 is a type layer. Each source layer 30 is disposed in an area that partially includes one surface 12a of the semiconductor substrate 12 and is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the trench 14 and faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends longitudinally in the y-axis direction along the side surface of the trench 14. That is, when the semiconductor substrate 12 is viewed from the one surface 12a side, each source layer 30 extends parallel to the longitudinal direction of the trench 14, extending from one end to the other end in the longitudinal direction of the trench 14. Note that the view from the one surface 12a side can also be referred to as the view from the z-axis direction or in the z-axis direction.

[0022] Each contact layer 32 has a high p-type impurity concentration. ＋The contact layers 32 are mold layers. Each contact layer 32 is disposed in an area that partially includes one surface 12a of the semiconductor substrate 12. More specifically, each contact layer 32 is disposed between two corresponding source layers 30. In other words, each contact layer 32 is disposed on the opposite side of the source layer 30 from the trench 14. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends elongately in the y-axis direction. That is, when the semiconductor substrate 12 is viewed from the one surface 12a side, each contact layer 32 extends parallel to the longitudinal direction of the trench 14, extending from one end to the other end in the longitudinal direction of the trench 14.

[0023] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is disposed below the source layers 30 and the contact layers 32, and is in contact with the source layers 30 and the contact layers 32 from below. In other words, the source layers 30 and the contact layers 32 are formed in a surface layer portion of the body layer 34. The body layer 34 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the source layers 30, and faces the gate electrode 18 via the gate insulating film 16.

[0024] Each p-type trench lower layer 35 is a p-type layer disposed below the corresponding trench 14. In other words, each p-type trench lower layer 35 is a p-type layer disposed so as to face the bottom surface of the corresponding trench 14. In this embodiment, each p-type trench lower layer 35 is disposed so as to contact the gate insulating film 16 covering the bottom surface of the corresponding trench 14. However, each p-type trench lower layer 35 may be formed slightly away from the bottom surface of the corresponding trench 14.

[0025] 3 , when the semiconductor substrate 12 is viewed from the one surface 12a side, each p-type trench lower layer 35 extends long along the longitudinal direction of the corresponding trench 14 (i.e., the y-axis direction in this embodiment), and extends continuously from one end to the other end in the longitudinal direction of the trench 14. Note that in this embodiment, an example will be described in which each p-type trench lower layer 35 extends continuously from one end to the other end in the longitudinal direction of the trench 14, but each p-type trench lower layer 35 may be arranged so as to have a divided portion between one end and the other end in the longitudinal direction of the trench 14.

[0026] As shown in FIGS. 1 and 2 , each p-type deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34. The p-type impurity concentration of each p-type deep layer 36 is higher than that of the body layer 34 and lower than that of the contact layer 32. When viewed from the first surface 12a of the semiconductor substrate 12 as shown in FIG. 4 , each p-type deep layer 36 extends elongatedly in the x-axis direction and is formed so as to be perpendicular to the longitudinal direction of the trench 14 (i.e., the y-axis direction in this embodiment). In other words, each p-type deep layer 36 is formed so as to extend in a direction intersecting the longitudinal direction of the trench 14. The multiple p-type deep layers 36 are spaced apart from one another in the y-axis direction. Hereinafter, the portions between the multiple p-type deep layers 36 are also referred to as spacing portions 39. As shown in FIG. 5 , the p-type deep layers 36 have a shape that is elongated in the z-axis direction in the y-z cross section. That is, the length of the p-type deep layer 36 in the z-axis direction (hereinafter referred to as depth Dp) is longer than the length of the p-type deep layer 36 in the y-axis direction (hereinafter referred to as width Wp). For example, the depth Dp of each p-type deep layer 36 is set to be 1 to 4 times the width Wp. As shown in FIGS. 1 and 6 , each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14. Each p-type deep layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. As shown in FIG. 3 , each p-type deep layer 36 is formed so as to intersect with the p-type trench lower layer 35 located below the trench 14 and be connected to the p-type trench lower layer 35. Therefore, the p-type trench lower layer 35 is connected to the body layer 34 via the p-type deep layer 36. In this embodiment, the position of the lower surface of the p-type deep layer 36 is set to be substantially the same as the position of the lower surface of the p-type trench lower layer 35. The lower surface of the p-type deep layer 36 refers to the surface of the p-type deep layer 36 facing the drain layer 40, and the lower surface of the p-type trench lower layer 35 refers to the surface of the p-type trench lower layer 35 facing the drain layer 40. In this embodiment, the distance from the one surface 12a to the lower surfaces of the p-type trench lower layer 35 and the p-type deep layer 36 (i.e., the depth) is set to be approximately 1.7 μm.

[0027] Each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38. Alternatively, each n-type deep layer 37 may have the same n-type impurity concentration as the drift layer 38. The n-type impurity concentration of each n-type deep layer 37 is lower than the p-type impurity concentration of each p-type deep layer 36. As shown in FIGS. 1 and 2 , each n-type deep layer 37 is disposed within a corresponding gap 39. Each n-type deep layer 37 contacts the lower surface of the body layer 34. Each n-type deep layer 37 contacts the side surfaces of the p-type deep layers 36 on both sides. Each n-type deep layer 37 extends from the lower surface of the body layer 34 to below the bottom surface of each trench 14, the lower surfaces of each p-type trench lower layer 35, and each p-type deep layer 36. As shown in FIG. 5 , the n-type deep layer 37 within the gap 39 has a shape elongated in the z-axis direction in the y-z cross section. That is, the length of the n-type deep layer 37 in the z-axis direction (hereinafter referred to as depth Dn) is longer than the length of the n-type deep layer 37 in the gap 39 in the y-axis direction (hereinafter referred to as width Wn). For example, the depth Dn of the n-type deep layer 37 is 1 to 4 times the width Wn. In this embodiment, the width Wn of the n-type deep layer 37 is approximately equal to the width Wp of the p-type deep layer 36. Each n-type deep layer 37 has a connection region 37a that extends to just below the lower surface of the adjacent p-type deep layer 36. Each connection region 37a contacts the lower surface of the corresponding p-type deep layer 36. The n-type deep layers 37 are connected to each other via the connection region 37a. The thickness T1 of the portion of the n-type deep layer 37 that protrudes below the lower surface of the p-type deep layer 36 is thin, for example, about 0.1 μm. The thickness T1 can also be considered as the length in the z-axis direction from the lower surface of the p-type deep layer 36 to the lower surface of the n-type deep layer 37. As shown in Figures 1 and 2, each n-type deep layer 37 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34 within each gap 39. As shown in Figure 3, each n-type deep layer 37 contacts the p-type trench lower layer 35 located below the trench 14 so as to intersect with it.

[0028] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than each of the n-type deep layers 37. The drift layer 38 is disposed below the n-type deep layers 37. The drift layer 38 contacts the n-type deep layers 37 from below.

[0029] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the other surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0030] 1 and 2 , in the present embodiment, the portions of the semiconductor substrate 12 located above the drain layer 40 are collectively referred to as the upper layer portion 120. That is, in the semiconductor substrate 12, the portion between the lower surface of the drift layer 38 (i.e., the interface between the drain layer 40 and the drift layer 38) and the surface 12a of the semiconductor substrate 12 is also referred to as the upper layer portion 120. In the present embodiment, the thickness of the upper layer portion 120 is set to 10 μm.

[0031] In the semiconductor device 10, ion implantation defects 50 are formed by ion implantation in the upper layer portion 120, which is an n-type layer located below the body layer 34. The ion implantation defects 50 are formed by ion implantation of an inert gas such as argon or helium, or hydrogen or the like that is commonly used as a lifetime killer. The defect density and defect positions of the ion implantation defects 50 will be described later.

[0032] The above is the configuration of the semiconductor device 10 in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. Next, the operation of the semiconductor device 10 will be described, along with the defect density and defect positions of the ion implantation defects 50.

[0033] The semiconductor device 10 described above is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential equal to or greater than the gate threshold is applied to each gate electrode 18 of the semiconductor device 10, a channel is formed in the body layer 34 near the gate insulating film 16, and the channel connects the source layer 30 and the n-type deep layer 37. As a result, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38, thereby turning the semiconductor device 10 into an ON state. When the potential of the gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears, the flow of electrons stops, and the semiconductor device 10 turns into an OFF state.

[0034] Here, the semiconductor device 10 of this embodiment includes a parasitic diode including an n-type drift layer 38, an n-type deep layer 37, a p-type trench lower layer 35, a p-type deep layer 36, a p-type body layer 34, and the like. When the semiconductor device 10 transitions from an on state to an off state, a reverse bias is applied to the parasitic diode, and holes that diffuse from the p-type layer side to the n-type layer side of the pn junction constituting the parasitic diode recombine with electrons in the n-type layer, generating a large recombination energy. Therefore, for example, if the semiconductor substrate 12 is made of silicon carbide as in this embodiment and basal plane dislocations are present in the semiconductor substrate 12, the basal plane dislocations may expand into stacking faults, potentially degrading characteristics such as on-resistance. In other words, electrical degradation may occur.

[0035] Therefore, in this embodiment, as described above, the ion implantation defects 50 are formed in the upper layer portion 120, in the portion of the n-type layer located below the body layer 34. The inventors then conducted extensive research into the relationship between the defect position (i.e., depth) of the ion implantation defects 50 and the defect density and hole density, and obtained the results shown in FIGS. 7 to 10 . Note that in FIGS. 7 to 10 , the depth from the surface 12 a of the semiconductor substrate 12 to the lower surface of the body layer 34 is 1 μm. That is, a defect position of 1 μm in FIGS. 7 to 10 means that the ion implantation defects 50 are formed at the interface between the n-type deep layer 37 and the body layer 34. Also, FIG. 10 is a representational diagram modified from FIG. 7 .

[0036] 7 to 10, it is confirmed that the hole density decreases as the defect density increases. Furthermore, as shown in FIGS. 7, 8, and 10, the hole density decreases when the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ It is confirmed that the hole density decreases significantly in the following range: As shown in FIG. 9, it is confirmed that the hole density decreases as the defect density increases, even at room temperature (i.e., 25° C.).

[0037] As shown in FIGS. 7, 8, and 10, the hole density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ When the defect density is 2.0×10 or less, it is confirmed that the hole density decreases sharply as the depth increases in the range of the defect position less than 2 μm. １６ / cm ３ Above 5.0 x 10 １６ / cm ３ When the defect position is 2 μm or more, it is confirmed that the hole density gradually decreases as the defect position becomes deeper. However, when the defect position is 6 μm or more, it is confirmed that the hole density hardly changes even when the defect position is made deeper.

[0038] Therefore, the ion implantation defects 50 have a defect density of 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３The ion implantation defects 50 have defect positions that are 2 μm or more and 6 μm or less. In other words, since the thickness of the upper layer portion 120 is 10 μm, the ratio of the defect positions of the ion implantation defects 50 to the thickness of the upper layer portion 120 is 0.2 or more and 0.6 or less. In this embodiment, by forming the ion implantation defects 50 in this manner, the hole density can be reduced and electrical degradation can be suppressed. Note that, in this embodiment, as described above, the depth from the one surface 12a to the p-type trench lower layer 35 and the p-type deep layer 36 is approximately 1.7 μm. Therefore, when defined by the depth, the defect positions of the ion implantation defects 50 can be said to be formed at positions deeper than the p-type trench lower layer 35 and the p-type deep layer 36.

[0039] The present inventors also investigated the effect of forming the ion implantation defects 50 on the on-resistance Ron, and obtained the results shown in FIG. 11. As shown in FIG. 11, when the defect density of the ion implantation defects 50 was set to 2.0×10 as described above, １６ / cm ３ Above 5.0 x 10 １６ / cm ３ It has been confirmed that the on-resistance Ron hardly changes when the following conditions are met. Therefore, the ion implantation defects 50 of this embodiment can reduce the hole density and suppress the occurrence of degradation in electrical conductivity without particularly changing the on-resistance Ron. In particular, when the ion implantation defects 50 are inert gas defects formed by ion implanting an inert gas, the inert gas defects as the ion implantation defects 50 are less likely to be charged, so that the effect of lifetime on electrons can be further reduced, and the on-resistance Ron can be further reduced.

[0040] In addition, FIG. 11 shows the defect density of 2.0×10 １６ / cm ３ However, in reality, the on-resistance Ron for other defect densities is also １６ / cm ３ Therefore, FIG. 11 shows the same result as the on-resistance Ron when the defect density is typically 2.0×10 １６ / cm ３Only the solid line for the case where

[0041] Furthermore, the inventors have investigated the DS leakage current between the drain and source due to the formation of ion implantation defects 50, and obtained the results shown in FIG. 12. As shown in FIG. 12, it is confirmed that the DS leakage current increases as the defect density increases. The DS leakage current increases when the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ In the following range, it has been confirmed that the DS leakage current increases as the defect position becomes deeper in the range of less than 2 μm, and decreases as the defect position becomes deeper in the range of 2 μm or more. It has also been confirmed that the DS leakage current decreases gradually when the defect position becomes 3 μm or more. Therefore, in consideration of the DS leakage current, it is preferable that the ion implantation defect 50 be located at a defect position of 3 μm or more.

[0042] Furthermore, the ion implantation defects 50 of this embodiment are formed using an ion implantation device. With current ion implantation devices, attempting to implant ions deeper than 5 μm can result in increased device size and complex control, potentially increasing costs. Therefore, taking into account the ion implantation device, it is more preferable that the ion implantation defects 50 be 5 μm or less. That is, taking into account the DS leakage current and the conditions of the ion implantation device, it is more preferable that the defect position of the ion implantation defects 50 be 3 μm or more and 5 μm or less. In other words, it is more preferable that the ratio of the defect position of the ion implantation defects 50 to the thickness of the upper layer portion 120 be 0.3 or more and 0.5 or less.

[0043] The inventors also studied the ion implantation defects 50 and the forward voltage Vf when the parasitic diode operates as a diode, and obtained the results shown in FIG.

[0044] As shown in FIG. 13 , it is confirmed that the forward voltage Vf increases as the defect density of the ion implantation defects 50 increases. However, the variation in the forward voltage Vf shown in FIG. 13 is approximately 0.3 V, which is within the range that can be caused by variations in impurity concentration in a normal manufacturing process. Therefore, it can be said that the influence of the forward voltage Vf is not so great for the ion implantation defects 50 of this embodiment. In other words, according to the semiconductor device 10 of this embodiment, it is possible to reduce the hole density and suppress the occurrence of electrical degradation without changing the forward voltage Vf much.

[0045] When the semiconductor device 10 is in an off state, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and each n-type deep layer 37. Therefore, a depletion layer spreads from the body layer 34 to each n-type deep layer 37. Furthermore, each p-type deep layer 36 is electrically connected to the body layer 34 and has substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and each n-type deep layer 37. Therefore, a depletion layer also spreads from each p-type deep layer 36 to each n-type deep layer 37. Furthermore, each p-type trench lower layer 35 is electrically connected to the body layer 34 via each p-type deep layer 36 and has substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type trench lower layer 35 and each n-type deep layer 37. In this way, each n-type deep layer 37 is quickly depleted by the depletion layer spreading from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36. In particular, because each p-type trench lower layer 35 is provided below the corresponding trench 14, the periphery of the bottom surface of the trench 14 is depleted well. This significantly alleviates electric field concentration near the bottom surface of the trench 14. Furthermore, each n-type deep layer 37 is entirely depleted by the depletion layer spreading from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36. Note that because each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38, the depletion layer is less likely to spread within each n-type deep layer 37 than within the drift layer 38. However, because each n-type deep layer 37 is sandwiched between the p-type deep layers 36 and the width Wn of each n-type deep layer 37 is narrow, each n-type deep layer 37 is entirely depleted. The depletion layer also spreads to the drift layer 38 via each n-type deep layer 37. Because the n-type impurity concentration of the drift layer 38 is low, almost the entire drift layer 38 is depleted. The depleted drift layer 38 and each n-type deep layer 37 support a high voltage applied between the drain electrode 24 and the source electrode 22. Therefore, the semiconductor device 10 has a high breakdown voltage.

[0046] Furthermore, in the semiconductor device 10, the p-type trench lower layer 35 is electrically connected to the body layer 34 via the p-type deep layer 36. This stabilizes the potential of the p-type trench lower layer 35, thereby preventing deterioration of the switching characteristics of the semiconductor device 10. In this way, in the semiconductor device 10, the combination of the p-type trench lower layer 35 and the p-type deep layer 36 can improve the breakdown voltage while preventing deterioration of the switching characteristics.

[0047] Furthermore, in the semiconductor device 10 of this embodiment, the p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the trench 14. This reduces the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 18 and the drain electrode 24. Furthermore, in the semiconductor device 10, each n-type deep layer 37 and each p-type deep layer 36 has a shape that is elongated vertically (i.e., in the z-axis direction). When each n-type deep layer 37 and each p-type deep layer 36 are configured in this manner, the feedback capacitance is reduced. These features enable the switching speed of the semiconductor device 10 to be improved.

[0048] Next, a method for manufacturing the ion implantation defects 50 in the semiconductor device 10 will be described.

[0049] When manufacturing the semiconductor device 10, first, a semiconductor substrate 12 is prepared, in which an upper layer portion 120 composed of an epitaxial layer is disposed on the drain layer 40. Then, using ion implantation technology, a p-type trench lower layer 35, a p-type deep layer 36, an n-type deep layer 37, a body layer 34, a source layer 30, a contact layer 32, etc. are formed, and predetermined dry etching technology, deposition technology, etc. are used to form a trench 14, a gate insulating film 16, a gate electrode 18, etc. Furthermore, using ion implantation technology, ion implantation defects 50 are formed. At this time, the ion implantation defects 50 have a defect density of 2.0×10 as described above. １６ / cm ３ Above 5.0 x 10 １６ / cm ３ The ion implantation defects 50 are formed so that the defect density is 2.0×10 or less, and the defect position is 2 μm or more and 6 μm or less. １６ / cm ３ Above 5.0 x 10１６ / cm ３ The ion implantation defects 50 are formed so that the ratio of the defect positions of the ion implantation defects 50 to the thickness of the upper layer portion 120 is 0.2 or more and 0.6 or less. The ion implantation defects 50 are formed by ion implanting an inert gas such as argon or helium, or hydrogen or the like commonly used as a lifetime killer. In this case, the ion implantation defects 50 are formed as inert gas defects formed with an inert gas such as argon, thereby reducing the impact on electron lifetime. When the ion implantation defects 50 are formed by ion implanting hydrogen or the like commonly used as a lifetime killer, they are formed using a conventional ion implantation apparatus. The semiconductor device 10 is then manufactured by forming the interlayer insulating film 20, the source electrode 22, the drain electrode 24, etc.

[0050] According to the present embodiment described above, the ion implantation defects 50 have a defect position of 2 μm or more and 6 μm or less, and a defect density of 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ The ion implantation defects 50 have a ratio of the defect positions of the ion implantation defects 50 to the thickness of the upper layer portion 120 of 0.2 or more and 0.6 or less, and the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ Therefore, deterioration due to current flow can be suppressed without increasing the on-resistance Ron or the forward voltage Vf of the parasitic diode.

[0051] (1) By forming the above-described ion implantation defects 50 in the semiconductor device 10 having a trench gate structure as in this embodiment, degradation due to electrical conduction can be suppressed without increasing the on-resistance Ron or the forward voltage Vf of the parasitic diode.

[0052] (2) This embodiment includes the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37. This improves the breakdown voltage.

[0053] (3) In this embodiment, the ion implantation defect 50 has a defect position of 3 μm or more and 5 μm or less, or the ratio of the defect position of the ion implantation defect 50 to the thickness of the upper layer portion 120 is 0.3 or more and 0.5 or less. This makes it possible to suppress an increase in DS leakage current while suppressing an increase in costs due to an increase in the size of the ion implantation device or complex control.

[0054] (4) In this embodiment, when the semiconductor substrate 12 is made of silicon carbide, by forming the ion implantation defects 50 as described above, it is possible to suppress the expansion of basal plane dislocations into stacking faults, and thus to suppress electrical degradation.

[0055] (5) In this embodiment, the ion implantation defects 50 are inert gas defects formed of an inert gas, which further reduces the influence of the lifetime on electrons and further reduces the on-resistance Ron.

[0056] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0057] For example, in the first embodiment, the semiconductor device 10 may be a planar gate type semiconductor device 10 instead of a trench gate type semiconductor device 10 .

[0058] Furthermore, in the semiconductor device 10 of the first embodiment, an n-channel MOSFET having an n-type first conductivity type and a p-type second conductivity type has been described. However, this is merely an example, and a p-channel MOSFET may be formed, for example, in which the conductivity types of the components of the n-channel MOSFET are reversed. Furthermore, the semiconductor device 10 may be configured to include an IGBT (short for Insulated Gate Bipolar Transistor) having a similar structure in addition to the MOSFET. In the case of an IGBT, the MOSFET is the same as the MOSFET described in the first embodiment, except that the drain layer 40 in the first embodiment is replaced with a p-type collector layer.

[0059] In the first embodiment, the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37 may not be provided.

[0060] In the first embodiment described above, when viewed from the one surface 12a side of the semiconductor substrate 12, each p-type deep layer 36 and each n-type deep layer 37 may be formed so as to intersect obliquely with each trench 14.

[0061] [Disclosure of the Present Invention] The present disclosure described above can be understood from the following viewpoints, for example. [First Aspect] A semiconductor device comprising: a semiconductor substrate (12) made of a compound semiconductor and having a first impurity layer (40) of a first conductivity type or a second conductivity type; an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type; a body layer (34) of the second conductivity type formed in a surface layer portion of the upper layer portion; and a third impurity layer (30) of the first conductivity type formed in a surface layer portion of the body layer, the semiconductor substrate having a surface (12a) opposite to the first impurity layer side; a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer; and a gate electrode (18) disposed on the gate insulating film, wherein ion implantation defects (50) are formed in the second impurity layer of the semiconductor substrate, and the ion implantation defects are located at a distance of 2 μm to 6 μm from the surface of the semiconductor substrate, and the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A semiconductor device that is:

[0062] [Second Aspect] The semiconductor device according to the first aspect, wherein a trench (14) is formed that penetrates the body layer from one surface side of the semiconductor substrate and has a longitudinal direction in one direction in the surface direction of the one surface of the semiconductor substrate, the gate insulating film is arranged on a wall surface of the trench, the third impurity layer is in contact with the trench, and the ion implantation defects are formed below a bottom surface of the trench.

[0063] a second-conductivity-type deep layer (36) that protrudes downward from the body layer and extends from the body layer to a position lower than a bottom surface of the trench, extending in a plane direction of the semiconductor substrate and in an intersecting direction that intersects with the longitudinal direction of the trench, the intersecting direction being a plane direction of the semiconductor substrate and arranged with a gap (39) in the longitudinal direction, and that is connected to the second-conductivity-type trench lower layer; and a first-conductivity-type deep layer (37) that is arranged in the gap, extends in the intersecting direction, and constitutes a part of the second impurity layer, and the ion implantation defects are formed below the second-conductivity-type trench lower layer and the second-conductivity-type deep layer.

[0064] [Fourth Aspect] The semiconductor device according to any one of the first to third aspects, wherein the ion implantation defects are located at a position not less than 3 μm and not more than 5 μm from one surface of the semiconductor substrate.

[0065] [Fifth Aspect] A semiconductor device comprising: a semiconductor substrate (12) made of a compound semiconductor, the semiconductor substrate having a first impurity layer (40) of a first conductivity type or a second conductivity type, an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type, a body layer (34) of the second conductivity type formed in a surface layer portion of the upper layer portion, and a third impurity layer (30) of the first conductivity type formed in a surface layer portion of the body layer, the semiconductor substrate having a surface (12a) opposite to the first impurity layer side; a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer; and a gate electrode (18) disposed on the gate insulating film, wherein ion implantation defects (50) are formed in the second impurity layer of the semiconductor substrate, The ion implantation defects have a ratio of the defect position from one surface of the semiconductor substrate to the thickness of the upper layer portion of 0.2 to 0.6, and a defect density of 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A semiconductor device that is:

[0066] [Sixth Aspect] The semiconductor device according to the fifth aspect, wherein a trench (14) is formed that penetrates the body layer from one surface side of the semiconductor substrate and has a longitudinal direction in one direction in a surface direction of the one surface of the semiconductor substrate, the gate insulating film is disposed on a wall surface of the trench, and the third impurity layer is in contact with the trench.

[0067] [Seventh Aspect] The semiconductor device according to the sixth aspect, wherein the semiconductor substrate has: a second-conductivity-type trench lower layer (35) disposed below the trench and extending along the longitudinal direction of the trench; a second-conductivity-type deep layer (36) protruding downward from the body layer and extending from the body layer to a position lower than the bottom surface of the trench, extending in a plane direction of the semiconductor substrate and in an intersecting direction intersecting the longitudinal direction of the trench, disposed with a gap (39) in the longitudinal direction, and connected to the second-conductivity-type trench lower layer; and a first-conductivity-type deep layer (37) disposed in the gap, extending in the intersecting direction, and constituting a part of the second impurity layer.

[0068] [Eighth Aspect] The semiconductor device according to any one of the fifth to seventh aspects, wherein the ratio of the defect position of the ion implantation defect from one surface of the semiconductor substrate to the thickness of the upper layer portion is 0.3 or more and 0.5 or less.

[0069] Ninth Aspect The semiconductor device according to any one of the first to eighth aspects, wherein the semiconductor substrate is made of silicon carbide.

[0070] [Tenth Aspect] The semiconductor device according to any one of the first to ninth aspects, wherein the ion implantation defects are inert gas defects.

[0071] [Eleventh Aspect] A semiconductor substrate (12) comprising a compound semiconductor and having a first impurity layer (40) of a first conductivity type or a second conductivity type, an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type, a body layer (34) of the second conductivity type formed in a surface layer portion of the upper layer portion, and a third impurity layer (30) of the first conductivity type formed in a surface layer portion of the body layer, the semiconductor substrate (12) having a surface (12a) opposite to the first impurity layer side, a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer, and a gate electrode (18) disposed on the gate insulating film, wherein ion implantation defects (50) are formed in the second impurity layer of the semiconductor substrate, and the ion implantation defects are located at a distance of 2 μm or more and 6 μm or less from the surface, with the surface of the semiconductor substrate being taken as a reference, and the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A method for manufacturing a semiconductor device, comprising: forming the ion implantation defects by performing ion implantation.

[0072] [Twelfth Aspect] A semiconductor substrate (12) comprising a compound semiconductor and having a first impurity layer (40) of a first conductivity type or a second conductivity type, an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type, a body layer (34) of the second conductivity type formed in a surface layer portion of the upper layer portion, and a third impurity layer (30) of the first conductivity type formed in a surface layer portion of the body layer, the semiconductor substrate (12) having a surface (12a) opposite to the first impurity layer side, a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer, and a gate electrode (18) disposed on the gate insulating film, wherein ion implantation defects (50) are formed in the second impurity layer of the semiconductor substrate, and the ratio of the defect positions of the ion implantation defects from the one surface of the semiconductor substrate to the thickness of the upper layer portion is 0.2 or more and 0.6 or less, and the defect density is 2.0×10 １６ / cm ３Above 5.0 x 10 １６ / cm ３ A method for manufacturing a semiconductor device, comprising: forming the ion implantation defects by performing ion implantation.

[0073] [Thirteenth Aspect] The method for manufacturing a semiconductor device according to the eleventh or twelfth aspect, wherein forming the ion implantation defects comprises ion implanting an inert gas to form the ion implantation defects.

Claims

1. A semiconductor device comprising: a semiconductor substrate (12) made of a compound semiconductor and having a first impurity layer (40) of a first conductivity type or a second conductivity type; an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type; a body layer (34) of the second conductivity type formed in a surface layer portion of the upper layer portion; and a third impurity layer (30) of the first conductivity type formed in a surface layer portion of the body layer; the semiconductor substrate (12) having a surface (12a) opposite to the first impurity layer side; a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer; and a gate electrode (18) disposed on the gate insulating film; and ion implantation defects (50) formed in the second impurity layer of the semiconductor substrate, the ion implantation defects being located at a distance of 2 μm to 6 μm from the surface of the semiconductor substrate, and having a defect density of 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A semiconductor device that is:

2. The semiconductor device according to claim 1, wherein a trench (14) is formed that penetrates from one surface side of the semiconductor substrate through the body layer and has a longitudinal direction in one direction in the surface direction of the one surface of the semiconductor substrate, the gate insulating film is arranged on a wall surface of the trench, the third impurity layer is in contact with the trench, and the ion implantation defects are formed below the bottom surface of the trench.

3. The semiconductor device according to claim 2, wherein the semiconductor substrate comprises: a second conductivity type trench lower layer (35) disposed below the trench and extending along the longitudinal direction of the trench; a second conductivity type deep layer (36) protruding downward from the body layer and extending from the body layer to a position lower than the bottom surface of the trench, extending in a plane direction of the semiconductor substrate and in an intersecting direction intersecting the longitudinal direction of the trench, disposed with a gap (39) in the longitudinal direction and connected to the second conductivity type trench lower layer; and a first conductivity type deep layer (37) disposed in the gap, extending in the intersecting direction, and constituting a part of the second impurity layer; and wherein the ion implantation defects are formed below the second conductivity type trench lower layer and the second conductivity type deep layer.

4. The semiconductor device according to claim 3, wherein the ion implantation defects are located at a position not less than 3 μm and not more than 5 μm from one surface of the semiconductor substrate.

5. A semiconductor device comprising: a semiconductor substrate (12) made of a compound semiconductor and having a first impurity layer (40) of a first conductivity type or a second conductivity type; an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type; a body layer (34) of the second conductivity type formed in a surface portion of the upper layer portion; and a third impurity layer (30) of the first conductivity type formed in a surface portion of the body layer; a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer; and a gate electrode (18) disposed on the gate insulating film; and ion implantation defects (50) formed in the second impurity layer of the semiconductor substrate, wherein the ratio of the defect position from the surface of the semiconductor substrate of the ion implantation defects to the thickness of the upper layer portion is 0.2 or more and 0.6 or less, and the defect density is 2.0 x 10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A semiconductor device that is:

6. The semiconductor device according to claim 5, wherein a trench (14) is formed that penetrates the body layer from one surface side of the semiconductor substrate and has a longitudinal direction in one direction in the surface direction of the one surface of the semiconductor substrate, the gate insulating film is arranged on a wall surface of the trench, and the third impurity layer is in contact with the trench.

7. The semiconductor device according to claim 6, wherein the semiconductor substrate comprises: a second conductivity type trench lower layer (35) disposed below the trench and extending along the longitudinal direction of the trench; a second conductivity type deep layer (36) protruding downward from the body layer and extending from the body layer to a position lower than the bottom surface of the trench, extending in a plane direction of the semiconductor substrate and in an intersecting direction intersecting the longitudinal direction of the trench, disposed with a gap (39) in the longitudinal direction and connected to the second conductivity type trench lower layer; and a first conductivity type deep layer (37) disposed in the gap, extending in the intersecting direction, and constituting a part of the second impurity layer.

8. The semiconductor device according to claim 7, wherein the ratio of the position of the ion implantation defects from one surface of the semiconductor substrate to the thickness of the upper layer portion is 0.3 or more and 0.5 or less.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate is made of silicon carbide.

10. A semiconductor device according to any one of claims 1 to 8, wherein the ion implantation defects are inert gas defects.

11. A semiconductor substrate (12) comprising a first impurity layer (40) of a first conductivity type or a second conductivity type, an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type, a body layer (34) of the second conductivity type formed in a surface layer portion of the upper layer portion, and a third impurity layer (30) of the first conductivity type formed in a surface layer portion of the body layer, the semiconductor substrate (12) being made of a compound semiconductor and having a surface (12a) opposite to the first impurity layer side, a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer, and a gate electrode (18) disposed on the gate insulating film, wherein ion implantation defects (50) are formed in the second impurity layer of the semiconductor substrate, and the ion implantation defects are located at a distance of 2 μm to 6 μm from the surface, with the surface of the semiconductor substrate being taken as a reference, and the defect density is 2.0×10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A method for manufacturing a semiconductor device, comprising: forming the ion implantation defects by performing ion implantation.

12. A semiconductor substrate (12) comprising a first impurity layer (40) of a first conductivity type or a second conductivity type, an upper layer portion (120) disposed on the first impurity layer and including a second impurity layer (38, 37) of the first conductivity type, a body layer (34) of the second conductivity type formed in a surface portion of the upper layer portion, and a third impurity layer (30) of the first conductivity type formed in a surface portion of the body layer, the semiconductor substrate (12) being made of a compound semiconductor and having a surface (12a) opposite to the first impurity layer side, a gate insulating film (16) disposed between the third impurity layer and the second impurity layer and in contact with the body layer, and a gate electrode (18) disposed on the gate insulating film, wherein ion implantation defects (50) are formed in the second impurity layer of the semiconductor substrate, and the ratio of the defect position from the one surface of the semiconductor substrate of the ion implantation defects to the thickness of the upper layer portion is 0.2 or more and 0.6 or less, and the defect density is 2.0 x 10 １６ / cm ３ Above 5.0 x 10 １６ / cm ３ A method for manufacturing a semiconductor device, comprising: forming the ion implantation defects by performing ion implantation.

13. The method for manufacturing a semiconductor device according to claim 11 or 12, wherein the forming of the ion implantation defects involves ion implantation of an inert gas to form the ion implantation defects.

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