Semiconductor module

Abstract

A semiconductor module (100) comprises: a submount substrate (11); a LID (1) having a top plate (2) and a side wall (3); a semiconductor element (31); a plurality of electrode pads (23); an adhesive (51) for fixing the LID (1) and the submount substrate (11); and a frame body (41). The frame body (41) is sandwiched between the side wall (3) of the LID (1) and the submount substrate (11), and the frame body (41) extends in a manner covering the plurality of electrode pads (23) in a plan view.

Description

Semiconductor Module

[0001] The present disclosure relates to a semiconductor module in which a semiconductor element is mounted on a submount substrate.

[0002] In recent years, the field of wireless communications has evolved from the fifth-generation mobile communications system (5G) to 5G-Advanced, and further to Beyond 5G (sixth-generation mobile communications system), promoting faster speeds and larger capacities. In Japan, 5G is allocated 28 GHz as a communication frequency, in addition to the 3.7 GHz and 4.5 GHz (Sub6) bands. As demand for even faster and larger-capacity communications continues, it will be necessary to utilize higher frequency bands that enable faster speeds and wider bandwidths. For 5G-Advanced and Beyond 5G, the use of frequency bands above 6 GHz, millimeter wave bands (30 GHz to 300 GHz), and terahertz bands (100 GHz to 1 THz) is being considered, requiring support for higher frequencies than ever before.

[0003] In such high frequency bands, the transmission of high frequency signals on submount substrates such as motherboards and package substrates is significantly affected. For example, the transmission loss increases as the frequency increases due to the resistance of the signal line and the dielectric properties of the insulator.

[0004] In order to ensure the required characteristics of a submount substrate equipped with a semiconductor element and a high-frequency band transmission line, it is desirable that other materials such as solder resist or resin with a dielectric constant be present as little as possible in the wiring portion of the submount substrate (the surface on which the semiconductor element is mounted).For this reason, for submount substrates on which semiconductor elements are mounted, overmolding is not performed to cover the semiconductor element with resin, and instead a hollow package structure in which the semiconductor element is covered with a LID (lid) is used.

[0005] In this case, the LID is fixed to the submount substrate using an adhesive or the like. However, during this fixing process, the adhesive may overflow inside the LID and adhere to the signal wiring on the submount substrate or the wires connecting the wiring to the semiconductor element. When adhesive adheres to the wiring on the submount substrate, the dielectric constant and dielectric loss tangent of the adhesive significantly affect the high-frequency transmission characteristics. Therefore, various techniques have been proposed to prevent the adhesive overflowing inside the LID from covering the signal wiring and wires on the submount substrate when fixing the LID to the submount substrate (for example, see Patent Document 1). Patent Document 1 discloses a technique for preventing the adhesive from flowing into the wiring by placing a dam-shaped member between the sidewall of the LID and the wiring on the submount substrate.

[0006] JP 2011-114192 A

[0007] However, the technology disclosed in Patent Document 1 requires the placement of a dam-like member between the sidewall of the LID and the wiring portion to prevent the adhesive from flowing in, thereby narrowing the area in which the semiconductor element and wiring pattern are arranged or increasing the size of the semiconductor module. Patent Document 1 also describes the use of a protective insulating film as the dam-like member, but does not specify its thickness, which is assumed to be approximately 20 to 30 μm. However, with this thickness, it is difficult to adequately prevent the adhesive from flowing in. As a result, the adhesive flows into the interior of the semiconductor module, degrading the characteristics of the semiconductor module.

[0008] The present disclosure has been made to solve such problems, and aims to provide a small semiconductor module that can suppress deterioration of characteristics caused by adhesive in a hollow semiconductor module in which a LID is fixed to a submount substrate with adhesive.

[0009] In order to achieve the above-mentioned object, a first semiconductor module according to one embodiment of the present disclosure comprises a rectangular submount substrate having a first main surface and a second main surface opposite the first main surface, a die pad and a wiring pattern provided on the first main surface of the submount substrate, a semiconductor element mounted on the die pad, a plurality of electrode pads provided on the second main surface of the submount substrate, a LID having a rectangular top plate and side walls along the four sides of the top plate, an adhesive that bonds the side walls of the LID to the first main surface of the submount substrate, and a frame body sandwiched between the side walls of the LID and the submount substrate, wherein the frame body extends so as to cover the plurality of electrode pads in a planar view.

[0010] Furthermore, a second semiconductor module according to one embodiment of the present disclosure includes a rectangular submount substrate having a first main surface and a second main surface opposite the first main surface, a die pad and wiring pattern arranged on a first wiring layer provided on the first main surface of the submount substrate, a semiconductor element mounted on the die pad, a plurality of electrode pads arranged on a second wiring layer provided on the second main surface of the submount substrate, a LID having a rectangular top plate and sidewalls along the four sides of the top plate, and an adhesive that bonds the sidewalls of the LID to the first main surface of the submount substrate, wherein a groove is provided along the inside of the sidewall of the LID, and the opening width of the top of the groove is wider than the opening width of the bottom of the groove.

[0011] According to the semiconductor module according to the present disclosure, it is possible to provide a small-sized semiconductor module that can suppress deterioration of characteristics due to the adhesive that bonds the submount substrate and the LID.

[0012] FIG. 1A is a plan view of a semiconductor module according to a first embodiment. FIG. 1B is a cross-sectional view of the semiconductor module according to the first embodiment. FIG. 2 is a plan view of the semiconductor module according to the first embodiment without a LID mounted thereon. FIG. 3A is a diagram showing an example of a positional relationship between a frame body and electrode pads in the semiconductor module according to the first embodiment. FIG. 3B is a diagram showing another example of a positional relationship between the frame body and electrode pads in the semiconductor module according to the first embodiment. FIG. 4 is a diagram showing an example of a positional relationship between a frame body and a matching circuit region in the semiconductor module according to the first embodiment. FIG. 5A is a diagram showing an example of a positional relationship between a frame body and a side wall of a LID in the semiconductor module according to the first embodiment. FIG. 5B is a diagram showing another example of a positional relationship between the frame body and a side wall of a LID in the semiconductor module according to the first embodiment. FIG. 6A is a diagram showing a first example of a configuration of a frame body in a semiconductor module according to a second embodiment. FIG. 6B is a diagram showing a second example of a configuration of a frame body in a semiconductor module according to the second embodiment. FIG. 6C is a diagram showing a third example of a configuration of a frame body in a semiconductor module according to the second embodiment. FIG. 6D is a diagram showing a fourth example of a configuration of a frame body in a semiconductor module according to the second embodiment. FIG. 7A is a diagram showing a first example of a plan view of a submount substrate of a semiconductor module according to embodiment 3. FIG. 7B is a diagram showing a second example of a plan view of a submount substrate of a semiconductor module according to embodiment 3. FIG. 7C is a diagram showing a third example of a plan view of a submount substrate of a semiconductor module according to embodiment 3. FIG. 8A is a diagram showing an example of a configuration of an alignment mark of a semiconductor module according to embodiment 3. FIG. 8B is a diagram showing another example of a configuration of an alignment mark of a semiconductor module according to embodiment 3. FIG. 9A is a cross-sectional view of a semiconductor module according to embodiment 4. FIG. 9B is a plan view of a semiconductor module according to embodiment 4 when a LID is not mounted. FIG. 10A is a cross-sectional view of a semiconductor module according to a modification of embodiment 4. FIG. 10B is a plan view of a semiconductor module according to a modification of embodiment 4 when a LID is not mounted.

[0013] Semiconductor modules according to embodiments will be described in detail below with reference to the drawings. Each of the embodiments described below represents a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement positions, and connection configurations shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact representation. In each figure, substantially identical components are designated by the same reference numerals, and redundant descriptions may be omitted or simplified. Furthermore, among the components in the following embodiments, components not described in the independent claims representing the highest concepts will be described as optional components.

[0014] First Embodiment First, a semiconductor module 100 according to a first embodiment will be described with reference to Figures 1A, 1B, and 2. Figure 1A is a plan view of the semiconductor module 100, and Figure 1B is a cross-sectional view of the semiconductor module 100 taken along line AA'. Figure 2 is a plan view showing the semiconductor module 100 according to the first embodiment before a LID 1 is mounted (when no LID is mounted).

[0015] 1B, the semiconductor module 100 includes a submount substrate 11, a semiconductor element 31, a LID 1, an adhesive 51, and a frame 41. As shown in FIG. 1A, in this embodiment, the outer shape of the semiconductor module 100 is rectangular in plan view.

[0016] As shown in FIG. 1B , the submount substrate 11 has a first main surface 12 and a second main surface 13 opposite the first main surface 12. A first wiring layer 14 is provided on the first main surface 12, and a second wiring layer 15 is provided on the second main surface 13. The submount substrate 11 has a configuration in which an insulating layer 18 is sandwiched between the first wiring layer 14 and the second wiring layer 15. The insulating layer 18 is, for example, a resin substrate formed from an insulating resin material or a ceramic substrate formed from a ceramic material. In other words, the submount substrate 11 is a resin substrate or a ceramic substrate. The submount substrate 11 is also a rectangular substrate that has a rectangular shape in a plan view. Note that the submount substrate 11 may have a rectangular shape as long as it is rectangular overall, and some of its sides or corners may be cut out.

[0017] The first wiring layer 14 and the second wiring layer 15 are layers in which conductors such as wiring are formed in a predetermined shape.

[0018] In this embodiment, a wiring pattern 21 and a die pad 22 are formed on the first wiring layer 14. That is, the wiring pattern 21 and the die pad 22 are provided on the first main surface 12 of the submount substrate 11. A semiconductor element 31 is disposed on the die pad 22. The semiconductor element 31 and the die pad 22 are bonded with a die bond material 27 (solder, Ag paste, AuSn paste, etc.). The wiring pattern 21 is electrically connected to the semiconductor element 31 with wires 25 (Au, Cu, Al), etc.

[0019] A plurality of electrode pads 23 are formed on the second wiring layer 15. That is, the plurality of electrode pads 23 are provided on the second main surface 13 of the submount substrate 11. The plurality of electrode pads 23 are provided along the outer periphery of the second main surface 13 of the submount substrate 11. The plurality of electrode pads 23 may be electrically connected to the wiring pattern 21 through vias 26 provided in the insulating layer 18. Furthermore, a ground pad 24 is provided on the second wiring layer 15. The ground pad 24 and the die pad 22 may be electrically connected through vias 26 provided in the insulating layer 18. Although not shown, the plurality of electrode pads 23 are electrically connected to electrode pads of a motherboard, for example.

[0020] The semiconductor element 31 is, for example, a high frequency power amplifier device, and is made of a compound semiconductor (such as GaAs or GaN) or a Si semiconductor (such as LDMOS).

[0021] Although not shown, the first main surface 12 of the submount substrate 11 may be mounted with components such as capacitors and inductors (e.g., chip components or IPDs (Integrated Passive Devices)) for configuring a high-frequency matching circuit or a power supply circuit. The high-frequency matching circuit on the first main surface 12 is provided inside the matching circuit region 61. The first main surface 12 of the submount substrate 11 may also be provided with a flow prevention insulating pattern (first insulating film) to prevent the conductive adhesive (e.g., solder) used when mounting the components from flowing. The second main surface 13 of the submount substrate 11 may also be provided with a short-circuit prevention insulating pattern (second insulating film) to prevent the multiple electrode pads 23 from shorting out due to solder between the multiple electrode pads 23.

[0022] Although the submount substrate 11 is illustrated as a single-layer substrate as an example, the present invention is not limited to this. For example, the submount substrate 11 may be a multi-layer substrate in which insulating layers and wiring layers are alternately stacked.

[0023] The LID 1 is a cover that covers the semiconductor element 31. The LID 1 has a top plate 2 that is rectangular in plan view and side walls 3 that extend along the four sides of the top plate 2. The top plate 2 covers a matching circuit region 61 (see FIG. 2 ) that includes the semiconductor element 31, the wiring pattern 21, or mounted components. The top plate 2 is spaced apart from the submount substrate 11. Thus, a hollow space exists between the top plate 2 and the first main surface 12 of the submount substrate 11. The semiconductor element 31 is disposed in this space. In other words, the semiconductor module 100 has a hollow package structure. The side walls 3 are rectangular and frame-shaped, and surround the matching circuit region 61 that includes the semiconductor element 31, the wiring pattern 21, or mounted components. The LID 1 may be an integrated type in which the top plate 2 and the side walls 3 are integrally configured, or a separate type in which the top plate 2 and the side walls 3 are combined as separate components. The top plate 2 and the side wall 3 may be made of the same material or different materials, such as resin, ceramic, or metal.

[0024] The adhesive 51 bonds the LID 1 to the submount substrate 11. Specifically, the adhesive 51 bonds the sidewall 3 of the LID 1 to the peripheral portion of the first main surface 12 of the submount substrate 11. The adhesive 51 is applied to the peripheral portion of the submount substrate 11 or the sidewall 3 of the LID 1 using a dispenser or by a printing method using a printing mask. Alternatively, the adhesive 51 may be transferred to the sidewall 3 of the LID 1, and the LID 1 to which the adhesive 51 has been transferred may be mounted on the submount substrate 11. The adhesive 51 may be a resin adhesive such as a thermosetting resin, or a metal adhesive such as solder or Ag paste.

[0025] The frame body 41 is configured in an annular shape and is disposed on the periphery of the first main surface 12 of the submount substrate 11. The frame body 41 is rectangular and has a shape that is continuous along the four sides of the semiconductor module 100 in a plan view. Specifically, the frame body 41 is formed in a pattern that extends along the four sides of the submount substrate 11 and is continuous along the four sides of the submount substrate 11. The frame body 41 is sandwiched between the sidewall 3 of the LID 1 and the submount substrate 11. The frame body 41 may be disposed so as to contact the first main surface 12 of the submount substrate 11, or may be disposed so as to contact the sidewall 3 of the LID 1. Alternatively, the frame body 41 may be disposed between the sidewall 3 of the LID 1 and the submount substrate 11 without contacting the submount substrate 11 or the sidewall 3 of the LID 1. The frame body 41 may be formed of a conductor formed in the first wiring layer 14 of the submount substrate 11, or may be formed of a first insulating film. Furthermore, even if the frame body 41 is made of a conductor, no potential is applied to the frame body 41, and the frame body 41 is in a floating state in terms of potential. The thickness of the frame body 41 is, for example, 20 μm to 30 μm, but is not limited to this.

[0026] 3A is a diagram showing an example of the positional relationship between a frame body 41 and electrode pads 23 in the semiconductor module 100 according to the first embodiment. The electrode pads 23 are formed on the second main surface 13 of the submount substrate 11. Specifically, the electrode pads 23 are arranged along each of the four sides of the submount substrate 11. Meanwhile, the frame body 41 is arranged on the first main surface 12 of the submount substrate 11. As shown in FIG. 3A , the frame body 41 extends to cover the electrode pads 23 in a planar view. Specifically, the frame body 41 extends along the side direction of the submount substrate 11 and covers the electrode pads 23 along the side direction of the submount substrate 11 in a planar view. In other words, the frame body 41 is arranged to straddle the electrode pads 23 along the side direction of the submount substrate 11.

[0027] 3B is a diagram showing another example of the positional relationship between the frame body 41 and the electrode pads 23 in the semiconductor module 100 according to the first embodiment. As shown in FIG. 3B , the frame body 41 does not have to be a closed, annular rectangular shape, and may be divided along the way. In FIG. 3B , the frame body 41 is divided at the four corners of the submount substrate 11 and is composed of multiple straight line portions. Specifically, the frame body 41 is composed of four straight line portions extending along each of the four sides of the submount substrate 11. In this case, the length of the frame body 41 may vary for each side of the submount substrate 11. In FIG. 3B as well, the frame body 41 extends to cover multiple electrode pads 23 in a plan view.

[0028] 4 is a diagram showing an example of the positional relationship between the frame body 41 and the matching circuit region 61 in the semiconductor module 100 according to the first embodiment. Similar to FIG. 3B , the frame body 41 shown in FIG. 4 is configured with four straight line portions extending along each of the four sides of the submount substrate 11. As shown in FIG. 4 , the length of each straight line portion of the frame body 41 is set to a length that faces all of the wire pads (wiring patterns 21) that are bonded to the semiconductor element 31 by wires 25. Furthermore, the length of each straight line portion of the frame body 41 is set to a length that faces all of the sides of the semiconductor element 31 that face each side of the submount substrate 11.

[0029] 3A, 3B, and 4, the provision of the frame 41 makes it possible to prevent the adhesive 51 from spilling out to the inside of the semiconductor module 100 (i.e., the inside of the LID 1) when the LID 1 and the submount substrate 11 are fixed together with the adhesive 51. In other words, the frame 41 functions as a structure that prevents the adhesive 51, which fixes the LID 1 and the submount substrate 11 together, from flowing into the interior of the semiconductor module 100.

[0030] However, the effect of the frame body 41 in suppressing the flow of the adhesive 51 differs depending on the position of the frame body 41. Below, the difference in the effect of the frame body 41 in suppressing the flow of the adhesive 51 depending on the position of the frame body 41 will be described.

[0031] Fig. 5A is a diagram showing an example of the positional relationship between the frame body 41 and the side wall 3 of the LID 1 in the semiconductor module 100 according to the first embodiment, and Fig. 5B is a diagram showing another example of the positional relationship between the frame body 41 and the side wall 3 of the LID 1. Figs. 5A and 5B are enlarged cross-sectional views of an area B surrounded by a dashed line in Fig. 1B, showing an example of the arrangement of the frame body 41.

[0032] 5A , the width center C2 of the frame 41 is located further outward from the semiconductor module 100 than the width center C1 of the side wall 3 of the LID 1. Here, the width refers to the length in a direction perpendicular to the extension direction of the frame 41 and the side wall 3 of the LID 1 in a plan view. In other words, it is the length from each side of the semiconductor module 100 toward the inside of the semiconductor module 100. As an example, the adhesive 51 is applied to the side wall 3 of the LID 1.

[0033] In the case of Figure 5A, the gap between the side wall 3 of LID 1 and the submount substrate 11 is wider on the inside of the semiconductor module 100 than on the outside, so when LID 1 is fixed to the submount substrate 11, a larger amount of adhesive 51 will overflow onto the inside of the semiconductor module 100 (i.e., the inside of LID 1).

[0034] 5B, the center C2 of the width of the frame 41 is located inside the semiconductor module 100 (i.e., inside the LID 1) relative to the center C1 of the side wall 3 of the LID 1. Also, in FIG. 5B, the frame 41 is arranged so as to protrude further inside the semiconductor module 100 from the side wall 3 of the LID 1 in a plan view.

[0035] In the case of Figure 5B, the gap between the side wall 3 of LID 1 and the submount substrate 11 is wider on the outside of LID 1 than on the inside, so when LID 1 is fixed to the submount substrate 11, a larger amount of adhesive 51 will spill out to the outside of the semiconductor module 100.

[0036] In addition, a portion of the frame body 41 may be located inside the semiconductor module 100 from the center C1 of the side wall 3 of the LID 1, or the entire frame body 41 may be located inside the semiconductor module 100 from the center C1 of the side wall 3 of the LID 1.

[0037] 5B , by positioning the frame body 41 sandwiched between the sidewall 3 of the LID 1 and the first main surface 12 of the submount substrate 11 so that the center C2 of the width of the frame body 41 is located inside the semiconductor module 100 with respect to the center C1 of the width of the sidewall 3 of the LID 1, it is possible to prevent the adhesive 51 from spilling out inside the semiconductor module 100. This makes it possible to reduce the amount of adhesive 51 spilling out inside the semiconductor module 100. As a result, it is possible to prevent the adhesive 51 from flowing into the matching circuit region 61.

[0038] Furthermore, adhesive 51 may protrude outside semiconductor module 100, find its way onto second main surface 13 of submount substrate 11, and adhere to multiple electrode pads 23. To avoid this, it is preferable to use an aggregate substrate in which multiple submount substrates 11 are arranged. In this way, by mounting LID 1 on each submount substrate 11 on the aggregate substrate and then separating the individual submount substrates 11, adhesive 51 protruding outside semiconductor module 100 can be prevented from protruding onto second main surface 13 of submount substrate 11.

[0039] Furthermore, if the adhesive 51 is a thermosetting resin, air between the LID 1 and the submount substrate 11 may expand when the adhesive 51 is thermally cured, potentially causing the mounting position of the LID 1 to shift. Therefore, it is preferable to provide an opening as a vent in a portion of the frame 41 to allow the expanded air to escape. In this case, as shown in FIG. 3B , it is preferable that the opening in the frame 41 be located in a corner of the frame 41. This is because the corner of the frame 41 is the farthest from the matching circuit region 61. Therefore, by providing the opening in the frame 41 in a corner of the frame 41, it is possible to make it more difficult for the adhesive 51 to reach the matching circuit region 61.

[0040] The openings do not have to be provided at all four corners of the frame body 41. Specifically, the openings at the corners of the frame body 41 may be provided at one of the four corners, or at two or three corners. Furthermore, the openings of the frame body 41 that serve as vents may be provided at locations other than the corners of the frame body 41.

[0041] As described above, the semiconductor module 100 according to this embodiment comprises a rectangular submount substrate 11, a die pad 22 and wiring pattern 21 provided on the first main surface 12 of the submount substrate 11, a semiconductor element 31 arranged on the die pad 22, a plurality of electrode pads 23 provided on the second main surface 13 of the submount substrate 11, a LID 1 having a rectangular top plate 2 and side walls 3 along the four sides of the top plate 2, an adhesive 51 that bonds the side walls 3 of the LID 1 to the first main surface 12 of the submount substrate 11, and a frame body 41 sandwiched between the side walls 3 of the LID 1 and the submount substrate 11, and the frame body 41 extends so as to cover the plurality of electrode pads 23 in a planar view.

[0042] With this configuration, when the LID 1 and the submount substrate 11 are fixed together with the adhesive 51, the frame 41 can block the adhesive 51 that tends to overflow into the semiconductor module 100. This prevents the adhesive 51 from overflowing into the interior (internal region) of the semiconductor module 100. In other words, the amount of adhesive 51 that overflows into the interior of the semiconductor module 100 can be reduced. This prevents the adhesive 51 that overflows into the interior of the semiconductor module 100 from covering the internal components of the semiconductor module 100 (such as the semiconductor element 31, wires 25, wiring circuits, and LCR components). As a result, it is possible to prevent the adhesive 51 that overflows into the interior of the semiconductor module 100 from deteriorating the characteristics of the semiconductor module 100.

[0043] Thus, according to the semiconductor module 100 of this embodiment, in a hollow structure semiconductor module 100 in which the LID 1 is fixed to the submount substrate 11 with adhesive 51, it is possible to prevent the characteristics from deteriorating due to the adhesive 51, and it is possible to provide a small semiconductor module 100.

[0044] Second Embodiment Next, a semiconductor module 100 according to a second embodiment will be described with reference to Figures 6A to 6D. Figures 6A to 6D are diagrams showing the configuration of a frame 41 in a semiconductor module 100 according to the second embodiment. Figure 6A shows a first example, Figure 6B shows a second example, Figure 6C shows a third example, and Figure 6D shows a fourth example. Figures 6A to 6D are enlarged views of a portion corresponding to region B surrounded by a dashed line in Figure 1B.

[0045] 6A to 6D , in the semiconductor module 100 of this embodiment, the frame body 41 sandwiched between the sidewall 3 of the LID 1 and the first main surface 12 of the submount substrate 11 is located inside the semiconductor module 100 with respect to the center C1 of the width of the sidewall 3 of the LID 1 (i.e., inside the LID 1). Specifically, the frame body 41 is disposed such that the center C2 of the width of the frame body 41 is located inside the semiconductor module 100 with respect to the center C1 of the width of the sidewall 3 of the LID 1.

[0046] 1A and 1B according to the first embodiment, the semiconductor module 100 further includes a frame body 41 that is configured with multiple layers. Note that, apart from the fact that the frame body 41 is configured with multiple layers, the semiconductor module 100 according to the second embodiment has the same configuration as the semiconductor module 100 according to the first embodiment.

[0047] In this embodiment, the frame body 41 is made up of two layers. Specifically, the frame body 41 is made up of a first frame body 41a as a lower layer and a second frame body 41b as an upper layer located on the first frame body 41a. In this manner, in this embodiment, the first frame body 41a and the second frame body 41b make up one frame body 41. The thickness of the two-layer frame body 41 is, for example, 40 μm to 50 μm, but is not limited to this.

[0048] 6A has a structure in which a first frame body 41a and a second frame body 41b are stacked on the first main surface 12 of the submount substrate 11. Specifically, the second frame body 41b is stacked on top of the first frame body 41a. The first frame body 41a and the second frame body 41b are in contact with each other.

[0049] 6B has a structure in which a first frame body 41a is provided on the first main surface 12 of the submount substrate 11, and a second frame body 41b is provided on the bottom surface of the side wall 3 of the LID 1. The first frame body 41a and the second frame body 41b are not in contact with each other, and are spaced apart from each other.

[0050] The frame body 41 shown in Figure 6C has a structure in which the upper second frame body 41b extends only on one side in the width direction, and the second frame body 41b rides over one end of the first frame body 41a. The end of the second frame body 41b on one side in the width direction that rides over the end of the first frame body 41a is in close contact with the first main surface 12 of the submount substrate 11. Also, in Figure 6C, the second frame body 41b extends toward the inside of the semiconductor module 100 and rides over the end of the first frame body 41a that is on the inside of the semiconductor module 100.

[0051] 6D has a structure in which the upper second frame body 41b extends on both sides in the width direction, and the second frame body 41b extends over both ends of the first frame body 41a. Both widthwise ends of the second frame body 41b that extend over both ends of the first frame body 41a are in close contact with the first main surface 12 of the submount substrate 11. In the frame body 41 configured in this manner, the second frame body 41b is formed to cover the entire first frame body 41a.

[0052] In Figures 6A to 6D, the multiple layers constituting the frame body 41 are made of different materials. For example, the multiple layers constituting the frame body 41 are made of a metal layer and an insulating film layer. In this embodiment, the multiple layers constituting the frame body 41 are a first frame body 41a and a second frame body 41b. In this case, the first frame body 41a can be made of, for example, a conductor (metal layer) formed on the first wiring layer 14, and the second frame body 41b can be made of, for example, a first insulating film (insulating film layer). Because the adhesive 51 made of resin and the metal layer formed on the first wiring layer 14 do not adhere well, it is preferable to place the second frame body 41b on top of the first frame body 41a and cover the entire first frame body 41a, which is a metal layer, with the second frame body 41b, which is an insulating film layer. This improves adhesion between the frame body 41 and the adhesive 51.

[0053] As described above, the semiconductor module 100 according to this embodiment also has a frame body 41 sandwiched between the side wall 3 of the LID 1 and the submount substrate 11, as in the first embodiment, and the frame body 41 extends to cover a plurality of electrode pads 23 in a planar view.

[0054] With this configuration, when the LID 1 and the submount substrate 11 are fixed with the adhesive 51, the adhesive 51 can be prevented from spilling out into the inside (internal region) of the semiconductor module 100, thereby preventing the adhesive 51 spilling out into the inside of the semiconductor module 100 from deteriorating the characteristics of the semiconductor module 100. Therefore, it is possible to provide a small-sized semiconductor module 100 in which deterioration of the characteristics due to the adhesive 51 can be prevented.

[0055] In the semiconductor module 100 according to the present embodiment, the frame body 41 is made up of a plurality of layers. Specifically, the frame body 41 is made up of a first frame body 41 a and a second frame body 41 b.

[0056] This configuration allows the height of the frame body 41 to be increased, thereby widening the gap between the bottom surface of the side wall 3 of the LID 1 and the first main surface 12 of the submount substrate 11. This further prevents the adhesive 51 from spilling out into the inside of the semiconductor module 100. This further prevents the characteristics of the semiconductor module 100 from deteriorating.

[0057] In particular, in this embodiment, the frame 41 is located inside the semiconductor module 100 from the center C1 of the width of the sidewall 3 of the LID 1. This allows the distance outside the semiconductor module 100 to be wider than the center C1 of the width of the sidewall 3 of the LID 1 between the bottom surface of the sidewall 3 of the LID 1 and the first main surface 12 of the submount substrate 11. As a result, the adhesive 51 can be made to protrude more outside the semiconductor module 100. In other words, the amount of adhesive 51 protruding inside the semiconductor module 100 can be reduced.

[0058] In the present embodiment, the frame body 41 is configured from two layers, and the layers (the first frame body 41a and the second frame body 41b) are configured from different materials. However, this is not limiting. That is, the layers constituting the frame body 41 may be configured from the same material. For example, the first frame body 41a and the second frame body 41b may be configured from the same material. When the layers constituting the frame body 41 are configured from the same material, it is preferable that the layers constituting the frame body 41 be configured from an insulating film, taking into account the adhesion with the adhesive 51.

[0059] Third Embodiment Next, a semiconductor module 100 according to a third embodiment will be described with reference to Figures 7A to 7C. Figures 7A to 7C are plan views of the submount substrate 11 of the semiconductor module 100 according to the third embodiment. Figure 7A shows a first example, Figure 7B shows a second example, and Figure 7C shows a third example.

[0060] 1A and 1B, the semiconductor module 100 according to the third embodiment further includes an alignment mark 28 on the first main surface 12 of the submount substrate 11. Apart from the provision of the alignment mark 28, the semiconductor module 100 according to the third embodiment has the same configuration as the semiconductor module 100 according to the first embodiment.

[0061] From the viewpoint of preventing the adhesive 51 from spilling out to the inside of the semiconductor module 100 (i.e., the inside of the LID 1), the positional relationship between the center C1 of the width of the sidewall 3 of the LID 1 and the center C2 of the width of the frame body 41 is extremely important. For this reason, it is important to improve the mounting accuracy of the LID 1. Therefore, in the semiconductor module 100 of this embodiment, an alignment mark 28 is provided on the first main surface 12 of the submount substrate 11 to improve the mounting accuracy of the LID 1. The alignment mark 28 can be made of, for example, the same material as the frame body 41, but is not limited to this.

[0062] 7A to 7C, the alignment marks 28 are provided at the corners of the submount substrate 11. In this embodiment, the alignment marks 28 are provided at diagonal positions on the first main surface 12 of the submount substrate 11. Specifically, the alignment marks 28 are provided at two locations on a diagonal line of the submount substrate 11. This allows the center of the submount substrate 11 to be calculated using the two alignment marks 28 located on the diagonal line, thereby improving the mounting accuracy of the LID 1. In other words, the LID 1 can be mounted with high mounting accuracy.

[0063] 7A, the alignment mark 28 is provided outside the frame body 41. By providing the alignment mark 28 outside the frame body 41, the matching circuit region 61 is not affected by the alignment mark 28. In other words, the area of ​​the matching circuit region 61 does not change.

[0064] 7B, the alignment mark 28 is provided inside the frame body 41. If the alignment mark 28 is provided inside the frame body 41, it is necessary to narrow the area of ​​the matching circuit region 61 or increase the size of the submount substrate 11.

[0065] 7C , alignment mark 28 is disposed on an extension of frame 41 divided at the corner. Specifically, openings are provided at the corners of frame 41, and alignment mark 28 is provided in those openings. In this case, alignment mark 28 does not affect matching circuit region 61, and the size of matching circuit region 61 does not change.

[0066] The planar shape of the alignment mark 28 is, for example, circular, but is not limited thereto. For example, the planar shape of the alignment mark 28 may be a polygon such as a rectangle or a triangle, or may be a cross shape. The alignment mark 28 may have a protruding (convex) shape protruding from the first main surface 12 of the submount substrate 11, or a concave shape recessed into a portion of the first main surface 12 of the submount substrate 11. The alignment mark 28 may be produced in either a negative or positive print. However, it is preferable that the alignment mark 28 have a shape different from the shape of its surroundings. For example, if the corners of the rectangular frame 41 themselves were used as the alignment mark 28, they might be mistaken for the corners of the wiring pattern 21 in the matching circuit region 61. The size of the alignment mark 28 should preferably be 0.1 mm or larger in its outermost dimension.

[0067] 8A and 8B, the alignment mark 28 may be provided on the frame 41. Fig. 8A is a diagram showing an example of the configuration of the alignment mark 28 of the semiconductor module 100 according to the third embodiment. Fig. 8B is a diagram showing another example of the configuration of the alignment mark 28 of the semiconductor module 100 according to the third embodiment. In Figs. 8A and 8B, the upper diagrams are enlarged plan views of the submount substrate 11, and the lower diagrams are cross-sectional views taken along line CC' in the upper diagrams.

[0068] 8A and 8B is provided on a frame 41 that is made up of two layers, a first frame 41a and a second frame 41b. The alignment mark 28 and the two-layer frame 41 serve as a combined structure. Therefore, the alignment mark 28 is made of the same material as the frame 41.

[0069] 8A, the first frame 41a is formed from a conductor formed in the first wiring layer 14, and the second frame 41b made of the first insulating film is formed in a predetermined shape (for example, a circle) partially on the first frame 41a, thereby providing the alignment mark 28. In this case, the alignment mark 28 is the second frame 41b.

[0070] 8B, the first frame body 41a is formed from a conductor formed in the first wiring layer 14, and the second frame body 41b made of the first insulating film is formed on top of the first frame body 41a in the same shape as the first frame body 41a, thereby overlapping the first frame body 41a and the second frame body 41b, and a predetermined shape (for example, a circle) is opened in part of the second frame body 41b to provide the alignment mark 28. In this case, the alignment mark 28 is the opening in the second frame body 41b.

[0071] In this way, by constructing the alignment mark 28 from the same material as the frame body 41, the frame body 41 and the alignment mark 28 can be manufactured simultaneously, and a frame body 41 can be realized that can be used as the alignment mark 28 while having the function of suppressing the overflow of the adhesive 51.

[0072] As described above, the semiconductor module 100 according to this embodiment also has a frame body 41 sandwiched between the side wall 3 of the LID 1 and the submount substrate 11, as in the first embodiment, and the frame body 41 extends to cover a plurality of electrode pads 23 in a planar view.

[0073] With this configuration, when the LID 1 and the submount substrate 11 are fixed together with the adhesive 51, the adhesive 51 can be prevented from spilling out into the inside (internal region) of the semiconductor module 100, thereby preventing the adhesive 51 spilling out into the inside of the semiconductor module 100 from deteriorating the characteristics of the semiconductor module 100. Therefore, it is possible to provide a small-sized semiconductor module 100 in which deterioration of the characteristics due to the adhesive 51 can be prevented.

[0074] Furthermore, in the semiconductor module 100 according to this embodiment, the alignment mark 28 made of the same material as the frame 41 is provided on the first main surface 12 of the submount substrate 11 .

[0075] This configuration improves the mounting accuracy of the LID 1 on the submount substrate 11. That is, the LID 1 can be fixed to a predetermined position on the submount substrate 11 with the adhesive 51. As a result, it is possible to further prevent the adhesive 51 from spilling out into the inside of the semiconductor module 100.

[0076] Furthermore, in the semiconductor module 100 according to this embodiment, alignment marks 28 are provided at diagonal positions on the first main surface 12 of the submount substrate 11 .

[0077] This configuration can further improve the mounting accuracy of the LID 1 on the submount substrate 11. This can further prevent the adhesive 51 from spilling out to the inside of the semiconductor module 100.

[0078] Fourth Embodiment Next, a semiconductor module 100a according to a fourth embodiment will be described with reference to Figures 9A and 9B. Figure 9A is a cross-sectional view of the semiconductor module 100a according to the fourth embodiment. Figure 9B is a plan view of the semiconductor module 100a according to the fourth embodiment before the LID 1 is mounted (when the LID is not mounted).

[0079] 9A and 9B, the semiconductor module 100a according to the fourth embodiment has a configuration in which the frame body 41 is not provided and a groove 71 is provided in the submount substrate 11 in the semiconductor module 100 according to the first embodiment shown in Figures 1A and 1B. Note that, apart from the absence of the frame body 41 and the provision of the groove 71, the semiconductor module 100a according to the fourth embodiment has the same configuration as the semiconductor module 100 according to the first embodiment.

[0080] Similar to the submount substrate 11 in the first embodiment, the submount substrate 11a in the present embodiment has a first main surface 12 and a second main surface 13 opposite to the first main surface 12. In the submount substrate 11a as well, a first wiring layer 14 is provided on the first main surface 12, and a second wiring layer 15 is provided on the second main surface 13. Similar to the submount substrate 11 in the first embodiment, the submount substrate 11a has a structure in which an insulating layer 18 is sandwiched between the first wiring layer 14 and the second wiring layer 15.

[0081] The groove 71 is provided on the first main surface 12 of the submount substrate 11a. The groove 71 is also provided along the inner side of the sidewall 3 of the LID 1. Specifically, the groove 71 is provided in a ring shape further inward of the semiconductor module 100a than the sidewall 3 of the LID 1 and along the four sides of the submount substrate 11a. The groove 71 can be provided using a laser (laser light) or a drill. As an example of how to create the groove 71, the groove 71 can be formed by forming recesses on the first main surface 12 of the submount substrate 11a using a laser used to form filled vias and then connecting these recesses. Specifically, the groove 71 can be formed by moving the laser little by little in one direction to continuously drill holes, thereby forming a rectangular groove 71 in a plan view. In this embodiment, the groove 71 is formed by continuously moving the laser along the four sides of the submount substrate 11a.

[0082] Moreover, groove 71 is formed so that the opening width at the top of groove 71 is wider than the opening width at the bottom of groove 71. In this embodiment, groove 71 has the widest opening width at the top, and the opening width narrows toward the bottom, with the opening width at the bottom being the narrowest. Specifically, the opening width of groove 71 gradually increases from the bottom to the top. As an example, the cross-sectional shape of groove 71 is an inverted trapezoid whose lower base is shorter than its upper base.

[0083] As described above, semiconductor module 100a according to this embodiment includes rectangular submount substrate 11a, die pad 22 and wiring pattern 21 provided on first main surface 12 of submount substrate 11a, semiconductor element 31 arranged on die pad 22, multiple electrode pads 23 provided on second main surface 13 of submount substrate 11a, rectangular top plate 2 and LID 1 having sidewalls 3 along the four sides of top plate 2, and adhesive 51 that bonds sidewalls 3 of LID 1 to first main surface 12 of submount substrate 11a. Groove 71 is provided along the inside of sidewall 3 of LID 1, and the opening width of the top of groove 71 is wider than the opening width of the bottom of groove 71.

[0084] With this configuration, when the LID 1 and the submount substrate 11 are fixed together with the adhesive 51, the adhesive 51 that protrudes into the semiconductor module 100a can be collected in the groove 71. This prevents the adhesive 51 from protruding into the interior (internal region) of the semiconductor module 100a. In other words, the amount of adhesive 51 that protrudes into the interior of the semiconductor module 100a can be reduced. This prevents the adhesive 51 that protrudes into the interior of the semiconductor module 100a from covering the internal components of the semiconductor module 100a (such as the semiconductor element 31, wires 25, wiring circuits, and LCR components). As a result, it is possible to prevent the adhesive 51 that protrudes into the interior of the semiconductor module 100a from deteriorating the characteristics of the semiconductor module 100a.

[0085] Thus, according to the semiconductor module 100a of this embodiment, in a hollow structure semiconductor module 100a in which the LID 1 is fixed to the submount substrate 11a with adhesive 51, it is possible to prevent the characteristics from deteriorating due to the adhesive 51, and to provide a small semiconductor module 100a.

[0086] Next, a modification of the fourth embodiment will be described with reference to Figures 10A and 10B. Figure 10A is a cross-sectional view of a semiconductor module 100b according to the modification of the fourth embodiment. Figure 10B is a plan view of the semiconductor module 100b according to the modification of the fourth embodiment before the LID 1 is mounted (when the LID is not mounted).

[0087] A semiconductor module 100b in this modification further includes a frame body 41 in addition to the semiconductor module 100a described above. Furthermore, in this modification, the submount substrate 11b further includes multiple wiring layers and multiple insulating layers in addition to the first wiring layer 14, the second wiring layer 15, and the insulating layer 18. Specifically, the submount substrate 11b includes a third wiring layer 16, a fourth wiring layer 17, a second insulating layer 19, and a third insulating layer 20 in addition to the first wiring layer 14, the second wiring layer 15, and the insulating layer 18 (first insulating layer). In other words, the submount substrate 11b is a multilayer substrate in which wiring layers and insulating layers are alternately stacked.

[0088] The frame body 41 is sandwiched between the sidewall 3 of the LID 1 and the submount substrate 11b. The groove 71 is provided inside the semiconductor module 100b from the frame body 41 in a plan view. In this modification, an annular wiring pattern 21a that overlaps with the groove 71 in a plan view is formed in the third wiring layer 16 below the groove 71. This allows the groove 71 to have a constant depth when formed with a laser.

[0089] In the semiconductor module 100b configured in this manner, the groove 71 is provided in the submount substrate 11b, so that, similarly to the semiconductor module 100a, when the LID 1 and the submount substrate 11b are fixed with the adhesive 51, the adhesive 51 can be prevented from spilling into the inside (internal region) of the semiconductor module 100b. This prevents the adhesive 51 spilling into the inside of the semiconductor module 100b from deteriorating the characteristics of the semiconductor module 100b. Therefore, it is possible to provide a compact semiconductor module 100b in which the deterioration of characteristics due to the adhesive 51 can be prevented.

[0090] Furthermore, in the semiconductor module 100b, a frame body 41 is provided between the side wall 3 of the LID 1 and the first main surface 12 of the submount substrate 11b, and the groove 71 is provided inside the semiconductor module 100b from the frame body 41 in a plan view.

[0091] With this configuration, the frame 41 reduces the amount of adhesive 51 that overflows into the semiconductor module 100b, and the overflowing adhesive 51 can be collected in the groove 71. This further prevents the adhesive 51 from overflowing into the semiconductor module 100b. This reliably prevents the adhesive 51 from flowing into the matching circuit region 61.

[0092] In this embodiment, the groove 71 has an annular shape, but this is not limiting. For example, the groove 71 may not be provided at the corners of a rectangle, and may instead be composed of multiple straight line portions, as shown in FIGS. 3B and 4 , which illustrate modified examples of the frame body 41. In this case, the groove 71 may be composed of four straight line portions extending along each of the four sides of the submount substrate 11 a (11 b). Note that the corners are the farthest from the matching circuit region 61, so even if the groove 71 is not provided at the corners, the adhesive 51 is less likely to reach the matching circuit region 61.

[0093] Furthermore, the groove 71, which is made up of multiple straight line portions, may have different lengths for each side of the submount substrate 11 a (11 b). The length of each straight line portion of the groove 71 may be a length that faces all of the wire pads (wiring patterns 21) that are bonded to the semiconductor element 31 by the wires 25, or a length that faces all of the sides of the semiconductor element 31 that face each side of the submount substrate 11 a (11 b).

[0094] (Other Modifications) Although the semiconductor module according to the present disclosure has been described above based on the first to fourth embodiments, the present disclosure is not limited to the first to fourth embodiments.

[0095] For example, the present disclosure also includes forms obtained by applying various modifications to the above-described embodiments that would occur to a person skilled in the art, and forms realized by arbitrarily combining the components and functions of each embodiment within the scope of the present disclosure. The present disclosure also includes any combination of two or more claims from among the multiple claims set forth in the claims at the time of filing, provided that there is no technical contradiction. For example, when a dependent claim set forth in the claims at the time of filing is made into a multiple claim or multiple multiple claims that cite all of the superordinate claims within the scope of the technical contradiction, the present disclosure also includes any combination of all claims included in that multiple claim or multiple multiple multiple claim.

[0096] A semiconductor module according to the present disclosure is useful as a semiconductor module for wireless communication with little degradation in high-frequency performance.

[0097] REFERENCE SIGNS LIST 1 LID 2 Top plate 3 Side wall 11, 11a, 11b Submount substrate 12 First main surface 13 Second main surface 14 First wiring layer 15 Second wiring layer 16 Third wiring layer 17 Fourth wiring layer 18 Insulating layer 19 Second insulating layer 20 Third insulating layer 21, 21a Wiring pattern 22 Die pad 23 Electrode pad 24 Ground pad 25 Wire 26 Via 27 Die bond material 28 Alignment mark 31 Semiconductor element 41 Frame 41a First frame 41b Second frame 51 Adhesive 61 Matching circuit region 71 Groove 100, 100a, 100b Semiconductor module

Claims

1. A semiconductor module comprising: a rectangular submount substrate having a first main surface and a second main surface opposite the first main surface; a die pad and wiring pattern provided on the first main surface of the submount substrate; a semiconductor element disposed on the die pad; a plurality of electrode pads provided on the second main surface of the submount substrate; a lid having a rectangular top plate and side walls along four sides of the top plate; an adhesive that secures the side walls of the lid to the first main surface of the submount substrate; and a frame sandwiched between the side walls of the lid and the submount substrate, wherein the frame extends so as to cover the plurality of electrode pads in a plan view.

2. The semiconductor module according to claim 1, wherein the frame body has a shape that is continuous along the four sides of the semiconductor module in a plan view.

3. The semiconductor module according to claim 1, wherein the frame is in a floating state in terms of potential.

4. The semiconductor module according to claim 1, wherein the frame is positioned inside the semiconductor module from the center of the width of the side wall of the LID.

5. The semiconductor module according to claim 1, wherein the frame is made up of a plurality of layers.

6. The semiconductor module according to claim 5, wherein the plurality of layers are made of different materials.

7. The semiconductor module according to claim 6, wherein the plurality of layers are composed of a metal layer and an insulating film layer.

8. The semiconductor module according to claim 7, wherein the insulating film layer is disposed on the metal layer.

9. The semiconductor module according to claim 8, wherein the insulating film layer covers the entire metal layer.

10. The semiconductor module according to claim 1, wherein an alignment mark made of the same material as the frame is provided on the first main surface of the submount substrate.

11. The semiconductor module according to claim 10, wherein the alignment marks are provided at diagonal positions on the first main surface of the submount substrate.

12. A semiconductor module comprising: a rectangular submount substrate having a first main surface and a second main surface opposite the first main surface; a die pad and wiring pattern provided on the first main surface of the submount substrate; a semiconductor element mounted on the die pad; a plurality of electrode pads provided on the second main surface of the submount substrate; a LID having a rectangular top plate and side walls along four sides of the top plate; and an adhesive that fixes the side walls of the LID to the first main surface of the submount substrate, wherein a groove is provided along the inside of the side wall of the LID, and the opening width of the uppermost part of the groove is wider than the opening width of the lowermost part of the groove.

13. The semiconductor module according to claim 12, further comprising a frame body sandwiched between a side wall of the LID and the submount substrate, and the groove is provided inside the semiconductor module from the frame body in a plan view.

Images