Method for manufacturing engineered growth substrate for high-quality group iii nitride semiconductor through hot self-split process

Abstract

Provided is a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, the method comprising: a seed substrate preparation step of preparing a seed substrate on which an epitaxial layer for forming a predetermined element is to be grown; a seed substrate reforming step of irradiating a stealth laser onto the seed substrate so as to form a reforming layer inside the seed substrate; a wafer bonding step of wafer-bonding the seed substrate and a support substrate by means of a predetermined wafer bonding layer; a hot self-split step in which each of seed substrates on two sides, with the reforming layer therebetween, has a structural asymmetry or quantitative difference of thermal properties including a thermal expansion coefficient, so as to be separated, without external force, by means of thermal stress or mechanical stress formed on the reforming layer; and a flattening step of flattening two mutually facing surfaces of a seed area formed to be separated from the seed substrate with the seed substrate and the reforming layer as a boundary.

Description

Method for fabricating engineered growth substrates for high-quality group III nitride semiconductors using a hot self-split process.

[0001] The present invention (Disclosure) relates to a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, which not only improves and stabilizes the physical properties of a device manufactured using an engineered growth substrate, but also significantly improves economic efficiency by reducing the loss of a seed substrate and the defect rate during the manufacturing process.

[0002] Conventional substrates for growing Group 3 Nitride Semiconductors use single material substrates.

[0003] Conventional single-material growth substrates have the problem of not being able to satisfy both quality and cost requirements, such as crystal defect density, surface polarity, device structure laminate thickness, and heat dissipation performance.

[0004] To address this, an engineered growth substrate having a composite laminate structure is being introduced as an improved growth substrate for group III nitride semiconductor growth.

[0005] However, for engineered growth substrates with such composite laminate structures, securing two key manufacturing technologies is essential.

[0006] Wafer slicing technology is used to secure a seed region, which is a part of a growth substrate, from a growth substrate in a thin substrate size, and wafer bonding technology is used to bond the seed region and the support substrate with high bonding homogeneity.

[0007] Wafer slicing technology includes methods that utilize physical cutting means such as wire saws, and methods that utilize ion implants or lasers.

[0008] However, these methods take a long time and have the problem that the seed area is broken by the separation force during the slicing process.

[0009] Wafer bonding technology has a very difficult problem in satisfying uniform bonding characteristics over the entire area facing the support substrate without damage or cracks during the wafer bonding process.

[0010] In conclusion, an optimized manufacturing process for an engineered growth substrate having a composite laminate structure for a group III nitride semiconductor growth substrate that satisfies its structural-functional characteristics and industrial characteristics has not yet been introduced, which is acting as an obstacle to the increase in the price of high-quality group III nitride semiconductors and the technological development of related industries.

[0011] The present invention (Disclosure) aims at providing a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process that can improve the characteristics and economic efficiency of a device to be manufactured.

[0012] An embodiment of the present invention provides a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, the method comprising: a seed substrate preparation step of preparing a seed substrate on which an epi layer for forming a predetermined element is to be grown; a seed substrate reforming step of irradiating the seed substrate with a stealth laser to form a reforming layer inside the seed substrate; a wafer bonding step of wafer-bonding the seed substrate and a support substrate using a predetermined wafer bonding layer; a hot self-split step of separating the seed substrates on both sides centered on the reforming layer without an external force by thermal stress or mechanical stress formed in the reforming layer, since each of the seed substrates has a quantitative difference in thermal characteristics including a thermal expansion coefficient or structural asymmetry; and a planarization step of planarizing two opposing surfaces of a seed region formed by separating the seed substrate with the seed substrate and the reforming layer as a boundary.

[0013] An embodiment of the present invention provides that, in the hot self-split step, during the process in which the heat supplied in the wafer bonding step is cooled, the seed substrates on both sides centered on the modified layer are separated without an external force due to a quantitative difference in thermal characteristics including a thermal expansion coefficient or structural asymmetry including a thickness difference.

[0014] In an embodiment of the present invention, the seed substrate is provided as a 4H-SiC material.

[0015] An embodiment of the present invention provides that one of the upper and lower surfaces of the seed substrate, the bonding surface facing the support substrate and bonded to the wafer via the wafer bonding layer, is a C-polar face crystal surface, and the exposed surface of the seed region is a Si-polar face crystal surface.

[0016] An embodiment of the present invention may further include, between the seed substrate modification step and the wafer bonding step, a bonding layer forming step of forming the wafer bonding layer on each of the surface of the support substrate and the bonding surface of the seed substrate; a bonding layer surface polishing step of performing surface polishing to reduce surface roughness of the wafer bonding layer provided in the bonding layer forming step; and a bonding layer surface treatment step of performing a predetermined surface treatment to increase surface energy of the wafer bonding layer provided in the bonding layer surface polishing step.

[0017] An embodiment of the present invention may further include, after the seed substrate modification step is performed, a split heat treatment step of heating the wafer-bonded seed substrate and the support substrate at a predetermined split heating temperature and then cooling them at a split cooling temperature.

[0018] In an embodiment of the present invention, the split heating temperature may be higher than the temperature at which the wafer bonding step is performed.

[0019] An embodiment of the present invention comprises: a seed substrate preparation step of preparing a seed substrate on which an epi layer for forming a predetermined element is to be grown; a seed substrate reforming step of irradiating the seed substrate with a stealth laser to form a reforming layer inside the seed substrate; a temporary substrate bonding step of bonding the seed substrate and a temporary substrate with a predetermined adhesive layer before or after the seed substrate reforming step; a hot self-split step in which the seed substrates on both sides centered on the reforming layer are separated without an external force due to a structural asymmetry including a quantitative difference in thermal characteristics including a thermal expansion coefficient or a thickness difference; a planarization step of planarizing two opposing surfaces of a seed region formed by separating the seed substrate with the seed substrate and the reforming layer as a boundary; and a wafer bonding step in which the seed region and the support substrate are wafer-bonded with a predetermined wafer bonding layer. A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process is provided, including a temporary substrate removal step of removing the temporary substrate to separate the seed region.

[0020] An embodiment of the present invention provides that, in the process of cooling the heat supplied in the temporary substrate bonding step, the seed substrates on both sides centered on the modified layer are separated without an external force due to a quantitative difference in thermal characteristics including a thermal expansion coefficient or structural asymmetry including a thickness difference.

[0021] In an embodiment of the present invention, the temporary substrate and the support substrate may have thermal characteristics including an effective thermal expansion coefficient and an effective thermal conductivity that are similar or identical to each other.

[0022] According to the present invention, by using a wafer bonding process and a hot self-split technology, it is easy to separate and process a thin seed region from a seed substrate, and by ensuring that the formed seed region has excellent physical properties, it is possible to manufacture an engineered growth substrate capable of forming a predetermined element that can secure characteristics and economic feasibility.

[0023] FIGS. 1 to 6 are drawings showing one embodiment of a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process according to the present invention.

[0024] FIGS. 7 to 13 are drawings showing another embodiment of a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process according to the present invention.

[0025] Hereinafter, an embodiment of a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process according to the present invention will be described in detail with reference to the drawings.

[0026] However, the essential technical idea of ​​the present invention is not limited in its possible implementation by the embodiments described below, and it is disclosed that the scope encompasses a range that can be easily proposed by a person skilled in the art by replacing or changing the embodiments described below based on the essential technical idea of ​​the present invention.

[0027] In addition, the terms used below have been selected for convenience of explanation, and therefore, in understanding the essential technical idea of ​​the present invention, they should be appropriately interpreted in a meaning that is consistent with the technical idea of ​​the present invention, without being limited to the dictionary meaning.

[0028] FIGS. 1 to 6 are drawings showing one embodiment of a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process according to the present invention.

[0029] Referring to FIGS. 1 to 6, a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process according to the present embodiment includes a seed substrate preparation step (S100), a seed substrate modification step (S200), a wafer bonding step (S300), a hot self-split step (S400), a planarization step (S500), and a growth substrate preparation step (S600).

[0030] The seed substrate preparation step (100) prepares a seed substrate (100) on which an epi layer for forming a predetermined device will be grown.

[0031] The given device may be any one of various group III nitride semiconductor devices, such as GaN HEMT, AlN BAW Filter, AlN Resonating Sensors, and microLED.

[0032] In the seed substrate reforming step (S200), a stealth laser (L) is irradiated onto the seed substrate (100) to form a reforming layer (110) inside the seed substrate (100).

[0033] The stealth laser (L) is a laser (Laser, Light Amplification by Stimulated Emission of Radiation) of a wavelength that can penetrate the seed substrate (100), and is an optical system configured to form a focal point at a specific point inside the seed substrate (100) using a separate optical system.

[0034] When the focal point where the photons of the stealth laser (L) are concentrated moves along a specific plane to form a scanning plane, a modified layer (110) is formed along the scanning plane.

[0035] Since the modified layer (110) secures a seed area with a thin substrate size, it is formed as a surface parallel to the upper surface of the seed substrate (100).

[0036] The wafer bonding step (S300) bonds the seed substrate (100) and the support substrate (220) via a predetermined wafer bonding layer (210).

[0037] The wafer bonding layer (210) is made of SiO2, SiN x , SOG (Spin-on-Glass), SiO2, SiN x , SOG (Spin-on-Glass), AlN, Al2O3 dielectric ceramic bonding material, and it is preferable that the surfaces of each of the seed substrate (100) and the support substrate (220) and the surface of the bonding layer (210) be performed by a permanent bonding process in which they are irreversibly and permanently bonded.

[0038] This allows the bonding characteristics to be maintained even when a high-temperature heating process that may be involved in a subsequent process is performed, allowing a wide range of process conditions to be applied in the epi-device-package process.

[0039] It is preferable that the wafer bonding step (S300) be performed at a bonding temperature of 250°C or higher.

[0040] Meanwhile, the wafer bonding layer (210) can be surface-treated with plasma or solution on the surface of the seed substrate (100) and the support substrate (220), and then a pre-bonding process can be performed first at room temperature.

[0041] As a heat treatment step to strengthen bonding strength after performing the pre-bonding process, a maximum temperature of 1,200°C is desirable.

[0042] In addition, the wafer bonding step (S300) may further include a step of removing bubble gas components such as OH and H2 within the dielectric ceramic bonding material described above.

[0043] The support substrate (220) is made of Si, SiC, AlN ceramic, or SiC ceramic materials.

[0044] In the hot self-split step (S400), the seed substrates (100) on both sides centered on the modified layer (110), that is, the seed region (120) on the upper side of the modified layer (110) of FIG. 3 and the seed substrate (100a) on the lower side of the modified layer (110) excluding the seed region (120), each have structural asymmetry including a quantitative difference in thermal characteristics including a thermal expansion coefficient or a thickness difference, thereby generating thermal stress or mechanical stress in the modified layer (110), and as a result, the seed region (120) and the seed substrate (100a) on the lower side of the modified layer (110) excluding the seed region (120) are separated without a mechanical external force.

[0045] Thermal stress or mechanical stress occurs during the cooling process of the heat supplied for bonding temperature during the wafer bonding step.

[0046] Structural asymmetry including quantitative differences in thermal properties including thermal expansion coefficient or thickness differences occurs on both sides of the modified layer (110).

[0047] Specifically, the seed region (120) on the upper side of the modified layer (110) has a wafer bonding layer (210) bonded thereto, and a support substrate (220) bonded thereto. On the other hand, the lower side of the modified layer (110) has a thickness that is thinner than the seed region (120) thickness of the seed substrate (100) before the formation of the modified layer (110).

[0048] The effective thermal expansion coefficient and effective thermal conductivity that can be applied to the actual physical interaction between the seed region (120) and the seed substrate (100a) with the modified layer (110) as the boundary are different from each other due to the thickness, the structure in which other materials are permanently bonded, and the properties of other materials bonded.

[0049] This is a factor that causes the degree of thermal expansion of each of the seed area (120) and the seed substrate (100a) to differ, and as a result, mechanical stress is generated in the modified layer (110) between the seed area (120) and the seed substrate (100a).

[0050] Therefore, the seed region (120) and the seed substrate (100a) act as a factor in ‘separating without external force’ centered on the modified layer (110).

[0051] The flattening step (S500) flattens two opposing surfaces of the seed substrate (100a) and the seed region (120) formed by separating from the seed substrate (100) with the modified layer (110) as the boundary.

[0052] In this way, an engineered growth substrate (200) including a support substrate (220), a seed region (120) on the upper side of the support substrate (220), and a wafer bonding layer (210) between the seed region (120) and the support substrate (220) is manufactured (S600).

[0053] Meanwhile, after the flattening step (S500) is performed, the seed region (120) is separated, and the remaining seed substrate (100a) can be repeatedly manufactured into an engineered growth substrate (200) by repeating all of the aforementioned steps (S100 to S500). This ensures the economic feasibility of the seed substrate.

[0054] In addition, since the seed region (120) is supported by wafer bonding to the support substrate (220), the physical properties of the device are improved and stabilized in subsequent epitaxial growth and device manufacturing processes. In addition, the ease of wafer and device processing can be maximized.

[0055] In this embodiment, the seed substrate (100) and the support substrate (220) are wafer bonded in a thick film form, so that stable bonding characteristics can be secured. Since the seed region (120) is already stably bonded to the support substrate (220) before being separated from the seed substrate (100), there is an advantage in that handling of the thin seed region (120) is very easy.

[0056] In addition, since the seed region (120) is completely separated from the seed substrate (100) while firmly bonded to the support substrate (220), the probability of occurrence of defects such as micro cracks that are very difficult to inspect and detect, as well as breakage during the separation process, can be greatly reduced.

[0057] Accordingly, the present embodiment is a technology for stably securing an engineered growth substrate having a composite laminate structure, and since a thick support substrate (220) is firmly bonded to a structure in which a thin but wide seed region (120) can be secured without damage, it can provide stable and excellent workability in the later process including the planarization and device manufacturing process, and further has the advantage of being able to secure a high yield.

[0058] Meanwhile, as a technology for securing a seed area (120), a technology using ion implant can be cited as an example.

[0059] Ion implant technology is based on accelerating hydrogen ions so that they can penetrate the target substrate surface and be embedded at a specific depth.

[0060] Therefore, ion implant technology has the problem of significantly damaging the film quality of the seed substrate along the path of hydrogen ions. In other words, the surface and interior of the seed substrate along the hydrogen ion path are inevitably damaged by hydrogen ions (implant damage), and to repair this damage, a separate high-temperature annealing process is required. This not only increases manufacturing costs but also leads to longer lead times due to the additional process.

[0061] Furthermore, the depth at which hydrogen ions penetrate varies depending on the applied energy and the energy lost from collisions with the surface. Consequently, securing a seed area of ​​uniform quality is difficult.

[0062] In this embodiment, the seed substrate (100) is preferably made of 4H-SiC.

[0063] The 4H-SiC structure with a hexagonal-Wurtzite structure is most suitable as a seed for group III nitride (GaN, AlGaN, AlN, AlGaInN) epitaxial growth.

[0064] The cubic structure of 3C-SiC material has a smaller band gap energy (Eg) than 4H-SiC and 6H-SiC materials, and in particular, its lattice constant is excessively large compared to that of group III nitrides, making it unsuitable as a seed substrate for group III nitride growth. Furthermore, 3C-SiC has low thermal conductivity, making it particularly unsuitable for power semiconductor devices.

[0065] Meanwhile, the ion implant technology has a problem in that it is not easy to form 4H-SiC as a seed substrate (100) or seed area (120).

[0066] Ion implant technology accelerates random ionized atoms and projects them onto a substrate, in this case the SiC substrate surface, and causes them to dig into the SiC substrate surface to a specific depth depending on the kinetic energy of the acceleration.

[0067] At this time, serious damage (implant damage) occurs in the SiC substrate corresponding to the depth that the ion atoms penetrate from the surface where the ion atoms are projected, and a high-temperature heat treatment process is essential to recover this.

[0068] However, in the case of SiC, which has a diverse crystal structure, the high-temperature heat treatment process cannot rule out the possibility of a side effect called polytype conversion.

[0069] That is, after applying the ion implant process to the seed substrate (100) of 4H-SiC and forming the seed region (120), the remaining seed substrate (100) must be heat treated, and there is a possibility that a part of the seed substrate (100) will be converted from a 4H crystal structure to a 3C crystal structure.

[0070] In particular, it can be said that the seed substrate (100) with implant damage caused by ion implantation has a higher possibility of polytype conversion compared to a 4H-SiC substrate without implant damage.

[0071] In order to exclude the possibility of polytype conversion, it is clear that the process difficulty increases because the heat treatment temperature for minimizing implant damage and recovering it must be closely compared with the polytype conversion temperature.

[0072] In contrast, in the present embodiment, since no damage occurs anywhere in the seed substrate (100) other than the modified layer (110) during the process of forming the modified layer (110) on the seed substrate (100), a separate annealing process that could cause concern about polytype conversion is unnecessary.

[0073] The fact that damage such as implant damage does not occur also provides the advantage that multiple seed regions (120) separated from one seed substrate (100) can maintain the same characteristics.

[0074] Meanwhile, in the present embodiment, it is more preferable that the bonding surface of the seed substrate (100) facing the support substrate (220) and bonded to the wafer via the wafer bonding layer (210) is a C-polar face crystal surface, and the exposed surface of the seed region (120) is formed as a Si-polar face crystal surface.

[0075] By this, the surface of the group III nitride (GaN, AlGaN, AlN, AlGaInN) grown based on the seed region (120) can be made into a Ga (or Al)-polar face, i.e., a metal-polarity surface.

[0076] The surface of the group III nitride (GaN, AlGaN, AlN, AlGaInN) region finished with the Ga (or Al)-polar face is thermally stable and, in particular, is chemically stable because it has significantly lower reactivity with hydroxide ion functional groups than the nitrogen (N)-polar face crystal plane.

[0077] Meanwhile, in the present embodiment, a bonding layer forming step (S210), a bonding layer surface polishing step (S220), and a bonding layer surface treatment step (S230) may be further included between the seed substrate modification step (S200) and the wafer bonding step (S300).

[0078] The bonding layer forming step (S210) forms a wafer bonding layer (210) on each of the surface of the support substrate (220) and the bonding surface of the seed substrate (100).

[0079] The bonding layer surface polishing step (S220) performs mechanical or chemical-mechanical surface polishing (Mechanical Polishing, or Chemical Mechanical Polishing) to reduce the surface roughness of the wafer bonding layer (210) provided in the bonding layer forming step (S210).

[0080] The bonding layer surface treatment step (S230) performs a predetermined surface treatment to increase the surface energy of the wafer bonding layer (210) provided in the bonding layer surface polishing step (S220).

[0081] Surface energy, which is proportional to the number of dangling bonds, can vary depending on the crystal planes exposed on the surface. Therefore, surface energy can be maximized through appropriate polishing of the surface and a specific surface treatment that allows for the exposure of specific crystal planes.

[0082] Accordingly, the wafer bonding layer (210) in which the bonding layer forming step (S210), the bonding layer surface polishing step (S220), and the bonding layer surface treatment step (S230) are performed has a higher bonding strength between the wafer bonding layers (210) formed on the surface of the support substrate (220) and the bonding surface of the seed substrate (100), respectively, due to the increased surface energy.

[0083] Meanwhile, in order to increase the surface energy and enhance the bonding strength between the wafer bonding layers as described above, the bonding surface surface treatment step (S230) may further perform an additional surface heat treatment process, and at this time, the surface heat treatment process is preferably performed at 250°C or higher.

[0084] Surface treatment can be performed using plasma or solution and at room temperature or higher.

[0085] Additionally, after surface treatment, the bonding strength can be increased by performing a pre-bonding process at room temperature (room temperature ~ 25℃).

[0086] Meanwhile, the present embodiment may further include a split heat treatment step after the seed substrate modification step (S200) is performed.

[0087] The split heat treatment step heats the wafer-bonded seed substrate (100) and support substrate (220) to a predetermined split heating temperature and then cools them to a split cooling temperature.

[0088] In this embodiment, the wafer bonding step (S300) is necessarily performed while maintaining a predetermined bonding temperature. Therefore, the thermal energy required for 'separation without external force' is supplied at the bonding temperature maintained in the wafer bonding step (S300).

[0089] Separation without external force occurs during the cooling process from the bonding temperature.

[0090] The split heat treatment step is to address the possibility that the bonding temperature may not provide sufficient energy to separate the seed substrate (100) and the seed region (120) without external force.

[0091] After the wafer bonding step (S300) is performed, a split heat treatment step of reheating and cooling the bonded seed substrate (100) and support substrate (220) may be further performed to ensure smooth performance of the hot self-split step.

[0092] It is preferable that the split heating temperature be higher than the temperature at which the wafer bonding step (S300) is performed.

[0093] Because the wafer bonding layer (210), the support substrate (220), and the seed substrate (100) are already fusion-bonded through an irreversible reaction, they are not separated even if reheated above the bonding temperature.

[0094] On the other hand, since the seed region (120) is not separated in the hot self-split step even after being heated to the bonding temperature in the wafer bonding step (S300), it is preferable to set the split heating temperature higher than the bonding temperature.

[0095] FIGS. 7 to 13 are drawings showing another embodiment of a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process according to the present invention.

[0096] This embodiment includes a seed substrate preparation step (S1100), a seed substrate modification step (S1200), a temporary substrate adhesion step (S1300), a hot self-split step (S1400), a planarization step (S1500), a wafer bonding step (S1600), and a temporary substrate removal and growth substrate preparation step (S1700).

[0097] The seed substrate preparation step (S110) prepares a seed substrate (1100) on which an epi layer for element formation will be grown.

[0098] The device may be any one of a variety of group III nitride semiconductor devices, such as GaN HEMTs, AlN BAW Filters, AlN Resonating Sensors, and microLEDs.

[0099] The seed substrate reforming step (S1200) forms a reforming layer (1110) inside the seed substrate by irradiating the seed substrate (1100) with a stealth laser (L).

[0100] The temporary substrate bonding step (S1300) is performed after the seed substrate modification step (S1200) is performed, by bonding the seed substrate (S1100) and the temporary substrate (1300) via a predetermined adhesive layer (1200).

[0101] In the hot self-split step (S1400), the seed substrates (1100a, 1120) on both sides centered on the modified layer (1110) are separated without external force due to structural asymmetry including quantitative differences in thermal characteristics including thermal expansion coefficient or thickness differences.

[0102] In the hot self-split step (S1400), during the process of cooling the heat supplied in the temporary substrate bonding step (S1300), the two sides centered on the modified layer (1110) are separated without external force due to a structural asymmetry including a quantitative difference in thermal characteristics including a thermal expansion coefficient or a difference in thickness.

[0103] The flattening step (S1500) flattens two opposing surfaces of the seed region (1120) formed by separating the seed substrate (1100a) and the modified layer (1110) from the seed substrate (1100a).

[0104] The wafer bonding step (S1600) bonds (attaches) the seed area (1120) and the support substrate (2100) on the opposite side of the temporary substrate with respect to the seed area (1120) as the medium through the wafer bonding layer (1130).

[0105] Finally, the temporary substrate (1300) is removed to separate the seed region (1120), and an engineered growth substrate (2000) including a support substrate (2100), a seed region (1120) on the upper side of the support substrate (2100), and a wafer bonding layer (1130) between the seed region (1120) and the support substrate (2100) is manufactured (S1700).

[0106] In this embodiment, an engineered growth substrate (2000) is formed after performing two wafer bonding (bonding: adhesion, joining) processes.

[0107] The two-step wafer bonding process is a process for forming an engineered growth substrate (2000) in which the exposed surface of the seed region (1120) becomes a Si-polar face, using a seed substrate (1100) whose surface is formed as a Si-polar face.

[0108] In this embodiment, it is preferable that the temporary substrate (1300) be selected to have thermal characteristics similar to or identical to those of the support substrate (2100), including the effective thermal expansion coefficient and effective thermal conductivity.

[0109] In addition, it is preferable that the crystal structures of each of the temporary substrate (1300) and the support substrate (2100) both have a single crystal structure.

[0110] This is intended to secure normal and excellent bonding characteristics between the support substrate (2100) and the seed region (1120) in the wafer bonding step (S1600).

[0111] Referring to FIG. 11, when the wafer bonding step (S1600) is performed, the temporary substrate (1300) and the seed region (1120) are already bonded via a predetermined adhesive layer.

[0112] Therefore, among the factors affecting the actual thermal characteristics including the thermal expansion coefficient of the seed region (1120), the thermal characteristics according to the properties of the temporary substrate (1300) are a dominant factor rather than the thermal characteristics according to the properties of the seed region (1120) itself.

[0113] That is, as can be seen in FIG. 11, the wafer bonding step (S1600) according to the present embodiment can be analyzed as a bonding process between a temporary substrate (1300) that can be approximated to the temporary substrate (1300) in terms of thermal characteristics and a structure in which a seed region (1120) is bonded and a support substrate (2100).

[0114] One of the typical process conditions for a typical wafer bonding process is to heat the substrate and bonding layer to be bonded to a predetermined temperature.

[0115] Therefore, if there is a large difference between the thermal characteristics of the temporary substrate (1300) and the support substrate (2100), a difference in the shrinkage characteristics of the interface between the support substrate (2100) and the seed region (1120) occurs during the bonding process, and thus, stable bonding characteristics cannot be expected.

[0116] In particular, the temporary substrate (1200) and the seed region (1120) have strong adhesive force via a predetermined bonding layer (1200).

[0117] In addition, the bonding layer (1200) that strongly bonds the temporary substrate (1200) and the seed region (1120) is a reversible and temporary wafer bonding layer (1200), unlike the wafer bonding layer (1130), and is preferably made of organic materials (polymers) such as resin, epoxy, SU-8, BCB, etc. that can easily remove and separate the temporary substrate (1200) in a subsequent process (S1700), and metal materials such as Sn, In, Zn, Ga, Au, Ni, Ag, Cu, etc., but in some cases, SiO2, SiN x , SOG (Spin-on-Glass), AlN, Al2O3, ITO, GaN, InGaN, AlGaN, AlGaInN, ZnO, ZITO, and other dielectric ceramic materials are also possible.

[0118] However, the wafer bonding process between the support substrate (2100) and the seed region (1120) is SiO2, SiN x , SOG (Spin-on-Glass), AlN, Al2O3, etc., because wafer bonding is performed using dielectric ceramic materials, it is desirable to have a smooth surface with a surface roughness of less than 1 nm before bonding, and furthermore, maintaining a state in which surface treatment such as plasma or solution that increases surface energy has been performed is one of the most important factors in obtaining excellent bonding characteristics.

Claims

1. A seed substrate preparation step for preparing a seed substrate on which an epi layer for forming a predetermined element is to be grown; A seed substrate reforming step of forming a reforming layer inside the seed substrate by irradiating the seed substrate with a stealth laser; A wafer bonding step of bonding the seed substrate and the support substrate using a predetermined wafer bonding layer; A hot self-split step in which the seed substrates on both sides centered on the modified layer are separated without external force by thermal stress or mechanical stress formed in the modified layer, since each of the seed substrates on both sides has a quantitative difference in thermal characteristics including thermal expansion coefficient or structural asymmetry; and A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, comprising: a planarization step of planarizing two opposing surfaces of a seed region formed by separating the seed substrate from the seed substrate with the modified layer as the boundary; 2. In claim 1, The hot self-split step is a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, wherein, during the process in which the heat supplied in the wafer bonding step is cooled, the seed substrates on both sides centered on the modified layer are separated without an external force due to a quantitative difference in thermal characteristics including a thermal expansion coefficient or a structural asymmetry including a thickness difference.

3. In claim 1, The above seed substrate is a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor using a hot self-split process, which is a 4H-SiC material.

4. In claim 1, One of the upper and lower surfaces of the seed substrate, and the bonding surface facing the support substrate and bonded to the wafer via the wafer bonding layer is a C-polar face crystal plane, A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, wherein the exposed surface of the above seed region is a crystal plane of the Si-polar face.

5. In claim 1, Between the seed substrate modification step and the wafer bonding step, A bonding layer forming step of forming the wafer bonding layer on each of the surface of the support substrate and the bonding surface of the seed substrate; A bonding layer surface polishing step for performing surface polishing to reduce the surface roughness of the wafer bonding layer provided in the bonding layer forming step; A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, further comprising a bonding layer surface treatment step of performing a predetermined surface treatment to increase the surface energy of the wafer bonding layer provided in the bonding layer surface polishing step.

6. In claim 1, After the above seed substrate modification step is performed, A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, further comprising a split heat treatment step of heating the wafer-bonded seed substrate and the support substrate at a split heating temperature higher than the temperature at which the wafer bonding step is performed and then cooling them at a split cooling temperature.

7. A seed substrate preparation step for preparing a seed substrate on which an epi layer for forming a predetermined element will be grown; A seed substrate reforming step of forming a reforming layer inside the seed substrate by irradiating the seed substrate with a stealth laser; A temporary substrate bonding step of bonding the seed substrate and the temporary substrate using a predetermined adhesive layer before or after the seed substrate modification step; A hot self-split step in which the seed substrates on both sides centered on the modified layer are separated without external force due to a quantitative difference in thermal characteristics including a thermal expansion coefficient or structural asymmetry including a thickness difference; A planarization step of planarizing two opposing surfaces of a seed region formed by separating the seed substrate from the seed substrate and the modified layer; and A wafer bonding step of bonding the seed region and the support substrate to a wafer using a predetermined wafer bonding layer; A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, comprising a temporary substrate removal step of removing the temporary substrate to separate the seed region.

8. In claim 7, The hot self-split step is a method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, wherein, during the process in which the heat supplied in the temporary substrate bonding step is cooled, the seed substrates on both sides centered on the modified layer are separated without an external force due to a quantitative difference in thermal characteristics including a thermal expansion coefficient or a structural asymmetry including a thickness difference.

9. In claim 7, A method for manufacturing an engineered growth substrate for a high-quality group III nitride semiconductor through a hot self-split process, wherein the temporary substrate and the support substrate have similar or identical thermal characteristics, including an effective thermal expansion coefficient and an effective thermal conductivity.

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