Transformerless pulsed bias voltage generator with damper

Abstract

A system including a pulsed bias voltage generator is described. The pulsed bias voltage generator includes a pulsed current source that increases a voltage during a charging process to create a pulse of a non-sinusoidal radio frequency (RF) signal. The pulsed bias voltage generator includes a pulsed current sink coupled to the pulsed current source. The pulsed current sink decreases the voltage to create the pulse of the non-sinusoidal RF signal. The pulsed current source repeats the increase in the voltage and the pulsed current sink repeats the decrease in the voltage to generate additional pulses of the non-sinusoidal RF signal. The system includes a damper coupled to the pulsed current sink to modify a voltage step of the pulse.

Description

TRANSFORMERLESS PULSED BIAS VOLTAGE GENERATOR WITH DAMPERFIELD

[0001] The embodiments described in the present disclosure relate to systems and methods for using transformerless pulsed bias voltage generator with damper.BACKGROUND

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In a plasma tool, a radio frequency (RF) generator is coupled to a plasma chamber. A wafer is placed within the plasma chamber. The RF generator supplies an RF signal to the plasma chamber. When process gases are supplied to the plasma chamber, plasma is generated within the plasma chamber and the plasma is used to process the wafer. It is desirable that the wafer is processed in a controlled manner.

[0004] It is in this context that embodiments described in the present disclosure arise.SUMMARY

[0005] Embodiments of the disclosure provide systems and methods for using transformerless pulsed bias voltage generator with damper. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0006] In one embodiment, a method and apparatus for generating pulsed voltage of a particular shape to bias a wafer and an edge ring of an etch tool. For example, instead of applying, in an etch tool, a sinusoidal voltage at 400 kilohertz (kHz) in frequency and up to several kilovolts in amplitude, a pulsed bias voltage is applied for better power efficiency, higher ion energy, and better control of ion energy distribution. Several factors for a system that provides the pulsed bias voltage include fast rise and fall times of a bias pulse, high power conversion efficiency, and an ability to freely adjust a pulse repetition frequency, a high-voltage to low-voltage phase duty ratio, a pulse amplitude, and a slope.

[0007] The systems and methods, described herein, achieve the factors by resonantly charging and discharging a plasma load, such as a plasma chamber. A bias voltage generator,such as a pulser, produces an inductor capacitor (LC) series resonance between an inductor and the plasma chamber, which usually presents capacitive impedance, and creates a rapid voltage upswing and downswing in an energy efficient manner. The bias voltage generator does not need any transformer, such as a step-up transformer, is smaller in size, simpler in hardware, and lower in build cost than one in which the transformer is used.

[0008] One approach to generate multi-kilovolt pulses is to use the step-up transformer. The approach has several downsides that make it unsuitable for etch applications. First, the step- up transformer is prone to have a large leakage inductance which slows down a pulse transition, hindering a pulsed device’s ability to meet rise and fall time specifications. Second, the transformer processes many kilowatts of power, if not tens of kilowatts. To process the many kilowatts of power, a large amount of magnetic material is used to build the transformer. As a result, the transformer is often bulky, expensive, difficult to source, heavy, and difficult to cool. Last, the step-up transformer is designed to prevent breakdown between its primary and secondary windings under the presence of a high voltage stress, which is provided by a full pulse voltage. The high voltage stress often degrades a long-term reliability, and an associated insulating material specification increases a volume and a build cost of the pulser.

[0009] In an embodiment, the bias voltage generator is free of any high-voltage transformer. For example, the bias voltage generator includes a pulsed current source and a pulsed current sink, each of which includes a switch, a diode, and an inductor. As another example, each of the pulsed current source and the pulsed current sink includes the switch, the diode, the inductor, and a capacitor. The switch, the diode, conductor, and a capacitor are small, low-cost, easy to assemble, and easy to manufacture compared to the transformer. The plasma chamber subject to a bias voltage generated by the bias voltage generator exhibits capacitive impedance, so the plasma chamber in series with the inductor forms an LC series resonant tank. When the switch closes in either the pulsed current source or the pulsed current sink, the LC resonance causes rapid transition in voltage that drives the plasma chamber, and after half of a resonance cycle, the diode turns off to automatically shut off a current path and prevent any backward current flow.

[0010] In an embodiment, two separate resonant inductors of the pulsed current source and the pulsed current sink are combined into one.

[0011] In one embodiment, a DC voltage source is provided within the pulsed current sink instead of within the pulsed current source or DC voltage sources are provided in both the pulsed current source and the pulsed current sink.

[0012] In an embodiment, a high-voltage switch and a the high-voltage diode are provided within the pulsed current source or the pulsed current sink by series-connecting multiple low-voltage switches and series-connecting multiple low-voltage diodes.

[0013] In one embodiment, a modular resonant switch (MRS) is used within the pulsed current source or the pulsed current sink or multiple modular resonant switches are used within the pulsed current source and the pulsed current sink.

[0014] In an embodiment, a constant or a time-varying current source is used to create a downward slope in an output voltage waveform generated at an output of the bias voltage generator.

[0015] In one embodiment, a damper is included within the pulsed current source or the pulsed current sink to expand a lower limit of an amplitude of the output voltage waveform.

[0016] In an embodiment, a system including a pulsed bias voltage generator is described. The pulsed bias voltage generator includes a pulsed current source that increases a voltage during a charging process to create a pulse of a non-sinusoidal radio frequency (RF) signal. The pulsed bias voltage generator includes a pulsed current sink coupled to the pulsed current source. The pulsed current sink decreases the voltage to create the pulse of the non- sinusoidal RF signal. The pulsed current source repeats the increase in the voltage and the pulsed current sink repeats the decrease in the voltage to generate additional pulses of the non- sinusoidal RF signal. The system includes a damper coupled to the pulsed current source to modify a voltage step of the pulse or includes a damper coupled to the pulsed current sink to modify a voltage step of the pulse or includes both the dampers.

[0017] Some advantages of the herein described systems and methods include providing a damper. The damper facilitates achieving a voltage range of operation of the bias voltage generator that is otherwise not achieved in a bias voltage generator without the damper.

[0018] Some other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0020] Figure 1 is a diagram of an embodiment of a system for illustrating a pulsed current source and a pulsed current sink.

[0021] Figure 2A is a diagram of an embodiment of a system to illustrate details of the pulsed current source and the pulsed current sink of Figure 1.

[0022] Figure 2B is an embodiment of a graph to illustrate an operation of the pulsed current source and the pulsed current sink of Figure 1.

[0023] Figure 3 is a diagram of an embodiment of a pulsed bias voltage generator to illustrate that instead of multiple inductors, one inductor is used.

[0024] Figure 4 is a diagram of an embodiment of a pulsed bias voltage generator to illustrate that a direct current (DC) voltage source is a component of a pulsed current sink.

[0025] Figure 5 is a diagram of an embodiment of a pulsed bias voltage generator to illustrate that multiple switches and multiple diodes are included within a pulsed current source or a pulsed current sink or a combination thereof, to modify an amount of a voltage that is applied to a point.

[0026] Figure 6 is a diagram of an embodiment of a pulsed bias voltage generator to illustrate a modular resonance switch.

[0027] Figure 7 is a diagram of an embodiment of a system to illustrate an ion flux compensation (IFC) that is provided by an IFC circuit.

[0028] Figure 8A is a diagram of an embodiment of a resonance damper.

[0029] Figure 8B is a diagram of an embodiment of a resonance damper.

[0030] Figure 8C is an embodiment of the graph to illustrate a non-sinusoidal signal.

[0031] Figure 8D is an embodiment of a graph to illustrate a non-sinusoidal signal.

[0032] Figure 8E is an embodiment of a graph to illustrate that by using the resonance damper of Figure 8 A or 8B, a voltage region of voltage amplitudes is achieved at the point.

[0033] Figure 9 is a diagram of an embodiment of a system to illustrate use of the pulsed current sink with a DC power sink for RF energy recovery and resonance dampening.

[0034] Figure 10A is a diagram of an embodiment of a system to illustrate use of a pulsed current source and the IFC to achieve multilevel pulsing.

[0035] Figure 10B is an embodiment of a multilevel pulse signal to illustrate operation of the system of Figure 10A.

[0036] Figure 11A is a diagram of an embodiment of a system to illustrate multilevel pulsing using an IFC.

[0037] Figure 11B is an embodiment of graphs to illustrate operation of the IFC of Figure 11 A.

[0038] Figure 11C is an embodiment of a multilevel pulse signal to illustrate a fast level -to-level transition of the multilevel pulse signal.

[0039] Figure 1 ID is an embodiment of a multilevel pulse signal to illustrate a slow level -to-level transition of the multilevel pulse signal.DETAILED DESCRIPTION

[0040] The following embodiments describe systems and methods for using a transformerless pulsed bias voltage generator with damper. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0041] Figure 1 is a diagram of an embodiment of a system 100 for illustrating a pulsed current source 102 and a pulsed current sink 104. As an example, the pulsed current source 102 excludes a transformer and the pulsed current sink 104 excludes a transformer. The pulsed current source 102 and the pulsed current sink 104 are components of a pulsed bias voltage generator 101. The system 100 further includes a plasma chamber 106. An example of the plasma chamber 106 is a capacitively coupled plasma (CCP) chamber. The plasma chamber 106 includes an upper electrode 108 and an electrostatic chuck (ESC) 110. The ESC 110 includes a lower electrode. For example, the lower electrode is embedded within the ESC 110. On a top surface of the lower electrode, a substrate SU, such as a semiconductor wafer, is placed for processing.

[0042] The pulsed current source 102 is coupled to the pulsed current sink 104 at a point Pout. The point Pout is coupled via an RF connection 112 to the lower electrode. For example, the point Pout is located on the RF connection 112. To illustrate, the point Pout is located on the RF connection 112 that is coupled to a connector of the pulsed current source 102 and to a connector of the pulsed current sink 104. An example of the RF connection 112 includes one or more RF straps. For example, multiple RF straps are coupled to each other in series to form the RF connection 112. A connector of the pulsed current source 102 is an example of an output of the pulsed current source 102 and a connector of the pulsed current sink 104 is an example of an output of the pulsed current sink 104.

[0043] It should be noted that there is no match, such as, an impedance matching circuit or an impedance matching network or an impedance match, between the point Pout and the lower electrode. For example, the match is not coupled to the pulsed bias voltage generator 101 and the plasma chamber 106. The upper electrode 108 is coupled to a ground potential.

[0044] The pulsed current source 102 generates a current ICH of a non-sinusoidal RF signal 114 during a charging phase and supplies the current ICH via the point Pout and the RF connection 112 to the lower electrode. The charging phase is sometimes referred to herein as a charging process. During the charging phase, a rise portion 116 of the non-sinusoidal RF signal 114 is generated. For example, the rise portion 116 extends from a low voltage level to a highvoltage level, and the high voltage level is greater than the low voltage level. Also, the rise portion 116 has a positive slope of voltage and the positive slope is formed during a transition between the low and high voltage levels.

[0045] During the charging phase, RF energy from the rise portion 116 of the non- sinusoidal signal 114 is supplied to the plasma chamber 106 to process the substrate SU. In addition, one or more process gases, such as an oxygen containing gas, or a fluorine containing gas, or a combination thereof, are supplied to the plasma chamber 106 to process the substrate SU. Examples of processing the substrate SU includes depositing one or more materials on the substrate SU, or, etching the substrate SU, or cleaning the substrate SU, or a combination thereof.

[0046] After the charging phase, a discharging phase is initiated. The discharging phase is sometimes referred to herein as a discharging process. During the discharging phase, some of the RF energy is recovered from the plasma chamber 106 via the RF connection 112 and the point Pout by the pulsed current sink 104. For example, during the discharging phase, a current IDCH of the non-sinusoidal signal 114 flows from the plasma chamber 106 via the RF connection 112 and the point Pout to the pulsed current sink 104. Because of the flow of the current IDCH, a fall portion 118 of the non-sinusoidal RF signal 114 is generated. In this manner, multiple pulses, such as instances, having the rise portion 116 and the fall portion 118 of the non-sinusoidal RF signal 114 are generated to generate the non-sinusoidal RF signal 114. The non-sinusoidal RF signal 114 is supplied from the pulsed bias voltage generator 101 via the point Pout and the RF connection 112 to the lower electrode to process the substrate SU.

[0047] In one embodiment, instead of the CCP chamber, an inductively coupled plasma (ICP) chamber is used.

[0048] Figure 2A is a diagram of an embodiment of a system 200 to illustrate details of the pulsed current source 102 and the pulsed current sink 104 (Figure 1). Figure 2B is an embodiment of a graph 250 to illustrate an operation of the pulsed current source 102 and the pulsed current sink 104. The graph 250 plots voltage on a y-axis and time t on an x-axis. Also, the graph 250 plots current on another y-axis.

[0049] With reference back to Figure 2A, the system 200 includes a pulsed bias voltage generator 201, which includes a pulse current source 202 and a pulsed current sink 204. The pulsed bias voltage generator 201 is an example of the pulsed bias voltage generator 101 (Figure 1). Also, the pulsed current source 202 is an example of the pulsed current source 102 (Figure 1) and the pulsed current sink 204 is an example of the pulsed current sink 104 (Figure 1).

[0050] The system 200 further includes a host computer 206. Examples of the host computer 206 include a controller, a desktop computer, a laptop computer, a tablet, and a smart phone. The host computer 206 includes a processor 208 and a memory device 210. Examples of the processor 208 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 210 include a read-only memory or a random access memory or a combination thereof.

[0051] The pulsed current source 202 includes a direct current (DC) voltage source 212, a switch SW1, a diode DI, and an inductor LI. As an example, a DC voltage source, described herein, includes one or more voltage supplies. In the example, each voltage supply is coupled via a respective switch to an output and the outputs of the voltage supplies are coupled to each other in parallel. An example of a voltage supply is a supply that converts a first DC voltage to a second DC voltage. To illustrate, the second DC voltage is greater than or less than the first DC voltage.

[0052] Also, the pulsed current sink 204 includes a switch SW2, a diode D2, an inductor L2, and a ground connection. The ground connection has a ground potential. An example of a switch is one or more transistors. For example, the multiple transistors that are coupled to each other in series form a switch.

[0053] The pulsed current source 202 has a point PC that is situated between the ground connection and the DC voltage source 212. The pulsed current sink 204 has a point PDC that is between the switch SW2 and the ground connection.

[0054] The processor 208 is coupled to the memory device 210, and to the switches SW1 and SW2. For example, the processor 208 is coupled to the switch SW1 via a connection CN1 and is coupled to the switch SW2 via a connection CN2. The DC voltage source 212 is coupled to the switch SW1, which is coupled in series to the diode DI. For example, the switch SW1 is coupled to an anode of the diode DI. A cathode of the diode DI is coupled in series of the inductor LI. Also, the switch SW2 is coupled to the ground potential of the ground connection at one end and is coupled in series to the diode D2 at an opposite end. For example, the switch SW2 is coupled to a cathode of the diode D2. The diode D2 is coupled in series to the inductor L2. For example, an anode of the diode D2 is coupled to the inductor L2. The inductors LI and L2 are coupled to each other at the point Pout. The processor 208 is also coupled to the DC voltage source 212.

[0055] With reference to Figures 2 A and 2B, during a first subphase, illustrated as 1CH, of a cycle n of the charging phase, both the switches SW1 and SW2 are open, where n is a positive integer. For example, the processor 208 sends an on control signal to the switch SW1via the connection CN1 to open the switch SW1 and sends an on control signal to the switch SW2 via the connection CN2 to open the switch SW2. The first sub phase of the charging phase is a negative voltage phase. When both the switches SW1 and SW2 are open, voltage at the point Pout is Vt, which has a first minimum voltage value, such as a first negative voltage value.

[0056] During a second subphase, illustrated as 2CH, of the cycle n of the charging phase, the processor 208 sends an on control signal to the switch SW1 via the connection CN1 to close the switch SW1. The switch SW2 remains open during the charging phase. When the switch SW1 is closed, the current ICH is supplied from the DC voltage source 212 via the switch SW1, the diode DI, the inductor LI, the point Pout, and the RF connection 112 to the plasma chamber 106 (Figure 1). The current ICH increases from zero to a first maximum current value, such as a positive current value, to increase the voltage Vt at the point Pout from the first minimum voltage value to zero and further to a maximum voltage value, such as a positive voltage value. Also, during the second subphase 2CH, the current ICH reaches the first maximum current value and starts decreasing to reach the value of zero. During the second subphase 2CH, the voltage Vt at the point Pout is maintained at the maximum voltage value. Also, during the second subphase 2CH, the diode DI is turned on and allows passage of the current ICH. During the second subphase 2CH, the rise portion 116 of the non-sinusoidal RF signal 114 is generated.

[0057] Also, during a third subphase, illustrated as 3CH, of the cycle n of the charging phase, when the voltage Vt is at the maximum voltage value, the diode DI turns off. After the diode DI turns off, during the third subphase, the processor 208 controls the switch SW1 to open.

[0058] Moreover, during a first subphase, illustrated as 1DCH, of the cycle n of the discharging phase, both the switches SW1 and SW2 are open. The first sub phase of the discharging phase is a positive voltage phase. When both the switches SW1 and SW2 are open, voltage at the point Pout is Vt, which has the maximum voltage value.

[0059] During a second subphase, illustrated as 2DCH, of the cycle n of the discharging phase, the processor 208 sends an on control signal to the switch SW2 via the connection CN2 to close the switch SW2. The switch SW1 remains open during the discharging phase. When the switch SW2 is closed, the current IDCH is transferred from the plasma chamber 106 via the point Pout, the inductor L2, the diode D2, and the switch SW2 to the ground connection. The current IDCH increases from zero to a second maximum current value, such as a positive current value, to decrease the voltage Vt at the point Pout from the maximum voltage value to zero and further to a second minimum voltage value, such as a second negative voltage value. As anexample, the second minimum voltage value is equal to or different from the first minimum voltage value. Also, during the second subphase 2DCH, the current IDCH reaches the maximum current value and starts decreasing to reach the value of zero. During the second subphase 2DCH, the voltage Vt at the point Pout is maintained at the second minimum voltage value. Also, during the second subphase 2DCH, the diode D2 is turned on and allows passage of the current IDCH. During the second subphase 2DCH, the fall portion 118 of the non-sinusoidal RF signal 114 is generated.

[0060] Also, during a third subphase, illustrated as 3DCH, of the cycle n of the discharging phase, when the voltage Vt is at the second minimum voltage value, the diode D2 turns off. After the diode D2 turns off, during the third subphase, the processor 208 controls the switch SW2 to open. In this manner, the charging and discharging phases repeat during another cycle (n+1) of the charging and discharging phases. It should be noted that the cycles n and (n+1) are also cycles of the non-sinusoidal signal 114 (Figure 1) and of a digital clock signal that is generated by the processor 208.

[0061] The processor 208 controls the time at which the switch SW1 is turned on, such as closed, and controls the time at which the switch SW1 is turned off, such as open, to change a duty cycle of a pulse of the non-sinusoidal signal 114. For example, during the cycle n, the processor 208 sends the on control signal to the switch SW 1 at a first cycle time and sends the off control signal to the switch SW1 at a second cycle time. Moreover, during the cycle (n+1), the processor 208 sends the on control signal to the switch SW 1 at a third cycle time and sends the off control signal to the switch SW1 at a fourth cycle time. When a first time difference between the first and second cycle times is less than a second time difference between the third and fourth cycle times, a duty cycle of a pulse of the non-sinusoidal signal 114 during the cycle n is less than a duty cycle of a pulse of the non-sinusoidal signal 114 during the cycle (n+1). On the other hand, in the example, when the first time difference is greater than the second time difference, the duty cycle of the pulse of the non-sinusoidal signal 114 during the cycle n is greater than the duty cycle of the pulse of the non-sinusoidal signal 114 during the cycle (n+1). An example of a pulse of a non-sinusoidal signal is a nanopulse.

[0062] An example of a pulse of a non-sinusoidal signal, described herein, includes a rise portion of the non-sinusoidal signal and a fall portion of the non-sinusoidal signal and a voltage level between the rise and fall portions. For example, a pulse 214 of the non-sinusoidal signal 114 occurring during the cycle n, includes the rise portion 116, the fall portion 118, and a voltage level 216, which provides a transition, such as a substantially horizontal level, from the rise portion 116 to the fall portion 118. To illustrate, the voltage level 216 between the portions116 and 118 include voltage values, within a predetermined range, that are substantially constant to have the substantially horizontal level. To further illustrate, the voltage level 216 between the portions 116 and 118 includes a single voltage value to be constant.

[0063] Moreover, the processor 208 controls the time at which the switch SW1 is turned on during each cycle of the charging and discharging phases to control a frequency of repetition of the charging and discharging phases. For example, during the cycle n, the processor 208 sends the on control signal to the switch SW1 at a first cycle time. Moreover, during the cycle (n+1), the processor 208 sends the on control signal to the switch SW 1 at a second cycle time. When a time difference between the first and second cycle times decreases, the frequency of repetition increases. On the other hand, when the time difference between the first and second cycle times increases, the frequency of repetition decreases.

[0064] Furthermore, the processor 208 controls the DC voltage source 212 to modify an amplitude, such as a maximum amplitude, of voltage of each pulse of the non-sinusoidal voltage signal 114. For example, the processor 208 sends one or more enable signals to the one or more switches coupled to the respective one or more voltage supplies of the DC voltage source 212 to turn on the switches. When the switches are turned on, there is an increase in the voltage at an output of the DC voltage source 212. On the other hand, the processor 208 sends one or more disable signals to the one or more switches coupled to the respective one or more voltage supplies of the DC voltage source 212 to turn off the switches. When the switches are turned off, there is a decrease in the voltage in an output of the DC voltage source 212. As an example, when there is an increase in the voltage level 216 of each pulse of the non-sinusoidal signal 114, another non-sinusoidal signal, such as a non-sinusoidal signal 218 or 220, having a higher voltage level, such as a higher maximum voltage level, is generated at the point Pout.

[0065] Figure 3 is a diagram of an embodiment of a pulsed bias voltage generator 300 to illustrate that instead of the inductors LI and L2 (Figure 2A), one inductor LCOM is used. The pulsed bias voltage generator 300 is an example of the pulsed bias voltage generator 101 (Figure 1).

[0066] The pulsed bias voltage generator 300 includes a pulsed current source 302 and a pulsed current sink 304. The pulsed current source 302 is an example of the pulsed current source 102 (Figure 1) and the pulsed current sink 304 is an example of the pulsed current sink 104 (Figure 1). The DC voltage source 212 is coupled to the ground connection. The pulsed current source 302 has the point PC that is situated between the ground connection and the DC voltage source 212. The pulsed current sink 304 has the point PDC that is between the switch SW2 and the ground connection.

[0067] The pulsed current source 302 has the same structure as that of the pulsed current source 202 (Figure 2A) except that the cathode of the diode DI is coupled to a point 306 and the anode of the diode D2 is coupled to the point 306. The point 306 is coupled via the inductor LCOM to the point Pout.

[0068] Also, an operation, such as functionality, of the pulsed current source 302 is the same as that of the pulsed current source 202 except the current ICH is sent from the diode DI via the point 306. Also, an operation, such as functionality, of the pulsed current sink 304 is the same as that of the pulsed current sink 204 except the current IDCH is received from the point Pout via the inductor LCOM and the point Pout by the diode D2.

[0069] Figure 4 is a diagram of an embodiment of a pulsed bias voltage generator 400 to illustrate that the DC voltage source 212 is a component of a pulsed current sink 404. The pulsed bias voltage generator 400 is an example of the pulsed bias voltage generator 101 (Figure 1).

[0070] The pulsed bias voltage generator 400 includes a pulsed current source 402 and the pulsed current sink 404. The pulsed current source 402 is an example of the pulsed current source 102 (Figure 1) and the pulsed current sink 404 is an example of the pulsed current sink 104 (Figure 1).

[0071] The pulsed bias voltage generator 400 has the same structure as that of the pulsed bias voltage generator 201 (Figure 2A) except that the DC voltage source 212 is coupled between the switch SW2 and the ground connection and the switch SW1 is coupled to the ground connection. For example, the DC voltage source 212 is coupled to the switch SW2 at one end and to the ground connection at an opposite end via the point PDC. Also, in the example, the switch SW1 is coupled via the point PC to the ground connection at one end and to the anode of the diode DI at an opposite end. The pulsed current source 402 has the point PC that is situated between the ground connection and the switch SW1. The pulsed current sink 404 has the point PDC that is between the DC voltage source 212 and the ground connection.

[0072] Figure 5 is a diagram of an embodiment of a pulsed bias voltage generator 500 to illustrate that multiple switches and multiple diodes are included within a pulsed current source 502 or a pulsed current sink 504 or a combination thereof, to modify an amount of the voltage Vt that is applied to the point Pout. The pulsed bias voltage generator 500 is an example of the pulsed bias voltage generator 101 (Figure 1). The pulsed current source 502 is an example of the pulsed current source 102 (Figure 1) and the pulsed current sink 504 is an example of the pulsed current sink 104 (Figure 1).

[0073] The pulsed current source 502 has the same structure as that of the pulsed current source 202 (Figure 2A) except that instead of the diode DI, multiple diodes DI a, Dlb, and Die are included and instead of the switch SW1, multiple switches SWla, SWlb, and SWlc are included. Also, the pulsed current sink 504 has the same structure as that of the pulsed current source 204 (Figure 2A) except that instead of the diode D2, multiple diodes D2a, D2b, and D2c are included and instead of the switch SW2, multiple switches SW2a, SW2b, and SW2c are included. As an example, each switch SWla, SWlb, SWlc, SW2a, SW2b, and SW2c is a field effect transistor (FET).

[0074] The pulsed current source 502 has the point PC that is situated between the ground connection and the DC voltage source 212. The pulsed current sink 504 has the point PDC that is between the switch SW2a and the ground connection.

[0075] The inductor LI is coupled to an anode of the diode Dla. A cathode of the diode Dla is coupled to an anode of the diode Dlb and a cathode of the diode Dlb is coupled to an anode of the diode Die. A cathode of the diode Die is coupled to a source terminal (S) of the switch SWla. A drain terminal (D) of the switch SWla is coupled to a source terminal of the switch SWlb and a drain terminal (D) of the switch SWlb is coupled to a source terminal (S) of the switch SWlc. A drain terminal (D) of the switch SWlc is coupled to the point Pout.

[0076] Also, the inductor L2 is coupled to an anode of the diode D2c. A cathode of the diode D2c is coupled to an anode of the diode D2b and a cathode of the diode D2b is coupled to an anode of the diode D2a. A cathode of the diode D2a is coupled to a drain terminal (D) of the switch SW2c. A source terminal (S) of the switch SW2c is coupled to a drain terminal (D) of the switch SW2b and a source terminal (S) of the switch SW2b is coupled to a drain (D) terminal of the switch SW2a. A source terminal of the switch SW2a is coupled to the point PDC, which is coupled to the ground connection.

[0077] The processor 208 is coupled to the switches SWla, SWlb, SWlc, SW2a, SW2b, and SW2c. The processor 208 controls the switches SWla, SWlb, and SWlc to close, such as turn on, or open, such as turn off, in the same manner in which the processor 208 controls the switch SW1. For example, during the charging phase, the processor 208 simultaneously sends on control signals to the switches SWla, SWlb, and SWlc to turn on the switches SWla, SWlb, and SWlc simultaneously. Also, in the example, the processor 208 simultaneously sends off control signals to the switches SWla, SWlb, and SWlc to turn off the switches SWla, SWlb, and SWlc simultaneously. Moreover, in the example, the diodes Dla, Dlb, and Die function in the same manner as that of the diode DI during the charging phase.

[0078] Also, the processor 208 controls the switches SW2a, SW2b, and SW2c to close, such as turn on, or open, such as turn off, in the same manner in which the processor controls the switch SW2. For example, during the discharging phase, the processor 208 simultaneously sends on control signals to the switches SW2a, SW2b, and SW2c to turn on the switches SW2a, SW2b, and SW2c simultaneously. Also, in the example, the processor 208 simultaneously sends off control signals to the switches SW2a, SW2b, and SW2c to turn off the switches SW2a, SW2b, and SW2c simultaneously. Moreover, in the example, the diodes D2a, D2b, and D2c function in the same manner as that of the diode D2 during the discharging phase.

[0079] It should be noted that the diodes DI a, Dlb, and Die and the switches SWla, SWlb, and SWlc are included in the pulsed current source 502 to increase a voltage that is applied at the point Pout. For example, each diode Dla, Dlb, and Die has a predetermined voltage rating, such as 3.3 kilovolts (kV), and each switch SWla, SWlb, and SWlc has a predetermined voltage rating, such as 3.3 kV. The voltage Vt that is applied at the point Pout increases by the voltage ratings of the diodes Dla, Dlb, and Die and the switches SWla, SWlb, and SWlc.

[0080] It should further be noted that the D2a, D2b, and D2c and the switches SW2a, SW2b, and SW2c are included in the pulsed current sink 504 to increase a voltage that is applied at the point Pout. For example, each diode D2a, D2b, and D2c has a predetermined voltage rating, such as 3.3 kV, and each switch SW2a, SW2b, and SW2c has a predetermined voltage rating, such as 3.3 kV. The voltage that is applied at the point Pout decreases by the voltage ratings of the diodes D2a, D2b, and D2c and the switches SW2a, SW2b, and SW2c. It should be noted that across the source and drain terminals of each of the switches SWla, SWlb, SWlc, SW2a, SW2b, and SW2c, a respective diode is coupled to protect the switch.

[0081] In one embodiment, any other number of switches, such as two or four switches, are coupled between the diode Die and the point Pout.

[0082] Also, in an embodiment, any other number of diodes, such as two or four diodes, are coupled between the inductor LI and the switch SWla.

[0083] In one embodiment, any other number of switches, such as two or four switches, are coupled between the diode D2a and the point PDC.

[0084] Also, in an embodiment, any other number of diodes, such as two or four diodes, are coupled between the inductor L2 and the switch SW2c.

[0085] Figure 6 is a diagram of an embodiment of a pulsed bias voltage generator 600 to illustrate a modular resonance switch (MRS). The pulsed bias voltage generator 600 is an example of the pulsed bias voltage generator 101 (Figure 1). The pulsed bias voltage generator600 includes a pulsed current source 602 and a pulsed current sink 604. The pulsed current source 602 is an example of the pulsed current source 102 (Figure 1) and the pulsed current sink 604 is an example of the pulsed current sink 104 (Figure 1).

[0086] The pulsed current source 602 has the point PC that is situated between the ground connection and the DC voltage source 212. The pulsed current sink 604 has the point PDC that is between the inductor L2a and the ground connection. Also, the point PDC is between the capacitor C2a and the ground connection.

[0087] The pulsed current source 602 includes the DC voltage source 212. The pulsed current source 602 further includes an MRS switch 606 and another MRS switch 608. The pulsed current sink 604 includes an MRS switch 610 and another MRS switch 612.

[0088] The MRS switch 606 includes the switch SWla, the diode DI a, an inductor LI a, and a capacitor Cl a. Also, a diode is coupled between the source terminal (S) and the drain terminal (D) of the switch SWla. Similarly, the MRS switch 608 includes the switch SWlb, the diode Dlb, an inductor Lib, and a capacitor Clb. Also, a diode is coupled between the source terminal (S) and the drain terminal (D) of the switch SWlb.

[0089] Moreover, the MRS switch 610 includes the switch SW2a, the diode D2a, an inductor L2a, and a capacitor C2a. Also, a diode is coupled between the source terminal (S) and the drain terminal (D) of the switch SW2a. Similarly, the MRS switch 612 includes the switch SW2b, the diode D2b, an inductor L2b, and a capacitor C2b. Also, a diode is coupled between the source terminal (S) and the drain terminal (D) of the switch SW2b.

[0090] The DC voltage source 212 is coupled via the point PC to the ground potential. The DC voltage source 212 is also coupled to the drain terminal of the switch SWla, which is coupled to the processor 208 (Figure 2). The source terminal of the switch SWla is coupled to the anode of the diode Dla and the cathode of the diode Dla is coupled to the inductor Lla to form a first series circuit. In the first series circuit, the switch SWla is coupled in series with the diode Dla and the inductor Lla. The capacitor Cla is coupled in parallel to the first series circuit.

[0091] The inductor Lla is coupled to the drain terminal of the switch SW2a, which is coupled to the processor 208 (Figure 2). The source terminal of the switch SW2a is coupled to the anode of the diode Dlb and the cathode of the diode Dlb is coupled to the inductor Lib to form a second series circuit. In the second series circuit, the switch SWlb is coupled in series with the diode Dlb and the inductor Lib. The capacitor Clb is coupled in parallel to the second series circuit.

[0092] The point PDC to the ground potential. The point PDC is also coupled to the inductor L2a. The inductor L2a is coupled to the cathode of the diode D2a and the anode of the diode D2a is coupled to the source terminal of the switch SW2a to form a third series circuit. In the third series circuit, the switch SW2a is coupled in series with the diode D2a and the inductor L2a. The capacitor C2a is coupled in parallel to the third series circuit. The switch SW2a is coupled to the processor 208.

[0093] The drain terminal of the switch SW2a is coupled to the inductor L2b. The inductor L2b is coupled to the cathode of the diode D2b and the anode of the diode D2b is coupled to the source terminal of the switch SW2b to form a fourth series circuit. In the fourth series circuit, the switch SW2b is coupled in series with the diode D2b and the inductor L2b. The capacitor C2b is coupled in parallel to the fourth series circuit. The switch SW2b is coupled to the processor 208. The inductor Lib is coupled to the drain terminal of the switch SW2b via the point Pout.

[0094] The operation of the pulsed current source 602 is similar to that of the pulsed current source 202. For example, when the processor 208 controls the switches SWla and SWlb to close, the current ICH generated by the DC voltage source 212 passes via the switch SWla, the diode Dla, the inductor Lla, the switch SWlb, the diode Dlb, the inductor Lib, the point Pout, and the RF connection 112 to the lower electrode of the plasma chamber 106.

[0095] Similarly, the operation of the pulsed current sink 604 is similar to that of the pulsed current sink 204. For example, when the processor 208 controls the switches SW2a and SW2b to close, the current IDCH is transferred from the plasma chamber 106 via the RF connection 112, the point Pout, the switch SW2b, the diode D2ba, the inductor L2b, the switch SW2a, the diode D2a, the inductor L2a, and the point PDC to the ground connection.

[0096] It should be noted that by coupling a capacitor in parallel to a series circuit, such as the first, second, third, or fourth series circuit, a switch of the series circuit is protected from being damaged. For example, the switches SWla and SW lb turn on or turn off at different times upon receiving control signals from the processor 208. To illustrate, the switch SWla turns on a first time and the switch SW2a turns on at a second time. The second time occurs before or after the first time to be different than the first time. In the illustration, the switch SWla turns on in response to receiving an on control signal from the processor 208 and the switch SW2a turns on in response to receiving an on control signal from the processor 208. The processor 208 sends the on control signals at the same time to the switches SWla and SW2a. Continuing with the example, when the switches SWla and SWlb turn on at different times, voltages across each of the switches SWla and SWlb, such as between source and drain terminals of the switch, do notchange rapidly because of a resonance period of the capacitor Cla and the inductor LI a and a resonance period of the capacitor Clb and the inductor Lib. Otherwise, when the voltages across each of the switches SWla and SWlb changes rapidly, the switch can be damaged. Damage to the switch interferes with processing of the substrate SU.

[0097] It should further be noted that a drain-to-source capacitance between the drain terminal and the source terminal of each of the switches SWla and SWlb is not rated. By coupling a capacitor across the series circuit, such as the first, second, third, or fourth series circuit, a practical rating is provided to the switch.

[0098] It should be noted that there is low power dissipation by the series circuit, such as the first, second, third, or fourth series circuit, when a capacitor is coupled in parallel to the series circuit. The capacitor forms a resonance circuit with an inductor of the series circuit. The resonance circuit facilitates, such as enables, the lower power dissipation. A heat sink that can be used with the series circuit is small when the resonance circuit facilitates the low power dissipation.

[0099] In one embodiment, the pulsed current source 602 includes any other number, such as three or five or one, of MRS switches.

[0100] In an embodiment, the pulsed current sink 604 includes any other number, such as three or five or one, of MRS switches.

[0101] Figure 7 is a diagram of an embodiment of a system 700 to illustrate an ion flux compensation (IFC) that is provided by an IFC circuit 702. The system 700 includes the processor 208, the IFC circuit 702, the pulsed bias voltage generator 101, and the plasma chamber 106. The IFC circuit 702 includes a DC voltage source 704 and an inductor 706. It should be noted that as an example, the DC voltage source 704 outputs a negative voltage. An example of a negative voltage output by the DC voltage source 704 is a voltage ranging from - 150 volts to -250 volts. To illustrate, the negative voltage output by the DC voltage source 704 is -200 volts.

[0102] The IFC circuit 702 is coupled in parallel with the pulsed current source 102 and with the pulsed current sink 104. For example, the DC voltage source 704 is coupled at one end in series with the inductor 706, which is coupled to the point Pout. Another end of the DC voltage source 704 is coupled to the ground connection. The processor 208 is coupled to the DC voltage source 704.

[0103] After each discharging phase and before a start of a consecutive charging phase, a ramp phase occurs. For example, after an occurrence of the fall portion 118 (Figure 1) of the cycle n of the non-sinusoidal signal 114 and before a consecutive occurrence of the rise portion116 (Figure 1) of the cycle (n+1), a ramp portion 701 of the non-sinusoidal signal 114 occurs during the cycle n. A ramp portion occurs during each cycle including the charging and discharging phases. The ramp portion 701 occurs during the ramp phase of each cycle including the charging and discharging phases. A combination of the rise portion 116, the fall portion 118, the high voltage level between the rise portion 116 and the fall portion 118, and the ramp portion 701 forms the pulse 214 of the non-sinusoidal signal 114.

[0104] During the ramp phase, the processor 208 sends a control signal to the DC voltage source 704 to control an amplitude of voltage that is output from the DC voltage source 704 to modify a slope of a ramp portion, such as the ramp portion 701, of the non-sinusoidal signal 114. For example, the processor 208 controls the DC voltage source 704 to increase an amplitude of voltage that is output from the DC voltage source 704. In the example, when the amplitude of voltage output from the DC voltage source 704 increases, a magnitude of a current IRAMP that is received from the plasma chamber 106 via the RF connection 112 and the point Pout by the IFC circuit 702 increases. Further in the example, when the magnitude of the current IRAMP increases, a slope of the ramp portion, such as the ramp portion 701, becomes more negative. To illustrate, the slope of the ramp portion becomes more negative when the slope negatively increases. As another example, the processor 208 controls the DC voltage source 704 to decrease an amplitude of voltage that is output from the DC voltage source 704. In the example, when the amplitude of voltage output from the DC voltage source 704 decreases, the magnitude of the current IRAMP that is received from the plasma chamber 106 by the IFC circuit 702 decreases. Further in the example, when the magnitude of current IRAMP decreases, the slope of the ramp portion, such as the ramp portion 701, becomes less negative. To illustrate, the slope of the ramp portion becomes less negative when the slope negatively decreases from a negative value towards a zero slope. The processor 208 controls the DC voltage source 704 in the same manner, described above, in which the processor 208 controls the DC voltage source 212.

[0105] It should be noted that when the magnitude of current IRAMP is within a predetermined range from, such as matches, a magnitude of ion flux on the substrate SU, an ion energy distribution of ions of plasma formed within the plasma chamber 106 is narrower. On the other hand, when the magnitude of current IRAMP is outside the predetermined range from the magnitude of ion flux on the substrate SU, the ion energy distribution of ions of plasma formed within the plasma chamber 106 is wider.

[0106] It should be noted that a voltage of the non-sinusoidal signal 114 during a rise portion, such as the rise portion 116, of each cycle of the charging and discharging cycles issometimes referred to herein as VstepA, which is a step, such as an increase, in a voltage. It should further be noted that a voltage of the non-sinusoidal signal 114 during a ramp portion, such as the ramp portion 701, of each cycle of the charging and discharging cycles is sometimes referred to herein as Vramp.

[0107] It should further be noted that the processor 208 controls the DC voltage source 212 (Figure 2A) to modify the slope of the ramp portion.

[0108] Figure 8A is a diagram of an embodiment of a resonance damper 800 that is implemented within the pulsed current sink 104 (Figure 1) or with the pulsed current sink 104. For example, the resonance damper 800 is located within a housing having the pulsed current sink 104 to be implemented within the pulsed current sink 104. The resonance damper 800 includes a transistor 802. A drain terminal (D) of the transistor 802 is coupled to the point PDC and a source terminal (S) of the transistor 802 is coupled to the ground connection. A gate terminal (G) of the transistor 802 is coupled to the processor 208.

[0109] Figure 8B is a diagram of an embodiment of a resonance damper 810 that is implemented within the pulsed current source 102 (Figure 1) or with the pulsed current source 102. For example, the resonance damper 810 is located within a housing having the pulsed current source 102 to be implemented within the pulsed current source 102. The resonance damper 810 includes a transistor 812. A source terminal (S) of the transistor 812 is coupled to the point PC and a drain terminal (D) of the transistor 812 is coupled to the ground connection. A gate terminal (G) of the transistor 812 is coupled to the processor 208.

[0110] Figure 8C is an embodiment of the graph 820 to illustrate the non-sinusoidal signal 114. The graph 820 plots amplitudes, such as -V3, -V2, -VI, zero, VI, V2, V2.7, and Vmax, of a voltage of the non-sinusoidal signal 114 on a y-axis and the time t on an x-axis. During the discharging phase, a voltage of the non-sinusoidal signal 114 decreases from the maximum voltage amplitude to a voltage amplitude, which is negative, such as -VI. For example, the voltage of the non-sinusoidal signal 114 transitions to the first negative voltage value, which is illustrated above with respect to Figure 2B. The transition from the maximum voltage amplitude to the voltage amplitude -VI is illustrated as Vstepl, which is a difference between the maximum voltage amplitude and the voltage amplitude -VI, of the pulse 214. The maximum voltage amplitude is illustrated in Figure 8C as Vmax. Moreover, during the ramp phase, the voltage of the non-sinusoidal signal 114 decreases to transition from the voltage amplitude -VI to another voltage amplitude, which is negative, such as -V3. It should be noted that the voltage amplitude -V3 is less than the voltage amplitude -VI. The transition from thevoltage amplitude -VI to the voltage amplitude -V3 is illustrated as Vrampl, which is a difference between the voltage amplitudes -VI and -V3.

[0111] The transitions Vstepl and Vrampl repeat with the cycles n and (n+1). For example, during the cycle n, the transitions Vstepl and Vrampl occur for a first instance and during the cycle (n+1), the transitions Vstepl and Vrampl occur for a second instance.

[0112] When a resonance damper, such as the resonance damper 800 or 810 (Figures 8A or 8B), is controlled to be partially on from being fully on, there is partial dampening of the non-sinusoidal signal 114. For example, during a time period in which the processor 208 sends a partially-on control signal to partially turn on a transistor, such as the transistor 802 or 812 (Figures 8 A and 8B), the maximum voltage amplitude of the non-sinusoidal signal 114 decreases to the voltage amplitude V2.7 to decrease the transition Vstepl to another transition Vstep2. To illustrate, the transition Vstep2 is a difference between the voltage amplitudes V2.7 and -VI. The decrease in the transition from Vstepl to Vstep2 is an example of the partial dampening. It should be noted that with the decrease in the transition from Vstepl to Vstep2, there is a decrease in the voltage step VstepA to a voltage step VstepB. The voltage step VstepA is a transition from the voltage -V3 to Vmax As an illustration, to turn the resonance damper partially on, the processor 208 sends a partially-on control signal to the resonance damper to achieve a gate-to-source voltage in a predetermined range, which extends from and including 0.7 volts to 15 volts. The gate-to-source voltage is a voltage between the gate and source terminals of the resonance damper.

[0113] On the other hand, when the resonance damper, such as the resonance damper 800 or 810, is controlled to be fully on from being partially on, there is no dampening of the non-sinusoidal signal 114. For example, during a time period in which the processor 208 sends a fully-on control signal to fully turn on the a transistor, such as the transistor 802 or 812, the voltage amplitude V2.7 increases to the maximum voltage amplitude of the non-sinusoidal signal 114 to increase the transition Vstep2 to the transition Vstepl. To illustrate, the transition Vstepl is a difference between the voltage amplitudes Vmax and -VI. The increase in the transition from Vstep2 to Vstepl is an example of no dampening. It should be noted that with the increase in the transition from Vstep2 to Vstepl, there is an increase from the voltage step VstepB to the voltage step VstepA. The voltage step VstepB is a transition from the voltage -V3 to the voltage V2.7.

[0114] In one embodiment, instead of or in addition to controlling the resonance damper to achieve the partial dampening, one or more switches of the pulsed current source 102 or one or more switches of the pulsed current sink 104 (Figure 1), or a combination thereof arecontrolled by the processor 208 to be partially turned on to achieve the partial dampening. For example, the processor 208 sends two partially-on control signals to the switches SWla and SW2a of the pulsed current source 502 (Figure 5) to partially turn on the switches SWla and SW2a to achieve the partial dampening.

[0115] In an embodiment, the terms partially on, partially turn on, partially-on, and partially active are used herein interchangeably. Also, the terms fully on, fully turn on, fully-on and fully active are used herein interchangeably.

[0116] Figure 8D is an embodiment of the graph 830 to illustrate a non-sinusoidal signal 832 generated by the pulsed bias voltage generator 101 having one or both of the resonance dampers 800 and 810 (Figures 8A and 8B). The graph 830 plots amplitudes, such as - Va, zero, Va, and Vb of a voltage of the non-sinusoidal signal 832 on a y-axis and the time t on an x-axis. When the resonance damper, such as the resonance damper 800 or 810, is controlled to be off from being fully on or from being partially active, there is full dampening of the non- sinusoidal signal 114. For example, during a time period in which the processor 208 sends the off control signal to fully turn off a transistor, such as the transistor 802 or 812 (Figures 8A and 8B), from having the transistor fully on, the transition Vstepl decreases to achieve a transition Vstep-rampl between the voltage amplitudes Vb and -Va. The transition Vstep-rampl is a difference between the voltage amplitudes Vb and -Va. In the example, it should be noted that the transition Vstep-rampl is less than a sum of the transitions Vstep2 and Vramp (Figure 8C). As an illustration, to turn the resonance damper off, the processor 208 sends the off control signal to the resonance damper to achieve the gate-to-source voltage in a predetermined range, which extends from and including 0 volts to 0.7 volts. As another example, during a time period in which the processor 208 sends the off control signal to turn off the transistor 802 from having the transistor 802 partially active, the transition Vstep2 decreases to achieve the transition Vstep- rampl.

[0117] On the other hand, when the resonance damper, such as the resonance damper 800 or 810, is controlled to be fully on from being off, there is no dampening of the non- sinusoidal signal 114. For example, during a time period in which the processor 208 sends the fully-on control signal to fully turn on the transistor 802 from having the transistor 802 off, the transition Vstep-rampl increases to achieve the transition Vstepl between the voltage amplitudes -V3 and Vmax. Also, when the resonance damper, such as the resonance damper 800 or 810, is controlled to be partially on from being off, there is some dampening of the non- sinusoidal signal 114. As another example, during a time period in which the processor 208sends the partially on control signal to turn the transistor 802 to be partially active from having the transistor 802 off, the transition Vstep-rampl increases to achieve the transition Vstep2.

[0118] When the resonance damper, such as the resonance damper 800 or 810 (Figures 8A or 8B), is controlled to be fully on, there is no dampening of the non-sinusoidal signal 114. For example, during a time period in which the processor 208 sends the on control signal to fully turn on the transistor 802, the transition Vstepl does not decrease to achieve the transition Vstep-rampl between the voltage amplitudes Vb and -Va. As an illustration, to turn the resonance damper fully on, the processor 208 sends the on control signal to the resonance damper to achieve the gate-to-source voltage in a predetermined range, which extends from and including 15 volts to 20 volts. It should be noted that 15 volts to 20 volts is a rating of the resonance damper.

[0119] Figure 8E is an embodiment of a graph 840 to illustrate that by using the resonance damper, such as the resonance damper 800 or 810 (Figures 8 A or 8B), a voltage region 842 of voltage amplitudes is achieved at the point Pout (Figure 1). The graph 840 plots a voltage Vramp on a y-axis and a voltage Vstep on an x-axis. A plot 844 of the graph 840 divides the graph 840 into the region 842 and a region 846. When the resonance damper 810 (Figure 8B) is implemented within or with the pulsed current source 102 (Figure 1) or the resonance damper 800 (Figure 8A) is implemented within or with the pulsed current sink 104 (Figure 1), or a combination thereof, voltage amplitudes within the region 842 are achievable at the point Pout (Figure 1). On the other hand, when the resonance damper 810 is not implemented with the pulsed current source 102 (Figure 1) and the resonance damper 800 is knocked implemented with the pulsed current sink 104, voltage amplitudes within the region 844 are achievable at the point Pout and the voltage amplitudes within the region 842 are not achievable at the point Pout.

[0120] Figure 9 is a diagram of an embodiment of a system 900 to illustrate use of the pulsed current sink 104 with a DC power sink 902 for RF energy recovery and resonance dampening. An example of the DC power sink 902 is one or more capacitors, or one or more batteries, or one or more voltage sources, or a DC voltage source, or a combination thereof. An example of a voltage source is a DC-to-DC converter.

[0121] The DC power sink 902 is coupled to the point PDC at one end and is coupled to the ground connection at an opposite end. Instead of power of the current IDCH being discharged to the ground connection, the power is recovered by, such as stored, in the DC power sink 902 for later access of the power. For example, the DC power sink 902 is coupled to the pulsed current source 102 (Figure 1) to provide power that is stored in the DC power sink 902 to the pulsed current source 102.

[0122] The resonance damper, such as the resonance damper 800 or 810 (Figures 8 A or 8B), being fully on corresponds to the DC power sink 902 providing zero voltage at the point PDC and no RF energy is recovered from the current IDCH by the DC power sink 902. For example, power output at the point PDC from the DC power sink 902 is zero because voltage output from the DC power sink 902 is zero. As another example, the processor 208 (Figure 2) is coupled to the DC power sink 902 and controls the DC power sink 902 to output the voltage of zero. When the voltage is output to be zero, there is no RF energy recovery by the DC power sink 902.

[0123] Also, the resonance damper, such as the resonance damper 800 or 810, being partially on corresponds to the DC power sink 902 providing some voltage at the point PDC and therefore recovering some RF energy from the current IDCH. For example, power output from the DC power sink 902 is greater than zero because voltage output from the DC power sink 902 is greater than zero. In the example, the voltage is less than a sufficiently high voltage, described below. As another example, the processor 208 controls the DC power sink 902 to output the voltage greater than zero and less than the sufficiently high voltage. When the voltage from the DC power sink 902 is output to be greater than zero and less than the sufficiently high voltage, there is RF energy recovered by the DC power sink 902.

[0124] Moreover, the resonance damper, such as the resonance damper 800 or 810, being off corresponds to the DC power sink 902 providing the sufficiently high voltage at the point PDC to prevent any net current flow between the plasma chamber 106 (Figure 1) and the DC power sink 902. An example of the sufficiently high voltage is an amplitude of a voltage at the point PDC that is equal to an amplitude of a voltage at the lower electrode. When the net current flow is prevented, such as zero current, between the plasma chamber 106 and the DC power sink 902, no power is output from the DC power sink 902 and therefore no RF energy is recovered from the current IDCH by the DC power sink 902. For example, power output from the DC power sink 902 is zero because net current output from the DC power sink 902 is zero. As another example, the processor 208 controls the DC power sink 902 to achieve the sufficiently high voltage to output the net zero current. When the net current is output to be zero, there is no RF energy recovered by the DC power sink 902.

[0125] The processor 208 controls the DC power sink 902 by providing one or more controls signals to the DC power sink 902. For example, the processor 208 controls the DC power sink 902 in the same manner in which the processor 902 controls the one or more voltage supplies of a DC voltage source, described herein.

[0126] Figure 10A is a diagram of an embodiment of a system 1000 to illustrate use of a pulsed current source 1002 and the IFC 702 to achieve multilevel pulsing. Figure 10B is an embodiment of a multilevel pulse signal 1050 to illustrate operation of the system 1000. The multilevel pulse signal 1050 is an example of the non-sinusoidal signal 114. For example, when the non-sinusoidal signal 114 has multiple levels instead of being a continuous signal, the non- sinusoidal signal 114 appears to be the multilevel pulse signal 1050. With reference to Figure 10A, the pulsed current source 1002 is an example of the pulsed current source 102 (Figure 1). Examples of the pulsed current source 1002 include the pulsed current source 202 (Figure 2A), the pulsed current source 302 (Figure 3), the pulsed current source 502 (Figure 5), and the pulsed current source 602 (Figure 6).

[0127] The processor 208 controls the maximum amplitude of the voltage of the non- sinusoidal signal 114 or controls the slope of the ramp portion 701 of the non-sinusoidal signal 114 or a combination thereof to achieve the multilevel pulsing. For example, with reference to Figure 10B, the processor 208 controls the maximum amplitude of the voltage of the non- sinusoidal signal 114 to decrease from a first level 1052, such as one including a local maximum amplitude, of the multilevel pulse signal 1050 to a second level 1054 of the multilevel pulse signal 1050. To illustrate, the processor 208 sends one or more disable signals to one or more switches coupled to the respective one or more voltage supplies of the DC voltage source 212 (Figure 2A) to turn off the one or more switches. When the one or more switches are turned off, the first level 1052 decreases to the second level 1054. In the example, remaining of the voltage supplies of the DC voltage source 212 are turned on by the processor 208 by sending enable signals to the remaining of the voltage supplies. In the example, a number of the voltage supplies of the DC voltage source 212 that are turned on to achieve the first level 1052 is greater than the number of the voltage supplies of the DC voltage source 212 that are turned on to achieve the second level 1054. In the example, the second level 1054 is lower than the first level 1052. To illustrate, a local maximum amplitude of the second level 1054 is less than the local maximum amplitude of the first level 1052. Continuing with the example, all amplitudes of voltage of the non-sinusoidal signal 114 at the first level 1052 are within a first predetermined range and all amplitudes of voltage of the non-sinusoidal signal 114 at the second level 1054 are within a second predetermined range. In the example, the second predetermined range is exclusive of the first predetermined range.

[0128] Continuing with the example, with reference to Figure 10B, the processor 208 controls the second level 1054 to increase to a third level 1056 of the multilevel pulse signal 1050. To illustrate, the processor 208 sends one or more enable signals to one or more switchescoupled to the respective one or more voltage supplies of the DC voltage source 212 to turn on the one or more switches. When the one or more switches are turned on, the second level 1054 increases to the third level 1056. In the example, remaining of the voltage supplies of the DC voltage source 212 are turned off by the processor 208 by sending disable signals to the remaining of the voltage supplies. In the example, a number of the voltage supplies of the DC voltage source 212 that are turned on to achieve the third level 1056 is greater than the number of the voltage supplies of the DC voltage source 212 that are turned on to achieve the second level 1054 and is greater than the number of the voltage supplies of the DC voltage source 212 that are turned on to achieve the first level 1052. In the example, the third level 1056 is greater than the second level 1054 and is greater than the first level 1052. To illustrate, a local maximum amplitude of the third level 1056 is greater than the local maximum amplitude of the first level 1052 and the local maximum amplitude of the second level 1054. In the example, all amplitudes of voltage of the non-sinusoidal signal 114 at the third level 1056 are within a third predetermined range. In the example, the third predetermined range is exclusive of the first predetermined range and exclusive of the second predetermined range.

[0129] As another example, with reference to Figure 10B, the processor 208 controls the slope of the ramp portion 701 of the non-sinusoidal signal 114 by controlling an amplitude of voltage that is output from the DC voltage source 704. When the slope of the ramp portion 701 is controlled to decrease from a value 1058 to value 1060, a voltage level 1062, such as the minimum voltage amplitude, of the non-sinusoidal signal 114 increases to a voltage level 1064. On the other hand, when the slope of the ramp portion 701 is controlled to increase from the value 1058 to a value 1066, the voltage level 1062 of the non-sinusoidal signal 114 decreases to a voltage level 1068. As yet another example, when the slope of the ramp portion 701 is controlled to increase from the value 1060 to the value 1066, the voltage level 1064 of the non- sinusoidal signal 114 decreases to the voltage level 1068.

[0130] Figure 11A is a diagram of an embodiment of a system 1100 to illustrate multilevel pulsing using an IFC 1102. Figure 1 IB is an embodiment of graphs 1150, 1152, 1154, 1156, and 1158 to illustrate operation of the IFC 1102. With reference to Figure 11 A, the IFC 1102 is an example of the IFC 702 (Figure 7). The IFC 1102 includes a constant current sink 1104 and a power multiplexer 1106. The constant current sink 1104 includes inductors Llx, L2x, and L3x, and further includes diodes Dlx, D2x, and D3x. The power multiplexer 1106 includes transistors Tbl, Tb2, and Tb3, diodes Dbl, Db2, and Db3, and voltage sources Vbl, Vb2, and Vb3. It should be noted that as an example, one or more of the voltage sources Vbl, Vb2, and Vb3 outputs respective one or more negative voltages. An example of a negativevoltage output by any one of the voltage sources Vbl, Vb2, and Vb3 is a voltage amplitude ranging from -20 volts to -30 volts. To illustrate, a negative voltage output from any one of the voltage sources Vbl, Vb2, and Vb3 is a voltage amplitude of -25 volts. As an example, each transistor Tbl, Tb2, and Tb3 is a FET, and each voltage source Vbl, Vb2, and Vb3 is a DC voltage source.

[0131] With reference to Figure 1 IB, the graph 1150 plots logic levels, such as 0 and 1, illustrating turning on and turning off of the transistor Tbl on a y-axis and the time t on an x- axis. For example, the logic level 1 represents turning on of the transistor Tbl and the logic level 0 represents turning off of the transistor Tbl. Also, the graph 1152 plots the logic levels illustrating turning on and turning off of the transistor Tb2 on a y-axis and the time t on an x- axis. The graph 1154 plots the logic levels illustrating turning on and turning off of the transistor Tb3 on a y-axis and the time t on an x-axis. The graph 1156 plots amplitudes of voltages output by the voltage sources Vbl through Vb3 (Figure 11 A). The graph 1150 plots amplitudes of the voltage Vt output at the point Pout (Figure 11 A).

[0132] With reference to Figure 11 A, the constant current sink 1104 is coupled to the point Pout. The inductor L3x is coupled to the point Pout at one end and to an anode of the diode D3x at another end. A cathode of the diode D3x is coupled to an end of the inductor L2x. An opposite end of the inductor L2x is coupled to an anode of the diode D2x and the cathode of the diode D2x is coupled to an end of the inductor Llx. An opposite end of the inductor Llx is coupled to an anode of the diode Dlx and a cathode of the diode Dlx is coupled to a point Pb of the power multiplexer 1106.

[0133] The point Pb is coupled to drain terminals (D) of the transistors Tbl, Tb2, and Tb3. A source terminal (S) of the transistor Tbl is coupled to an anode of the diode Dbl, a source terminal (S) of the transistor Tb2 is coupled to an anode of the diode Db2, and a source terminal (S) of the transistor Tb3 is coupled to an anode of the diode Db3. A cathode of the diode Dbl is coupled to the voltage source Vbl, a cathode of the diode Db2 is coupled to the voltage source Vb2, and a cathode of the diode Db3 is coupled to the voltage source Vb3. Each of the voltage sources Vbl through Vb3 are coupled to the ground connection. Gate terminals (G) of the transistors Tbl through Tb3 are coupled to the processor 208. Also, a diode is coupled between drain and source terminals of each of the transistors Tbl through Tb3 to protect the transistors Tbl through Tb3.

[0134] With reference to Figure 1 IB, the processor 208 sends an on control signal to the transistor Tbl at a time tl to turn on the transistor Tbl at the time tl, and sends off control signals to the transistors Tb2 and Tb3 at the time tl to turn off the transistors Tb2 and Tb3 at thetime tl . When the transistor Tbl is on and the transistors Tb2 and Tb3 are off, an amplitude of voltage Vb at the point Pb is equal to an amplitude of voltage output from the voltage source Vbl. As an example, the amplitude voltage output from the voltage source Vbl is 1054 (Figure 10B).

[0135] The processor 208 sends an on control signal at a time t2 to the transistor Tb2 to turn on the transistor Tb2 at the time t2, and sends an off control signal at the time t2 to the transistor Tbl to turn off the transistor Tbl. At the time t2, the transistor Tb3 is turned off. When the transistor Tb2 is on and the transistors Tbl and Tb3 are off, an amplitude of the voltage Vb at the point Pb is equal to an amplitude of voltage output from the voltage source Vb2. As an example, the amplitude voltage output from the voltage source Vb2 is 1056 (Figure 10B).

[0136] The processor 208 sends an on control signal at a time t3 to the transistor Tb3 to turn on the transistor Tb3 at the time t3, and sends an off control signal at the time t3 to the transistor Tb2 to turn off the transistor Tb2. At the time t3, the transistor Tbl is turned off. When the transistor Tb3 is on and the transistors Tbl and Tb2 are off, an amplitude of the voltage Vb at the point Pb is equal to an amplitude of voltage output from the voltage source Vb3.

[0137] It should be noted that the diodes Dbl through Db3 provide an OR ring. For example, when more than one of the transistors Tbl through Tb3 are controlled to be on by the processor 208, an amplitude of the voltage Vb at the point Pb is equal to the lowest among the amplitudes of the voltages output from the voltage sources Vbl through Vb3. To illustrate, when the transistors Tbl and Tb2 are turned on, an amplitude of the voltage Vb at the point Pb is equal to the lowest among the amplitudes of the voltages output from the voltage sources Vbl through Vb2.

[0138] Figure 11C is an embodiment of a multilevel pulse signal 1170 to illustrate a fast level -to-level transition 1172 of the multilevel pulse signal 1170. The multilevel pulse signal 1170 is an example of the non-sinusoidal signal 114 (Figure 1A). For example, when the non- sinusoidal signal 114 has multiple levels instead of being a continuous signal, the non-sinusoidal signal 114 appears to be the multilevel pulse signal 1170.

[0139] When the processor 208 (Figure 2) sends the on control signal to the transistor Tb2 (Figure 11 A) to increase voltage between the gate and source terminals of the transistor Tb2 within a time interval less than a preset time interval, the voltage Vb changes from the second level 1054 to the third level 1056 at a first rate greater than a predetermined rate. When the voltage Vb changes from the second level 1054 to the third level 1056 at the first rate, the fast level -to-level transition 1172 occurs. It should be noted that a slope of the fast level -to-leveltransition 1172 is positive. For example, the slope of the fast level -to-level transition 1172 is not infinite.

[0140] Figure 11D is embodiment of a multilevel pulse signal 1180 to illustrate a slow level -to-level transition 1182 of the multilevel pulse signal 1180. The multilevel pulse signal 1180 is an example of the non-sinusoidal signal 114 (Figure 1A). For example, when the non- sinusoidal signal 114 has multiple levels instead of being a continuous signal, the non-sinusoidal signal 114 is the multilevel pulse signal 1180.

[0141] When the processor 208 (Figure 2) sends the on control signal to the transistor Tb2 (Figure 11 A) to increase voltage between the gate and source terminals of the transistor Tb2 within a time interval greater than the preset time interval, the voltage Vb changes from the second level 1054 to the third level 1056 at a second rate less than the predetermined rate. When the voltage Vb changes from the second level 1054 to the third level 1056 at the second rate, the slow level -to-level transition 1182 occurs. It should be noted that a slope of the slow level-to- level transition 1182 is positive. For example, the slope of the slow level -to-level transition 1182 is not infinite. Also, the slope of the slow level -to-level transition 1182 is less than the slope of the fast level-to-level transition 1172.

[0142] Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessorbased or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0143] In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and / or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid deliverysettings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with the system.

[0144] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0145] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0146] In some embodiments, a remote computer (e.g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits locatedremotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

[0147] Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and / or manufacturing of semiconductor wafers.

[0148] It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a capacitively-coupled plasma (CCP) chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor within the ICP plasma chamber.

[0149] As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0150] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are those that manipulate physical quantities.

[0151] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0152] In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in acomputer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0153] One or more embodiments, described herein, can also be fabricated as computer- readable code on a non-transitory computer-readable medium. The non-transitory computer- readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non- transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[0154] Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[0155] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[0156] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

CLAIMS1. A system comprising: a pulsed bias voltage generator having: a pulsed current source, wherein the pulsed current source is configured to increase a voltage during a charging process to create a pulse of a non-sinusoidal radio frequency (RF) signal; a pulsed current sink coupled to the pulsed current source, wherein the pulsed current sink is configured to decrease the voltage to create the pulse of the non- sinusoidal RF signal, wherein the pulsed current source is configured to repeat the increase in the voltage and the pulsed current sink is configured to repeat the decrease in the voltage to generate additional pulses of the non-sinusoidal RF signal; and a damper coupled to the pulsed current sink to modify a voltage step of the pulse.

2. The system of claim 1, wherein the damper is configured to be off, partially active, or fully active, wherein the damper is configured to decrease an amplitude of the voltage step when the damper transitions from being fully active to being partially active and transitions from being partially active to being off.

3. The system of claim 1, wherein the damper is configured to be off, partially active, or fully active, wherein the damper is configured to increase an amplitude of the voltage step when the damper transitions from being off to being partially active and transitions from being partially active to being fully active.

4. The system of claim 1, wherein the damper includes a transistor.

5. The system of claim 1, wherein the pulsed current source excludes a transformer, and the pulsed current sink excludes a transformer.

6. The system of claim 1, further comprising: an ion flux compensation circuit coupled to the pulsed current source and the pulsed current sink, wherein the ion flux compensation circuit is configured to modify a slope of a ramp of the non-sinusoidal RF signal.

7. The system of claim 6, wherein the pulsed current source includes a first direct current (DC) voltage source and the ion flux compensation circuit includes a second DC voltage source, wherein the first and second DC voltage sources are configured to be controlled to achieve multi-level pulsing.

8. The system of claim 1, further comprising: a power multiplexer coupled to the pulsed current source and the pulsed current sink, wherein the power multiplexer is configured to be controlled to achieve multi-level pulsing.

9. The system of claim 1, wherein the pulsed current source includes: a (DC) voltage source; a switch coupled in series with the DC voltage source; a diode coupled in series with the switch; and an inductor coupled in series with the diode.

10. The system of claim 1, wherein the pulsed current sink includes: an inductor; a diode coupled in series with the inductor; a switch coupled in series with the diode, wherein the switch is coupled to a ground potential.

11. A system comprising: a pulsed bias voltage generator having: a pulsed current source, wherein the pulsed current source is configured to increase a voltage during a charging process to create a pulse of a non-sinusoidal radio frequency (RF) signal; a pulsed current sink coupled to the pulsed current source, wherein the pulsed current sink is configured to decrease the voltage to create the pulse of the non- sinusoidal RF signal, wherein the pulsed current source is configured to repeat the increase in the voltage and the pulsed current sink is configured to repeat the decrease in the voltage to generate additional pulses of the non-sinusoidal RF signal; and a damper coupled to the pulsed current source to modify a voltage step of the pulse.

12. The system of claim 11, wherein the damper is configured to be off, partially active, or fully active, wherein the damper is configured to decrease an amplitude of the voltage step when the damper transitions from being fully active to being partially active and transitions from being partially active to being off.

13. The system of claim 11, wherein the damper is configured to be off, partially active, or fully active, wherein the damper is configured to increase an amplitude of the voltage step when the damper transitions from being off to being partially active and transitions from being partially active to being fully active.

14. The system of claim 11, wherein the damper includes a transistor.

15. The system of claim 11, wherein the pulsed current source excludes a transformer, and the pulsed current sink excludes a transformer.

16. The system of claim 11, further comprising: an ion flux compensation circuit coupled to the pulsed current source and the pulsed current sink, wherein the ion flux compensation circuit is configured to modify a slope of a ramp of the non-sinusoidal RF signal.

17. The system of claim 11, wherein the pulsed current source includes a first direct current (DC) voltage source and the ion flux compensation circuit includes a second DC voltage source, wherein the first and second DC voltage sources are configured to be controlled to achieve multi-level pulsing.

18. The system of claim 11, further comprising: a power multiplexer coupled to the pulsed current source and the pulsed current sink, wherein the power multiplexer is configured to be controlled to achieve multi-level pulsing.

19. The system of claim 11, wherein the pulsed current source includes: a (DC) voltage source; a switch coupled in series with the DC voltage source; a diode coupled in series with the switch; and an inductor coupled in series with the diode.

20. The system of claim 11, wherein the pulsed current sink includes: an inductor; a diode coupled in series with the inductor; a switch coupled in series with the diode, wherein the switch is coupled to a ground potential.

21. A system comprising: a pulsed bias voltage generator having: a pulsed current source, wherein the pulsed current source is configured to increase a voltage during a charging process to create a pulse of a non-sinusoidal radio frequency (RF) signal; a pulsed current sink coupled to the pulsed current source, wherein the pulsed current sink is configured to decrease the voltage to create the pulse of the non- sinusoidal RF signal,wherein the pulsed current source is configured to repeat the increase in the voltage and the pulsed current sink is configured to repeat the decrease in the voltage to generate additional pulses of the non-sinusoidal RF signal; a first damper coupled to the pulsed current source to modify the voltage step; and a second damper coupled to the pulsed current sink to modify the voltage step.

22. The system of claim 21, wherein the first damper is configured to be off, partially active, or fully active, wherein the first damper is configured to decrease an amplitude of the voltage step when the first damper transitions from being fully active to being partially active and transitions from being partially active to being off, wherein the second damper is configured to be off, partially active, or fully active, wherein the second damper is configured to decrease an amplitude of the voltage step when the second damper transitions from being fully active to being partially active and transitions from being partially active to being off.

23. The system of claim 21, wherein the first damper is configured to be off, partially active, or fully active, wherein the first damper is configured to increase an amplitude of the voltage step when the first damper transitions from being off to being partially active and transitions from being partially active to being fully active, wherein the second damper is configured to be off, partially active, or fully active, wherein the second damper is configured to increase an amplitude of the voltage step when the second damper transitions from being off to being partially active and transitions from being partially active to being fully active.

24. The system of claim 21, wherein the first damper includes a first transistor and the second damper includes a second transistor.

Images