Rectifier, methods of forming and operating the same

Abstract

Various embodiments may relate to a rectifier. The rectifier may include a complementary cross-coupled circuit arrangement configured to generate a direct current (DC) output voltage based on a first input alternating current (AC) input voltage and a second input AC input voltage. The rectifier may also include a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement and a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The n-MOS bias circuit arrangement may be configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to a first n- channel metal oxide semiconductor (n-MOS) core transistor or a second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement based on a mode voltage applied to the n-MOS bias circuit arrangement.

Description

RECTIFIER, METHODS OF FORMING AND OPERATING THE SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of Singapore application No. 10202400719X filed March 15, 2024, the contents of it being hereby incorporated by reference in its entirety for all purposes.TECHNICAL FIELD

[0002] Various embodiments of this disclosure may relate to a rectifier. Various embodiments of this disclosure may relate to a method of forming a rectifier. Various embodiments of this disclosure may relate to a method of operating a rectifier.BACKGROUND

[0003] The adoption of dedicated wireless power transfer (WPT) and energy harvesting (EH) is important to realize a wireless sensor network (WSN) on a massive scale. It relieves the reliance on an onboard battery and reduces the node form factor to achieve a reasonable economy of scale in areas such as structural health monitoring and logistic tracking. The frontend of the radio frequency energy harvesting (RFEH) system is widely implemented with the cross-coupled rectifier for having higher power conversion efficiency (PCE) and sensitivity than the Dickson rectifier. FIG. 1A shows (above) a schematic of a conventional Dickson rectifier; and (below) a plot of power conversion efficiency (PCE) (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) of the conventional Dickson rectifier. It is the diode voltage (VDIODE) drop in the Dickson rectifier in FIG. 1A that reduces the maximum output voltage (VOUT) of the rectifier. As a result, a larger chip area is required to accommodate a greater number of cascading Dickson rectifiers to achieve the required VOUT-

[0004] Instead of a diode, a diode configured metal oxide semiconductor (MOS) transistor can be utilized to potentially lower the dropout voltage to the MOS threshold voltage (VTH). Exploitation of the body effect of the MOS was previously demonstrated to further improve the sensitivity by reducing the VTH at the expense of higher losses at high input power (PIN). FIG. IB shows (above) a schematic of a conventional cross-coupled rectifier; and (below) a plot of power conversion efficiency (PCE) (in percent or %) as a function of input power PIN(in dccibcls-milliwatts or dBm) of the conventional cross-coupled rectifier. The cross-coupled rectifier in FIG. IB eliminates the VDIODE by operating the transistors as switches and having a dropout voltage based on their on-rcsistancc (EON). It adopts the back-to-back inverter feedback structure similar to the static random-access memory (SRAM) structure. Inevitably, the crosscoupled rectifier also inherited some of the drawbacks, such as the shoot-through current (ISIIOOT).

[0005] Currently, systems that utilize radio frequency (RF) energy as their primary source arc plagued by a slew of losses, such as frcc-spacc path loss and obstruction between the linc- of-sight when operating at far field. Even though these losses are of lesser concern when operating in the near field, the system front-end exhibits rapid PCE degradation when high PIN incidence on the rectifier leads to a limited and narrow PIN dynamic range. The PCE of the rectifier can be calculated as follows:wherein PLOAD is the resistive load at the output of the rectifier, Pour is the output power of the rectifier, and PIN is the input power at the rectifier.SUMMARY

[0006] Various embodiments may relate to a rectifier. The rectifier may include a complementary cross-coupled circuit arrangement configured to generate a direct current (DC) output voltage based on a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage. The complementary cross-coupled circuit arrangement may include a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal, as well as a second core capacitor having a first terminal for receiving the second input alternating cunent (AC) input voltage, and a second terminal. The complementary cross-coupled circuit arrangement may also include a first p- channel metal oxide semiconductor (p-MOS) core transistor (Ml) in electrical connection with the second terminal of the first core capacitor, as well as a second p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The complementary cross-coupled circuit arrangement may further include a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the secondterminal of the second core capacitor. The rectifier may also include a p-channcl metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The rectifier may further include a n- channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement may be configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the fust n- channcl metal oxide semiconductor (n-MOS) core transistor or the second n-channcl metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement based on a mode voltage applied to the n-channel metal oxide semiconductor (n- MOS) bias circuit arrangement.

[0007] Various embodiments may relate to a method of forming a rectifier. The method may include forming a complementary cross -coupled circuit arrangement configured to generate a direct cunent (DC) output voltage based on a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage. The complementary cross-coupled circuit arrangement may include a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal, as well as a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal. The complementary cross-coupled circuit arrangement may also include a first p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second p-channcl metal oxide semiconductor (p-MOS) core transistor in electrical connection with tire second terminal of the second core capacitor. The complementary crosscoupled circuit arrangement may further include a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The method may also include forming a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The method may further include forming a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement maybe configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor or the second n-channcl metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement based on a mode voltage applied to the n- channel metal oxide semiconductor (n-MOS) bias circuit arrangement.[0008J Various embodiments may provide a method of operating a rectifier. The method may include providing a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage to a complementary cross-coupled circuit arrangement, the complementary cross-coupled circuit arrangement configured to generate a direct current (DC) output voltage based on the first input alternating current (AC) input voltage and the second input alternating current (AC) input voltage. The complementary cross-coupled circuit arrangement may include a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal, as well as a second core capacitor having a first terminal for receiving the second input alternating cunent (AC) input voltage, and a second terminal. The complementary cross-coupled circuit arrangement may also include a first p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second p-channcl metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The complementary cross-coupled circuit arrangement may further include a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second n- channcl metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The rectifier may also include a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The rectifier may further include a n- channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The method may include applying a mode voltage to the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement, the n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channcl metal oxide semiconductor (n-MOS) core transistor or the secondn-channcl metal oxide semiconductor (n-MOS) core transistor of the complementary crosscoupled circuit arrangement based on the mode voltage.BRIEF DESCRIPTION OF THE DRAWINGS[0009J In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings arc not necessarily drawn to scale, emphasis instead generally being placed upon illustrating the principles of various embodiments. In the following description, various embodiments of the invention are described with reference to the following drawings.FIG. 1 A shows (above) a schematic of a conventional Dickson rectifier; and (below) a plot of power conversion efficiency (PCE) (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) of the conventional Dickson rectifier.FIG. IB shows (above) a schematic of a conventional cross-coupled rectifier; and (below) a plot of power conversion efficiency (PCE) (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) of the conventional cross-coupled rectifier.FIG. 2 shows a general illustration of a rectifier according to various embodiments.FIG. 3 shows a general illustration of a method of forming a rectifier according to various embodiments.FIG. 4 shows a general illustration of a method of operating a rectifier according to various embodiments.FIG. 5A shows a block diagram of a radio frequency energy harvesting (RFEH) system which may include a rectifier.FIG. 5B shows a schematic of the rectifier according to various embodiments, which may be a part of the radio frequency energy harvesting (RFEH) system.FIG. 6 shows (right) a schematic of a multi-path rectifier for input power (PIN) dynamic range improvement; and (left) a plot of power conversion efficiency (PCE) (in percent or %) as a function of input power (PIN) (in decibels-milliwatts or dBm) of the multi-path rectifier.FIG. 7A shows an illustration of a half-circuit cross-coupled rectifier.FIG. 7B shows a plot of voltage as a function of time illustrating the timing analysis of the reverse conduction current (IREV) and the forward conduction current (IFWD) for Mi and M3 of the half-circuit cross-coupled rectifier shown in FIG. 7A.FIG. 8A shows the schematic of the rectifier with a switchable self-bias polarity according to various embodiments.FIG. 8B illustrates the operation of the rectifier for the first mode (low input power or PIN) when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage (VRFP > VRFN) according to various embodiments.FIG. 8C illustrates the operation of the rectifier for the first mode (low input power or PIN) when the first input alternating current (AC) input voltage is less than the second input alternating current (AC) input voltage (VRFP < VRFN) according to various embodiments.FIG. 8D illustrates the operation of the rectifier for the second mode (high input power or PIN) when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage (VRFP > VRFN) according to various embodiments.FIG. 8E illustrates the operation of the rectifier for the second mode (high input power or PIN) when the first input alternating current (AC) input voltage is less than the second input alternating current (AC) input voltage (VRFP < VRFN) according to various embodiments.FIG. 9A shows a simulated plot of voltage VNA or VNB (VC6 or Vcs) (in volts or V) as a function of input power PIN (in decibels-milliwatts or dBm) of the rectifier according to various embodiments.FIG. 9B shows a simulated plot of k (ratio of voltage Vci / Vour) as a function of input power PIN (in decibels-milliwatts or dBm) of the rectifier according to various embodiments.FIG. 10A shows a plot of voltage (in volts or V) as a function of time (in nanoseconds or ns) illustrating a transient simulation of voltages VOUT and VOP of the rectifier according to various embodiments.FIG. 10B shows a plot of current (in micro-Amperes or pA) as a function of time (in nanoseconds or ns) illustrating drain-source currents of p-doped metal oxide semiconductor (p- MOS) transistors IDP and n-doped metal oxide semiconductor (n-MOS) transistors IDN according to various embodiments.FIG. 11 shows a schematic of a common-gate comparator used to switch between the low input power (PIN) mode and the high input power (PIN) mode of the rectifier according to various embodiments.FIG. 12 is a simulated plot of mode voltage VMODE (in volts or V) as a function of output voltage Vour (in volts or V) of the common-gate comparator at different reference voltages VRFF according to various embodiments.FIG. 13 A shows a simulated plot of current (in pico- Amperes or pA) as a function of output voltage VOUT (V) illustrating total current consumption from both the reference voltage VREF and the output voltage VOUT of the comparator by varying the reference voltage VREF at the typical process comer according to various embodiments.FIG. 13B shows a plot of the comparator-to-rectifier current ratio ICOMPARATOR / IOUT (inpercent or %) as a function of rectifier current I0UT(in milli-Amperes or mA) illustrating the I COMPARATOR / I OUTat aload resistance I0UTof 50 kQ and a reference voltage VREFof 0.6V according to various embodiments.FIG. 14A shows a micrograph of the chip including the rectifier and the comparator according to various embodiments.FIG. 14B shows another micrograph of the chip including the rectifier according to various embodiments.FIG. 14C shows a layout of the rectifier according to various embodiments.FIG. 15 shows a table illustrating the device parameters of the switchable polarity bias rectifier and the comparator according to various embodiments.FIG. 16A shows a block diagram of a measurement setup for the rectifier in comparator-track (CT) according to various embodiments.FIG. 16B shows the configuration for the rectifier in comparator-track (CT) according to various embodiments.FIG. 17A shows the measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 25 kQ and reference voltage VREF of 0.7 V according to various embodiments.FIG. 17B shows the measured output voltage VOUT (in volts or V) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 25 kQ and reference voltage VREF of 0.7 V according to various embodiments.FIG. 18A shows the measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 50 kQ and reference voltage VREF of 0.6 V according to various embodiments.FIG. 18B shows the measured output voltage VOUT (in volts or V) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 50 kQ and reference voltage VREF of 0.6 V according to various embodiments.FIG. 19A shows the measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 100 kQ and reference voltage VREF of 0.5 V according to various embodiments.FIG. 19B shows the measured output voltage VOUT (in volts or V) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 100 kQ and reference voltage VREF of 0.5 V according to various embodiments.FIG. 20 shows a plot of measured peak power conversion efficiency PCEPEAK (in percent or %) as a function of load resistance RLOAD (in kilo-Ohms or kQ) of the rectifier according to various embodiments.FIG. 21 shows a plot of measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) with a load resistance RLOAD of 50 kQ at various reference voltages VREF according to various embodiments.FIG. 22 shows a table comparing the performance of the rectifier according to various embodiments with state-of-the-art rectifiers.DESCRIPTION

[0010] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments arc not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0011] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and / or combinations and / or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0012] In the context of various embodiments, the articles “a”, “an” and “the” as used with regard to a feature or clement include a reference to one or more of the features or elements.

[0013] In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance, e.g., within 10% of the specified value.

[0014] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0015] By “comprising” it is meant including, but not limited to, whatever follows the word “comprising”. Thus, use of the term “comprising” indicates that the listed elements are required or mandatory', but that other elements arc optional and may or may not be present.

[0016] By “consisting of’ it is meant including, and limited to, whatever follows the phrase “consisting of’. Thus, the phrase “consisting of’ indicates that the listed elements are required or mandatory', and that no other elements may be present.

[0017] Embodiments described in the context of one of the rectifiers are analogously valid for the other rectifiers. Similarly, embodiments described in the context of a method are analogously valid for a rectifier, and vice versa.

[0018] FIG. 2 shows a general illustration of a rectifier according to various embodiments. The rectifier may include a complementary cross-coupled circuit arrangement 202 configured to generate a direct current (DC) output voltage based on a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage. The complementary cross-coupled circuit arrangement 202 may include a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal, as well as a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal. The complementary cross-coupled circuit arrangement 202 may also include a first p-channel metal oxide semiconductor (p-MOS) core transistor (Ml) in electrical connection with the second terminal of the first core capacitor, as well as a second p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The complementary crosscoupled circuit arrangement 202 may further include a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second n-channcl metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The rectifier may also include a p-channcl metal oxide semiconductor (p-MOS) bias circuit arrangement 204 in electrical connection with the complementary cross-coupled circuitarrangement 202. The rectifier may further include a n-channcl metal oxide semiconductor (n- MOS) bias circuit arrangement 206 in electrical connection with the complementary crosscoupled circuit arrangement 202. The n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may be configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor or the second n-channel metal oxide semiconductor (n- MOS) core transistor of the complementary cross-coupled circuit arrangement 202 based on a mode voltage applied to the n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement 206.

[0019] In other words, the rectifier may include a complementary cross-coupled circuit arrangement 202, as well as a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204 and a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement 206 connected to the complementary cross-coupled circuit arrangement 202. Depending on a mode voltage applied to the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement 206, the n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may switch between a first biasing mode or a second biasing mode to change a polarity of a bias voltage provided to a first n-channcl metal oxide semiconductor (n-MOS) core transistor I a second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement 202.

[0020] Various embodiments may relate to a rectifier using self-bias as the primary technique to achieve the wide PIN range, which reduces the circuitry complexity. Various embodiments may provide a tuning option in the self-bias structure for post-fabrication to address the potential process variation.

[0021] Various embodiments may provide an approach different from that of the multi-path rectifier, by adapting the biasing on the rectifier to achieve two different peak power conversion efficiency (PCEPEAK) at two different input powers (PIN). The first biasing mode may also be referred to as a low input power (low PIN) mode (or “0” mode), while the second biasing mode may also be referred to as a high input power (high PIN) mode (or “1” mode). The abovementioned approach may advantageously provide a more gradual power conversion efficiency (PCE) profile transition due to a single core rectifier being used. This is unlike having multiple rectifiers with rapid PCE degradation at their respective high PIN. The control of this approach may be simple and may alleviate the sudden transition typically associatedwith a multi-path rectifier. During the initialization of the system, various embodiments may allow rudimentary resistive feedback for reasonable rectifier’s PCE until the system stabilizes and enables the higher performance comparator-based tracking of the PIN.

[0022] A common-gate comparator may be used to switch the rectifier between the first biasing mode (low input power (low PIN) mode) and the second biasing mode (high input power (high PIN) mode).

[0023] A “core capacitor” as described herein may refer to a capacitor of the complementary cross-couplcd circuit arrangement 202. Also, a “core transistor” may refer to a transistor of the complementary cross-coupled circuit arrangement 202. More specifically, a “p-channel metal oxide semiconductor (p-MOS) core transistor” may refer to a p-channel transistor of the complementary cross-coupled circuit arrangement 202, while a “n-channel metal oxide semiconductor (n-MOS) core transistor” may refer to a n-channel transistor of the complementary cross-coupled circuit arrangement 202.

[0024] In various embodiments, the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204 may include a first p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor. The p-channel metal oxide semiconductor (p- MOS) bias circuit arrangement 204 may also include a second p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the first p- channcl metal oxide semiconductor (p-MOS) core transistor. The p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204 may further include a first p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the second p-MOS bias circuit arrangement bias capacitor. The p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204 may additionally include a second p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the first p-MOS bias circuit arrangement bias capacitor.

[0025] A “p-MOS bias circuit arrangement bias capacitor” may refer to a capacitor of the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204. Also, a “p- channcl metal oxide semiconductor (p-MOS) bias transistor” may refer to a p-channel transistor of the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204.The p-channcl metal oxide semiconductor (p-MOS) bias circuit arrangement 204 may be devoid of n-channel transistors.

[0026] A transistor being “diode-configured” may mean that the transistor is connected or configured in such a way that it behaves similarly to a diode.

[0027] In various embodiments, a drain electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor may be in connection with a gate electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the second p-MOS bias circuit arrangement bias capacitor. A drain electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be in connection with a gate electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the first p-MOS bias circuit arrangement bias capacitor.

[0028] In various embodiments, a source electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor may be in electrical connection with a source electrode of the first p-channcl metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202. A source electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be in electrical connection with a source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202.

[0029] In various embodiments, the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 204 may be configured to switch between the first biasing mode and the second biasing mode. The p-mctal oxide semiconductor (p-MOS) bias circuit arrangement 204 may be configured such that during the second biasing mode, a current flows from the source electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second p- channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the second p-channcl metal oxide semiconductor (p-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

[0030] In various embodiments, the rectifier may be configured such that a current flows from a drain electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202 to the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary crosscoupled circuit arrangement 202 when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage. The rectifier may be further configured such that a current flows from a drain electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202 to the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202 when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

[0031] In various embodiments, the rectifier may additionally include a load capacitor connected to the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202, and the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement 202. A “load capacitor” may be a capacitor connected to a node or terminal providing the output voltage. In other words, the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor and the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor may provide the output voltage or connected to a node or terminal providing the output voltage.

[0032] In various embodiments, a threshold voltage of the first p-channel metal oxide semiconductor (p-MOS) bias transistor may be higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p-channel metal oxide semiconductor (p-MOS) core transistor, the first n-channel metal oxide semiconductor (n-MOS) core transistor and the second n-channel metal oxide semiconductor (n-MOS) core transistor. A threshold voltage of the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be also higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p-channel metal oxide semiconductor (p-MOS) core transistor, the first n-channel metal oxide semiconductor (n-MOS) core transistor and the second n-channel metal oxide semiconductor (n-MOS) core transistor. In this regard, the first p-channel metal oxide semiconductor (p-MOS)core transistor, the second p-channcl metal oxide semiconductor (p-MOS) core transistor, the first n-channel metal oxide semiconductor (n-MOS) core transistor and the second n-channel metal oxide semiconductor (n-MOS) core transistor may be referred to as low threshold voltage (low VTH) devices or transistors, while the first p-channel metal oxide semiconductor (p-MOS) bias transistor and the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be referred to as high threshold voltage (high VTH) devices or transistors.

[0033] In various embodiments, the n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may include a first n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor (of the complementary cross-coupled circuit arrangement 202). The n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may also include a second n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor (of the complementary cross-coupled circuit arrangement 202). The n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may further include a first n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor. The n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may additionally include a second n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor.

[0034] The n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may further include a third n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage. The n-metal oxide semiconductor (n-MOS) bias circuitarrangement 206 may also include a fourth n-channcl metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage. The n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may also include a first bias resistor having a first terminal in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n- MOS) bias transistor and the source electrode of the third n-channcl metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor. The n- metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may additionally include a second bias resistor having a first terminal in electrical connection with a gate electrode of the third n-channel metal oxide semiconductor (n-MOS) bias transistor and the source electrode of the fourth n-channel metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the second n-channcl metal oxide semiconductor (n-MOS) bias transistor.

[0035] A “n-MOS bias circuit arrangement bias capacitor” may refer to a capacitor of the n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 Also, a “n-channel metal oxide semiconductor (n-MOS) bias transistor” may refer to a n-channel transistor of the n- channel metal oxide semiconductor (n-MOS) bias circuit arrangement 206. The n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may be devoid of p-channel transistors. A “bias resistor” may refer to a resistor of the n-metal oxide semiconductor (n- MOS) bias circuit arrangement 206.

[0036] In various embodiments, the first n-channel metal oxide semiconductor (n-MOS) bias transistor, the second n-channel metal oxide semiconductor (n-MOS) bias transistor, the third n-channel metal oxide semiconductor (n-MOS) bias transistor and the fourth n-channel metal oxide semiconductor (n-MOS) bias transistor may be low threshold voltage (low VTH) devices or transistors. In other words, a threshold voltage of each of the n-MOS bias transistor may be lower than a threshold voltage of the first p-MOS bias transistor or the second p-MOS bias transistor.

[0037] In various embodiments, the n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may be configured such that during the first biasing mode, a current flowsfrom the source electrode of the first n-channcl metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating cunent (AC) input voltage.

[0038] In various embodiments, the n-metal oxide semiconductor (n-MOS) bias circuit arrangement 206 may be configured such that during the second biasing mode, a current flows from the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage, and a current flows from the drain electrode of the second n-channcl metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

[0039] The change in the polarity of the bias voltage may result in the opposite current flows in the first n-channel metal oxide semiconductor (n-MOS) bias transistor / second n-channel metal oxide semiconductor (n-MOS) bias transistor.

[0040] In various embodiments, the rectifier may be configured such that a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement 202 to a drain electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement 202 when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage. The rectifier may be further configured such that a current flows from the source electrode of the second n- channcl metal oxide semiconductor (n-MOS) core transistor of the complementary crosscoupled circuit arrangement 202 to a drain electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuitarrangement 202 when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

[0041] In various embodiments, an on-rcsistancc of the third n-channcl metal oxide semiconductor (n-MOS) bias transistor may be less than an on-resistance of the first bias resistor. An on-resistance of the fourth n-channel metal oxide semiconductor (n-MOS) bias transistor may be less than an on-resistance of the second bias resistor.

[0042] FIG. 3 shows a general illustration of a method of forming a rectifier according to various embodiments. The method may include, in 302, forming a complementary crosscoupled circuit arrangement configured to generate a direct current (DC) output voltage based on a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage. The complementary cross-coupled circuit arrangement may include a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal, as well as a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal. The complementary cross-coupled circuit arrangement may also include a first p-channcl metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second p-channcl metal oxide semiconductor (p-MOS) core transistor n electrical connection with the second terminal of the second core capacitor. The complementary cross-coupled circuit arrangement may further include a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The method may also include, in 304, forming a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The method may further include, in 306, forming a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement may be configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor or the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupledcircuit arrangement based on a mode voltage applied to the n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement.

[0043] In other words, various embodiments may relate to a method of forming a rectifier as described herein by connecting together a complementary cross-coupled circuit arrangement, a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement, and a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement.

[0044] For avoidance of doubt, FIG. 3 is intended to illustrate the steps of forming a rectifier according to various embodiments, and is not intended to limit the sequence of the various steps. For instance, step 302 may occur before, after, or at the same time as step 304.

[0045] In various embodiments, the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement may include a first p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor. The p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement may also include a second p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor. The p-channel metal oxide semiconductor (p- MOS) bias circuit arrangement may further include a first p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the second p-MOS bias circuit arrangement bias capacitor. The p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement may also include a second p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the first p-MOS bias circuit arrangement bias capacitor.

[0046] In various embodiments, a drain electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor is in connection with a gate electrode of the first p- channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the second p-MOS bias circuit arrangement bias capacitor. A drain electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be in connection with a gate electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the first p-MOS bias circuit arrangement bias capacitor.

[0047] In various embodiments, a source electrode of the first p-channcl metal oxide semiconductor (p-MOS) bias transistor may be in electrical connection with a source electrode of the first p-channcl metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement. A source electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be in electrical connection with a source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement.

[0048] In various embodiments, the p-channcl metal oxide semiconductor (p-MOS) bias circuit arrangement may be configured to switch between the first biasing mode and the second biasing mode. The p-metal oxide semiconductor (p-MOS) bias circuit arrangement may be configured such that during the second biasing mode, a current flows from the source electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second p-channcl metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

[0049] In various embodiments, the rectifier may be configured such that a current flows from a drain electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement to the source electrode of the first p- channcl metal oxide semiconductor (p-MOS) core transistor of the complementary crosscoupled circuit arrangement when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage. The rectifier may be further configured such that a current flows from a drain electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement to the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

[0050] In various embodiments, the method may also include a load capacitor connected to the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistorof the complementary cross-coupled circuit arrangement, and the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement.

[0051] In various embodiments, a threshold voltage of the first p-channel metal oxide semiconductor (p-MOS) bias transistor may be higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p-channel metal oxide semiconductor (p-MOS) core transistor, the first n-channel metal oxide semiconductor (n-MOS) core transistor and the second n-channcl metal oxide semiconductor (n-MOS) core transistor. A threshold voltage of the second p-channel metal oxide semiconductor (p-MOS) bias transistor may be also higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p-channel metal oxide semiconductor (p-MOS) core transistor, the first n-channel metal oxide semiconductor (n-MOS) core transistor and the second n-channel metal oxide semiconductor (n-MOS) core transistor.

[0052] In various embodiments, the n-mctal oxide semiconductor (n-MOS) bias circuit arrangement may include a first n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor. The n-metal oxide semiconductor (n-MOS) bias circuit arrangement may also include a second n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the first n-channcl metal oxide semiconductor (n-MOS) core transistor.

[0053] The n-metal oxide semiconductor (n-MOS) bias circuit arrangement may further include a first n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor. The n- mctal oxide semiconductor (n-MOS) bias circuit arrangement may additionally include a second n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of thesecond n-channcl metal oxide semiconductor (n-MOS) core transistor. The n-mctal oxide semiconductor (n-MOS) bias circuit arrangement may also include a third n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage. The n-metal oxide semiconductor (n-MOS) bias circuit arrangement may further include a fourth n-channcl metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage.

[0054] The n-metal oxide semiconductor (n-MOS) bias circuit arrangement may additionally include a first bias resistor having a first terminal in electrical connection with a gate electrode of the first n-channcl metal oxide semiconductor (n-MOS) bias transistor and the source electrode of the third n-channel metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the first n-channcl metal oxide semiconductor (n-MOS) bias transistor. The n-metal oxide semiconductor (n- MOS) bias circuit arrangement may also include a second bias resistor having a first terminal in electrical connection with a gate electrode of the third n-channel metal oxide semiconductor (n-MOS) bias transistor and the source electrode of the fourth n-channel metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor.

[0055] In various embodiments, the n-metal oxide semiconductor (n-MOS) bias circuit arrangement may be configured such that during the first biasing mode, a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the second n-channcl metal oxide semiconductor (n-MOS) bias transistor when the secondinput alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

[0056] In various embodiments, the n-mctal oxide semiconductor (n-MOS) bias circuit arrangement may be configured such that during the second biasing mode, a current flows from the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage, and a current flows from the drain electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

[0057] In various embodiments, the rectifier may be configured such that a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement to a drain electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage. The rectifier may be further configured such that a current flows from the source electrode of the second n- channel metal oxide semiconductor (n-MOS) core transistor of the complementary crosscoupled circuit arrangement to a drain electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

[0058] In various embodiments, an on-resistance of the third n-channel metal oxide semiconductor (n-MOS) bias transistor may be less than an on-resistance of the first bias resistor. An on-resistance of the fourth n-channel metal oxide semiconductor (n-MOS) bias transistor may be less than an on-resistance of the second bias resistor.

[0059] FIG. 4 shows a general illustration of a method of operating a rectifier according to various embodiments. The method may include, in 402, providing a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage to a complementary cross-coupled circuit arrangement, the complementary cross-coupled circuitarrangement configured to generate a direct current (DC) output voltage based on the first input alternating current (AC) input voltage and the second input alternating current (AC) input voltage. The complementary cross-coupled circuit arrangement may include a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal, as well as a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal. The complementary cross-coupled circuit arrangement may also include a first p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The complementary cross-coupled circuit arrangement may further include a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor, as well as a second n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor. The rectifier may also include a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The rectifier may further include a n-channel metal oxide semiconductor (n- MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement. The method may include, in 404, applying a mode voltage to the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement, the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor or the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement based on the mode voltage.

[0060] In other words, various embodiments may relate to using a rectifier as described herein to generate an output voltage by providing the first input alternating current (AC) input voltage, the second input alternating current (AC) input voltage, and the mode voltage.

[0061] Step 404 may occur before, after or at the same time as step 402.

[0062] FIG. 5A shows a block diagram of a radio frequency energy harvesting (RFEH) system which may include a rectifier 500. FIG. 5B shows a schematic of the rectifier according to various embodiments, which may be a part of the radio frequency energy harvesting (RFEH)system. The cascading direct current - direct current (DC - DC) boost converter 502 may provide a regulated supply voltage (VSUP) for the sensor node, and functions as a regulated load RLOAD to the rectifier to provide optimal PCE performance. A buck-boost converter operating in the discontinuous current mode (DCM) was demonstrated to be able to maintain the rectifier PCE above 70% across an RLOAD from 10 Q to 10 kQ. It was achieved by regulating the input impedance of the converter, making it independent of the converter input voltage (Vour of the rectifier) while also providing decoupling of the actual RLOAD from the rectifier. In contrast, another study proposed using a maximum power point tracking (MPPT) algorithm to maintain impedance matching at the interface between the rectifier and DC-DC converter by reconfiguring the number of rectifier stages to achieve a dynamic range from -20 dBm to 20 dBm. At the same time, in addition to modulating the input impedance similar to the abovementioned example, another study also changes the matching network at the input of the rectifier to achieve both input and output matching for its rectifier front-end. However, in applications without the boost converter, an N-stage cascading rectifier offers VOUT boosting at a low PLN to meet the minimum VSUP but incurs a higher loss at a high PIN. Furthermore, to achieve an overall higher system efficiency, the rectifier must also address the varying PIN. The RFEH may also include a matching network 504 and a control 506.[ 00631 FIG. 6 shows (right) a schematic of a multi-path rectifier for input power (PIN) dynamic range improvement; and (left) a plot of power conversion efficiency (PCE) (in percent or %) as a function of input power (PIN) (in decibels-milliwatts or dBm) of the multi-path rectifier. FIG. 6 shows the concept of the multi-path approach may achieve an improved PIN dynamic range by dynamically switching between two rectifiers optimized at two targeted PIN. The two rectifiers need not be of the same structure, where the cross-coupled and Dickson rectifiers were used for low and high PIN, respectively. It allows the effective use of the Dickson rectifier at a higher PIN when the dropout voltage is of lesser concern. It may avoid the drawback of the increased losses in the cross-coupled rectifier. However, it may be challenging to predetermine the optimal transition between the two rectifiers, resulting in sub-optimal performance and power loss.

[0064] A series -parallel reconfiguring of an N-stagc rectifier also demonstrates an improved PIN dynamic range. A 6-stage to 12-stage Dickson rectifier was able to achieve a 15 dB dynamic range but suffered from downtime due to the difficulty of the control circuit to discern the appropriate configuration. An interesting reconfiguring approach was proposed by stackingdifferent VTH devices to achieve a dynamic range of 22.8 dB. ft uses native devices for low PIN and sequentially stacks higher VTH devices in series to limit the losses and obtain an equivalent longer channel length device. It is important to note that this may require extensive and careful optimization due to the use of different devices, which severely limits its practicality against device variation during mass production. However, the rectifier input impedance (ZREC) also requires meticulous optimization or an adaptive matching network to address the change in ZREC based on the configuration. Lastly, self-biasing improves the PET dynamic range by reducing the reverse conduction loss (PREV) from the p-MOS by limiting the reverse conduction current (IREV) and improves the sensitivity by increasing the overdrive on the n-MOS. However, this also results in a reduced p-MOS forward conduction current (IFWD) and introduces a conduction imbalance between the p-MOS and the n-MOS, resulting in the inefficiency of the voltage boosting introduced by the coupling capacitors. Studies have also proposed the underdrive of the n-MOS to mitigate the conduction imbalance at high PIN, which requires extensive optimization to ensure reasonable sensitivity at low PIN. Furthermore, the diode-configured transistors used to generate the self-bias voltage may also be susceptible to process and temperature variations with minimally accessible tune options. Studies addressed this issue by tracking VOUT and providing continuous active compensation on the n-MOS.

[0065] Various embodiments may propose a simpler approach for low-costs systems by switching the polarity of the self-bias voltage applied to the gate terminal of the n-MOS to achieve two different peak PCE (PCEPEAK) at two different PIN. The advantage of this approach is that it may provide two distinct PCE profile transitions with a single rectifier and may offer a tuning option.

[0066] The cross-coupled rectifier is fundamentally formed by two inverter structures in feedback. When considering half of the period (VRP > VRN) and with reference to FIG. IB, the differential input VRFP and VRFN is rectified by transferring charges from Ci to CL when VOP > VOUT and replenishing the charges in C2 from the ground (Vss) when Vss > VON- The sinusoidal VOP or VON results in a reverse conduction current IREV when VOUT > VOP or VON due to the p- MOS bidirectional characteristic. A single-sided self-bias may reduce IREV by introducing a clamping voltage for the p-MOS at the expense of the forward conduction current (IFWD). The role of the n-MOS is often treated as a means for current continuity. However, due to the sinusoidal nature of VOP and VON, the n-MOS also experiences a similar issue as the p-MOS. The double-sided self-bias may positively bias the n-MOS to lower the overdrive to improvethe sensitivity. However, this resulted in severe PCE degradation at high PLN due to the timing mismatch between the p-MOS and n-MOS. FIG. 7 A shows an illustration of a half-circuit cross-couplcd rectifier. FIG. 7B shows a plot of voltage as a function of time illustrating the timing analysis of the reverse conduction current (IREV) and the forward conduction current (IFWD) for Mi and M3 of the half-circuit cross-coupled rectifier shown in FIG. 7A.

[0067] FIG. 7B shows a timing mismatch between Mi and M3. The charges are transferred by IFWD.MI from Ci to CL through Mi when VOP > kVouT- As Vop transits, Mi discharges CL when kVouT > Vop and until Mi turns off when kVour - VON < |VTHP| shown in IREV, ML At the same time, M3 also turns on when VON>Vss > VTHN resulting in an IREV,M3 discharging CL M3 is only able to replenish the charges in Ci with IFWD,M3 when Vss > Vop and VON - VOP > VTHN.

[0068] The key observations are: (1) an overlap of IREV provides a conduction path from VQUT to Vss, resulting in ISHOOT, and (2) if IREV for M3 is longer than Mi, it reduces the number of charges stored in Ci and degrades the effectiveness of the voltage boosting provided by the coupling capacitor. This can be expressed as follows:V0P=2 ^OUT + VCOUPLINGVRFP (2)where k factors the deviation from the analytical result of ’A, and ^COUPLING is the coupling efficiency between Ci and the parasitic capacitance (CPARASTTIC) on node VOP in Equation (3). The equivalent CPARASITIC is the sum of the gate-drain overlap capacitance, gate-source overlap capacitance and gate-body oxide capacitance contributed by the p-MOS and n-MOS. Under a steady-state operation, the variation in VOLT is minimal with a suitable CL and can be regarded as an AC virtual ground.

[0069] FIG. 8A shows the schematic of the rectifier with a switchable self-bias polarity according to various embodiments. The main complementary cross-coupled circuit arrangement 802 may be formed by M1-M4 and C1-C2 similar to FIG. IB. In other words, the complementary circuit arrangement 802 may include a first core capacitor Ci, a second core capacitor C2, a first p-channel metal oxide semiconductor (p-MOS) core transistor Mi, a second p-channel metal oxide semiconductor (p-MOS) core transistor M2, a first n-channel metal oxide semiconductor (n-MOS) core transistor M3, and a second n-channel metal oxide semiconductor(n-MOS) core transistor M4. The low VTH (LVT) core devices may be used for M1-M4 to achieve better sensitivity. On the other hand, metal-insulator-metal (MIM) capacitors may be used for C1-C2 to minimize the amount of bottom plate parasitic capacitors while maximizingthe amount of capacitance per unit area. Unlike FIG. IB, the gate terminal of M1-M4 is not connected to VQP and VON, but instead, the first input alternating current (AC) input voltage VRFP and the second input alternating current (AC) input voltage VRFN arc coupled through C3- Ce. It allows the voltage stored in C3-C6 to assist or restrict the overdrive to turn on M1-M4.

[0070] The p-MOS positive self-bias voltage may be generated using a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 804 including the diode-configured M5-M6 and C3-C4. In other words, the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement 804 may include a first p-MOS bias circuit arrangement bias capacitor (C3), a second p-MOS bias circuit arrangement bias capacitor (C4), a first p-channel metal oxide semiconductor (p-MOS) bias transistor (M5), and a second p-channel metal oxide semiconductor (p-MOS) bias transistor (M6), wherein the first p-channel metal oxide semiconductor (p-MOS) bias transistor (M5) and the second p-channel metal oxide semiconductor (p-MOS) bias transistor (M6) may be diode-configured. In this diode configuration, Ms-Me may provide a unidirectional conducting path to charge and store the charges in C3-C4. It may only happen when VOUT is sufficiently large to forward bias Ms-Me. Ms-Me are implemented with high VTH (HVT) devices to prevent degrading the IFWD at low PIN due to the generated p-MOS self-bias voltage. The p-MOS positive self-bias voltage may be crucial during high PIN to limit IREV-

[0071] In other words, during low PIN, the first p-channel metal oxide semiconductor (p- MOS) bias transistor (Ms), and the second p-channel metal oxide semiconductor (p-MOS) bias transistor (Me) may not be activated, and there may not be any charging (i.e., charging due to a current which is above the leakage current) to the first p-MOS bias circuit arrangement bias capacitor (C3), and the second p-MOS bias circuit arrangement bias capacitor (C4). However, during high PIN, the first p-channel metal oxide semiconductor (p-MOS) bias transistor (Ms), and the second p-channel metal oxide semiconductor (p-MOS) bias transistor (Mg) may be activated and may allow positive charges to be stored in the first p-MOS bias circuit arrangement bias capacitor (C3), and the second p-MOS bias circuit arrangement bias capacitor (C4). The charging of C3 and C4 may be dependent on whether VRFP > VRFN or VRPN < VRFN- The positive charges stored in C3 and / or C4 may help limit IREV flowing through Mi and / or M2. A transistor being “activated” may refer to the transistor being turned on to provide a conducting path (i.c., a current that is above the subthrcshold conduction current) between the source terminal and the drain terminal of the transistor. Conversely, a transistor being“deactivated” may refer to the transistor being turned off such that there is no conducting path, except maybe for a subthreshold conduction current, between the source terminal and the drain terminal of the transistor.

[0072] The n-MOS positive and negative self-bias voltage may be generated with a n- channel metal oxide semiconductor (n-MOS) bias circuit arrangement 806 including LVT M7- M10, R1-R2 and C5-C6. In other words, the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement 806 may include a first n-MOS bias circuit arrangement bias capacitor (C5), a second n-MOS bias circuit arrangement bias capacitor (Ce), a first n-channcl metal oxide semiconductor (n-MOS) bias transistor (M7), a second n-channel metal oxide semiconductor (n-MOS) bias transistor (Ms), a third n-channel metal oxide semiconductor (n-MOS) bias transistor (M9), a fourth n-channel metal oxide semiconductor (n-MOS) bias transistor (Mio), a first bias resistor (Ri) and a second bias resistor (R2). The performance at low PIN may be improved using a positive n-MOS self-bias voltage. This may be performed by turning off M9- M10 and allowing R1-R2 to provide a dc-short between the gate-source terminal of M; Ms. The conducting path of the diodc-configurcd M7-M8 may allow charges to flow from Vss to C5-C6. The positive n-MOS self-bias voltage may make it easier to turn on M3-M4 even with a smaller VRFP and VRFN. However, an n-MOS positive self-bias voltage may introduce mismatch during high PIN, as illustrated in FIGS. 7A-B. As such, a negative n-MOS self-bias may be generated by turning on M9-M10 to address the conduction mismatch. It may reconfigure M? Ms by providing a dc-short between the gate-drain terminal to change the conducting path from C5- Q> to Vss- This operation may deplete the charges stored in C5-C6, resulting in a negative selfbias voltage. The TON of M9-M10 may be much smaller than R1-R2. In other words, the ro_N of M9 and Mio may be designed to be less than the TON of Ri and R2, respectively. The TON of M9 and Mio are designed to be less than the TON of Ri and R2 (respectively) in order to provide stronger electrical connectivity between the gate terminal and drain terminal of M? and Mw when mode voltage is asserted.

[0073] In other words, during low PIN, the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement may provide a positive bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor M3 or the second n-channcl metal oxide semiconductor (n-MOS) core transistor M4 of the complementary cross-coupled circuit arrangement. More specifically, the positive bias may be provided to M3 or M4 based on whether VRFP > VRFN or VRPN < VRFN- The slight positive bias provided to M3 or M4 may make them easier to turn on,and may help with the sensitivity performance, which may be critical during low PIN operation (because generally voltage swing is small with the same input impedance). During high PIN, the n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement may provide a negative bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor Ms or the second n-channel metal oxide semiconductor (n-MOS) core transistor M4 of the complementary cross-coupled circuit arrangement. More specifically, the negative bias may be provided to M3 or M4 based on whether VRFP > VRFN or VRPN < VRFN- During high PIN, it may be desirable to provide a slightly negative bias to M3 or M4 to make them easier to turn off (and therefore prevent or reduce IREV or leakage current discharging to VSS) as well as better matching to p-MOS transistors in terms of transient timing, while sensitivity may be less of a concern.

[0074] FIG. 8B illustrates the operation of the rectifier for the first mode (low input power or PIN) when the first input alternating current (AC) input voltage is greater than the second input alternating c Line nt (AC) input voltage (VRFP > VRFN) according to various embodiments. FIG. 8C illustrates the operation of the rectifier for the first mode (low input power or PIN) when the first input alternating current (AC) input voltage is less than the second input alternating current (AC) input voltage (VRFP < VRFN) according to various embodiments. FIG. 8D illustrates the operation of the rectifier for the second mode (high input power or PIN) when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage (VRFP > VRFN) according to various embodiments. FIG. 8E illustrates the operation of the rectifier for the second mode (high input power or PIN) when the first input alternating current (AC) input voltage is less than the second input alternating current (AC) input voltage (VRFP < VRFN) according to various embodiments.

[0075] The rectifier may be configured to provide a conducting path to charge Ce from ground when VRFP > VRFN at low PIN, a conducting path to charge C5 from ground when VRFP < VRFN at low PIN, a conducting path to discharge C5 to ground when VRFP > VRFN at high PIN, and a conducting path to discharge Ce to ground when VRFP < VRFN at high PIN. RI - R2 in the arrangement electrically provides a pull-down conducting path for the gate terminal of M7 - Ms during initialization and low PIN. When VRFP > VRFN as shown in FIG. 8B and FIG. 8D, only Mi and M4 are participating in the rectification. Tire generating of the bias voltages involves M5, Mg, Mio, C4, C5 and R2. The generating of the bias voltages involves M5, Mg, Mio, C4, C5 and R2. Similar analysis can be performed for M2, M3, Me, M7, M9, C3, Ce and Ri whenVRFP < VRFN as shown in FIG. 8C and FIG. 8E. The body-terminal of all p-MOS and n-MOS have been connected to the VOUT and the Vss (ground), respectively. For the following analysis, the voltages may be mentioned in the format of VX,Y,P where X indicates the voltage type, Y represents the device when applicable, and P indicates the phase as c|)l: VRFP > VRFN and c|>2: VRFP < VRFN when applicable.

[0076] During low PIN operation (mode = 0 or first mode), the diode-configured Ms may inhibit the conduction path from VOUT due to the high VTH (HVT) device where VOUT>VPA.O < |VTHP,MS| and as such, VPA.O ~ VRFN^I. The reverse overdrive of Mi may be VSG-REV,M 1,4.1 = VOUT>VPA,4>I due to the bidirectional conduction characteristics of the device (VOUT > VOP,4>I)- The reverse conduction current (IREV) may still be manageable due to a small VSG-REV,MI,4>I at low PIN- It may favor maintaining a larger forward conduction current (IFWD). IFWD may occur only when VOP,<|>I > VOUT; where the forward overdrive of Ml VDG-FWD,MI,<|>I = Vop.oi - VPA,<|>I = (V2V01 1 + VRFP, 41) - VRFN,I . As for M4, a previous study demonstrated an improved sensitivity by providing a positive bias onto the gate terminal of M4 to lower the overdrive VGSN required to turn M4 on. The rectifier may adopt a similar configuration using Ms and R2. The bias may be generated with R2 providing a dc-short between the gate terminal and the source terminal of Ms (Mg may be diode-configured through R2) and stored in Cs as Vcs,<|>2 = Vss - VTHN.MS>VRFP.42 during c[>2. At <[> 1, VGSN,M4,4>I = VRFP, 4.1 + Vcs,4>2 ~ Vss-

[0077] During high PIN operation (mode = 1 or second mode), Mi is self-biased with diode- configured Ms as VPA,I is sufficient to forward bias and turn on Ms to charge C4 to generate a positive Vc4,4>i = VOUT - |VTHP,MS| - VRFN,4>I voltage when VOUT - VPA,4>I > |VTHP,MS|. The bias reduces the IREV by limiting the Mi’s VSG-REV,4>I = VOUT - VPA,4>I = VOUT - (Vc4,4>i + VRFN, 4.1) = |VTHP,MS|. The reduction in IREV comes at the expense of IFWD when the charges in Ci are transferred to the output. IFWD occurs only when VA,4>I > VOUT; where the Mi’s VDG-FWD,4>I = VA,4>I - VPA,4>I = (GVOLT + VRFP,4>I) - (Vc4,4>i + VRFN, 4,1) = VRFP, 4,1 - ' / AVOU I + |VTHP,MS|- For comparison, the cross-coupled rectifier has a higher VSG,REV,4>I = IYVOUT - VRFN, 4.1 and VDG,FWD,4>I = 2VRFP,4>I without a bias voltage on Mi. As for M4, even though the positive bias improved the sensitivity during low PIN, it may also be irrefutable that it is harder to turn M4 off. As a result, in every rectification cycle, M4 remains conducting longer even though Mi enters subthreshold conduction earlier. This timing difference may cause unnecessary discharge of C2. Mio is a switch to reconfigure the conduction direction of Mg to limit the overdrive voltage permissible at the gate-terminal of M4 at VGSN,M4.4>I = VDS,MIO + VTHN.MS. Theon-rcsistancc of Mw may be designed to be much smaller than R2.

[0078] FIG. 9A shows a simulated plot of voltage VNA or VNB (VC6 or Ves) (in volts or V) as a function of input power PIN (in dccibcls-milliwatts or dBm) of the rectifier according to various embodiments. It can be observed in FIG. 9A that Ves increases with PIN. Despite the improved sensitivity at low PIN, as mentioned above, it may be irrefutable that the assistance in the overdrive also leads to difficulty in turning off M4. Consequentially, it results in a rapid PCE degradation due to a conduction mismatch between the p-MOS and n-MOS, resulting in the unnecessary discharge of Ci and C2 and reduced efficiency of the voltage doubling functionality. This effect can be observed in FIG. 9B for mode = 0 with the rapid decrease in * / 2k = VCI / VOUT with increasing PIN. FIG. 9B shows a simulated plot of k (ratio of voltage Vci / Vour) as a function of input power PIN (in decibels-milliwatts or dBm) of the rectifier according to various embodiments. In this mode, a higher Vouris generated at a lower PIN due to an increased PCE. As such, an excessively high PIN must not be applied to the rectifier to prevent overvoltage beyond the rated |VDS| across M2 and M3 in the off state. FIG. 10A shows a plot of voltage (in volts or V) as a function of time (in nanoseconds or ns) illustrating a transient simulation of voltages VOUT and VOP of the rectifier according to various embodiments. FIG. 10B shows a plot of current (in micro-Ampcrcs or pA) as a function of time (in nanoseconds or ns) illustrating drain-source currents of p-doped metal oxide semiconductor (p-MOS) transistors IDP and n-doped metal oxide semiconductor (n-MOS) transistors IDN according to various embodiments. FIGS. 10A-B further show a reduced +IDN,M3- It indicates the reduction in unnecessary discharge of Ci. However, there is a reduced |_IDN,M3| from 454 u A to 78 pA, which hinders the ability to replenish Ci with M3. Therefore, during the design of the proposed rectifier, the net flow of charges to Ci and C2 AQ = QN-MOS - Qp-.vios > 0 C may be considered to ensure the effectiveness of M3 and M4 and prevent excessive negative bias.

[0079] FIG. 11 shows a schematic of a common-gate comparator used to switch between the low input power (PIN) mode and the high input power (PIN) mode of the rectifier according to various embodiments. The common-gate comparator may be a low-power common-gate comparator, and may include HVT devices. Various embodiments may relate to a circuit arrangement including the rectifier and the common-gate comparator. The common-gate comparator may operate at the subthrcshold region to minimize the power consumption of the comparator. A hysteresis may be provided by M15 and Mi6 in positive feedback when VMODE= 0 V. It may ensure that the comparator initializes with VMODE = 0 V and requires VOUT to be sufficiently high to overcome the hysteresis to trigger a change in VMODE- The comparator may configure the rectifier in the low-power mode (mode = 0) during the power-up sequence. The high-power mode (mode = 1) may reduce the rectifier sensitivity due to a reduced n-MOS overdrive voltage and potentially prevent sufficient VOUT from being generated in a low PIN condition. During system initialization, the equivalent RLOAD at the rectifier may be high, with most of the system in either the standby or sleep mode. In the low -power mode, the rate of VOUT versus PIN profile is gentler than in the high-power mode, which prevents a rapid VOUT build-up at high PIN. The functional comparison is performed by Kirchoff s voltage loop between Mu and M12 as follows:w wherein ID0is the characteristic current of the transistor, — is the aspect ratio of the transistor, VTis the thermal voltage, n is the channel length modulation coefficient and AV can be determined from Equation (5) for the overdrive voltage. AVM11contributes to the offset voltage (Vos) as ID, MU T50, while AVM12 is negligible due to ID,MI2 ~ 0 when VREF> V0UT. Assuming that Vos is compensated with VREF, the effect of Vos can be neglected for simplicity . The output of the comparator (VMODE) tracks VOLT when V0UT> VREF, as shown in FIG. 12. FIG. 12 is a simulated plot of mode voltage VMODE (in volts or V) as a function of output voltage VOUT (in volts or V) of the common-gate comparator at different reference voltages VREF according to various embodiments.

[0080] FIG. 13A shows a simulated plot of current (in pico-Amperes or pA) as a function of output voltage VOUT (V) illustrating total current consumption from both the reference voltage VREF and the output voltage VOUT of the comparator by varying the reference voltage VRI I at the typical process comer according to various embodiments. The various process corners are simulated, and the upper and lower bound of the total current consumption having ITOTAL < 6 nA with the worst corner at the ff corner due to a lowering of both p-MOS and n- MOS VTH. FIG. 13B shows a plot of the comparator-to-rectifier current ratio COMPARATOR / I0UT(in percent or %) as a function of rectifier current l0UT(in milli-Amperes or mA) illustrating the 1 COMPARATOR FL OUTaload resistance IOUT °f 50 k£l and a reference voltage VREFof 0.6V according to various embodiments. FIG. 13B shows the impact of the comparatoron the PCE of the proposed rectifier by examining the current ratio between the comparator and the IOUT- The comparator contributes less than 0.1% of IOUT, making it suitable for the rectifier operating at low PIN in a harvesting application.

[0081] The proposed rectifier is implemented in a 40 nm low-power complementary metal oxide semiconductor (CMOS) node. FIG. 14A shows a micrograph of the chip including the rectifier and the comparator according to various embodiments. FIG. 14B shows another micrograph of the chip including the rectifier according to various embodiments. The rectifier may be 125 pm x 140 pm, and implemented in a 40 nm low-power complementary metal oxide semiconductor (CMOS) node. FIG. 14C shows a layout of the rectifier according to various embodiments. The rectifier may be optimized at PIN = -16 dBm, and the device parameters are tabulated in FIG. 15. FIG. 15 shows a table illustrating the device parameters of the switchable polarity bias rectifier and the comparator according to various embodiments.

[0082] FIG. 16A shows a block diagram of a measurement setup for the rectifier in comparator-track (CT) according to various embodiments.

[0083] The measurement setup in FIG. 16A may include a vector network analyzer (VNA) 1602 (Agilent E5061B), a digital multimeter 1604 (Agilent 34461A) and a test fixture 1606 with the rectifier in QFN40 (denoted as Dcvicc-Undcr-Tcst or DUT) connected to the VNA 1602 and the digital multimeter 1604. An adjustable load (RLOAD) 1608 may be connected to the test fixture 1606 / rectifier. VOIJT and Si i are recorded while sweeping the VNA output port power. S 11 is determined by de-embedding the test fixture and setting the reference plane at the pads of the package. The rectifier’s effective PIN is determined as follows:PIN — PSOURCE ~ ^INSERT + lOlog (1 - |S1X|2) (6)[dbm] [dBm] [dB] [dB] where PSOURCE isoutput power of the VNA port, and LINSERTis the insertion loss due to the test fixture.

[0084] The rectifier may be measured with different configurations to determine its performance through the MODE pin. FIG. 16B shows the configuration for the rectifier in comparator-track (CT) according to various embodiments. The low-power (LP) mode with VMODE — ^s’s and the high-power (HP) mode with VM0DE— TIP are characterized to determine the two PCEPEAK. The comparator-track (CT) mode switches between the two PCEPEAKwith an external VREFfor the measurement; VREFis available from the power management unit (PMU).

[0085] FIG. 17A shows the measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 25 kQ and reference voltage VREF of 0.7 V according to various embodiments. FIG. 17B shows the measured output voltage VOUT (in volts or V) as a function of input power PIN (in decibels- milliwatts or dBm) for a load resistance RLOAD of 25 kQ and reference voltage VREF of 0.7 V according to various embodiments. FIG. 18A shows the measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 50 kQ and reference voltage VREF of 0.6 V according to various embodiments. FIG. 18B shows the measured output voltage VOUT (in volts or V) as a function of input power PLN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 50 kQ and reference voltage VREF of 0.6 V according to various embodiments. FIG. 19A shows the measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 100 kQ and reference voltage VREF of 0.5 V according to various embodiments. FIG. 19B shows the measured output voltage VOUT (in volts or V) as a function of input power PIN (in decibels-milliwatts or dBm) for a load resistance RLOAD of 100 kQ and reference voltage VREF of 0.5 V according to various embodiments.

[0086] The measured PCE versus PIN is shown in FIGS. 17A, 18A, 19A for different RLOAD, while FIGS. 17B, 18B, 19B show VOUT versus PIN for different RI OAD. The measurement is performed at 900 MHz with a RLOAD of 50 kQ and a CL of 10 pF. The proposed rectifier in the LP mode has a PCEPEAK— 69% at a PIN— — 21dBm; while operating in the HP mode, it has a PCEPEAK— 75% at a PIN— — 17.5dBm. During the CT mode, it exhibited an improved PINdynamic range performance of 11.5 dB across a 0.8 X PCEPEAKwith an externally provided reference voltage (VREF) of 0.6 V. The CT has a sensitivity of -20.8 dBm to achieve a VOUT of 1 V for an RLOAD of 1MQ.

[0087] FIG. 20 shows a plot of measured peak power conversion efficiency PCEPEAK (in percent or %) as a function of load resistance RLOAD (in kilo-Ohms or kQ) of the rectifier according to various embodiments. The rectifier may have the optimal performance at RLOAD = 50 kQ. However, with an increasing RLOAD, the internal losses in the rectifier may dominate over POUT, resulting in PCE degradation. Furthermore, a higher VOUT may be generated at a much lower PIN, which prematurely switches the polarity of the n-MOS bias and shifts the operating conditions between the p-MOS and n-MOS, resulting in a degraded kzk when therectifier is operating in the CT mode. On the other hand, PCE also degrades with further reducing RLOAD as RIN / RLOAD reduces the VOUT / 2|VRFP| despite an increase to IOUT / IINTERNAL; RIN is the inverse of the real admittance of the rectifier and IINTERNAL is the internal current of the rectifier. The PCE profile can be tuned by varying VREF- FIG. 21 shows a plot of measured power conversion efficiency PCE (in percent or %) as a function of input power PIN (in decibels-milliwatts or dBm) with a load resistance RLOAD of 50 kQ at various reference voltages VREF according to various embodiments.

[0088] FIG. 22 shows a table comparing the performance of the rectifier according to various embodiments with state-of-the-art rectifiers. The proposed switchable polarity bias according to various embodiments can provide a PIN dynamic range of 11.5 dB and 17 dB to maintain a PCE > 0.8XPCEPEAK (PR1 , i.e., PIN range 1 ) and PCE > 20% (PR2, i.e., Pi\ range 2) at a RLOAD of 50 kQ, respectively. The sensitivity of the proposed rectifier characterized at 100 kQ may be comparable to other work, but it may fare 2 dB higher than some devices (References 4, 6) due to an increase in the parasitic loading on the n-MOS. Under the VOUT = 1 V condition for sensitivity characterization, the proposed rectifier according to various embodiments operating in high PIN with negative polarity bias at the gate terminal of the n- MOS which degrades the sensitivity. Despite this trade-off, the proposed rectifier may achieve a better PR1 and PR2 than the abovementioned devices (References 4, 6). Wider PR2 may be achieved by improving the low PIN performance with the use of native devices with three configuration modes for Reference 1, while dynamic body bias was implemented on top of self-biasing for Reference 3. On the other hand, the study in Reference 2 uses a Dickson rectifier in the last stage of a 3-stagc rectifier to minimize IREV at high PIN, thereby changing the PCE degradation characteristic and achieving an additional PIN dynamic range. To normalize the performance of the rectifiers, the figure-of-merits (FOM) #1 has been modified from a reference work by including the number of stages (N) and determining the PIN range for PCE > 0.8XPCEPEAK (PR1), as it will allow the assessment of the rectifier’s PCE capability per stage while also examining the PCE profile's quality. The proposed rectifier according to various embodiments shows an improved FOM #1 of 9.48 dB / stage compared to other works.

[0089] Various embodiments may relate to a switchable polarity bias scheme that enhanced the PIN dynamic range of a differential CMOS rectifier. It may achieve a PCEPEAK of 72.1% and a PIN dynamic range of 11.5 dB for PCE > 0.8XPCEPEAK for RLOAD = 50 kQ. The PIN dynamic range enhancement may be achieved by producing different polarity biasing to adaptthe overdrive voltage at the n-MOS: positive during low PIN and negative during high PIN. The switching of the polarity may change the optimal operating condition of the rectifier, thereby resulting in two distinct PCE peaks. Having two PCE peaks from a single rectifier may be desirable as multiple rectifiers are commonly used in literature to address the different PIN domains. The switchover may be performed with an auxiliary low-power comparator to monitor the VOUT and compare it with a VREF to trigger a VMODE signal. The control signal VMODE may be simple compared to other similar adaptive bias which requires extensive control circuits to generate a continuous analog bias on the gate terminal of the n-MOS. The mode pin may allow trimming to be performed externally or adjusted by the control of the cascading DC-DC boost converter in an Intemet-Of-Things (loT) application. The p-MOS may also be biased positively during high PIN to reduce the reverse conduction loss. The proposed rectifier may be implemented in a 40 nm process node operating at 900 MHz. The proposed rectifier may have an improved dynamic range PR1 of 11.5 dB while maintaining a PCE above 80% of its PCEPEAK despite having a simpler implementation compared with other state-of-the-art rectifiers.

Claims

Claims1. A rectifier comprising : a complementary cross-coupled circuit arrangement configured to generate a direct current (DC) output voltage based on a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage, the complementary cross-coupled circuit arrangement comprising: a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal; a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal; a first p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor; a second p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor; a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor; and a second n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor; a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement; and a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement; wherein the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement is configured to switch between a first biasing mode and a secondbiasing mode to change a polarity of a bias voltage to the first n-channcl metal oxide semiconductor (n-MOS) core transistor or the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary crosscoupled circuit arrangement based on a mode voltage applied to the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement.

2. The rectifier according to claim 1, wherein the p-channcl metal oxide semiconductor (p-MOS) bias circuit arrangement comprises: a first p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor; a second p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor; a first p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the second p- MOS bias circuit arrangement bias capacitor; and a second p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the first p- MOS bias circuit arrangement bias capacitor.

3. The rectifier according to claim 2, wherein a drain electrode of the first p-channel metal oxide semiconductor (p- MOS) bias transistor is in connection with a gate electrode of the first p- channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the second p-MOS bias circuit arrangement bias capacitor; andwherein a drain electrode of the second p -channel metal oxide semiconductor (p-MOS) bias transistor is in connection with a gate electrode of the second p- channcl metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the first p-MOS bias circuit arrangement bias capacitor.

4. The rectifier according to claim 3. wherein a source electrode of the first p-channcl metal oxide semiconductor (p-MOS) bias transistor is in electrical connection with a source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement; and wherein a source electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor is in electrical connection with a source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross -coupled circuit arrangement.

5. The rectifier according to claim 4, wherein the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement is configured to switch between the first biasing mode and the second biasing mode; and wherein the p-metal oxide semiconductor (p-MOS) bias circuit arrangement is configured such that during the second biasing mode, a current flows from the source electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second p- channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the second p-channcl metal oxide semiconductor (p-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

6. The rectifier according to claim 5, wherein the rectifier is configured such that a current flows from a drain electrode of the first p-channcl metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement to the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage; and wherein the rectifier is further configured such that a current flows from a drain electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement to the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

7. The rectifier according to claim 6, further comprising: a load capacitor connected to the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary crosscoupled circuit arrangement, and the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement.

8. The rectifier according to any one of claims 2 to 7, wherein a threshold voltage of the first p-channel metal oxide semiconductor (p-MOS) bias transistor is higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p- channel metal oxide semiconductor (p-MOS) core transistor, the first n- channcl metal oxide semiconductor (n-MOS) core transistor and the second n- channel metal oxide semiconductor (n-MOS) core transistor; and wherein a threshold voltage of the second p-channcl metal oxide semiconductor (p-MOS) bias transistor is also higher than a threshold voltageof each of the first p-channcl metal oxide semiconductor (p-MOS) core transistor, the second p-channel metal oxide semiconductor (p-MOS) core transistor, the first n-channcl metal oxide semiconductor (n-MOS) core transistor and the second n-channel metal oxide semiconductor (n-MOS) core transistor.

9. The rectifier according to any one of claims 1 to 8, wherein the n-mctal oxide semiconductor (n-MOS) bias circuit arrangement comprises: a first n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor; a second n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor; a first n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the first n-channel metal oxide semiconductor (n-MOS) core tran istor; a second n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor;a third n-channcl metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage; a fourth n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage; a first bias resistor having a first terminal in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n- MOS) bias transistor and the source electrode of the third n-channcl metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor; and a second bias resistor having a first terminal in electrical connection with a gate electrode of the third n-channel metal oxide semiconductor (n-MOS) bias transistor and the source electrode of the fourth n- channcl metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor.

10. The rectifier according to claim 9, wherein the n-metal oxide semiconductor (n-MOS) bias circuit arrangement is configured such that during the first biasing mode, a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the first n-channcl metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current(AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second n- channcl metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

11. The rectifier according to claim 9 or claim 10, wherein the n-metal oxide semiconductor (n-MOS) bias circuit arrangement is configured such that during the second biasing mode, a current flows from the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage, and a current flows from the drain electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

12. The rectifier according to any one of claims 9 to 11, wherein the rectifier is configured such that a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement to a drain electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage; and wherein the rectifier is further configured such that a current flows from the source electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement to a drain electrode of the second n-channel metal oxide semiconductor (n-MOS)core transistor of the complementary cross-coupled circuit arrangement when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

13. The rectifier according to any one of claims 9 to 12, wherein an on-resistance of the third n-channel metal oxide semiconductor (n- MOS) bias transistor is less than an on-resistance of the first bias resistor; and wherein an on-rcsistancc of the fourth n-channcl metal oxide semiconductor (n-MOS) bias transistor is less than an on-resistance of the second bias resistor.

14. A method of forming a rectifier, the method comprising: forming a complementary cross-coupled circuit arrangement configured to generate a direct current (DC) output voltage based on a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage, the complementary cross-coupled circuit arrangement comprising: a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal; a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal; a first p-channcl metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor; a second p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor; a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor; anda second n-channcl metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor; forming a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement; and forming a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement; wherein the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement is configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channel metal oxide semiconductor (n-MOS) core transistor or the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary crosscoupled circuit arrangement based on a mode voltage applied to the n-channcl metal oxide semiconductor (n-MOS) bias circuit arrangement.

15. The method according to claim 14, wherein the p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement comprises: a first p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the second p-channel metal oxide semiconductor (p-MOS) core tran istor; a second p-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current input voltage, and a second terminal in electrical connection with a gate electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor;a first p-channcl metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the second p- MOS bias circuit arrangement bias capacitor; and a second p-channel metal oxide semiconductor (p-MOS) bias transistor being diode-configured and in electrical connection with the first p- MOS bias circuit arrangement bias capacitor.

16. The method according to claim 15, wherein a drain electrode of the first p-channel metal oxide semiconductor (p- MOS) bias transistor is in connection with a gate electrode of the first p- channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the second p-MOS bias circuit arrangement bias capacitor; and wherein a drain electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor is in connection with a gate electrode of the second p- channel metal oxide semiconductor (p-MOS) bias transistor and is in connection with the second terminal of the first p-MOS bias circuit arrangement bias capacitor.

17. The method according to claim 16, wherein a source electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor is in electrical connection with a source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement; and wherein a source electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor is in electrical connection with a source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement.

18. The method according to claim 17,wherein the p-channcl metal oxide semiconductor (p-MOS) bias circuit arrangement is configured to switch between the first biasing mode and the second biasing mode; and wherein the p-metal oxide semiconductor (p-MOS) bias circuit arrangement is configured such that during the second biasing mode, a current flows from the source electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the first p-channel metal oxide semiconductor (p-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second p- channel metal oxide semiconductor (p-MOS) bias transistor to the drain electrode of the second p-channel metal oxide semiconductor (p-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

19. The method according to claim 18, wherein the rectifier is configured such that a current flows from a drain electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement to the source electrode of the first p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage; and wherein the rectifier is further configured such that a current flows from a drain electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement to the source electrode of the second p-channel metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

20. The method according to claim 19, further comprising:a load capacitor connected to the source electrode of the first p-channcl metal oxide semiconductor (p-MOS) core transistor of the complementary crosscoupled circuit arrangement, and the source electrode of the second p-channcl metal oxide semiconductor (p-MOS) core transistor of the complementary cross-coupled circuit arrangement.

21. The method according to any one of claims 15 to 20. wherein a threshold voltage of the first p-channcl metal oxide semiconductor (p-MOS) bias transistor is higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p- channel metal oxide semiconductor (p-MOS) core transistor, the first n- channel metal oxide semiconductor (n-MOS) core transistor and the second n- channel metal oxide semiconductor (n-MOS) core transistor; and wherein a threshold voltage of the second p-channel metal oxide semiconductor (p-MOS) bias transistor is also higher than a threshold voltage of each of the first p-channel metal oxide semiconductor (p-MOS) core transistor, the second p-channcl metal oxide semiconductor (p-MOS) core transistor, the first n-channel metal oxide semiconductor (n-MOS) core transistor and the second n-channel metal oxide semiconductor (n-MOS) core transistor.

22. The method according to any one of claims 14 to 21, wherein the n-metal oxide semiconductor (n-MOS) bias circuit arrangement comprises: a first n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor; a second n-MOS bias circuit arrangement bias capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal in electrical connection with a gateelectrode of the first n-channcl metal oxide semiconductor (n-MOS) core transistor; a first n-channcl metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor; a second n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, and a source electrode in electrical connection with a source electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor; a third n-channcl metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the second n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage; a fourth n-channel metal oxide semiconductor (n-MOS) bias transistor having a drain electrode in electrical connection with the second terminal of the first n-MOS bias circuit arrangement bias capacitor, a source electrode in electrical connection with a gate electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor, and a gate electrode for receiving the mode voltage; a first bias resistor having a first terminal in electrical connection with a gate electrode of the first n-channel metal oxide semiconductor (n- MOS) bias transistor and the source electrode of the third n-channcl metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor; anda second bias resistor having a first terminal in electrical connection with a gate electrode of the third n-channel metal oxide semiconductor (n-MOS) bias transistor and the source electrode of the fourth n- channel metal oxide semiconductor (n-MOS) bias transistor, and a second terminal in electrical connection with the source electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor.

23. The method according to claim 22, wherein the n-metal oxide semiconductor (n-MOS) bias circuit arrangement is configured such that during the first biasing mode, a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage, and a current flows from the source electrode of the second n- channcl metal oxide semiconductor (n-MOS) bias transistor to the drain electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage.

24. The method according to claim 22 or claim 23, wherein the n-metal oxide semiconductor (n-MOS) bias circuit arrangement is configured such that during the second biasing mode, a current flows from the drain electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the first n-channel metal oxide semiconductor (n-MOS) bias transistor when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage, and a current flows from the drain electrode of the second n-channel metal oxide semiconductor (n-MOS) bias transistor to the source electrode of the second n-channel metal oxide semiconductor (n-MOS) biastransistor when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

25. The method according to any one of claims 22 to 24, wherein the rectifier is configured such that a current flows from the source electrode of the first n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement to a drain electrode of the first n-channcl metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement when the second input alternating current (AC) input voltage is greater than the first input alternating current (AC) input voltage; and wherein the rectifier is further configured such that a current flows from the source electrode of the second n-channel metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement to a drain electrode of the second n-channcl metal oxide semiconductor (n-MOS) core transistor of the complementary cross-coupled circuit arrangement when the first input alternating current (AC) input voltage is greater than the second input alternating current (AC) input voltage.

26. The method according to any one of claims 22 to 25, wherein an on-resistance of the third n-channel metal oxide semiconductor (n- MOS) bias transistor is less than an on-rcsistancc of the first bias resistor; and wherein an on-resistance of the fourth n-channel metal oxide semiconductor (n-MOS) bias transistor is less than an on-resistance of the second bias resistor.

27. A method of operating a rectifier, the method comprising: providing a first input alternating current (AC) input voltage and a second input alternating current (AC) input voltage to a complementary cross-coupled circuit arrangement, the complementary cross-coupled circuit arrangement configured to generate a direct current (DC) output voltage based on the first input alternating current (AC) input voltage and the second input alternatingcurrent (AC) input voltage, the complementary cross-coupled circuit arrangement comprising: a first core capacitor having a first terminal for receiving the first input alternating current (AC) input voltage, and a second terminal; a second core capacitor having a first terminal for receiving the second input alternating current (AC) input voltage, and a second terminal; a first p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the first core capacitor; a second p-channel metal oxide semiconductor (p-MOS) core transistor in electrical connection with the second terminal of the second core capacitor; a first n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the first core capacitor; and a second n-channel metal oxide semiconductor (n-MOS) core transistor in electrical connection with the second terminal of the second core capacitor; wherein the rectifier also comprises a p-channel metal oxide semiconductor (p-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement; and wherein the rectifier further comprises a n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement in electrical connection with the complementary cross-coupled circuit arrangement; and wherein the method also comprises applying a mode voltage to the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement, the n-channel metal oxide semiconductor (n-MOS) bias circuit arrangement configured to switch between a first biasing mode and a second biasing mode to change a polarity of a bias voltage to the first n-channel metal oxide semiconductor (n- MOS) core transistor or the second n-channel metal oxide semiconductor (n- MOS) core transistor of the complementary cross-coupled circuit arrangement based on the mode voltage.

Images