Display substrate

Abstract

The present disclosure provides a display substrate, comprising a base and a transistor located on one side of the base, the transistor comprising a gate, an active layer, and a first insulating layer, which is located on the side of the active layer facing away from the base and covering the active layer. The first insulating layer comprises a first insulating sub-layer close to the active layer and a second insulating sub-layer away from the active layer, and the oxygen content of the second insulating sub-layer is higher than the oxygen content of the first insulating sub-layer.

Description

Display substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate. Background Art

[0002] With the increasing demand for high-performance displays such as high resolution, high refresh rate, low power consumption, and narrow bezels, the demand for high-mobility oxide transistors is becoming increasingly apparent. Using high-mobility oxide materials as the active layer is the primary method for improving the performance of oxide transistors. However, the increased mobility of high-mobility oxide transistors can easily lead to reduced stability, which is a key constraint on the performance improvement of oxide products.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, comprising a substrate and a transistor located on one side of the substrate, wherein the transistor comprises a gate, an active layer, and

[0005] a first insulating layer located on a side of the active layer facing away from the substrate and covering the active layer; wherein the first insulating layer includes a first insulating sublayer close to the active layer and a second insulating sublayer away from the active layer, and the oxygen content of the second insulating sublayer is higher than that of the first insulating sublayer.

[0006] In some embodiments, the difference in oxygen content between the first insulating sublayer and the second insulating sublayer is in the range of 1-15%.

[0007] In some embodiments, a ratio of a difference in oxygen content between the first insulating sublayer and the second insulating sublayer to the oxygen content of the first insulating sublayer is in a range of 3-10%.

[0008] In some embodiments, the thickness of the first insulating sublayer is The thickness of the second insulating sublayer is

[0009] In some embodiments, the sum of the thickness of the first insulating sublayer and the thickness of the second insulating sublayer is

[0010] In some embodiments, the oxygen content of the first insulating sublayer is less than 65%, and the oxygen content of the second insulating sublayer is greater than 70%.

[0011] In some embodiments, the first insulating layer includes silicon and oxygen, and the first insulating sub-layer and the second insulating sub-layer have different Si—O peak positions.

[0012] In some embodiments, the transistor further includes a second insulating layer located between the gate and the active layer, wherein the second insulating layer contains silicon and oxygen.

[0013] In some embodiments, the oxygen content of the second insulating layer is greater than the oxygen content of the first insulating sublayer and less than the oxygen content of the second insulating sublayer.

[0014] In some embodiments, the Si-O peak position of the first insulating sublayer is smaller than the Si-O peak position of the second insulating layer, and the Si-O peak position of the second insulating layer is smaller than the Si-O peak position of the second insulating sublayer.

[0015] In some embodiments, the second insulating layer includes a third insulating sublayer close to the active layer and a fourth insulating sublayer away from the active layer, and the oxygen content of the fourth insulating sublayer is higher than that of the third insulating sublayer.

[0016] In some embodiments, the thickness of the third insulating sublayer is The thickness of the fourth insulating sublayer is

[0017] In some embodiments, the oxygen content of the fourth insulating sublayer is greater than 70%, and the oxygen content of the third insulating sublayer is less than 65%.

[0018] In some embodiments, the Si—O peak position of the fourth insulating sub-layer is different from the Si—O peak position of the third sub-layer.

[0019] In some embodiments, the oxygen content of the first insulating sublayer and the third insulating sublayer is less than the oxygen content of the second insulating sublayer and the fourth insulating sublayer.

[0020] In some embodiments, the Si—O peak positions of the first insulating sub-layer and the third insulating sub-layer are smaller than the Si—O peak positions of the second insulating sub-layer and the fourth insulating sub-layer.

[0021] In some embodiments, the transistor further includes a first source-drain electrode layer and a second source-drain electrode layer, wherein the second source-drain electrode layer has the same pattern as the first source-drain electrode layer and completely covers the first source-drain electrode layer.

[0022] In some embodiments, the material of the second source-drain electrode layer is an oxidation-resistant metal.

[0023] In some embodiments, a width of a sidewall of the second source-drain electrode layer in a direction parallel to the substrate is greater than 0.5 μm.

[0024] In some embodiments, the thickness of the metal oxide material between the second source-drain electrode layer and the first source-drain electrode layer is less than 0.1 μm.

[0025] In some embodiments, the active layer is located on a side of the gate closer to the substrate, and the first insulating layer is located on a side of the gate farther from the substrate.

[0026] In some embodiments, the difference in oxygen content between the first insulating sublayer and the second insulating sublayer is in the range of 1-15%.

[0027] In some embodiments, a ratio of a difference in oxygen content between the first insulating sublayer and the second insulating sublayer to the oxygen content of the first insulating sublayer is in a range of 3-10%.

[0028] In some embodiments, the thickness of the first insulating sublayer is The thickness of the second insulating sublayer is

[0029] In some embodiments, the oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

[0030] In some embodiments, the first insulating layer includes silicon and oxygen, and the first insulating sub-layer and the second insulating sub-layer have different Si—O peak positions.

[0031] In some embodiments, the active layer includes a channel region and a first end and a second end respectively located on both sides of the channel region, the first end and the second end are conductorized, and the transistor also includes a source electrode and a drain electrode arranged above the active layer, one of the source electrode and the drain electrode is in contact with the first end, and the other of the source electrode and the drain electrode is in contact with the second end.

[0032] In some embodiments, the active layer includes a metal oxide material, and includes a first metal oxide layer and a second metal oxide layer, the second metal oxide layer is located on at least one of the side of the first metal oxide layer facing the substrate or the side away from the substrate, the carrier concentration of the second metal oxide layer is lower than the carrier concentration of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than the band gap of the first metal oxide layer.

[0033] In some embodiments, the material of the second metal oxide layer is the same type as the material of the first metal oxide layer.

[0034] In some embodiments, the active layer contains indium and at least one element selected from gallium, zinc, and tin. The oxygen content of the first metal oxide layer is less than that of the second metal oxide layer. The indium content of the first metal oxide layer is 1%-8% higher than that of the second metal oxide layer.

[0035] In some embodiments, the active layer contains zinc, gallium and rare earth elements, and the contents of zinc, gallium and rare earth elements in the first metal oxide layer are respectively lower than those in the second metal oxide layer.

[0036] In some embodiments, the material of the second metal oxide layer is a different type of material from the material of the first metal oxide layer.

[0037] In some embodiments, the second metal oxide layer is located on a side of the first metal oxide layer facing the substrate and a side away from the substrate, the first metal oxide layer includes a rare earth-doped metal oxide material, the second metal oxide layer located on the side of the first metal oxide layer facing the substrate includes a non-rare earth-doped metal oxide material, and the indium content of the second metal oxide layer located on the side of the first metal oxide layer away from the substrate is lower than the indium content of the first metal oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] FIG1 shows a schematic cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0040] FIG2 shows a schematic diagram of a first silicon oxide layer with a low oxygen content in a first passivation layer protecting an active layer;

[0041] FIG3 is a schematic diagram showing that the second silicon oxide layer with a high oxygen content in the first passivation layer supplements oxygen to the active layer;

[0042] FIG4( a ) shows a SEM cross-sectional view of a transistor in which a silicon oxide stack is used as the first passivation layer;

[0043] FIG4( b ) shows an SEM cross-sectional view of a transistor in which the first passivation layer is formed only with high-oxygen-content silicon oxide;

[0044] FIG5( a ) shows a transfer characteristic curve of a transistor using a low-oxygen-content silicon oxide layer as the first passivation layer;

[0045] FIG5( b ) shows a transfer characteristic curve of a transistor using a high oxygen content silicon oxide layer as the first passivation layer;

[0046] FIG5( c ) shows the transfer characteristic curve of a transistor using a low-oxygen content / high-oxygen content silicon oxide stack as the first passivation layer;

[0047] FIG6 shows FT-IR test curves of a silicon oxide layer with low oxygen content and a silicon oxide layer with high oxygen content;

[0048] FIG7 shows a schematic cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0049] FIG8 shows a schematic cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0050] FIG9 shows a schematic cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0051] FIG10 is a schematic diagram of a channel defect state and a channel trapped center of a rare earth element-doped oxide material in the related art;

[0052] FIG11 is a diagram showing a transistor PBTS test result in the related art;

[0053] FIG12 is a schematic diagram showing a cross-sectional structure of a transistor according to an embodiment of the present disclosure;

[0054] FIG13 shows a schematic cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0055] FIG14 shows a schematic cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0056] FIG15 is a diagram showing a PBTS test result of a transistor according to an embodiment of the present disclosure;

[0057] FIG16 is a diagram showing NBTIS test results of transistors with single-layer oxide and stacked-layer oxide active layers;

[0058] FIG17 is a TEM cross-sectional view of a stacked oxide structure of an active layer;

[0059] 18( a )-18 ( f ) are schematic cross-sectional views illustrating a process for fabricating a transistor according to an embodiment of the present disclosure;

[0060] FIG19 is a schematic cross-sectional view showing a process for manufacturing a transistor according to an embodiment of the present disclosure;

[0061] FIG20 is a schematic cross-sectional view showing a process for manufacturing a transistor according to an embodiment of the present disclosure;

[0062] FIG21 is a schematic cross-sectional view showing a process for manufacturing a transistor according to an embodiment of the present disclosure;

[0063] FIG22 is a schematic cross-sectional view showing a process for manufacturing a transistor according to an embodiment of the present disclosure;

[0064] FIG23 is a schematic cross-sectional view showing a transistor fabrication process according to an embodiment of the present disclosure.

[0065] It should be understood that the accompanying drawings are merely schematic illustrations of exemplary embodiments of the present disclosure and are not intended to limit the present disclosure, and need not be drawn strictly to scale. In addition, in the accompanying drawings, the same or similar reference numerals are used to refer to the same or similar components. DETAILED DESCRIPTION

[0066] At present, the use of high-mobility oxide materials as active layers is the mainstream method for improving the performance of oxide transistors. In order to improve the problem that high-mobility oxide materials are prone to causing negative bias in transistors and other characteristics, it is usually necessary to supplement oxygen in the active layer through a high-oxygen-content dielectric layer, among which the insulating layer adjacent to the active layer is a key film layer that affects the characteristics. However, the high power used when depositing the insulating layer with a high oxygen content will cause damage to the channel. In addition, the insulating layer with a high oxygen content is also prone to cause severe oxidation of the source and drain metal layers, resulting in damage to the device structure. The structure of the oxide transistor in the related art has contradictions in the two aspects of channel oxygen supplementation and avoiding channel damage and avoiding oxidation of the source and drain metal layers, which are difficult to take into account.

[0067] At the same time, the inventors also realized that when the high mobility (20-40cm 2 / Vs) oxide transistors and ultra-high mobility (greater than 40cm 2 When a single-layer high-mobility oxide material is used as the active layer of a (Vs mobility) oxide transistor, it is easily affected by impurity elements such as H in the passivation layer or the etching solution during the source and drain patterning process, forming a large number of defects in the back channel or a large number of defect states in the channel, resulting in a significant decrease in stability and seriously affecting device characteristics.

[0068] The inventors of this application have proposed a transistor display substrate comprising a substrate and a transistor located on one side of the substrate. The substrate is characterized in that the insulating layer adjacent to the active layer is configured as a low-oxygen / high-oxygen stacked structure, wherein the side closest to the active layer utilizes a low-oxygen insulating layer, while the side further from the active layer utilizes a high-oxygen insulating layer. This structure protects the active layer from plasma damage caused by high-power deposition. Furthermore, it reduces oxidation of the metal in the source and drain electrode layers, preventing structural damage caused by severe oxidation. Furthermore, the high-oxygen insulating layer undergoes an annealing process, replenishing oxygen to the active layer through diffusion, thereby improving characteristics such as negative bias that are common in high-mobility oxide transistors and ensuring high-performance device characteristics.

[0069] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0070] It should be understood that the various drawings in the embodiments of the present disclosure are merely schematic illustrations of the connections between the various components. The sizes of the components in the drawings are not drawn to scale, and their relative positions do not necessarily correspond exactly to their actual positions. In the drawings, the proportions of certain regions and layers may be exaggerated for clarity.

[0071] Typically, a transistor includes a gate, an active layer, a source, and a drain. An embodiment of the present disclosure provides a display substrate comprising a substrate and a transistor located on one side of the substrate. FIG1 shows a cross-sectional schematic diagram of a transistor according to an embodiment of the present disclosure. As shown in FIG1 , the transistor includes a gate 12, a gate insulating layer 13 / 14, an active layer 15, a drain 16, a first passivation layer 171 / 172, a second passivation layer 18, etc., which are sequentially arranged on a substrate 11. The transistor shown in FIG1 is a bottom-gate structure, that is, the active layer 15 is located on the side of the gate 12 away from the substrate 11. The active layer 15 may include a high-mobility metal oxide material, wherein the first passivation layer includes a first insulating layer, the first insulating layer includes a first insulating sublayer 171 close to the active layer and a second insulating sublayer 172 away from the active layer, and the oxygen content of the second insulating sublayer 172 is higher than the oxygen content of the first insulating sublayer 171.

[0072] It should be noted that the first insulating layer may include multiple sublayers. Multiple sublayers may refer to layer structures with obvious interfaces between each other at the microscopic level, or may refer to layer structures with different materials, or layer structures containing the same element but with different element contents and no obvious interfaces.

[0073] In the transistor embodiment shown in FIG1 , the first passivation layer utilizes a stacked structure of a first insulating layer, wherein a first silicon oxide layer 171 located near the active layer 15 utilizes silicon oxide with a low oxygen content, while a second silicon oxide layer 172 located further away from the active layer 15 utilizes silicon oxide with a high oxygen content. This structure, on the one hand, prevents plasma damage caused by the high power plasma used to directly deposit high-oxygen-content silicon oxide on the active layer, thereby protecting the active layer. Furthermore, this structure reduces the oxidation of the metal in the source and drain electrode layers, preventing structural damage caused by severe oxidation of the metal in the source and drain electrode layers. Furthermore, the high-oxygen-content silicon oxide layer undergoes an annealing process, replenishing oxygen to the active layer through diffusion. This improves characteristics such as negative bias that are common in high-mobility oxide transistors, ensuring high-performance device characteristics.

[0074] Figure 2 shows a schematic diagram of a low-oxygen-content first silicon oxide layer in the first passivation layer protecting the active layer. Figure 3 shows a schematic diagram of a high-oxygen-content second silicon oxide layer in the first passivation layer supplementing oxygen to the active layer. After the device is immersed in hydrofluoric acid and then inspected under a scanning electron microscope, the various film layers can be clearly distinguished. Figure 4(a) shows an SEM cross-sectional view of a transistor in which the first passivation layer uses a low-oxygen-content / high-oxygen-content silicon oxide stack; wherein, the film layer indicated by PVX1-1 Bottom SiO corresponds to the low-oxygen-content first silicon oxide layer 171 in the first passivation layer in Figure 1, the film layer indicated by PVX1-1 Top SiO corresponds to the high-oxygen-content second silicon oxide layer 172 in the first passivation layer in Figure 1, the film layer indicated by PVX1-2 SiN corresponds to the second passivation layer 18 in Figure 1, and the structure indicated by SD corresponds to the source-drain metal layer 16 in Figure 1. Figure 4(b) shows an SEM cross-sectional view of a transistor whose first passivation layer uses only high-oxygen silicon oxide. The film layer indicated by PVX1-1 SiO corresponds to the first passivation layer using only high-oxygen silicon oxide, the film layer indicated by PVX1-2 SiN corresponds to the second passivation layer, and the structure indicated by SD corresponds to the source and drain metal layers. It should be understood that the thickness of the oxide layer of the source and drain metal layers is not significantly correlated with the thickness of the source and drain metal layers themselves. The metal oxidation of the source and drain electrode layers is primarily determined by the chamber atmosphere during deposition, rather than the oxygen content within the film after deposition. The high power, high N2O ratio, and high temperature used during the deposition of high-oxygen silicon oxide can easily lead to metal oxidation in the source and drain electrode layers. The metal oxide layer of the source and drain electrode layers primarily appears on the sidewalls of the source and drain electrode layer metal, as indicated by the arrows in Figure 4(b). Metal oxidation in the source and drain electrode layers can potentially lead to cracking of the first passivation layer, so metal oxidation in the source and drain electrode layers should be avoided as much as possible. By using the silicon oxide low-oxygen content / high-oxygen content stack proposed in the present invention as the first passivation layer, as shown in Figure 4(a), a low-oxygen content silicon oxide layer is first deposited on the source and drain metal layer, which can effectively prevent the side walls of the source and drain electrode layer metal from being oxidized, thereby avoiding the risk of cracking the first passivation layer.

[0075] Figure 5(a) shows the transfer characteristic curves of a transistor using a low-oxygen silicon oxide layer as the first passivation layer; Figure 5(b) shows the transfer characteristic curves of a transistor using a high-oxygen silicon oxide layer as the first passivation layer; and Figure 5(c) shows the transfer characteristic curves of a transistor using a low-oxygen / high-oxygen silicon oxide stack as the first passivation layer. As can be seen from Figures 5(a)-5(c), the Id-Vg characteristics of the transistor using the low-oxygen / high-oxygen silicon oxide stack as the first passivation layer are significantly better than those of the transistor using only a low-oxygen silicon oxide layer or only a high-oxygen silicon oxide layer as the first passivation layer.

[0076] In some embodiments, the difference in oxygen content between the first insulating sublayer and the second insulating sublayer is in the range of 1-15%. Optionally, the difference in oxygen content between the first insulating sublayer and the second insulating sublayer is in the range of 2-5%.

[0077] In some embodiments, a ratio of a difference in oxygen content between the first insulating sublayer and the second insulating sublayer to the oxygen content of the first insulating sublayer is in a range of 3-10%.

[0078] In the present disclosure, oxygen content refers to the atomic percentage content of oxygen element in the target film layer or target area obtained by certain testing means, and the testing means include but are not limited to EDX, DSIMS or Tof-SIM.

[0079] In some embodiments, the thickness of the first insulating sublayer 171 may be The thickness of the second insulating sublayer 172 can be Optionally, the sum of the thickness of the first insulating sublayer and the thickness of the second insulating sublayer is

[0080] In some embodiments, the first insulating layer includes silicon and oxygen, and the Si-O peak positions of the first insulating sublayer and the second insulating sublayer are different. FIG6 shows FT-IR test curves of a low-oxygen silicon oxide layer and a high-oxygen silicon oxide layer, wherein arrow 1 indicates the FT-IR test curve of the first silicon oxide layer with low oxygen content, and arrow 2 indicates the FT-IR test curve of the second silicon oxide layer with low oxygen content. In some embodiments, the Si-O peak position of the first silicon oxide layer is less than 1062 cm -1 The Si-O peak of the second silicon oxide layer is greater than 1064 cm -1 .

[0081] The oxygen content of the first silicon oxide layer and the second silicon oxide layer can also be tested by EDS. In some embodiments, the oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

[0082] In some embodiments, as shown in FIG1 , the gate insulating layer of the transistor may include a silicon nitride layer 13 located on the gate 12 and a second insulating layer 14 located on a side of the silicon nitride layer facing away from the gate. Optionally, the oxygen content of the first silicon oxide layer 171 is less than that of the second insulating layer 14, and the oxygen content of the second insulating layer 14 is less than that of the second silicon oxide layer 172. Optionally, the Si-O peak position of the first silicon oxide layer 171 is less than that of the second insulating layer 14, and the Si-O peak position of the third silicon oxide layer 14 is less than that of the second silicon oxide layer 142.

[0083] In some embodiments, as shown in Figure 7, the second insulating layer in the gate insulating layer includes a stacked structure 141 / 142, that is, the second insulating layer includes a third insulating sublayer 142 close to the active layer 15 and a fourth insulating sublayer 141 away from the active layer 15, and the oxygen content of the fourth insulating sublayer 141 is higher than the oxygen content of the third insulating sublayer 142.

[0084] In the embodiment shown in FIG7 , a stacked silicon oxide layer is used in the gate insulating layer. By using a high-oxygen-content silicon oxide layer in the fourth insulating sublayer 141 away from the active layer 15 , hydrogen diffusion of the silicon nitride layer 13 of the gate insulating layer during the annealing process can be blocked. By using a low-oxygen-content silicon oxide layer in the third insulating sublayer 142 close to the active layer 15 , interface defects between the silicon oxide layer of the gate insulating layer and the active layer can be reduced, thereby ensuring high-performance device characteristics.

[0085] In some embodiments, the thickness of the third insulating sublayer 142 is The thickness of the fourth insulating sublayer 141 is

[0086] In some embodiments, the oxygen content of the fourth insulating sublayer 141 is greater than 70%, and the oxygen content of the third insulating sublayer 142 is less than 65%.

[0087] In some embodiments, the Si-O peak position of the fourth insulating sublayer is different from that of the third insulating sublayer. Optionally, the Si-O peak position of the fourth insulating sublayer 141 is greater than 1060 cm - 1 The Si-O peak position of the third insulating sublayer 142 is less than 1055 cm -1 .

[0088] In some embodiments, the oxygen content of the first insulating sub-layer 171 and the third insulating sub-layer 142 is less than the oxygen content of the second insulating sub-layer 172 and the fourth insulating sub-layer 141 .

[0089] In some embodiments, the Si—O peak position of the first insulating sub-layer 171 and the third insulating sub-layer 142 is smaller than the Si—O peak position of the second insulating sub-layer 172 and the fourth insulating sub-layer 141 .

[0090] The embodiment shown in FIG7 shows a stacked silicon oxide structure provided in both the first passivation layer and the gate insulating layer, but this is not essential. Those skilled in the art will appreciate that, in practice, the stacked silicon oxide structure may be provided only in the gate insulating layer, with a high-oxygen-content silicon oxide layer disposed on the side away from the active layer to prevent hydrogen diffusion from the silicon nitride layer of the gate insulating layer during the annealing process, and a low-oxygen-content silicon oxide layer disposed on the side closer to the active layer to reduce interface defects between the silicon oxide layer of the gate insulating layer and the active layer, thereby ensuring high-performance device characteristics.

[0091] Figure 8 shows a schematic cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the transistor's source-drain electrode layer has a double-layer structure. As shown in Figure 8 , the transistor includes a first source-drain electrode layer 161 and a second source-drain electrode layer 162 . The second source-drain electrode layer 162 has the same pattern as the first source-drain electrode layer 161 and completely covers the first source-drain electrode layer 161 .

[0092] By depositing the second source-drain electrode layer 162 on the first source-drain electrode layer 161 , the sidewall of the first source-drain electrode layer 161 can be protected from oxidation.

[0093] In some embodiments, the second source / drain electrode layer may be made of an oxidation-resistant metal. Here, an oxidation-resistant metal may refer to a metal with low electrochemical activity, a low tendency to undergo oxidation reactions with water and oxygen, and chemical stability, thereby preventing the diffusion and penetration of other metals. For example, the second source / drain electrode layer may be made of an alloy such as MO, MoNb, MoNi, or MoNiTi.

[0094] In some embodiments, the thickness of the sidewall of the second source-drain electrode layer in a direction parallel to the substrate (such as the width indicated by W in FIG8 ) is greater than 0.5 μm.

[0095] The transistors shown in FIG1 , FIG7 , and FIG8 are bottom-gate structures, and the inventive concepts disclosed herein are also applicable to transistors with top-gate structures.

[0096] Figure 9 shows a schematic cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the transistor has a top-gate structure. As shown in Figure 9, the transistor includes a light shielding layer 23, a buffer layer 24 / 25, an active layer 26 / 261 / 262, a gate insulating layer 27, a gate 28, an interlayer dielectric layer 301 / 302, a source-drain electrode layer 31, a passivation layer 32, etc., which are sequentially arranged on a substrate 11. The interlayer dielectric layer adopts a stacked structure of a first insulating layer, and the first insulating layer includes a first insulating sublayer 301 close to the active layer and a second insulating sublayer 302 away from the active layer. The oxygen content of the second insulating sublayer 302 is higher than that of the first insulating sublayer 301. In the embodiment shown in Figure 9, the first insulating sublayer 301 can be a first silicon oxide layer 301 with a low oxygen content, and the second insulating sublayer 302 can be a second silicon oxide layer 302 with a high oxygen content.

[0097] In some embodiments, the active layer includes a channel region 26 and a first end 261 and a second end 262 respectively located on both sides of the channel region 26, the first end 261 and the second end 262 are conductorized, and the transistor also includes a source electrode and a drain electrode arranged above the active layer, one of the source electrode and the drain electrode is in contact with the first end 261, and the other of the source electrode and the drain electrode is in contact with the second end 262.

[0098] The transistor shown in FIG9 employs a stacked silicon oxide structure for its interlayer dielectric layer. The first silicon oxide layer 301, located near the active layers 26 / 261 / 262, is constructed with a low oxygen content. This prevents increased resistance in the conductive region due to interlayer dielectric deposition and oxygen addition. It also prevents oxidation of the gate 28 side surfaces, which could damage the structure. The second silicon oxide layer 302, located further away from the active layers 26 / 261 / 262, is constructed with a high oxygen content. This prevents hydrogen diffusion from layers such as the passivation layer during subsequent annealing, allowing oxygen addition to the channel, ensuring device performance.

[0099] In some embodiments, the thickness of the first silicon oxide layer is The thickness of the second silicon oxide layer is

[0100] In some embodiments, the oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

[0101] In some embodiments, the Si-O peak position of the first silicon oxide layer is different from the Si-O peak position of the second silicon oxide layer. Optionally, the Si-O peak position of the first silicon oxide layer is less than 1062 cm -1 The Si-O peak of the second silicon oxide layer is greater than 1064 cm -1.

[0102] In the above embodiments, a single layer of high mobility oxide material is used as the active layer. In the related art, high mobility (20-40 cm 2 / Vs) oxide transistors and ultra-high mobility (greater than 40cm 2 Oxide transistors with high mobility (Vs / Vs mobility) typically use an oxide material doped with a small amount of elements as the active layer, such as oxides doped with rare earth elements and elements such as Ta and W. Rare earth elements include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y), and scandium (Sc). The main elements are materials formed by two or more of In, Ga, Zn, and Sn, such as IZO+rare earth, ITO+rare earth, IZO+rare earth, IGZO+rare earth, and ITZO+rare earth. By adding rare earth materials to the main material, high / ultra-high mobility oxide transistors can be achieved, and the light stability of the transistor can be significantly improved. However, the inventors have realized that this type of oxide material is significantly more sensitive to defects (acceptor state defects), and is prone to voltage resistance, current resistance, and high temperature stability problems. For example, when the gate is biased at high temperatures, the threshold voltage V th Figure 10 is a schematic diagram of the channel defect state and the center of the channel trap of the rare earth element doped oxide material in the related art. Figure 11 is a diagram of the PBTS test results of the transistor in the related art. In the case of the defect shown in Figure 10, the threshold voltage V th Continuous positive offset, as shown in Figure 11, will seriously affect the normal operation of the device. In addition, when rare earth doped oxide is used in back channel etched devices, if the back channel is severely damaged, the threshold voltage V th Continuous negative deviation.

[0103] The present disclosure proposes an active layer with a multi-layer oxide structure, which can solve the above-mentioned problems of insufficient bias stability and insufficient light stability, and effectively improve the stability of the device.

[0104] In an embodiment of the present disclosure, the active layer includes a metal oxide material, and includes a first metal oxide layer and a second metal oxide layer, the second metal oxide layer is located on at least one of a side of the first metal oxide layer facing the substrate or a side away from the substrate, the first metal oxide layer is composed of an oxide material doped with a small amount of elements having a high carrier concentration, the carrier concentration of the second metal oxide layer is lower than the carrier concentration of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than the band gap of the first metal oxide layer.

[0105] Figure 12 shows a schematic diagram of the cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the active layer includes a first metal oxide layer 151 and a second metal oxide layer 152, the second metal oxide layer 152 is located on the side of the first metal oxide layer 151 facing away from the substrate 11, the first metal oxide layer 151 is composed of a small amount of element-doped oxide material with a high carrier concentration, the carrier concentration of the second metal oxide layer 152 is lower than the carrier concentration of the first metal oxide layer 151, and the band gap of the second metal oxide layer 152 is wider than the band gap of the first metal oxide layer 151.

[0106] Figure 13 shows a schematic diagram of the cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the active layer includes a first metal oxide layer 151 and two second metal oxide layers 152, and the second metal oxide layers 152 are respectively located on the side of the first metal oxide layer 151 facing the substrate and the side away from the substrate 11, the first metal oxide layer 151 is composed of a small amount of element-doped oxide material with a high carrier concentration, the carrier concentration of the second metal oxide layer 152 is lower than the carrier concentration of the first metal oxide layer 151, and the band gap of the second metal oxide layer 152 is wider than the band gap of the first metal oxide layer 151.

[0107] Figures 12 and 13 show the arrangement of the active layer in a bottom-gate structure transistor, wherein the first passivation layer is shown as the first insulating layer of a stacked structure. However, this does not represent a limitation of the present disclosure. Those skilled in the art will understand that the improvement scheme proposed in the present disclosure may be adopted for both the active layer and the passivation layer, or only the active layer may be improved. The scheme of improving only the active layer also falls within the scope of protection of the present disclosure.

[0108] The improved active layer solution proposed in this application is also applicable to transistors with a top-gate structure. Figure 14 shows a schematic cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the transistor has a top-gate structure, and the active layer includes a first metal oxide layer 261 and a second metal oxide layer 262. The second metal oxide layer 262 is located on the side of the first metal oxide layer 261 facing the substrate 11. The first metal oxide layer 261 is composed of an oxide material doped with a small amount of elements having a high carrier concentration. The carrier concentration of the second metal oxide layer 262 is lower than that of the first metal oxide layer 261, and the band gap of the second metal oxide layer 262 is wider than the band gap of the first metal oxide layer 261.

[0109] In an embodiment of the present disclosure, the material of the first metal oxide layer may be, for example, an oxide material such as IGZO, ITZO, IZO, IGO, ITO, etc. doped with a small amount of elements, including lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y) and scandium (Sc), tungsten (W), and tantalum (Ta). It may be an impurity composed of one or more of the above elements, such as a Pr-doped IGZO material.

[0110] In some embodiments, the material of the second metal oxide layer 152 / 262 can be the same as the material of the first metal oxide layer 151 / 261. In this disclosure, the term "same material" refers to the same type of metal element in the resulting thin film. The oxygen content of the first metal oxide layer 151 / 261 can be reduced relative to the oxygen content of the second metal oxide layer 152 / 262 by modifying film formation conditions or performing post-processing.

[0111] In some embodiments, the active layer contains indium and at least one element selected from gallium, zinc, and tin. The oxygen content of the first metal oxide layer is less than that of the second metal oxide layer. The indium content of the first metal oxide layer is 1%-8% higher than that of the second metal oxide layer.

[0112] In some embodiments, the active layer contains zinc, gallium and rare earth elements, and the contents of zinc, gallium and rare earth elements in the first metal oxide layer are respectively lower than those in the second metal oxide layer.

[0113] Optionally, the material of the second metal oxide layer 152 / 262 and the material of the first metal oxide layer 151 / 261 can both be rare earth-doped IGZO, the oxygen content of the first metal oxide layer 151 / 261 is less than the oxygen content of the second metal oxide layer 152 / 261, the In content of the first metal oxide layer 151 / 261 is higher than the In content of the second metal oxide layer 152 / 262, and the Zn, Ga, and rare earth element contents of the first metal oxide layer 151 / 261 are lower than the Zn, Ga, and rare earth element contents of the second metal oxide layer 152 / 262, respectively.

[0114] In some embodiments, the material of the second metal oxide layer 152 / 262 and the material of the first metal oxide layer 151 / 261 can be different types of materials. In the present disclosure, different types of materials refer to different types of metal elements in the formed thin films.

[0115] In some embodiments, the material of the first metal oxide layer 151 / 261 can be any one selected from rare earth-doped IGZO, ITZO, IZO, IGO, and ITO, and the material of the second metal oxide layer 152 / 262 is a material containing In different from the first metal oxide layer, and the In content of the first metal oxide layer 151 / 261 is higher than the In content of the second metal oxide layer 152 / 262. For example, the second metal oxide layer 152 / 262 can be IGZO(136), IGZO(423), or IGZO(111).

[0116] In the embodiment shown in Figure 13, the active layer includes a first metal oxide layer 151 and two second metal oxide layers 152, the second metal oxide layers 152 are respectively located on the side of the first metal oxide layer 151 facing the substrate and the side away from the substrate 11, the first metal oxide layer 151 includes a rare earth-doped metal oxide material, the second metal oxide layer 152 located on the side of the first metal oxide layer 151 facing the substrate includes a non-rare earth-doped metal oxide material, and the indium content of the second metal oxide layer 152 located on the side of the first metal oxide layer 151 away from the substrate is lower than the indium content of the first metal oxide layer 151.

[0117] The present disclosure proposes a technical solution of arranging multiple layers of oxide as the active layer, wherein the second metal oxide layer is an oxide with a relatively low carrier concentration, which mainly plays the role of protecting the channel, and it can be a polycrystalline oxide or an amorphous oxide; the first metal oxide layer is an oxide material with a relatively high carrier concentration, and the carrier supply layer mainly plays the role of providing carriers, and it can be a polycrystalline oxide or an amorphous oxide. Through this material selection and structural design,

[0118] It can avoid exposing the channel area to channel defects caused by etching and patterning of the source and drain electrode layer or deposition of other film layers, and significantly improve the stability and mobility of the oxide transistor. Moreover, when the multi-layer oxide film is made of the same material, the deposition of the multi-layer oxide film does not involve adding a mask and etching process. Figure 15 is a PBTS test result diagram of a transistor according to an embodiment of the present disclosure. It can be seen that when the multi-layer metal oxide proposed in the present disclosure is used as the active layer, the threshold voltage V th The positive offset is significantly reduced (compared to the related art shown in FIG11 ), and the positive voltage stability of the oxide transistor is significantly improved.

[0119] Figure 16 shows the NBTIS test results of transistors with single-layer oxide and stacked oxide as active layers. During the NBTIS test for 1 hour, the V th The offset is -3V (the bar graph corresponding to sample 1 in Figure 16), while the V th The offset is only -1.5 V (the bar graph corresponding to sample 2 in FIG16 ). It can be seen that by using the multilayer metal oxide proposed in the present disclosure as the active layer, the negative voltage stability of the oxide transistor is also significantly improved.

[0120] FIG17 is a TEM cross-sectional view of a stacked oxide structure of an active layer.

[0121] According to another aspect of the present disclosure, a method for manufacturing a transistor is provided. Figures 18(a)-18(f) show schematic cross-sectional views of a transistor manufacturing process according to an embodiment of the present disclosure. As shown in Figures 18(a)-18(f), the transistor manufacturing process according to an embodiment of the present disclosure includes: forming a gate metal layer on a substrate 11, and patterning to form a gate 12, to obtain a structure as shown in Figure 18(a); forming a gate insulating layer 13 / 14 on the substrate 11 on which the gate 12 is formed; forming a metal oxide layer on the substrate 11 on which the gate insulating layer 13 / 14 is formed, and patterning to form an active layer 15, to obtain a structure as shown in Figure 18(b); forming a metal on the substrate 11 on which the active layer 15 is formed, and patterning to form a source-drain metal layer 16, A structure as shown in FIG18( c ) is obtained; a passivation layer is formed on the substrate on which the source / drain metal layer 16 is formed, wherein forming a passivation layer on the substrate on which the source / drain metal layer 16 is formed comprises: forming a first silicon oxide layer 171 on the substrate 11 on which the source / drain metal layer 16 is formed, to obtain a structure as shown in FIG18( d ); forming a second silicon oxide layer 172 on the substrate 11 on which the first silicon oxide layer 171 is formed, to obtain a structure as shown in FIG18( e ); wherein the oxygen content of the second silicon oxide layer 172 is higher than the oxygen content of the first silicon oxide layer 171. Next, a second passivation layer 18 and a resin layer 19 are formed and patterned to obtain a structure as shown in FIG18( f ); then, a first transparent conductive layer is formed and patterned to form a first transparent electrode layer 20, a third passivation layer 21 is formed and patterned, a second transparent conductive layer is formed and patterned to form a second transparent electrode layer 22, to obtain a transistor structure as shown in FIG1 .

[0122] In some embodiments, forming a gate insulating layer 13 / 14 on the substrate 11 on which the gate 12 is formed includes: forming a third silicon oxide layer 14 on the substrate 11 on which the gate 12 is formed, wherein the oxygen content of the first silicon oxide layer 171 is less than the oxygen content of the third silicon oxide layer 14, and the oxygen content of the third silicon oxide layer 14 is less than the oxygen content of the second silicon oxide layer 172.

[0123] In some embodiments, as shown in Figure 19, forming a gate insulating layer on the substrate 11 on which the gate 12 is formed includes: forming a fifth silicon oxide layer 141 on the substrate 11 on which the gate 12 is formed; forming a fourth silicon oxide layer 142 on the substrate on which the fifth silicon oxide layer is formed; wherein the oxygen content of the fifth silicon oxide layer 141 is higher than the oxygen content of the fourth silicon oxide layer 142.

[0124] According to another aspect of the present disclosure, a method for manufacturing a transistor is provided. Figures 20(a)-20(d) show schematic cross-sectional views of a transistor manufacturing process according to an embodiment of the present disclosure. As shown in Figures 20(a)-20(d), the transistor manufacturing process according to an embodiment of the present disclosure includes: depositing metal on a substrate 11 and patterning it to form a light shielding layer 23; forming a buffer layer 24 / 25 on the substrate on which the light shielding layer 23 is formed; forming a metal oxide layer on the substrate 11 on which the buffer layer 24 / 25 is formed, and patterning to form an active layer 26 to obtain a structure as shown in Figure 20(a); forming a gate insulating layer 27 on the substrate 11 on which the active layer 26 is formed; forming a gate metal layer on the substrate on which the gate insulating layer 27 is formed, and patterning A gate electrode 28 is formed by patterning to obtain the structure shown in FIG20(b); an interlayer dielectric layer is formed on the substrate 11 on which the gate electrode 28 is formed, wherein forming the interlayer dielectric layer on the substrate on which the gate electrode is formed includes: forming a first silicon oxide layer 301 on the substrate on which the gate electrode is formed to obtain the structure shown in FIG20(c); forming a second silicon oxide layer 302 on the substrate on which the first silicon oxide layer 301 is formed to obtain the structure shown in FIG20(d); wherein the oxygen content of the second silicon oxide layer 302 is higher than the oxygen content of the first silicon oxide layer 301. Next, a metal layer is formed and patterned to obtain a source-drain electrode layer 31, and then a passivation layer 32 and a resin layer 19 are formed and patterned; then, a first transparent conductive layer is formed and patterned to form a first transparent electrode layer 20, a third passivation layer 21 is formed and patterned, and a second transparent conductive layer is formed and patterned to form a second transparent electrode layer 22, thereby obtaining the transistor structure shown in FIG9.

[0125] In the above-mentioned embodiment of fabricating a transistor, forming a metal oxide layer may include: forming a first metal oxide layer 151 on the substrate, as shown in FIG21; and forming a second metal oxide layer 152 after forming the first metal oxide layer 151. Alternatively, forming a metal oxide layer may include: forming a first metal oxide layer 161 on the substrate, as shown in FIG22; and forming the second metal oxide layer 162 before forming the first metal oxide layer. Alternatively, forming a metal oxide layer may include: forming a first metal oxide layer 151 on the substrate, as shown in FIG23; and forming the second metal oxide layer 152 both before and after forming the first metal oxide layer 151. The second metal oxide layer is located on at least one of a side of the first metal oxide layer facing the substrate or a side facing away from the substrate. The first metal oxide layer is composed of an oxide material doped with a small amount of an element having a high carrier concentration. The carrier concentration of the second metal oxide layer is lower than that of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than that of the first metal oxide layer.

[0126] In the accompanying drawings, the thickness of certain areas and layers may be exaggerated for clarity. The same reference numerals in the figures represent the same or similar structures, and their detailed descriptions will be omitted. The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the description of the present disclosure, many specific details are provided so as to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0127] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed above can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0128] Spatially relative terms such as "row," "column," "under," "above," "left," "right," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary term "under" can encompass both orientations of above and below. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0129] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily need to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, those skilled in the art may combine different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0130] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0131] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0132] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0133] As will be appreciated by those skilled in the art, although the various steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in that particular order unless the context clearly indicates otherwise. Additionally or alternatively, multiple steps may be combined into a single step and / or a single step may be broken down into multiple steps and performed. In addition, other method steps may be inserted between steps. An inserted step may represent an improvement to a method such as that described herein, or may be unrelated to the method. In addition, a given step may not be fully completed before the next step begins.

[0134] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a substrate and a transistor located on one side of the substrate, wherein the transistor comprises a gate, an active layer, and a first insulating layer, located on a side of the active layer facing away from the substrate and covering the active layer; wherein, The first insulating layer includes a first insulating sublayer close to the active layer and a second insulating sublayer away from the active layer, and the oxygen content of the second insulating sublayer is higher than that of the first insulating sublayer. 2 . The display substrate according to claim 1 , wherein a difference in oxygen content between the first insulating sublayer and the second insulating sublayer is in a range of 1-15%. 3 . The display substrate according to claim 1 , wherein a ratio of a difference in oxygen content between the first insulating sublayer and the second insulating sublayer to the oxygen content of the first insulating sublayer is in a range of 3-10%.

4. The display substrate according to claim 1, wherein: The thickness of the first insulating sublayer is The thickness of the second insulating sublayer is 5. The display substrate according to claim 4, wherein: The sum of the thickness of the first insulating sublayer and the thickness of the second insulating sublayer is The display substrate according to claim 1 , wherein: The oxygen content of the first insulating sublayer is less than 65%, and the oxygen content of the second insulating sublayer is greater than 70%.

7. The display substrate according to claim 1, wherein: The first insulating layer includes silicon and oxygen, and the first insulating sub-layer and the second insulating sub-layer have different Si—O peak positions.

8. The display substrate according to any one of claims 2 to 7, wherein the transistor further comprises a second insulating layer located between the gate and the active layer, The second insulating layer contains silicon and oxygen.

9. The display substrate according to claim 8, wherein: The oxygen content of the second insulating layer is greater than the oxygen content of the first insulating sublayer and less than the oxygen content of the second insulating sublayer.

10. The display substrate according to claim 8, wherein The Si-O peak position of the first insulating sublayer is smaller than the Si-O peak position of the second insulating layer, and the Si-O peak position of the second insulating layer is smaller than the Si-O peak position of the second insulating sublayer.

11. The display substrate according to claim 8, wherein the transistor The second insulating layer includes a third insulating sublayer close to the active layer and a fourth insulating sublayer away from the active layer. The oxygen content of the fourth insulating sublayer is higher than that of the third insulating sublayer.

12. The display substrate according to claim 11, wherein: The thickness of the third insulating sublayer is The thickness of the fourth insulating sublayer is 13. The display substrate according to claim 11, wherein: The oxygen content of the fourth insulating sublayer is greater than 70%, and the oxygen content of the third insulating sublayer is less than 65%.

14. The display substrate according to claim 11, wherein The Si—O peak position of the fourth insulating sub-layer is different from the Si—O peak position of the third sub-layer.

15. The display substrate according to any one of claims 11 to 14, wherein: The oxygen content of the first insulating sublayer and the third insulating sublayer is smaller than the oxygen content of the second insulating sublayer and the fourth insulating sublayer.

16. The display substrate according to any one of claims 11 to 14, wherein: The Si—O peak positions of the first insulating sublayer and the third insulating sublayer are smaller than the Si—O peak positions of the second insulating sublayer and the fourth insulating sublayer.

17. A transistor according to any one of claims 1 to 16, wherein the transistor further comprises a first source-drain electrode layer and a second source-drain electrode layer, wherein the second source-drain electrode layer has the same pattern as the first source-drain electrode layer and completely covers the first source-drain electrode layer.

18. The display substrate according to claim 17, wherein: The material of the second source-drain electrode layer is an oxidation-resistant metal.

19. The display substrate according to claim 18, wherein: The width of the sidewall of the second source-drain electrode layer in a direction parallel to the substrate is greater than 0.5 μm.

20. The display substrate according to claim 18, wherein The thickness of the metal oxide material between the second source-drain electrode layer and the first source-drain electrode layer is less than 0.1 μm.

21. The display substrate according to claim 1, wherein The active layer is located on a side of the gate closer to the substrate, and the first insulating layer is located on a side of the gate farther from the substrate. 22 . The display substrate according to claim 21 , wherein a difference in oxygen content between the first insulating sublayer and the second insulating sublayer is in a range of 1-15%. 23 . The display substrate according to claim 21 , wherein a ratio of a difference in oxygen content between the first insulating sublayer and the second insulating sublayer to the oxygen content of the first insulating sublayer is in a range of 3-10%.

24. The display substrate according to claim 21, wherein The thickness of the first insulating sublayer is The thickness of the second insulating sublayer is 25. The display substrate according to claim 21, wherein The oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

26. The display substrate according to claim 21, wherein The first insulating layer includes silicon and oxygen, and the first insulating sub-layer and the second insulating sub-layer have different Si—O peak positions.

27. The display substrate according to claim 21, wherein The active layer includes a channel region and a first end and a second end respectively located on both sides of the channel region, the first end and the second end are conductively processed, and the transistor also includes a source electrode and a drain electrode arranged above the active layer, one of the source electrode and the drain electrode is in contact with the first end, and the other of the source electrode and the drain electrode is in contact with the second end.

28. A display substrate according to any one of claims 1 to 27, wherein the active layer comprises a metal oxide material, and comprises a first metal oxide layer and a second metal oxide layer, the second metal oxide layer is located on at least one of a side of the first metal oxide layer facing the substrate or a side away from the substrate, the carrier concentration of the second metal oxide layer is lower than the carrier concentration of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than the band gap of the first metal oxide layer.

29. The display substrate according to claim 28, wherein: The material of the second metal oxide layer is the same as that of the first metal oxide layer.

30. The display substrate according to claim 29, wherein The active layer contains indium and at least one element selected from gallium, zinc, and tin. The oxygen content of the first metal oxide layer is less than that of the second metal oxide layer. The indium content of the first metal oxide layer is 1%-8% higher than that of the second metal oxide layer.

31. The display substrate according to claim 30, wherein: The active layer contains zinc, gallium and rare earth elements, and the contents of zinc, gallium and rare earth elements in the first metal oxide layer are respectively lower than those in the second metal oxide layer.

32. The display substrate according to claim 28, wherein The material of the second metal oxide layer is different from the material of the first metal oxide layer.

33. The display substrate according to claim 28, wherein the second metal oxide layer is located on a side of the first metal oxide layer facing the substrate and a side away from the substrate, the first metal oxide layer comprises a rare earth-doped metal oxide material, the second metal oxide layer located on a side of the first metal oxide layer facing the substrate comprises a non-rare earth-doped metal oxide material, and the indium content of the second metal oxide layer located on a side of the first metal oxide layer away from the substrate is lower than the indium content of the first metal oxide layer.

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