Display substrate and display apparatus

Abstract

A display substrate and a display apparatus, the display substrate comprising a display area (AA) and a border area (BB) located on at least one side of the display area (AA). The border area (BB) is provided with a first power line (VSS) and at least one gate driving circuit (10). Different types of gate driving circuits (10) are sequentially arranged in a direction from the display area (AA) to the border area (BB), and a plurality of gate driving circuits (10) of the same type are arranged in a direction of extension of the border area (BB). The first power line (VSS) comprises a plurality of branch structures, and the plurality of branch structures are arranged in the direction from the display area (AA) to the border area (BB) and extend in the direction of extension of the border area (BB). In a direction perpendicular to the plane on which the display substrate is located, the plurality of branch structures are located on the side of the gate driving circuits (10) away from the substrate, and the orthographic projections of at least part of the branch structures on the substrate at least partially overlap the orthographic projections of at least some types of the gate driving circuits (10) on the substrate.

Description

Display substrate, display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate. In a direction parallel to a plane on which the display substrate is located, the display substrate includes a display area and a frame area located on at least one side of the display area. The frame area is provided with a first power line and at least one gate drive circuit. Different types of gate drive circuits are arranged sequentially along a direction from the display area to the frame area, and multiple gate drive circuits of the same type are arranged along an extension direction of the frame area. The first power line includes multiple branch structures. The multiple branch structures are arranged sequentially along a direction from the display area to the frame area and extend along the extension direction of the frame area.

[0006] In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a base, the multiple branch structures are located on a side of the gate driving circuit away from the base, and the positive projections of at least some of the branch junctions on the base at least partially overlap with the positive projections of at least some types of gate driving circuits on the base.

[0007] In an exemplary embodiment, the at least one type of gate driving circuit includes a first gate driving circuit, and the plurality of branch structures includes a first branch structure;

[0008] An orthographic projection of the first branch structure on the substrate at least partially overlaps with an orthographic projection of the first gate driving circuit on the substrate.

[0009] In an exemplary embodiment, the first gate driving circuit includes a plurality of transistors including an output transistor, and an orthographic projection of the first branch structure on the substrate at least partially overlaps with an orthographic projection of the output transistor in the first gate driving circuit on the substrate.

[0010] In an exemplary embodiment, an orthographic projection of the output transistor in the first gate driving circuit on the substrate is located within a range of an orthographic projection of the first branch structure on the substrate.

[0011] In an exemplary embodiment, the display area includes multiple rows of sub-pixels, the sub-pixels include at least a pixel driving circuit, the pixel driving circuit includes at least one first type of low-temperature polysilicon transistor, the first gate driving circuit is electrically connected to the control electrode of at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one first type of low-temperature polysilicon transistor in the at least one row of sub-pixels.

[0012] In an exemplary embodiment, the at least one first type low temperature polysilicon transistor includes a data write transistor and an initialization transistor.

[0013] In an exemplary embodiment, the at least one type of gate driving circuit further includes a second gate driving circuit and a third gate driving circuit, and the plurality of branch structures further includes a second branch structure and a third branch structure;

[0014] In the direction from the display area to the border area, the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit are arranged in sequence, and the first branch structure, the second branch structure, and the third branch structure are arranged in sequence. The orthographic projection of the second branch structure on the substrate is located between the orthographic projection of the second gate driving circuit on the substrate and the orthographic projection of the third driving circuit on the substrate, and the orthographic projection of the third branch structure on the substrate is located on the side of the orthographic projection of the third gate driving circuit on the substrate away from the orthographic projection of the second gate driving circuit on the substrate.

[0015] In an exemplary embodiment, the display area includes multiple rows of sub-pixels, the sub-pixels include at least a pixel driving circuit, the pixel driving circuit includes at least one oxide transistor, and the second gate driving circuit is electrically connected to the control electrode of at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one oxide transistor in the at least one row of sub-pixels.

[0016] In an exemplary embodiment, the pixel driving circuit also includes at least one second type of low-temperature polysilicon transistor, and the third gate driving circuit is electrically connected to the control electrode of at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels.

[0017] In an exemplary embodiment, the at least one oxide transistor comprises a compensation transistor, and the at least one second type low-temperature polysilicon transistor comprises a light emitting transistor.

[0018] In an exemplary embodiment, in a direction parallel to the plane where the display substrate is located, the border area is located at the periphery of the display area, in a first direction, the gate drive circuit and the first power line are located in the border areas on both sides of the display area, and in a second direction, a binding area is provided in the border area on one side of the display area, and the first direction intersects with the second direction; the display substrate is symmetrical with respect to a first center line, and the first center line is the center line of the display substrate extending along the second direction.

[0019] In an exemplary embodiment, in the border area located on the same side of the display area in the first direction, the first to last levels of multiple gate driving circuits of the same type are arranged in sequence along the direction from the display area to the binding area, and at least some of the signal lines in the last level of at least two gate driving circuits share a signal line on the side close to the binding area.

[0020] In an exemplary embodiment, in the frame region located on the same side of the display area in the first direction, the multiple gate driving circuits include a second gate driving circuit and a third gate driving circuit, and the second gate driving circuit and the third gate driving circuit are arranged in sequence in the direction from the display area to the frame region;

[0021] At least part of the signal lines in the last stage of the second gate driving circuit and the last stage of the third gate driving circuit share a signal line on a side close to the binding domain.

[0022] In an exemplary embodiment, the at least some signal lines include clock signal lines; in a frame region located on the same side of the display region along the first direction, the third gate driving circuit includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; and the second gate driving circuit includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line;

[0023] On a side close to the binding area, the first clock signal line and the fifth clock signal line share a clock signal line, the second clock signal line and the sixth clock signal line share a clock signal line, the third clock signal line and the seventh clock signal line share a clock signal line, and the fourth clock signal line and the eighth clock signal line share a clock signal line.

[0024] In an exemplary embodiment, the at least part of the signal lines includes a high-voltage power line and a low-voltage power line; in a frame area located on the same side of the display area along the first direction, the third gate drive circuit includes a first high-voltage power line, a second high-voltage power line, a first low-voltage power line, and a second low-voltage power line; the second gate drive circuit includes a third high-voltage power line, a fourth high-voltage power line, a third low-voltage power line, and a fourth low-voltage power line;

[0025] On a side close to the binding area, the first high-voltage power line and the third high-voltage power line share a high-voltage signal line, the second high-voltage power line and the fourth high-voltage power line share a high-voltage signal line, the first low-voltage power line and the third low-voltage power line share a low-voltage signal line, and the second low-voltage power line and the fourth low-voltage power line share a low-voltage signal line.

[0026] In an exemplary embodiment, the frame area includes: a first frame area and a second frame area located on both sides of the display area along the second direction, a third frame area and a fourth frame area located on both sides of the display area along the first direction, a first corner area connecting the first frame area and the third frame area, a second corner area connecting the third frame area and the second frame area, a third corner area connecting the second frame area and the fourth frame area, and a fourth corner area connecting the fourth frame area and the first frame area;

[0027] The gate drive circuit and the first power line are located in the third border area and the fourth border area, the first power line and the gate drive circuit located in the third border area extend to the first corner area and the second corner area, the first power line and the gate drive circuit located in the fourth border area extend to the third corner area and the fourth corner area, and the third border area and the fourth border area are symmetrical with respect to the first center line.

[0028] In an exemplary embodiment, the binding area is located in the first border area;

[0029] In the third border area, at least part of the signal lines in the last stage of at least two gate driving circuits share a signal line at one end of the first corner area close to the binding area;

[0030] In the fourth border region, at least some of the signal lines in the last stage of at least two gate driving circuits share a signal line at one end of the fourth corner region close to the binding region.

[0031] In an exemplary embodiment, the branch structure includes a first end and a second end, the first ends of the plurality of branch structures extend to the frame area where the binding area is located, and the second ends of the plurality of branch structures extend to the frame area on a side of the display area away from the binding area;

[0032] Among the multiple branch structures located on the same side of the display area in the first direction, the first ends of the multiple branch structures serve as connecting ends and are connected in the border area where the binding area is located, or the second ends of the multiple branch structures serve as connecting ends and are connected in the border area on the side of the display area away from the binding area.

[0033] In an exemplary embodiment, the display substrate further includes a collecting line of first power lines, the collecting line of the first power lines being located in a frame region where the binding region is located, or in a frame region on a side of the display region away from the binding region; the collecting line of the first power lines being located on the same side of the display region in the first direction and in a direction from the display region to the frame region, the plurality of branch structures including a first branch structure, a second branch structure, and a third branch structure arranged in sequence;

[0034] In a direction perpendicular to the plane of the display substrate, the aggregation line of the first power line is located between the substrate and the first power line, and the orthographic projection of the aggregation line of the first power line on the substrate and the orthographic projection of the connecting end of the third branch structure on the substrate have an overlapping area, and the connecting ends of the first branch structure and the second branch structure are both connected to the connecting end of the third branch structure.

[0035] In an exemplary embodiment, the aggregation line of the first power line and the third branch structure are directly connected in the overlapping area to form a double-layer structure.

[0036] In an exemplary embodiment, the display substrate further includes an auxiliary structure of the third branch structure, the third branch structure and the auxiliary structure of the third branch structure have an overlapping area with an orthographic projection on the substrate, and the third branch structure and the auxiliary structure of the third branch structure are directly connected in the overlapping area;

[0037] The first branch structure, the second branch structure, and the third branch structure are located in the second source-drain metal layer, the aggregation line of the first power line and the auxiliary structure of the third branch structure are located in the first source-drain metal layer; the auxiliary structure of the third branch structure and the aggregation line of the first power line are an integrated structure.

[0038] In an exemplary embodiment, the display substrate further includes an anti-static circuit, a first bending structure is provided at a connection end of the first branch structure and is bent in a direction away from the display area, and a second bending structure is provided at a connection end of the second branch structure and is bent in a direction away from the display area. In a frame area on the same side of the display area, the first bending structure and the second bending structure are arranged sequentially in a direction from the display area to the frame area.

[0039] In the first direction, the anti-static circuit is located between the first bending structure and the second bending structure. In the second direction, the anti-static circuit is located between the connecting end of the first branch structure and the connecting end of the third branch structure.

[0040] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, an anode conductive layer and a cathode layer are sequentially provided on the side of the first power line away from the substrate, the anode conductive layer includes a plurality of switching electrodes, the orthographic projections of the plurality of switching electrodes on the substrate at least partially overlap with the orthographic projections of the cathode layer and the plurality of branch structures on the substrate, the plurality of branch structures of the first power line are electrically connected to the plurality of switching electrodes through a plurality of connecting vias, and the cathode layer is connected to the plurality of switching electrodes.

[0041] In an exemplary embodiment, the plurality of branch structures include a first branch structure, a second branch structure, and a third branch structure, the plurality of switching electrodes include a first switching electrode, a second switching electrode, and a third switching electrode, and the plurality of connection vias include a first connection via, a second connection via, and a third connection via;

[0042] The orthographic projection of the first connecting via on the substrate at least partially overlaps with the orthographic projection of the first branch structure and the first switching electrode on the substrate, the orthographic projection of the second connecting via on the substrate at least partially overlaps with the orthographic projection of the second branch structure and the second switching electrode on the substrate, and the orthographic projection of the third connecting via on the substrate at least partially overlaps with the orthographic projection of the third branch structure and the third switching electrode on the substrate.

[0043] In an exemplary embodiment, the gate driving circuit includes a plurality of transistors and at least one capacitor, and includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate in a direction perpendicular to a plane where the display substrate is located;

[0044] The semiconductor layer includes: active layers of a plurality of transistors in the at least one gate drive circuit;

[0045] The first conductive layer includes: control electrodes of multiple transistors in the at least one gate drive circuit, and a first plate of the at least one capacitor;

[0046] The second conductive layer includes: a second plate of at least one capacitor in the at least one gate drive circuit;

[0047] The third conductive layer includes: first electrodes and second electrodes of a plurality of transistors in the at least one gate driving circuit;

[0048] The fourth conductive layer includes: a plurality of branch structures of the first power line.

[0049] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0050] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0052] FIG1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0053] FIG2 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0054] FIG3 is a schematic diagram showing a partial cross-sectional structure of a display area of ​​a display substrate provided by an embodiment of the present disclosure;

[0055] FIG4 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0056] FIG5 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0057] FIG6 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0058] FIG7 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0059] FIG8 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0060] FIG9 is a schematic structural diagram of a binding area provided by an exemplary embodiment of the present disclosure;

[0061] FIG10 is a schematic diagram showing a structure of a display substrate after a binding area is bent, provided by an exemplary embodiment of the present disclosure;

[0062] FIG11a is an equivalent circuit diagram of a first gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0063] FIG11 b is a planar structural diagram of a first gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0064] FIG12 a is an equivalent circuit diagram of a second gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0065] FIG12 b is a planar structural diagram of a second gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0066] FIG13a is an equivalent circuit diagram of a third gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0067] FIG13 b is a planar structural diagram of a third gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0068] FIG14a is a schematic diagram showing an enlarged structure of a third frame area provided by an exemplary embodiment of the present disclosure;

[0069] FIG14 b is a schematic diagram showing an enlarged structure of a third frame area provided by an exemplary embodiment of the present disclosure;

[0070] FIG14c is a schematic diagram showing an enlarged structure of a third frame area provided by an exemplary embodiment of the present disclosure;

[0071] FIG15a is a schematic diagram showing an enlarged structure of a third frame area provided by an exemplary embodiment of the present disclosure;

[0072] FIG15 b is a schematic structural diagram showing an exemplary embodiment of the present disclosure after an active layer is formed in a third border region;

[0073] FIG15c is a schematic structural diagram showing a third frame region after a first conductive layer is formed therein, according to an exemplary embodiment of the present disclosure;

[0074] FIG15 d is a schematic structural diagram showing a third frame region after a second conductive layer is formed therein, according to an exemplary embodiment of the present disclosure;

[0075] FIG15e is a schematic structural diagram showing a third conductive layer formed in a third border region according to an exemplary embodiment of the present disclosure;

[0076] FIG15f is a schematic structural diagram showing a structure after a fourth conductive layer is formed in a third border region according to an exemplary embodiment of the present disclosure;

[0077] FIG16 is a schematic diagram showing an enlarged structure of a first border area provided by an exemplary embodiment of the present disclosure;

[0078] FIG17 is a schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0080] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0081] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0082] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0083] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0084] In this specification, a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0085] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In addition, the gate electrode can also be called a control electrode. In cases where transistors with opposite polarity are used or the direction of current changes during circuit operation, the functions of "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable. In the embodiments of the present disclosure, the gate electrode can be called a control electrode.

[0086] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0087] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0088] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0089] In this specification, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In this disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0090] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0091] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0092] FIG1 is a schematic diagram of the outer shape of a display device, which has a rectangular shape with rounded corners. The display device may include: a display substrate. In some examples, the display substrate may be a closed polygon including linear edges, a circle or ellipse including curved edges, or a semicircle or semi-ellipse including linear edges and curved edges. In some examples, when the substrate has linear edges, at least some of the corners of the substrate may be curved. When the substrate has a rectangular shape, the portion where adjacent linear edges meet may be replaced with a curve having a predetermined curvature. The curvature may be set according to the position of the curve. For example, the curvature may be varied according to the position where the curve begins, the length of the curve, etc.

[0093] In some examples, as shown in Figure 1, the display substrate may include a display area AA and a peripheral area BB located around the display area. In some examples, the display area AA may include a first edge (lower edge) and a second edge (upper edge) arranged relative to each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged relative to each other in the first direction X. Adjacent edges may be connected by arc-shaped chamfers to form a quadrilateral shape with rounded corners. In some examples, the peripheral area BB may include: a first frame (lower frame) B1 and a second frame (upper frame) B2 arranged relative to each other in the second direction Y, and a third frame (left frame) B3 and a fourth frame (right frame) B4 arranged relative to each other in the first direction X. The first frame B1 is connected to the third frame B3 and the fourth frame B4, and the second frame B2 is connected to the third frame B3 and the fourth frame B4.

[0094] In some examples, as shown in FIG1 , the display area AA includes at least a plurality of sub-pixels PX, a plurality of gate lines G, and a plurality of data lines D. The plurality of gate lines G may extend along a first direction X, and the plurality of data lines D may extend along a second direction Y. The orthographic projections of the plurality of gate lines G and the plurality of data lines D on the substrate intersect to form a plurality of sub-pixel regions, with a sub-pixel PX disposed in each sub-pixel region. The plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light-emitting control signals.

[0095] 1 , the first direction X may be the extending direction (row direction) of the gate lines G in the display area, and the second direction Y may be the extending direction (column direction) of the data lines D in the display area. The first direction X and the second direction Y may be perpendicular to each other.

[0096] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0097] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0098] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure.

[0099] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0100] FIG2 is a schematic diagram of the structure of a display device. In some examples, as shown in FIG2 , the display device may include: a timing controller 201, a data driver 202, a scan driver circuit 203, a light-emitting driver circuit 204, and a display substrate 205. In some examples, the display area of ​​the display substrate 205 may include a plurality of regularly arranged sub-pixels PX. The scan driver circuit 203 may be configured to provide scan signals to the sub-pixels PX along scan lines; the data driver 202 may be configured to provide data voltages to the sub-pixels PX along data lines; the light-emitting driver circuit 204 may be configured to provide light-emitting control signals to the sub-pixels PX along light-emitting control lines; and the timing controller 201 may be configured to control the scan driver circuit 203, the light-emitting driver circuit 204, and the data driver 202.

[0101] In some examples, the timing controller 201 can provide grayscale values ​​and control signals suitable for the specifications of the data driver 202 to the data driver 202. The timing controller 201 can also provide scan clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit 203 to the scan driver circuit 203. The timing controller 201 can also provide light-emission clock signals, light-emission start signals, etc. suitable for the specifications of the light-emission driver circuit 204 to the light-emission driver circuit 204. The data driver 202 can use the grayscale values ​​and control signals received from the timing controller 201 to generate data voltages to be provided to the data lines D1 to Dn. For example, the data driver 202 can sample grayscale values ​​using clock signals and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Dn in units of sub-pixel rows. The scan driver circuit 203 can generate scan signals to be provided to the scan lines S1 to Sm using the scan clock signals, scan start signals, etc. received from the timing controller 201. For example, the scan driver circuit 203 can sequentially provide scan signals having on-level pulses to the scan lines. In some examples, the scan driver circuit 203 can include a shift register that can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a scan clock signal to generate scan signals. The light-emitting driver circuit 204 can generate light-emitting control signals to be provided to the light-emitting control lines E1 to Eo based on the light-emitting clock signal, light-emitting start signal, etc. received from the timing controller 201. For example, the light-emitting driver circuit 204 can sequentially provide light-emitting start signals having off-level pulses to the light-emitting control lines. The light-emitting driver circuit 204 can include a shift register that can sequentially transmit light-emitting start signals provided in the form of off-level pulses to the next-stage circuit under the control of the light-emitting clock signal to generate light-emitting control signals. Where n, m, and o are all natural numbers.

[0102] In some examples, the scan driver circuit and the light driver circuit can be directly disposed on the display substrate. For example, the scan driver circuit can be disposed on the third frame of the display substrate, and the light driver circuit can be disposed on the fourth frame of the display substrate; alternatively, the scan driver circuit and the light driver circuit can be disposed on both the third frame and the fourth frame of the display substrate. In some examples, the scan driver circuit and the light driver circuit can be formed together with the sub-pixels during the process of forming the sub-pixels.

[0103] In some examples, the data driver can be provided on a separate chip or printed circuit board to be connected to the sub-pixels via signal access pins on the display substrate. For example, the data driver can be formed using a chip on glass, a chip on plastic, a chip on film, etc. to form a first frame provided on the display substrate to be connected to the signal access pins. The timing controller can be provided separately from the data driver or integrated with the data driver. However, this embodiment is not limited to this. In some examples, the data driver can be provided directly on the display substrate.

[0104] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0105] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the drive of the anode 301 and the cathode 303. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0106] In an exemplary embodiment, the organic light-emitting layer 302 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0107] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG4 , the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The pixel driving circuit may be connected to seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light emitting signal line E, an initial signal line INIT, a second power line VDD, and a first power line VSS).

[0108] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0109] In an exemplary embodiment, a first end of the storage capacitor C is connected to the second power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0110] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0111] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0112] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the second power line VDD and the first power line VSS based on the potential difference between the control electrode and the first electrode of the third transistor T3.

[0113] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0114] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the second power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the second power line VDD and the first power line VSS, causing the light-emitting device to emit light.

[0115] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0116] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a first power line VSS. The signal of the first power line VSS is a low-level signal, and the signal of the second power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines in the display panel and achieve a narrow bezel of the display panel.

[0117] In an exemplary embodiment, the first and second scan signal lines S1 and S2 , the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the first and second power lines VSS and VDD, and the data signal line D extend in a vertical direction.

[0118] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0119] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor (as shown in FIG4 ), or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor. As shown in FIG5 , it is a schematic diagram of an equivalent circuit of a pixel driving circuit, in which the second transistor T2 is an N-type transistor (i.e., an oxide thin film transistor), the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors (i.e., low-temperature polycrystalline silicon thin film transistors), the active layer of the low-temperature polycrystalline silicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, abbreviated as LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality. As shown in Figure 5, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C. The pixel driving circuit may be connected to 10 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line E, initial signal line INIT, third initial signal line INIT3, second power line VDD, and first power line VSS). Compared with Figure 4, the difference of Figure 5 is that: an eighth transistor T8, a third initial signal line INIT3, a third scan signal line S3 and a fourth scan signal line S4 are newly added, the third scan signal line S3 is connected to the control electrode of the second transistor T2, and the fourth scan signal line S4 is connected to the control electrode of the fourth transistor T4; the second transistor T2 is an N-type transistor, the first scan signal line S1 is also electrically connected to the control electrode of the eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the first node N; the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0120] In an exemplary embodiment, the first initial signal line INIT1 and the second initial signal line INIT2 in FIG. 4 and FIG. 5 may share one initial signal line INIT.

[0121] In some examples, the second power line VDD can be configured to provide a constant second voltage signal to the pixel circuit, the first power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal can be greater than the second voltage signal. The first scan line S1 can be configured to provide a first scan signal to the pixel circuit, the second scan line S2 can be configured to provide a second scan signal to the pixel circuit, the third scan line S3 can be configured to provide a third scan signal to the pixel circuit, the fourth scan line S4 can be configured to provide a fourth scan signal to the pixel circuit, the data line D can be configured to provide a data signal to the pixel circuit, and the emission control line E can be configured to provide an emission control signal to the pixel circuit.

[0122] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0123] A curved edge design can be used on a large-size display panel to maximize the display area and achieve an extremely narrow frame in the display screen, that is, the GOA rotates along with the layout of the pixel circuit. As shown in Figure 6, it is a structural schematic diagram of a display device. The display device may include a display panel, the display panel may include a display substrate, the display substrate may include: a display area AA and a frame area BB located around the display area, the display area AA may include at least one corner area, the frame area BB may include at least one corner area, and the at least one corner area of ​​the display area AA corresponds to the at least one corner area of ​​the frame area BB; a plurality of sub-pixels PX are located in the display area AA; at least some of the sub-pixels PX are located in at least one corner area of ​​the display area AA and are arranged in a stepped manner; a plurality of driving circuits 10 may be provided in at least one corner area of ​​the frame area BB, and the driving circuit 10 may be a gate driver on the array substrate. Array (abbreviated as GOA) circuit, the GOA circuit can be a gate drive circuit, and the gate drive circuit is configured to provide a gate drive signal to the sub-pixel PX in the display area AA (for example, the gate drive signal can be a signal provided to the first scan line S1, the second scan line S2, and the light-emitting control line E in Figure 4).

[0124] In some exemplary embodiments, as shown in Figure 6, the border area BB may also include: a first border area B1 and a second border area B2 located on both sides of the display area AA along the second direction Y, and a third border area B3 and a fourth border area B4 located on both sides of the display area AA along the first direction X; at least one corner area of ​​the border area BB may include: a first corner area C1 connecting the first border area B1 and the third border area B3, a second corner area C2 connecting the third border area B3 and the second border area B2, a third corner area C3 connecting the second border area B2 and the fourth border area B4, and a fourth corner area C4 connecting the fourth border area B4 and the first border area B1.

[0125] In some exemplary embodiments, as shown in FIG. 6 , a plurality of driving circuits 10 may be located in the third frame area B3 , the fourth frame area B4 , the first corner area C1 , the second corner area C2 , the third corner area C3 , and the fourth corner area C4 .

[0126] In some exemplary embodiments, as shown in FIG6 , a first power line VSS may be further provided in the border area BB. In the first direction X, the first power line VSS may be located on a side of the GOA circuit away from the display area AA. For example, in the third border area B3 and the fourth border area B4, the first power line VSS may be located on a side of the GOA circuit away from the display area AA. The cathode of the light-emitting element EL is typically provided as a common electrode layer. The first power line VSS is provided to provide a second voltage signal to the common electrode layer, which in turn provides the second voltage signal to the plurality of light-emitting elements EL. However, the first power line VSS is typically not provided in the corner (rounded) area of ​​the display panel.

[0127] In order to better meet people's needs for various functions and a better screen experience (for example, a display screen with an ultra-high screen-to-body ratio), the design of a display screen with a narrow border has gradually become the mainstream form of display devices. However, in some implementations, the layout of some signal lines and circuits in the display panel makes it impossible for the display panel to achieve a narrow border, or when the border area BB is narrow, the width of the signal line located in the border area BB is small, and there is a technical problem of signal line burns. For example, in the structure shown in Figure 6, the first power line VSS is set on the side of the GOA circuit 10 away from the display area AA, that is, in the third border area B3, the first power line VSS and the GOA circuit 10 are arranged in sequence along the first direction X; in the fourth border area B4, the GOA circuit 10 and the first power line VSS are arranged in sequence along the first direction X. In the narrow border structure, the dimensions of the third border area B3 and the fourth border area B4 along the first direction X are limited, and the dimension (i.e., width) of the first power line VSS along the first direction X is small, and there is a technical problem of burns caused by the small width of the first power line VSS.

[0128] An embodiment of the present disclosure provides a display substrate. The display substrate may include, in a direction parallel to a plane on which the display substrate is located, a display area and a frame area located on at least one side of the display area. The frame area is provided with a first power line and at least one gate drive circuit. Different types of gate drive circuits are arranged sequentially along a direction pointing from the display area to the frame area, and multiple gate drive circuits of the same type are arranged along an extension direction of the frame area. The first power line may include multiple branch structures. The multiple branch structures are arranged sequentially along a direction pointing from the display area to the frame area and extend along the extension direction of the frame area.

[0129] In a direction perpendicular to the plane of the display substrate, the display substrate may include a base, and a plurality of branch structures are located on a side of the gate driving circuit away from the base, and the positive projections of at least some of the branch junctions on the base at least partially overlap with the positive projections of at least some types of gate driving circuits on the base.

[0130] The display substrate provided in this embodiment has multiple branch structures of the first power line arranged in the frame area, which can increase the width of the first power line and reduce the risk of burns caused by the small width of the first power line.

[0131] As shown in FIG7 and FIG8 , in the display substrate provided by the embodiment of the present disclosure, in a direction parallel to the plane of the display substrate, the display substrate may include a display area AA and a frame area BB located on at least one side of the display area AA. The frame area BB may be provided with a first power line VSS and at least one gate driver circuit 10. Different types of gate driver circuits 10 are arranged in sequence along the direction pointing from the display area AA to the frame area BB, and multiple gate driver circuits 10 of the same type are arranged along the extension direction of the frame area BB. The first power line VSS may include multiple branch structures, and the multiple branch structures are arranged in sequence along the direction pointing from the display area AA to the frame area BB and extend along the extension direction of the frame area BB.

[0132] In a direction perpendicular to the plane of the display substrate, the display substrate may include a base, and multiple branch structures are located on a side of the gate driving circuit 10 away from the base, and the positive projections of at least some of the branch junctions on the base at least partially overlap with the positive projections of at least some types of gate driving circuits 10 on the base.

[0133] In an exemplary embodiment, at least one type of gate driving circuit may include a first gate driving circuit 10P, and the plurality of branch structures may include a first branch structure VSS1; the orthographic projection of the first branch structure VSS1 on the substrate may at least partially overlap with the orthographic projection of the first gate driving circuit 10P on the substrate.

[0134] In an exemplary embodiment, the first gate driver circuit 10P may include a plurality of transistors, which may include output transistors. The orthographic projection of the first branch structure VSS1 on the substrate at least partially overlaps with the orthographic projection of the output transistor in the first gate driver circuit 10P on the substrate. In an exemplary embodiment, the orthographic projection of the output transistor in the first gate driver circuit 10P on the substrate may be within the range of the orthographic projection of the first branch structure VSS1 on the substrate.

[0135] In an exemplary embodiment, the display area AA may include multiple rows of sub-pixels, the sub-pixels include at least a pixel driving circuit, the pixel driving circuit may include at least one first type of low-temperature polysilicon transistor, and the first gate driving circuit 10P may be electrically connected to the control electrode of at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels.

[0136] In an exemplary embodiment, at least one first-type low-temperature polysilicon transistor may include a data write transistor and an initialization transistor. As shown in FIG5 , the data write transistor may include a fourth transistor T4 (i.e., the fourth transistor T4 may function as the data write transistor), and the initialization transistor may include a first transistor T1, a seventh transistor T7, and an eighth transistor T8 (i.e., the first transistor T1, the seventh transistor T7, and the eighth transistor T8 may function as the initialization transistor).

[0137] In an exemplary embodiment, the at least one type of gate driving circuit may further include a second gate driving circuit 10N and a third gate driving circuit 10EM, and the plurality of branch structures may further include a second branch structure VSS2 and a third branch structure VSS3;

[0138] In the direction from the display area AA to the border area BB, the first gate driving circuit 10P, the second gate driving circuit 10N, and the third gate driving circuit 10EM are arranged in sequence, and the first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 are arranged in sequence. The orthographic projection of the second branch structure VSS2 on the substrate is located between the orthographic projection of the second gate driving circuit 10N on the substrate and the orthographic projection of the third driving circuit on the substrate. The orthographic projection of the third branch structure VSS3 on the substrate is located on the side of the orthographic projection of the third gate driving circuit 10EM on the substrate away from the orthographic projection of the second gate driving circuit 10N on the substrate.

[0139] In an exemplary embodiment, the pixel driving circuit may include at least one oxide transistor, and the second gate driving circuit 10N is electrically connected to the control electrode of at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scan signal to at least one oxide transistor in at least one row of sub-pixels.

[0140] In an exemplary embodiment, the pixel driving circuit may further include at least one second type of low-temperature polysilicon transistor, and the third gate driving circuit 10EM is electrically connected to the control electrode of at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels.

[0141] In an exemplary embodiment, at least one oxide transistor includes a compensation transistor, and at least one second-type low-temperature polysilicon transistor includes a light-emitting transistor. As shown in FIG5 , the compensation transistor may include a second transistor T2, i.e., the second transistor T2 may function as a compensation transistor, and the light-emitting transistor may include a fifth transistor T5 and a sixth transistor T6, i.e., the fifth transistor T5 and the sixth transistor T6 may function as light-emitting transistors.

[0142] In an exemplary embodiment, in a direction parallel to the plane of the display substrate, the border area BB may be located around the display area AA. In a first direction X, the gate drive circuit 10 and the first power line VSS may be located in the border area BB on both sides of the display area AA. In a second direction Y, the border area BB located on one side of the display area AA is provided with a binding area 63. The first direction X intersects with the second direction Y. The display substrate may be symmetrical with respect to a first center line QQ, which is the center line of the display substrate extending along the second direction Y.

[0143] In an exemplary embodiment, in the frame area BB located on the same side of the display area AA in the first direction X, the first stage 10-1 to the last stage 10-N of the plurality of gate driver circuits 10 of the same type are arranged sequentially along the direction from the display area AA to the binding area 63. At least some signal lines of the last stage of at least two types of gate driver circuits 10 share a common signal line on the side near the binding area. As shown in FIG. 8 , the first stage 10P-1 to the last stage 10P-N of the plurality of first gate driver circuits 10P are arranged sequentially along the direction from the display area AA to the binding area 63.

[0144] In an exemplary embodiment, in the frame area BB located on the same side of the display area AA in the first direction X, the multiple gate driving circuits 10 may include a second gate driving circuit 10N and a third gate driving circuit 10EM. In the direction from the display area AA to the frame area BB, the second gate driving circuit 10N and the third gate driving circuit 10EM are arranged in sequence.

[0145] At least part of the signal lines in the last stage of the second gate driving circuit 10N and the last stage of the third gate driving circuit 10EM share a signal line on a side close to the bonding domain.

[0146] In an exemplary embodiment, as shown in FIG8 , the first stage 10N-1 to the last stage 10P-N of the plurality of second gate driving circuits 10N are arranged in sequence along the direction from the display area AA to the binding area 63 ; the first stage 10EM-1 to the last stage 10EM-N of the plurality of third gate driving circuits 10EM are arranged in sequence along the direction from the display area AA to the binding area 63 .

[0147] In an exemplary embodiment, as shown in Figures 14a to 14c, in a direction perpendicular to the plane of the display substrate, an anode conductive layer and a cathode layer VSS0 are sequentially provided on the side of the first power line VSS away from the substrate. The anode conductive layer may include a plurality of switching electrodes ZM. The orthographic projections of the plurality of switching electrodes ZM on the substrate at least partially overlap with the orthographic projections of the cathode layer VSS0 and the plurality of branch structures on the substrate. The plurality of branch structures of the first power line VSS are electrically connected to the plurality of switching electrodes ZM through a plurality of connecting vias Vm, and the cathode layer VSS0 is connected to the plurality of switching electrodes (for example, directly connected, overlapped connected).

[0148] In an exemplary embodiment, the plurality of branch structures may include a first branch structure VSS1, a second branch structure VSS2, and a third branch structure VSS3, the plurality of switching electrodes ZM may include a first switching electrode ZM1, a second switching electrode ZM2, and a third switching electrode ZM3, and the plurality of connection vias Vm may include a first connection via Vm1, a second connection via Vm2, and a third connection via Vm3;

[0149] The orthographic projection of the first connecting via Vm1 on the substrate at least partially overlaps with the orthographic projection of the first branch structure VSS1 and the first switching electrode ZM on the substrate, the orthographic projection of the second connecting via Vm2 on the substrate at least partially overlaps with the orthographic projection of the second branch structure VSS2 and the second switching electrode ZM on the substrate, and the orthographic projection of the third connecting via Vm3 on the substrate at least partially overlaps with the orthographic projection of the third branch structure VSS3 and the third switching electrode ZM3 on the substrate.

[0150] In an exemplary embodiment, the gate driving circuit 10 may include a plurality of transistors and at least one capacitor, and in a direction perpendicular to the plane where the display substrate is located, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially provided on a base;

[0151] The semiconductor layer may include: an active layer of a plurality of transistors in at least one gate driving circuit 10;

[0152] The first conductive layer may include: control electrodes of multiple transistors in at least one gate driving circuit 10, and a first plate of at least one capacitor;

[0153] The second conductive layer may include: a second plate of at least one capacitor in at least one gate drive circuit 10;

[0154] The third conductive layer may include: first electrodes and second electrodes of multiple transistors in at least one gate driving circuit 10;

[0155] The fourth conductive layer may include a plurality of branch structures of the first power line VSS.

[0156] The technical solutions of the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0157] As shown in Figures 7 and 8, the display substrate may include a display area AA and a border area BB located around the display area AA. The border area BB may include: a first border area B1 and a second border area B2 located on both sides of the display area AA along the second direction Y, a third border area B3 and a fourth border area B4 located on both sides of the display area AA along the first direction X, and at least one corner area; the at least one corner area of ​​the border area BB may include: a first corner area C1 connecting the first border area B1 and the third border area B3, a second corner area C2 connecting the third border area B3 and the second border area B2, a third corner area C3 connecting the second border area B2 and the fourth border area B4, and a fourth corner area C4 connecting the fourth border area B4 and the first border area B1.

[0158] As shown in Figure 8, the display substrate may further include a bonding region 63 located on one side of the display area AA. The bonding region 63 may be located in the first border region B1. In a direction perpendicular to the plane of the display substrate, the display area AA may include a substrate and a plurality of subpixels PX disposed thereon. The plurality of subpixels PX may form multiple rows and columns. The subpixels PX may include pixel driver circuitry and light-emitting devices. The bonding region 63 may include a bonding circuit for connecting signal lines to an external driver device. The third and fourth border regions B3 and B4 may include a gate driver circuit 10 and a first power line VSS that transmits voltage signals to the plurality of subpixels. In an exemplary embodiment, the first power line VSS and gate driver circuit 10 located in the third border region B3 may extend to the first and second corner regions C1 and C2. The first power line VSS and gate driver circuit 10 located in the fourth border region B4 may extend to the third and fourth corner regions C3 and C4. The third and fourth border regions B3 and B4 are symmetrical with respect to the first centerline QQ.

[0159] Figure 9 is an enlarged structural schematic diagram of the first border region B1 in Figure 8. As shown in Figures 8 and 9, within a plane parallel to the display substrate, the first border region B1 may include a first fan-out region 61, a bend region 62, a second fan-out region 631, and a bonding region 63, sequentially arranged along a direction away from the display region AA. The bonding region 63 may include a driver chip region 632 and a bonding electrode region 633, sequentially arranged along the direction away from the bend region 62 from the second fan-out region 631. The first fan-out region 61 may include a data fan-out line, a second power line, and a first power line VSS. The data fan-out line is located in the center of the first fan-out region 61 and includes multiple data connection lines. The multiple data connection lines are configured to connect to the data lines (Data Line) of the display region AA in a fan-out routing manner. The second power line is configured to connect to the high voltage power line (VDD) of the display region AA. The first power line is a low voltage power line (VSS) located in the third and fourth border regions B3 and B4. The bending area 62 may include a composite insulating layer provided with grooves, configured to bend the binding area 63 to the back of the display area AA. The second fan-out area 631 includes a plurality of data connection lines led out in a fan-out routing manner. The driver chip area 632 may be provided with an integrated circuit (IC) 70, configured to be connected to the plurality of data connection lines. The binding electrode area 633 includes a plurality of bonding pads (Bonding Pads), configured to be bound and connected to the flexible printed circuit (FPC) 80. In an exemplary embodiment, the integrated circuit (IC) 400 may be bound and connected to the driver chip area 205, and the flexible printed circuit (FPC) 80 may be bound and connected to the binding electrode area 633. In an exemplary embodiment, the integrated circuit 70 may generate a driving signal required to drive the sub-pixel, and may provide the driving signal to the sub-pixel PX located in the display area AA. For example, the driving signal may be a data signal that controls the luminous brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode region 632 may be provided with a pad (PAD) including a plurality of pins (PINs), and the flexible circuit board 80 may be bonded and connected to the pad.

[0160] 10 , the bending region 62 may reverse the surface of the binding region 63, i.e., the surface of the binding region 63 facing upward may be reversed to face downward by bending the bending region 62. In an exemplary embodiment, when the bending region 62 is bent, the binding region 63 may overlap with the display area AA in the thickness direction of the display panel.

[0161] In an exemplary embodiment, for a large-sized display substrate, multiple data driver ICs and multiple FPCs may be provided. The multiple FPCs are respectively connected to the multiple data driver ICs. For example, four data driver ICs may be provided and respectively connected to four FPCs. The present disclosure is not limited to four ICs and four FPCs. For example, two data driver ICs and two FPCs may be provided. In the present disclosure, the number of data driver ICs and FPCs may be set according to the size and function requirements of the display substrate, and the present disclosure is not limited thereto.

[0162] As shown in Figures 7 and 8, in a plane parallel to the display substrate, in a direction pointing from the display area AA to the third border area B3, the gate driving circuit 10 in the third border area B3 may include a first gate driving circuit 10P, a second gate driving circuit 10N and a third gate driving circuit 10EM arranged in sequence; in a direction pointing from the display area AA to the fourth border area B4, the gate driving circuit 10 in the fourth border area B4 may include a first gate driving circuit 10P, a second gate driving circuit 10N and a third gate driving circuit 10EM arranged in sequence.

[0163] In an exemplary embodiment, the first gate drive circuit 10P can be configured to provide a scan signal to at least a portion of the low-temperature polysilicon transistors in at least one row of sub-pixel circuits, the second gate drive circuit 10N can be configured to provide a scan signal to at least one oxide transistor in at least one row of sub-pixels, and the third gate drive circuit 10EM can be configured to provide a scan signal to at least one light-emitting control transistor in at least one row of sub-pixels. Taking the pixel driving circuit shown in Figure 5 as an example: the first gate driving circuit 10P can be configured to provide scanning signals to the first transistor T1, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 of at least one row of sub-pixel circuits, that is, the first gate driving circuit 10P can include three types. The first type of first gate driving circuit 10P can be configured to provide a first scanning signal to the first scanning signal line S1, the second type of first gate driving circuit 10P can be configured to provide a second scanning signal to the second scanning signal line S2, and the third type of first gate driving circuit 10P can be configured to provide a fourth scanning signal to the fourth scanning signal line S4; the second gate driving circuit 10N can be configured to provide a third scanning signal to the third scanning signal line S3; the third gate driving circuit 10EM can be configured to provide a light-emitting control signal to the light-emitting signal line E.

[0164] In an exemplary embodiment, as shown in Figures 7 and 8, the first power line VSS can be arranged in the third border area B3 and the fourth border area B4. In the direction from the display area AA to the border area BB, the first power line VSS can include a plurality of branch structures arranged in sequence, the first ends of the plurality of branch structures can extend to the first border area B1, the second ends of the plurality of branch structures can extend to the second border area B2, the first ends of the plurality of branch structures can be electrically connected to each other in the first border area B1, or the second ends of the plurality of branch structures can be electrically connected to each other in the second border area B2.

[0165] In an exemplary embodiment, the first power line VSS may include a first branch structure VSS1, a second branch structure VSS2, and a third branch structure VSS3. In the direction from the display area AA to the border area BB, the first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 may be arranged in sequence, wherein the orthographic projection of the first branch structure VSS1 on the substrate at least partially overlaps with the orthographic projection of at least partially the first gate driving circuit 10P on the substrate.

[0166] As shown in Figure 11a, it is an equivalent circuit diagram of a first gate drive circuit 10P, and Figure 11b is a schematic diagram of a planar structure of the first gate drive circuit 10P. The first gate drive circuit 10P can be a 9T3C structure, that is, the first gate drive circuit 10P can include nine transistors and three capacitors. The nine transistors can include a first transistor T101 to a ninth transistor T109, and the three capacitors can include a first capacitor C11 to a third capacitor C13, wherein the circuit connection relationship of the first gate drive circuit 10P is as follows: the control electrode of the first transistor T101 is connected to the clock signal line CK, the first electrode of the first transistor T101 is connected to the first initial signal line STV1, and the second electrode of the first transistor T101 is connected to the first node N11; the control electrode of the second transistor T102 is connected to the third node N13, the first electrode of the second transistor T102 is connected to the second node N12, and the second electrode of the second transistor T102 is connected to the fourth node N14; the control electrode of the third transistor T103 ... The first electrode of the third transistor T103 is connected to the low-voltage power supply line VGL, and the second electrode of the third transistor T103 is connected to the second node N12; the control electrode of the fourth transistor T104 is connected to the second node N12, the first electrode of the fourth transistor T104 is connected to the high-voltage power supply line VGH, and the second electrode of the fourth transistor T104 is connected to the first output terminal OUT1; the control electrode of the fifth transistor T105 is connected to the fifth node N15; the first electrode of the fifth transistor T105 is connected to the clock signal line CB, and the second electrode of the fifth transistor T105 is connected to the first output terminal OUT1; the control electrode of the sixth transistor T106 is connected to the second node N12, the first electrode of the sixth transistor T106 is connected to the sixth node N16, and the second electrode of the sixth transistor T106 is connected to the fourth node N14; the control electrode of the seventh transistor T107 is connected to the third node N13, the first electrode of the seventh transistor T107 is connected to the high-voltage power supply line VGH, and the seventh transistor T107 is connected to the first output terminal OUT1. a second electrode of the eighth transistor T108 is connected to the seventh node N17; a control electrode of the eighth transistor T108 is connected to the low-voltage power supply line VGL, a first electrode of the eighth transistor T108 is connected to the first node N11, and a second electrode of the eighth transistor T108 is connected to the fifth node N15; a control electrode of the ninth transistor T109 is connected to the clock signal line CB, a first electrode of the ninth transistor T109 is connected to the first node N11, and a second electrode of the ninth transistor T109 is connected to the sixth node N16; one plate of the first capacitor C11 is connected to the first output terminal OUT1, and the other plate is connected to the fifth node N15; one plate of the second capacitor C12 is connected to the high-voltage power supply line VGH, and the other plate is connected to the second node N12; one plate of the third capacitor C13 is connected to the low-voltage power supply line VGL, and the other plate is connected to the seventh node N17.

[0167] As shown in FIG12a, an equivalent circuit diagram of a second gate drive circuit 10N is shown. FIG12b is a schematic diagram of a planar structure of the second gate drive circuit 10N. The second gate drive circuit 10N may be a 16T3C structure, that is, the second gate drive circuit 10N may include sixteen transistors and three capacitors. The sixteen transistors may include a first transistor T201 to a sixteenth transistor T216, and the three capacitors may include a first capacitor C21 to a third capacitor C23. The circuit connection relationship of the second gate drive circuit 10N is as follows: the control electrode of the first transistor T201 is connected to the fifth clock signal line CK5, and the first electrode of the first transistor T201 is connected to the second initial signal line STV2. The second electrode of the first transistor T201 is connected to the first node N21; the control electrode of the second transistor T202 is connected to the first node N21, the first electrode of the second transistor T202 is connected to the seventh clock signal line CK7, and the second electrode of the second transistor T202 is connected to the second node N22; the control electrode of the third transistor T203 is connected to the fifth clock signal line CK5, the first electrode of the third transistor T203 is connected to the second low voltage power supply line VGL2, and the second electrode of the third transistor T203 is connected to the second node N22; the control electrode of the fourth transistor T204 is connected to the ninth node N29, the first electrode of the fourth transistor T204 is connected to the sixth clock signal line N26, and the fourth transistor T20 4 is connected to the fifth node N25; the control electrode of the fifth transistor T205 is connected to the second node N22; the first electrode of the fifth transistor T205 is connected to the third high voltage power supply line VGH3, and the second electrode of the fifth transistor T205 is connected to the fifth node N25; the control electrode of the sixth transistor T206 is connected to the sixth node N26, the first electrode of the sixth transistor T206 is connected to the eighth clock signal line CK8, and the second electrode of the sixth transistor T206 is connected to the third node N23; the control electrode of the seventh transistor T207 is connected to the eighth clock signal line CK8, the first electrode of the seventh transistor T207 is connected to the third node N23, and the second electrode of the seventh transistor T207 is connected to the fourth node N2 4; a control electrode of the eighth transistor T208 is connected to the first node N21, a first electrode of the eighth transistor T208 is connected to the fourth high-voltage power line VGH4, and a second electrode of the eighth transistor T208 is connected to the fourth node N24; a control electrode of the ninth transistor T209 is connected to the fourth node N24, a first electrode of the ninth transistor T209 is connected to the fourth high-voltage power line VGH4, and a second electrode of the ninth transistor T209 is connected to the second output terminal OUT2; a control electrode of the tenth transistor T210 is connected to the seventh node N27, a first electrode of the tenth transistor T210 is connected to the third low-voltage power line VGL3, and a second electrode of the tenth transistor T210 is connected to the second output terminal OUT2;The control electrode of the eleventh transistor T211 is connected to the fourth low-voltage power line VGL4, the first electrode of the eleventh transistor T211 is connected to the second node N22, and the second electrode of the eleventh transistor T211 is connected to the sixth node N26; the control electrode of the twelfth transistor T212 is connected to the fourth low-voltage power line VGL4, the first electrode of the twelfth transistor T212 is connected to the first node N21, and the second electrode of the twelfth transistor T212 is connected to the seventh node N27; the control electrode of the thirteenth transistor T213 is connected to the power line VEL, the first electrode of the thirteenth transistor T213 is connected to the fourth high-voltage power line VGH4, and the second electrode of the thirteenth transistor T213 is connected to the first node N21; the control electrode of the fourteenth transistor T214 is connected to the fifth clock signal line CK5, and the first electrode of the fourteenth transistor T214 is connected to the second initial signal line STV 2, a second electrode of the fourteenth transistor T214 is connected to the eighth node N28; a control electrode of the fifteenth transistor T215 is connected to the fourth low-voltage power line VGL4, a first electrode of the fifteenth transistor T215 is connected to the eighth node N28, and a second electrode of the fifteenth transistor T215 is connected to the ninth node N29; a control electrode and a first electrode of the sixteenth transistor T216 are both connected to the ninth node N29, and a second electrode of the sixteenth transistor T216 is connected to the seventh node N27; one plate of the first capacitor C21 is connected to the third node N23, and the other plate is connected to the sixth node N26; one plate of the second capacitor C22 is connected to the fourth high-voltage power line VGH4, and the other plate is connected to the fourth node N24; one plate of the third capacitor C23 is connected to the fifth node N25, and the other plate is connected to the ninth node N29.

[0168] As shown in FIG13a, an equivalent circuit diagram of a third gate drive circuit 10EM is shown. FIG13b is a schematic planar structure diagram of the third gate drive circuit 10EM. The third gate drive circuit 10EM may be a 12T3C structure, that is, the third gate drive circuit 10EM may include twelve transistors and three capacitors. The twelve transistors may include a first transistor T301 to a twelfth transistor T312, and the three capacitors may include a first capacitor C31 to a third capacitor C33. The connection relationship of the third gate drive circuit 10EM is as follows: the control electrode of the first transistor T301 is connected to the first clock signal line CK1, and the first electrode of the first transistor T301 is connected to the third initial signal line ST V3 is connected, the second electrode of the first transistor T301 is connected to the first node N31; the control electrode of the second transistor T302 is connected to the first node N31, the first electrode of the second transistor T302 is connected to the third clock signal line CK3, and the second electrode of the second transistor T302 is connected to the second node N32; the control electrode of the third transistor T303 is connected to the first clock signal line CK1, the first electrode of the third transistor T303 is connected to the second low voltage power supply line VGL2, and the second electrode of the third transistor T303 is connected to the second node N32; the control electrode of the fourth transistor T304 is connected to the seventh node N37, the first electrode of the fourth transistor T304 is connected to the second clock signal line N32, and the fourth transistor T3 The second electrode of the fifth transistor T305 is connected to the fifth node N35; the control electrode of the fifth transistor T305 is connected to the second node N32; the first electrode of the fifth transistor T305 is connected to the second high voltage power supply line VGH1, and the second electrode of the fifth transistor T305 is connected to the fifth node N35; the control electrode of the sixth transistor T306 is connected to the sixth node N36, the first electrode of the sixth transistor T306 is connected to the fourth clock signal line CK4, and the second electrode of the sixth transistor T306 is connected to the third node N33; the control electrode of the seventh transistor T307 is connected to the fourth clock signal line CK4, the first electrode of the seventh transistor T307 is connected to the third node N33, and the second electrode of the seventh transistor T307 is connected to the fourth node N 34; a control electrode of the eighth transistor T308 is connected to the first node N31, a first electrode of the eighth transistor T308 is connected to the first high-voltage power line VGH2, and a second electrode of the eighth transistor T308 is connected to the fourth node N34; a control electrode of the ninth transistor T309 is connected to the fourth node N34, a first electrode of the ninth transistor T309 is connected to the second high-voltage power line VGH2, and a second electrode of the ninth transistor T309 is connected to the third output terminal OUT3; a control electrode of the tenth transistor T310 is connected to the seventh node N37, a first electrode of the tenth transistor T310 is connected to the first low-voltage power line VGL1, and a second electrode of the tenth transistor T310 is connected to the third output terminal OUT3;The control electrode of the eleventh transistor T311 is connected to the second low-voltage power line VGL2, the first electrode of the eleventh transistor T311 is connected to the second node N32, and the second electrode of the eleventh transistor T311 is connected to the sixth node N36. The control electrode of the twelfth transistor T312 is connected to the second low-voltage power line VGL2, the first electrode of the twelfth transistor T312 is connected to the first node N31, and the second electrode of the twelfth transistor T312 is connected to the seventh node N37. One plate of the first capacitor C31 is connected to the third node N33, and the other plate is connected to the sixth node N36. One plate of the second capacitor C32 is connected to the second high-voltage power line VGH2, and the other plate is connected to the fourth node N34. One plate of the third capacitor C33 is connected to the fifth node N35, and the other plate is connected to the seventh node N37.

[0169] In an exemplary embodiment, the second gate driver circuit 10N is not limited to a 16T3C structure, and for example, a 9T3C structure or a 12T3C structure may be employed. The third gate driver circuit 10EM is not limited to a 12T3C structure, and for example, a 9T3C structure or a 16T3C structure may be employed. In an exemplary embodiment, as shown in FIG14a , the first gate driver circuit 10P, the second gate driver circuit 10N, and the third gate driver circuit 10EM may be arranged sequentially along a direction from the display area AA toward the border area BB. The output transistors in the first gate driver circuit 10P may include a fourth transistor T104 and a fifth transistor T105. The fourth transistor T104 and the fifth transistor T105 may be arranged sequentially along the second direction Y. The fourth transistor T104 and the fifth transistor T105 may be located on a side of the second gate driver circuit 10N away from the third gate driver circuit 10EM, that is, the fourth transistor T104 and the fifth transistor T105 may be located on a side closer to the display area AA.

[0170] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the display substrate may include a base, and a semiconductor layer, a first conductive layer (GATE1), a second conductive layer (GATE2), a third conductive layer (SD1), and a fourth conductive layer (SD2) sequentially disposed on the base. In an exemplary embodiment, a first insulating layer is disposed between the active layer and the first conductive layer, a second insulating layer is disposed between the first conductive layer and the second conductive layer, a third insulating layer is disposed between the second conductive layer and the third conductive layer, a fourth insulating layer and a first planarizing layer are disposed between the third conductive layer and the fourth conductive layer (the fourth insulating layer is disposed between the third conductive layer and the first planarizing layer, and the first planarizing layer is disposed between the fourth insulating layer and the fourth conductive layer), and a second planarizing layer is disposed between the fourth conductive layer and the fifth conductive layer. In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, on a side of the fourth conductive layer away from the substrate, the display area AA may further be provided in sequence with: a fifth conductive layer (which may be referred to as an anode conductive layer, including multiple anodes 301), a pixel definition layer, a light-emitting layer (for example, the organic light-emitting layer 302 in FIG. 3 ), and a sixth conductive layer (which may be referred to as a cathode layer VSS0, which may include the cathode 303 in FIG. 3 ). As shown in FIG. 14 b , the anode conductive layer may include multiple switching electrodes ZM, and the orthographic projections of the multiple switching electrodes ZM on the substrate at least partially overlap with the orthographic projections of the cathode layer VSS0 and the multiple branch structures on the substrate, respectively. The multiple switching electrodes ZM may be electrically connected to the multiple branch structures through multiple connecting vias Vm, and the cathode layer VSS0 may extend to the frame area BB and be connected to the multiple switching electrodes ZM (for example, directly connected or overlapped), thereby realizing multiple branch structures (VSS1, VSS2, VSS3, VSS4, VSS5, VSS6, VSS7, VSS8, VSS9, VSS10, VSS11, VSS12, VSS13, VSS14, VSS15, VSS16, VSS17, VSS18, VSS19, VSS20, VSS21, VSS22, VSS23, VSS24, VSS17, VSS25, VSS26, VSS18, VSS27, VSS28, VSS29, VSS30, VSS31, VSS32, VSS33, VSS34, VSS35, VSS36, VSS37, VSS38, VSS39, VSS40, VSS41, VSS42, VSS43, VSS44, VSS50, VSS51, VSS52, VSS53, 2. Electrical connection between the cathode layer VSS0 and the cathode layer VSS3. For example, a plurality of connection vias Vm are provided on the second planar layer (PLN2). The connection vias Vm may include a first connection via Vm1, a second connection via Vm2, and a third connection via Vm2. The plurality of transfer electrodes ZM may include a first transfer electrode ZM1, a second transfer electrode ZM2, and a third transfer electrode ZM3. The orthographic projection of the first connection via Vm1 on the substrate at least partially overlaps with the orthographic projection of the first branch structure VSS1 and the first transfer electrode ZM1 of the first power line VSS on the substrate. The orthographic projection of the second connection via Vm2 on the substrate at least partially overlaps with the orthographic projection of the second branch structure VSS2 and the second transfer electrode ZM2 of the first power line VSS on the substrate. The orthographic projection of the third connection via Vm3 on the substrate at least partially overlaps with the orthographic projection of the third branch structure VSS3 and the third transfer electrode ZM3 of the first power line VSS on the substrate. In an exemplary embodiment, the cathode layer VSS0 may be connected to the plurality of organic light-emitting layers 302 in the display area AA.

[0171] In an exemplary embodiment, the semiconductor layer may include: an active layer of the first transistor T101 to the ninth transistor T109 in the first gate driving circuit 10P, an active layer of the first transistor T201 to the sixteenth transistor T216 in the second gate driving circuit 10N, and an active layer of the first transistor T301 to the twelfth transistor T212 in the third gate driving circuit 10EM; wherein, a planar structural schematic diagram of the semiconductor layer of the first gate driving circuit 10P to the third gate driving circuit 10EM may be shown in Figure 15b.

[0172] The first conductive layer may include: control electrodes of the first transistor T101 to the ninth transistor T109 in the first gate drive circuit 10P, control electrodes of the first transistor T201 to the sixteenth transistor T216 in the second gate drive circuit 10N, control electrodes of the first transistor T301 to the twelfth transistor T212 in the third gate drive circuit 10EM, first plates of the first capacitor C11 to the third capacitor C13 in the first gate drive circuit 10P, first plates of the first capacitor C21 to the third capacitor C23 in the second gate drive circuit 10N, and first plates of the first capacitor C31 to the third capacitor C33 in the third gate drive circuit 10EM; wherein, a schematic diagram of the planar structure of the first conductive layer of the first gate drive circuit 10P to the third gate drive circuit 10EM may be shown in Figure 15c, and the area of ​​the first conductive layer overlapping with the transistor active layer may serve as the control electrode of the transistor.

[0173] The second conductive layer may include: the second plates of the first capacitor C11 to the third capacitor C13 in the first gate drive circuit 10P, the second plates of the first capacitor C21 to the third capacitor C23 in the second gate drive circuit 10N, the second plates of the first capacitor C31 to the third capacitor C33 in the third gate drive circuit 10EM, the second output terminal OUT2, and the third output terminal OUT3; wherein, the planar structure schematic diagram of the second conductive layer of the first gate drive circuit 10P to the third gate drive circuit 10EM can be shown in Figure 15d.

[0174] The third conductive layer may include: the first and second electrodes of the first transistor T101 to the ninth transistor T109 in the first gate drive circuit 10P, the first and second electrodes of the first transistor T201 to the sixteenth transistor T216 in the second gate drive circuit 10N, the first and second electrodes of the first transistor T301 to the twelfth transistor T212 in the third gate drive circuit 10EM, the first output terminal OUT1, and the first low-voltage power line VGL1 to the second low-voltage power line VGL2; wherein, the planar structure schematic diagram of the third conductive layer of the first gate drive circuit 10P to the third gate drive circuit 10EM may be shown in Figure 15e.

[0175] The fourth conductive layer may include: multiple branch structures of the first power line VSS, the third low voltage power line VGL3 to the fourth low voltage power line VGL4, the first high voltage power line VGJ1 to the fourth high voltage power line VGH4, the first clock signal line CK1 to the eighth clock signal line CK8, the first initial signal line STV1 to the third initial signal line STV3, the low voltage power line VGL and the high voltage power line VGH; wherein, the planar structure schematic diagram of the fourth conductive layer located in the border area (for example, located in the third border area B3) can be shown in Figure 15f.

[0176] In an exemplary embodiment, the first output terminal OUT1 is configured to provide a scan signal to the P-type transistor (i.e., a low-temperature polysilicon transistor) shown in Figure 4 or Figure 5, for example, to provide a scan signal to the control electrodes of the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 in Figure 4, or to provide a scan signal to the control electrodes of the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 in Figure 5; the second output terminal OUT2 is configured to provide a scan signal to the N-type transistor (i.e., an oxide transistor) shown in Figure 5, for example, to provide a scan signal to the control electrode of the second transistor T2 in Figure 5; the third output terminal OUT3 is configured to provide a scan signal to the light-emitting transistor shown in Figure 4 or Figure 5, for example, to provide a scan signal to the control electrodes of the fifth transistor T5 and the sixth transistor T6 in Figure 5, or to provide a scan signal to the control electrodes of the fifth transistor T5 and the sixth transistor T6 in Figure 4.

[0177] As shown in Figures 14 to 15f, which are partial enlarged schematic diagrams of the third border area B3, the structure of the fourth border area B4 can be symmetrically arranged with the structure of the third border area B3 along the center line of the display substrate along the second direction Y. Combined with Figures 7 and 14, the orthographic projection of the first branch structure VSS1 on the substrate can at least partially overlap with the orthographic projection of the output transistor in the first gate drive circuit 10P on the substrate. For example, the orthographic projection of the output transistor (the fourth transistor T104 and the fifth transistor T105) in the first gate drive circuit 10P on the substrate can be located within the range of the orthographic projection of the first branch structure VSS1 on the substrate. The first branch structure VSS1 can shield the output transistor in the first gate drive circuit 10P, thereby reducing the influence of interference signals on the output transistor in the gate drive circuit 10P.

[0178] As shown in Figures 7 and 14, in the direction from the display area AA to the border area BB, the orthographic projection of the second branch structure VSS2 on the substrate can be located between the orthographic projection of the second gate driving circuit 10N on the substrate and the orthographic projection of the third gate driving circuit 10EM on the substrate, and the orthographic projection of the third branch structure VSS3 on the substrate can be located on the side of the orthographic projection of the third gate driving circuit 10EM on the substrate away from the orthographic projection of the second gate driving circuit 10N on the substrate.

[0179] In an exemplary embodiment, the first power line VSS is configured as a plurality of branch structures to increase the width of the first power line VSS, and to some extent, reduce the risk of burns caused by the first power line VSS being too narrow.

[0180] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the first power line VSS may be located on a side of the gate driver circuit 10 that is away from the substrate. As shown in FIG14 , the locations of the multiple branch structures of the first power line VSS generally take into account the limitations of other signal lines (e.g., the clock signal line CK and the power signal lines VGL and VGH) and the shielding effect. For example, the first gate driver circuit 10P may adopt a 9T3C structure, and the first branch structure VSS1 of the first power line VSS may shield the output transistors in the first gate driver circuit 10P of the 9T3C structure, thereby shielding the signal. The second branch structure VSS2 may not overlap with the gate driver circuit 10 (avoiding other signal lines). The branch structure of the first power line VSS in the embodiment of the present disclosure may not be limited to the positional relationship of the multiple branch structures of the first power line VSS shown in Figures 7 and 14. When the circuit structure of the gate drive circuit 10 changes, the positions of the multiple branch structures of the first power line VSS may change accordingly. The positions of the multiple branch structures of the first power line VSS may take two factors into consideration: on the one hand, avoid other signal lines to avoid short circuits with other signal lines; on the other hand, try to completely block the transistors in the corresponding gate drive circuit to play a shielding role.

[0181] In an exemplary embodiment, as shown in FIG14 , the second branch structure VSS2 and the third branch structure VSS3 are spatially limited due to other signal line routing, and thus do not overlap any transistors (TFTs). Consequently, there is no overlap with the internal TFTs, and thus no shielding effect is achieved. However, for other products, the signal line distribution on the GOA may vary, and the locations covered by the multiple branch structures of the first power line VSS may vary. If the branch structure of the first power line VSS overlaps the TFTs of an effective GOA, in addition to meeting the spatial distribution requirements, the covered TFTs can also be completely shielded, thereby achieving a shielding effect. If the branch structure (routing) of the first power line VSS does not overlap the TFTs (transistors) of an effective GOA, only meeting the spatial distribution requirements is considered.

[0182] In an exemplary embodiment, as shown in Figures 15a and 15b, multiple branch structures of the first power line VSS are provided on the side of the first gate driver circuit 10P (P-Gate GOA), the second gate driver circuit 10N (N-Gate GOA), and the third gate driver circuit 10EM (EM GOA) away from the substrate. Multiple branch structures of the first power line VSS can be provided on the side of the dummy gate driver circuit (dummy GOA, which can be referred to as a dummy GOA) corresponding to the gate driver circuit 10 away from the substrate. The relative positions of the multiple branch structures of the first power line VSS and the dummy gate driver circuit (dummy GOA) can be the same as the relative positions of the corresponding effective GOA. Thus, multiple branch structures (i.e., branch routing) of the first power line VSS are formed on the side of the GOA region away from the substrate. As shown in Figure 15a, the GOA in the upper half is the effective GOA, and the GOA in the lower half is the dummy GOA. As shown in Figure 15b, the poly layer in the effective GOA is fully connected, while the poly layer in the dummy GOA has been interrupted, disconnecting the channel layer of the transistor (TFT) and preventing the transistor in the dummy gate drive circuit (dummy GOA circuit) from turning on. Multiple branch structures of the first power line VSS located in the third border area B3 and the fourth border area B4 extend from the second border area B2 to the bonding electrode area 633 (pad area) of the first border area B1.

[0183] As shown in FIG15a and FIG15b, the display substrate may include a first dummy gate driving circuit D10P, a second dummy gate driving circuit D10N, and a third dummy gate driving circuit D10EM, wherein, in the arrangement direction of the first gate driving circuits 10P, the first dummy gate driving circuit D10P may be located on one side of one of the first gate driving circuits 10P; in the arrangement direction of the second gate driving circuits 10N, the second dummy gate driving circuit D10N may be located on one side of one of the second gate driving circuits 10N; and in the arrangement direction of the third gate driving circuits 10EM, the third dummy gate driving circuit D10EM may be located on one side of one of the third gate driving circuits 10EM.

[0184] As shown in Figure 15a, the orthographic projection of the first branch structure VSS1 on the substrate can at least partially overlap with the orthographic projection of the output transistors in the first gate drive circuit 10P and the positions of the output transistors of the first virtual gate drive circuit D10P on the substrate. For example, the orthographic projections of the output transistors in the first gate drive circuit 10P (the fourth transistor T104 and the fifth transistor T105) and the positions of the output transistors of the first virtual gate drive circuit D10P (the position T104D where the fourth transistor T104 is located and the position T105D where the fifth transistor T105 is located) on the substrate can be within the range of the orthographic projection of the first branch structure VSS1 on the substrate.

[0185] As shown in Figure 15a, in the direction from the display area AA to the border area BB, the orthographic projection of the second branch structure VSS2 on the substrate can be located between the orthographic projection of the second virtual gate driving circuit D10N on the substrate and the orthographic projection of the third virtual gate driving circuit D10EM on the substrate, and the orthographic projection of the third branch structure VSS3 on the substrate can be located on the side of the orthographic projection of the third virtual gate driving circuit D10EM on the substrate away from the orthographic projection of the second virtual gate driving circuit D10N on the substrate.

[0186] As shown in FIG15b , in the virtual gate drive circuit, the active layer can be interrupted to prevent signal connectivity. For example, the active layer in the transistor can be interrupted at the channel region to prevent the transistor in the virtual gate drive circuit from being turned on.

[0187] In an exemplary embodiment, as shown in Figures 7 and 16, the branch structure may include a first end (D11, D21, D31) and a second end (D12, D22, D32), and the first ends of the plurality of branch structures may extend to the frame area where the binding area 63 is located (for example, the frame area where the binding area 63 is located may be the first frame area B1), and the second ends of the plurality of branch structures may extend to the frame area on the side of the display area AA away from the binding area 63; for example, the first ends of the plurality of branch structures may extend to the first frame area B1, and the second ends of the plurality of branch structures may extend to the second frame area B2. Among the plurality of branch structures located on the same side of the display area AA in the first direction, the first ends of the plurality of branch structures may be connected as connecting ends in the frame area where the binding area 63 is located (for example, the frame area where the binding area 63 is located may be the first frame area B1), or the second ends of the plurality of branch structures may be connected as connecting ends in the frame area on the side of the display area AA away from the binding area 63.

[0188] In an exemplary embodiment, as shown in FIG16 , the display substrate may further include a collection line VSSL of the first power line VSS. The collection line VSSL of the first power line may be located in a frame area where the binding area 63 is located (for example, the frame area where the binding area 63 is located may be the first frame area B1), or located in a frame area on a side of the display area AA away from the binding area 63 (for example, the second frame area B2). In the first direction X, the first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 are sequentially arranged on the same side of the display area AA and in a direction from the display area AA to the frame area BB.

[0189] In a direction perpendicular to the plane of the display substrate, the aggregation line VSSL of the first power line VSS is located between the substrate and the first power line VSS. The orthographic projection of the aggregation line VSSL of the first power line on the substrate and the orthographic projection of the connection end (for example, D31) of the third branch structure VSS3 on the substrate have an overlapping area, and the connection ends of the first branch structure VSS1 and the second branch structure VSS2 are both connected to the connection end of the third branch structure.

[0190] In an exemplary embodiment, the first power line aggregation line VSSL and the third branch structure VSS3 are connected in the overlapping region to form a double-layer structure, which increases the thickness of the first power line VSS and reduces impedance and voltage drop. In an exemplary embodiment, the connection end (D31) between the first power line aggregation line VSSL and the third branch structure VSS3 can be electrically connected to the driver chip IC via the bonding region 63.

[0191] In an exemplary embodiment, the display substrate may further include an auxiliary structure VSS31 of the third branch structure, and the third branch structure VSS3 and the auxiliary structure VSS31 of the third branch structure have an overlapping area between their orthographic projections on the substrate. The third branch structure VSS3 and the auxiliary structure VSS31 of the third branch structure are directly connected in the overlapping area, which can reduce the voltage drop and impedance of the third branch structure VSS3.

[0192] In an exemplary embodiment, as shown in FIG16 , the branch structures of the first power line VSS can be located on a side of the gate driver circuit 10 (GOA circuit) away from the substrate. The first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 can be located on the second source / drain metal layer (SD2) on the side of the gate driver circuit 10 away from the substrate. The first power line aggregation line VSSL and the auxiliary structure VSS31 of the third branch structure can be located on the first source / drain metal layer (SD1). The auxiliary structure VSS31 of the third branch structure and the first power line aggregation line VSSL can be an integral structure. In the border region (e.g., the first border region B1) where the bonding region 63 is located, the orthographic projections of the first power line aggregation line VSSL and the third branch structure VSS3 on the substrate at least partially overlap. The first power line aggregation line VSSL located on the first source / drain metal layer SD1 and the third branch structure VSS3 located on the second source / drain metal layer SD2 can form a double-layer structure, thereby reducing impedance and voltage drop.

[0193] In an exemplary embodiment, as shown in FIG16 , the display substrate may further include an anti-static circuit ESD. A first bending structure ZA is provided at a connection end of the first branch structure VSS1 and is bent in a direction away from the display area AA. A second bending structure Z2 is provided at a connection end of the second branch structure VSS2 and is bent in a direction away from the display area AA. In the frame area BB on the same side of the display area AA, the first bending structure Z1 and the second bending structure Z2 are sequentially arranged in a direction from the display area AA to the frame area BB. For example, in the third frame area B3, the first bending structure Z1 and the second bending structure Z2 may be sequentially arranged in a direction from the display area AA to the third frame area B3.

[0194] In the first direction X, the anti-static circuit ESD may be located between the first bending structure Z1 and the second bending structure Z2 . In the second direction Y, the anti-static circuit ESD may be located between the connection ends of the first branch structure VSS1 and the third branch structure VSS3 .

[0195] In an exemplary embodiment, as shown in FIG16 , an anti-static circuit ESD can be provided in the space between the multiple branch structures of the first power line VSS in the first frame area B1 (lower frame area) (that is, other TFT devices such as ESD can be placed in the space between the multiple branch structures), thereby improving space utilization and widening the width of VSS as a whole. As shown in FIG16 , in the first frame area B1, in the first direction X, the anti-static circuit ESD can be located between the first branch structure VSS1 and the second branch structure VSS2, that is, the anti-static circuit ESD can be provided between the multiple branch structures of the first power line VSS at the confluence interface of the first frame area B1. The multiple branch structures of the first power line VSS of the disclosed embodiment are not limited to being aggregated and connected in the first frame area B1. For example, they can be aggregated into the aggregation line VSSL of the first power line in the second frame area B2 or other locations.

[0196] In an exemplary embodiment, as shown in FIG16 , at least some of the signal lines in the last stage 10N-N of the second gate driver circuit 10N and the last stage 10EM-N of the third gate driver circuit 10EM can share a signal line in a corner area near the binding area 63. While ensuring signal sharing, on the one hand, more space can be provided for routing the first power line VSS. On the other hand, while the space occupied by the first power line VSS remains unchanged, the border can be reduced and the border can be further narrowed.

[0197] As shown in Figures 7, 8 and 16, in the third border area B3, at least some of the signal lines in the last level of at least two gate driving circuits 10 share a signal line at one end of the first corner area C1 close to the binding area 63; in the fourth border area B4, at least some of the signal lines in the last level of at least two gate driving circuits 10 share a signal line at one end of the fourth corner area C4 close to the binding area 63.

[0198] As shown in Figure 16, at least some of the signal lines may include clock signal lines. In the border area BB located on the same side of the display area AA along the first direction X, the third gate drive circuit 10EM may include a first clock signal line CK1, a second clock signal line CK3, a third clock signal line CK4, and a fourth clock signal line CK4. The second gate drive circuit 10N may include a fifth clock signal line CK5, a sixth clock signal line CK6, a seventh clock signal line CK7, and an eighth clock signal line CK8. On the side close to the binding area 63 (for example, the gate drive circuit 10 located in the third border area B3 may be in the first corner area C1, and the gate area circuit located in the fourth border area B4 may be in the fourth corner area C4), the first clock signal line CK1 can share a clock signal line with the fifth clock signal line CKV5, the second clock signal line CK2 can share a clock signal line with the fifth clock signal line CKV6, the third clock signal line CK3 can share a clock signal line with the seventh clock signal line CKV7, and the fourth clock signal line CK4 can share a clock signal line with the eighth clock signal line CKV8.

[0199] As shown in FIG16 , at least some of the signal lines may include high-voltage power lines and low-voltage power lines. In the frame area BB located on the same side of the display area AA along the first direction X, the third gate driver circuit 10EM may include a first high-voltage power line VGH1, a second high-voltage power line VGH2, a first low-voltage power line VGL1, and a second low-voltage power line VGL2. The second gate driver circuit 10N may include a third high-voltage power line VGH3, a fourth high-voltage power line VGH4, a third low-voltage power line VGL3, and a fourth low-voltage power line VGL4. The first gate driver circuit 10P includes a low-voltage power line VGL on a side close to the second gate driver circuit 10N. On a side close to the binding area 63 (for example, the gate located in the third frame area B3), the first gate driver circuit 10P includes a low-voltage power line VGL. The gate driving circuit 10 can be in the first corner area C1, and the gate area circuit located in the fourth border area B4 can be in the fourth corner area C4), the first high voltage power line VGH1 can share a high voltage signal line with the third high voltage power line VGH3, the second high voltage power line VGH2 can share a high voltage signal line with the fourth high voltage power line VGH4, the first low voltage power line VGL1 can share a low voltage signal line with the third low voltage power line VGL3, the low voltage power line VGL in the first gate driving circuit 10P and the third low voltage power line VGL3 in the second gate driving circuit 10N can share a signal line, and the second low voltage power line VGL2 can share a low voltage signal line with the fourth low voltage power line VGL4.

[0200] In the structure shown in FIG16 , at the end of the last level GOA of the lower fillet, the CK1 / CK5, CK2 / CK6, CK3 / CK7, CK4 / CK8, VGH1 / VGH3, VGH2 / VGH4, VGL1 / VGL3, and VGL2 / VGL4 signals are connected in pairs to the PAD area (i.e., the first border area B1 where the binding area 63 is located), thereby providing more space for VSS routing while ensuring signal sharing.

[0201] The present disclosure provides a display device, as shown in FIG17 , which may include a display substrate according to any of the aforementioned embodiments. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0202] The display substrate and display device provided in this embodiment have multiple branch structures of the first power line arranged in the frame area of ​​the display substrate, which can increase the width of the first power line and reduce the risk of burns caused by the small width of the first power line.

[0203] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0204] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0205] Although the embodiments disclosed in the present disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising, in a direction parallel to a plane of the display substrate, a display area and a frame area located on at least one side of the display area; the frame area being provided with a first power line and at least one gate drive circuit; different types of gate drive circuits being arranged sequentially along a direction from the display area to the frame area; and multiple gate drive circuits of the same type being arranged along an extension direction of the frame area; the first power line comprising a plurality of branch structures, the plurality of branch structures being arranged sequentially along a direction from the display area to the frame area and extending along the extension direction of the frame area; In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a base, the multiple branch structures are located on a side of the gate driving circuit away from the base, and the positive projections of at least some of the branch junctions on the base at least partially overlap with the positive projections of at least some types of gate driving circuits on the base.

2. The display substrate according to claim 1, wherein The at least one type of gate driving circuit includes a first gate driving circuit, and the plurality of branch structures include a first branch structure; An orthographic projection of the first branch structure on the substrate at least partially overlaps with an orthographic projection of the first gate driving circuit on the substrate.

3. The display substrate according to claim 2, wherein: The first gate driving circuit includes a plurality of transistors including an output transistor, and an orthographic projection of the first branch structure on the substrate at least partially overlaps with an orthographic projection of the output transistor in the first gate driving circuit on the substrate.

4. The display substrate according to claim 3, wherein: The orthographic projection of the output transistor in the first gate driving circuit on the substrate is located within the range of the orthographic projection of the first branch structure on the substrate.

5. The display substrate according to any one of claims 2 to 4, wherein: The display area includes multiple rows of sub-pixels, each of which includes at least a pixel driving circuit, and the pixel driving circuit includes at least one first type of low-temperature polysilicon transistor. The first gate driving circuit is electrically connected to the control electrode of at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one first type of low-temperature polysilicon transistor in the at least one row of sub-pixels. The display substrate according to claim 5 , wherein: The at least one first type low temperature polysilicon transistor includes a data writing transistor and an initialization transistor.

7. The display substrate according to claim 2, wherein: The at least one type of gate driving circuit further includes a second gate driving circuit and a third gate driving circuit, and the plurality of branch structures further include a second branch structure and a third branch structure; In the direction from the display area to the border area, the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit are arranged in sequence, and the first branch structure, the second branch structure, and the third branch structure are arranged in sequence. The orthographic projection of the second branch structure on the substrate is located between the orthographic projection of the second gate driving circuit on the substrate and the orthographic projection of the third driving circuit on the substrate, and the orthographic projection of the third branch structure on the substrate is located on the side of the orthographic projection of the third gate driving circuit on the substrate away from the orthographic projection of the second gate driving circuit on the substrate.

8. The display substrate according to claim 7, wherein: The display area includes multiple rows of sub-pixels, each of which includes at least a pixel driving circuit, and the pixel driving circuit includes at least one oxide transistor. The second gate driving circuit is electrically connected to the control electrode of at least one oxide transistor in at least one row of sub-pixels and is configured to provide a scanning signal to the at least one oxide transistor in the at least one row of sub-pixels.

9. The display substrate according to claim 8, wherein: The pixel driving circuit also includes at least one second type of low-temperature polysilicon transistor, and the third gate driving circuit is electrically connected to the control electrode of at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels.

10. The display substrate according to claim 9, wherein: The at least one oxide transistor comprises a compensation transistor, and the at least one second type low temperature polysilicon transistor comprises a light emitting transistor.

11. The display substrate according to any one of claims 1 to 4 and 7 to 10, wherein: In a direction parallel to the plane where the display substrate is located, the border area is located around the display area. In a first direction, the gate drive circuit and the first power line are located in the border areas on both sides of the display area. In a second direction, a binding area is provided in the border area on one side of the display area. The first direction intersects with the second direction. The display substrate is symmetrical with respect to a first center line, and the first center line is the center line of the display substrate extending along the second direction.

12. The display substrate according to claim 11, wherein: In the border area located on the same side of the display area in the first direction, the first to last levels of multiple gate driving circuits of the same type are arranged in sequence along the direction from the display area to the binding area, and at least some of the signal lines in the last level of at least two gate driving circuits share a signal line on the side close to the binding area.

13. The display substrate according to claim 12, wherein: In a frame area located on the same side of the display area in the first direction, the multiple gate driving circuits include a second gate driving circuit and a third gate driving circuit, and the second gate driving circuit and the third gate driving circuit are arranged in sequence in a direction from the display area to the frame area; At least part of the signal lines in the last stage of the second gate driving circuit and the last stage of the third gate driving circuit share a signal line on a side close to the binding domain.

14. The display substrate according to claim 13, wherein: At least part of the signal lines include clock signal lines; in the frame area located on the same side of the display area along the first direction, the third gate drive circuit includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; and the second gate drive circuit includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line; On a side close to the binding area, the first clock signal line and the fifth clock signal line share a clock signal line, the second clock signal line and the sixth clock signal line share a clock signal line, the third clock signal line and the seventh clock signal line share a clock signal line, and the fourth clock signal line and the eighth clock signal line share a clock signal line.

15. The display substrate according to claim 13, wherein: At least part of the signal lines include a high-voltage power line and a low-voltage power line; in a frame area located on the same side of the display area along the first direction, the third gate drive circuit includes a first high-voltage power line, a second high-voltage power line, a first low-voltage power line, and a second low-voltage power line; the second gate drive circuit includes a third high-voltage power line, a fourth high-voltage power line, a third low-voltage power line, and a fourth low-voltage power line; On a side close to the binding area, the first high-voltage power line and the third high-voltage power line share a high-voltage signal line, the second high-voltage power line and the fourth high-voltage power line share a high-voltage signal line, the first low-voltage power line and the third low-voltage power line share a low-voltage signal line, and the second low-voltage power line and the fourth low-voltage power line share a low-voltage signal line.

16. The display substrate according to claim 12, wherein: The frame area includes: a first frame area and a second frame area located on both sides of the display area along the second direction, a third frame area and a fourth frame area located on both sides of the display area along the first direction, a first corner area connecting the first frame area and the third frame area, a second corner area connecting the third frame area and the second frame area, a third corner area connecting the second frame area and the fourth frame area, and a fourth corner area connecting the fourth frame area and the first frame area; The gate drive circuit and the first power line are located in the third frame area and the fourth frame area. The first power line and the gate drive circuit located in the third frame area extend to the first corner area and the second corner area. The first power line and the gate drive circuit located in the fourth frame area extend to the third corner area. And the fourth corner area, the third frame area and the fourth frame area are symmetrical with respect to the first center line.

17. The display substrate according to claim 16, wherein: The binding area is located in the first border area; In the third border area, at least part of the signal lines in the last stage of at least two gate driving circuits share a signal line at one end of the first corner area close to the binding area; In the fourth border region, at least some of the signal lines in the last stage of at least two gate driving circuits share a signal line at one end of the fourth corner region close to the binding region.

18. The display substrate according to claim 11, wherein The branch structure includes a first end and a second end, the first ends of the plurality of branch structures extend to the frame area where the binding area is located, and the second ends of the plurality of branch structures extend to the frame area on a side of the display area away from the binding area; Among the multiple branch structures located on the same side of the display area in the first direction, the first ends of the multiple branch structures serve as connecting ends and are connected in the border area where the binding area is located, or the second ends of the multiple branch structures serve as connecting ends and are connected in the border area on the side of the display area away from the binding area.

19. The display substrate according to claim 18, further comprising a first power line aggregation line, the first power line aggregation line being located in a frame area where the binding area is located, or in a frame area on a side of the display area away from the binding area; the plurality of branch structures including a first branch structure, a second branch structure, and a third branch structure arranged in sequence along a direction from the display area to the frame area, being located on the same side of the display area in the first direction; In a direction perpendicular to the plane of the display substrate, the aggregation line of the first power line is located between the substrate and the first power line, and the orthographic projection of the aggregation line of the first power line on the substrate and the orthographic projection of the connecting end of the third branch structure on the substrate have an overlapping area, and the connecting ends of the first branch structure and the second branch structure are both connected to the connecting end of the third branch structure.

20. The display substrate according to claim 19, wherein The aggregation line of the first power line and the third branch structure are directly connected in the overlapping area to form a double-layer structure.

21. The display substrate according to claim 20, further comprising an auxiliary structure of the third branch structure, wherein the third branch structure and the auxiliary structure of the third branch structure have an overlapping area with each other in orthographic projection on the substrate, and the third branch structure and the auxiliary structure of the third branch structure are directly connected in the overlapping area; The first branch structure, the second branch structure, and the third branch structure are located in the second source-drain metal layer, and the aggregation line of the first power line and the auxiliary structure of the third branch structure are located in the first source-drain metal layer; The third The auxiliary structure of the branch structure and the aggregation line of the first power line are an integrated structure.

22. The display substrate according to claim 19, further comprising an anti-static circuit, wherein a connecting end portion of the first branch structure is provided with a first bending structure that bends in a direction away from the display area, and a connecting end portion of the second branch structure is provided with a second bending structure that bends in a direction away from the display area, and in a frame area on the same side of the display area, the first bending structure and the second bending structure are arranged in sequence from the display area to the frame area; In the first direction, the anti-static circuit is located between the first bending structure and the second bending structure. In the second direction, the anti-static circuit is located between the connecting end of the first branch structure and the connecting end of the third branch structure.

23. The display substrate according to claim 1, wherein: In a direction perpendicular to the plane where the display substrate is located, an anode conductive layer and a cathode layer are sequentially provided on the side of the first power line away from the substrate, the anode conductive layer includes a plurality of switching electrodes, the orthographic projections of the plurality of switching electrodes on the substrate at least partially overlap with the orthographic projections of the cathode layer and the plurality of branch structures on the substrate, the plurality of branch structures of the first power line are electrically connected to the plurality of switching electrodes through a plurality of connecting vias, and the cathode layer is connected to the plurality of switching electrodes.

24. The display substrate according to claim 23, wherein: The plurality of branch structures include a first branch structure, a second branch structure, and a third branch structure; the plurality of switching electrodes include a first switching electrode, a second switching electrode, and a third switching electrode; and the plurality of connecting vias include a first connecting via, a second connecting via, and a third connecting via; The orthographic projection of the first connecting via on the substrate at least partially overlaps with the orthographic projection of the first branch structure and the first switching electrode on the substrate, the orthographic projection of the second connecting via on the substrate at least partially overlaps with the orthographic projection of the second branch structure and the second switching electrode on the substrate, and the orthographic projection of the third connecting via on the substrate at least partially overlaps with the orthographic projection of the third branch structure and the third switching electrode on the substrate.

25. The display substrate according to claim 1, wherein The gate driving circuit includes a plurality of transistors and at least one capacitor, and includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the substrate in a direction perpendicular to the plane where the display substrate is located; The semiconductor layer includes: active layers of a plurality of transistors in the at least one gate drive circuit; The first conductive layer includes: control electrodes of multiple transistors in the at least one gate drive circuit, and a first plate of the at least one capacitor; The second conductive layer includes: a second plate of at least one capacitor in the at least one gate drive circuit; The third conductive layer includes: first electrodes and second electrodes of a plurality of transistors in the at least one gate driving circuit; The fourth conductive layer includes: a plurality of branch structures of the first power line.

26. A display device comprising the display substrate according to any one of claims 1 to 25.

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