Preparation method for semiconductor device, and wafer structure and semiconductor device

Abstract

A preparation method for a semiconductor device, and a semiconductor device, which are applied to the technical field of semiconductor device preparation. The method comprises: obtaining a wafer that has a front surface configured for the formation of a functional area and a non-functional area; etching an alignment point with a preset depth in the non-functional area, wherein the distance between the bottom surface of the alignment point and the back surface of the wafer is less than the thickness reduction of the back surface of the wafer; after the alignment point and a functional structure are provided, thinning the wafer on the back surface of the wafer to expose the alignment point; and providing a back functional structure on the back surface of the wafer to complete the preparation of a semiconductor device. By means of providing an alignment point with a preset depth on the front surface of a wafer, a front functional structure of the wafer can be aligned with the alignment point. After the back surface of the wafer is thinned, the alignment point is exposed on the back surface of the wafer, and when a back functional structure is provided, it is necessary to align the back functional structure with the alignment point, thus realizing the mutual alignment of the front functional structure and the back functional structure.

Description

Semiconductor device manufacturing method, wafer structure and semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 19, 2024, with application number 202410316160.0 and invention name “A method for preparing a semiconductor device, a wafer structure and a semiconductor device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a semiconductor device, a wafer structure, and a semiconductor device. Background Art

[0003] Photolithography is a process that removes specific portions of a thin film from the wafer surface through a series of production steps. This process leaves a thin film with a micropatterned structure on the wafer surface. The photolithography process typically involves cleaning and drying the wafer substrate surface, applying a primer, spin-coating photoresist, soft baking, alignment and exposure, post-baking, developing, hard baking, etching, and testing.

[0004] With the diversification of semiconductor device structures, functional structures now need to be placed on both sides of the wafer, and the functional structures on the front and back sides need to be aligned with each other. However, existing exposure machines cannot currently achieve this alignment of the front and back sides of the wafer and lack the process capabilities. Therefore, how to achieve the alignment of the functional structures on the front and back sides of the wafer is an urgent problem that technicians in this field need to solve.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to provide a method for preparing a semiconductor device, which can realize the alignment of functional structures on the front and back sides of a wafer; the present invention also provides a wafer structure and a semiconductor device, which can realize the alignment of functional structures on the front and back sides of a wafer.

[0007] To solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:

[0008] Obtaining a wafer having a functional area and a non-functional area formed on the front side, wherein the functional area is used to set the functional structure of the chip;

[0009] An alignment point of a preset depth is etched in the non-functional area; the distance between the bottom surface of the alignment point and the back surface of the wafer is less than the thinning thickness of the back surface of the wafer; the position of the front functional structure can be aligned with the position of the alignment point;

[0010] After setting the alignment points and the functional structure, thinning the wafer from the back side of the wafer to expose the alignment points;

[0011] A back surface functional structure is provided on the back surface of the wafer to complete the preparation of the semiconductor device; the position of the back surface functional structure is aligned with the position of the alignment point.

[0012] Optionally, etching alignment points of a preset depth in the non-functional area includes:

[0013] Setting photoresist on the front side of the wafer and exposing it to expose the preset alignment point position;

[0014] An alignment point of a preset depth is etched at the alignment point position on the front side of the wafer by a plasma etching process.

[0015] Optionally, before providing photoresist on the front side of the wafer and performing exposure to expose the preset alignment point positions, the process further includes:

[0016] A front functional structure is provided on the front side of the wafer.

[0017] Optionally, before thinning the wafer from the back side of the wafer to expose the alignment point, the method further includes:

[0018] The front side of the wafer is packaged.

[0019] Optionally, packaging the front side of the wafer includes:

[0020] Fill PI glue on the front side of the wafer;

[0021] Immersion gold on the front side of the wafer based on the ENIG process.

[0022] Optionally, after packaging the front side of the wafer, the process further includes:

[0023] A substrate is bonded to the front side of the wafer.

[0024] Optionally, etching an alignment point of a preset depth on the front side of the wafer where the front side functional structure is provided includes:

[0025] A plurality of alignment points of preset depths are etched on the front side of the wafer where the front side functional structure is provided.

[0026] Optionally, the distance between the plurality of alignment points is not less than the radius of the wafer.

[0027] Optionally, providing a back functional structure on the back side of the wafer includes:

[0028] A back-gold array is provided on the back side of the wafer; the back-gold array includes a plurality of back-gold modules, and the back-gold array and the alignment points are aligned with each other, so that the back-gold modules and the functional areas are aligned with each other.

[0029] Optionally, providing a back-gold array on the back side of the wafer includes:

[0030] providing a seed layer on the back side of the wafer;

[0031] Based on the position of the positioning point, an isolation layer corresponding to the backside cutting line is provided on the surface of the seed layer;

[0032] Plate a back-gold module on the area of ​​the seed layer surface not shielded by the isolation layer to form a back-gold array;

[0033] After forming the back gold array, the isolation layer is removed to expose the backside cutting lanes.

[0034] The present invention also provides a wafer structure, wherein a functional area on the front side of the wafer is provided with a front functional structure, a back side of the wafer is provided with a back side functional structure, and a non-functional area of ​​the wafer is provided with an alignment point extending from the front side to the back side, wherein the distance between the bottom surface of the alignment point and the initial back side of the wafer is less than the thinning thickness of the back side of the wafer;

[0035] The position of the front functional structure and the position of the alignment point are aligned with each other, and the position of the back functional structure and the position of the alignment point are aligned with each other.

[0036] Optionally, the wafer is provided with a plurality of alignment points.

[0037] Optionally, at least one layer of the back functional structure is a graphic structure, and the graphic structure is aligned with the alignment point.

[0038] The present invention also provides a semiconductor device, comprising a substrate, a front functional structure, and a back functional structure separated from a wafer, wherein the front functional structure and the back functional structure are aligned with each other based on an alignment point, wherein the alignment point is arranged in a non-functional area of ​​the wafer before the wafer is separated, the alignment point extends from the front to the back, and the distance between the bottom surface of the alignment point and the initial back surface of the wafer is less than the thinning thickness of the back surface of the wafer

[0039] Optionally, a step structure is formed between the edge of the back functional structure and the edge of the substrate, and the step structure is a step structure formed by cutting the wafer based on the back cutting road formed on the back side of the wafer, and the back cutting road is aligned with the front cutting road of the wafer through the alignment point.

[0040] The present invention provides a method for preparing a semiconductor device, comprising: obtaining a wafer having a functional area and a non-functional area formed on the front side, wherein the functional area is used to set the functional structure of the chip; etching an alignment point of a preset depth in the non-functional area; the distance between the bottom surface of the alignment point and the back side of the wafer is less than the thinning thickness of the back side of the wafer; the position of the front functional structure can be aligned with the position of the alignment point; after setting the alignment point and the functional structure, thinning the wafer from the back side of the wafer to expose the alignment point; setting the back side functional structure on the back side of the wafer to complete the preparation of the semiconductor device; the position of the back side functional structure is aligned with the position of the alignment point.

[0041] By setting an alignment point at a preset depth on the front side of the wafer, the front functional structure of the wafer can be aligned with this alignment point. After thinning the back side of the wafer, the alignment point will be exposed on the back side of the wafer. When setting the back side functional structure, the back side functional structure needs to be aligned with the alignment point. Because the position of the alignment point is fixed, the front functional structure and the back functional structure can be aligned with each other.

[0042] The present invention also provides a wafer structure and a semiconductor device, which also have the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] 1 to 4 are process flow charts of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0045] 5 to 12 are process flow charts of a specific method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0046] In the figure: 1. Wafer, 2. Front functional structure, 3. Alignment point, 4. Back functional structure, 5. PI glue, 6. Protective layer, 7. Adhesive layer, 8. Substrate. DETAILED DESCRIPTION

[0047] The core of the present invention is to provide a method for preparing a semiconductor device. In the prior art, existing exposure machines cannot achieve wafer front and back alignment and do not have such process capabilities.

[0048] The present invention provides a method for preparing a semiconductor device, including: obtaining a wafer with a functional area and a non-functional area formed on the front side, wherein the functional area is used to set the functional structure of the chip; etching an alignment point of a preset depth in the non-functional area; the distance between the bottom surface of the alignment point and the back side of the wafer is less than the thinning thickness of the back side of the wafer; the position of the front functional structure can be aligned with the position of the alignment point; after setting the alignment point and the functional structure, thinning the wafer from the back side of the wafer to expose the alignment point; setting the back side functional structure on the back side of the wafer to complete the preparation of the semiconductor device; the position of the back side functional structure is aligned with the position of the alignment point.

[0049] By setting an alignment point at a preset depth on the front side of the wafer, the front functional structure of the wafer can be aligned with this alignment point. After thinning the back side of the wafer, the alignment point will be exposed on the back side of the wafer. When setting the back side functional structure, the back side functional structure needs to be aligned with the alignment point. Because the position of the alignment point is fixed, the front functional structure and the back functional structure can be aligned with each other.

[0050] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0051] Please refer to FIG. 1 to FIG. 4 , which are process flow charts of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0052] Referring to FIG. 1 , in an embodiment of the present invention, a method for manufacturing a semiconductor device includes:

[0053] S101: Obtain a wafer having a front surface for forming a functional area and a non-functional area, wherein the functional area is used to set the functional structure of the chip.

[0054] The functional area is an area used to form various functional structures required for semiconductor devices such as chips or separation devices, that is, an area used for subsequent graphical processing; the non-functional area is an area such as a cutting path, a PCM (process control monitor) area, etc. that does not affect the function of the semiconductor device, that is, an area that does not require subsequent graphical processing.

[0055] S102: etching an alignment point of a preset depth in the non-functional area.

[0056] Referring to Figure 2, in an embodiment of the present invention, the distance between the bottom surface of the alignment point 3 and the back surface of the wafer 1 is less than the thinning thickness of the back surface of the wafer 1; the position of the front functional structure 2 can be aligned with the position of the alignment point 3.

[0057] This embodiment specifically refers to the steps performed after the functional structure is prepared on the front side of the wafer 1, that is, after the FAB (semiconductor manufacturing) process is completed. In this embodiment, the functional structure set on the front side of the wafer 1 is the front functional structure 2. The specific content of the front functional structure 2 can be set according to actual conditions and is not specifically limited here. It can specifically be a related structure of the function required by the chip, a HEMT (high electron mobility transistor) structure, a related structure required for a separation device, etc.

[0058] In this step, an alignment point 3 of a preset depth will be etched on the front side of the wafer 1. First, the alignment point 3 will be exposed on the front side of the wafer 1. Secondly, the alignment point 3 needs to have a certain depth so that the distance between the bottom surface of the alignment point 3 and the back side of the wafer 1 that has not been thinned at this time is less than the thinning thickness of the back side of the wafer 1, that is, it is necessary to ensure that the alignment point 3 can be exposed after the back side of the wafer 1 is thinned.

[0059] After the alignment points 3 are set, the entire front functional structure 2 and the alignment points 3 will have a fixed corresponding relationship, and the position of the front functional structure 2 will be aligned with the position of the alignment points 3. The specific etching process will be described in detail in the following embodiments of the invention and will not be repeated here.

[0060] S103: After setting the alignment points and functional structures, the wafer is thinned from the back side of the wafer to expose the alignment points.

[0061] 3 , in this step, the backside of wafer 1 is thinned. Since the distance between the bottom surface of alignment point 3 and the backside of wafer 1 before thinning is less than the thickness of the backside of wafer 1 before thinning, alignment point 3 is exposed on the backside of wafer 1 after this step.

[0062] Before this step, the front side of the wafer 1 is usually packaged to protect the front functional structure 2. After packaging, the wafer 1 is usually also fixed. The details of this will be described in detail in the following embodiments of the invention and will not be repeated here.

[0063] S104: Setting a back functional structure on the back side of the wafer to complete the preparation of the semiconductor device.

[0064] Referring to Figure 4, in an embodiment of the present invention, the position of the back functional structure 4 is aligned with the position of the alignment point 3. The above-mentioned back functional structure 4 is a structure arranged on the back of the wafer 1 and has a certain function. Since the back functional structure 4 will be arranged based on the exposed alignment point 3 in this step, the position of the back functional structure 4 will be aligned with the position of the alignment point 3. At the same time, since the position of the alignment point 3 is fixed, the back functional structure 4 and the front functional structure 2 will be aligned with each other in this embodiment, thereby realizing the alignment of the functional structures on the front and back sides of the wafer 1. Similar to the above-mentioned front functional structure 2, the functional structure arranged on the back of the wafer 1 in this embodiment is the back functional structure 4. The specific content of the back functional structure 4 can be set according to actual conditions and is not specifically limited here. The back functional structure 4 can specifically be a structure with a certain pattern formed by electroplating and / or etching processes after photolithography, and the above-mentioned process can refer to the position of the alignment point 3 to realize the alignment of the functional structures on the front and back sides of the wafer 1.

[0065] It should be emphasized that the backside photoresist pattern used to prepare the above-mentioned backside functional structure 4 is the pattern corresponding to the normal state of the chip flipped 180 degrees, with the back side facing up. In other words, the backside photoresist pattern design needs to be flipped 180 degrees to achieve the front and back side alignment of the wafer.

[0066] In a method for fabricating a semiconductor device provided by an embodiment of the present invention, alignment points 3 are provided at a preset depth on the front surface of a wafer 1. This allows the front functional structure 2 of the wafer 1 to be aligned with the alignment points 3. After thinning the back surface of the wafer 1, the alignment points 3 are exposed. When the back functional structure 4 is subsequently provided, the back functional structure 4 needs to be aligned with the alignment points 3. Because the position of the alignment points 3 is fixed, alignment between the front functional structure 2 and the back functional structure 4 can be achieved.

[0067] The specific contents of the method for preparing a semiconductor device provided by the present invention will be described in detail in the following embodiments of the invention.

[0068] Please refer to FIG. 5 to FIG. 12 , which are process flow charts of a specific method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0069] 5 , in an embodiment of the present invention, a method for manufacturing a semiconductor device includes:

[0070] S201: Setting a front functional structure on the front side of the wafer.

[0071] Referring to Figure 6, in this step, a front functional structure 2 will first be set on the front side of the wafer 1. The specific content of the front functional structure 2 has been introduced in detail in the above-mentioned invention embodiment, and the specific setting process of the front functional structure 2 needs to be determined according to its structure, so no specific limitation is made here.

[0072] S202: placing photoresist on the front side of the wafer and performing exposure to expose the preset alignment point positions.

[0073] The alignment point 3 is a preset position on the front side of the wafer 1 where the alignment point 3 needs to be set. For example, the front side functional structure 2 generally includes functional modules corresponding to the respective chips, and dicing lanes are generally provided between the functional modules. The alignment point 3 is generally provided in the dicing lanes to prevent the alignment point 3 from damaging the front side functional structure 2. The specific type of photoresist used in this step and the specific morphology of the photoresist layer formed can be set according to actual conditions and are not specifically limited here.

[0074] S203: etching an alignment point of a preset depth at the alignment point position on the front side of the wafer through a plasma etching process.

[0075] In this step, a dry etching process, specifically a plasma etching process, is used to etch the alignment points 3 at the predetermined locations on the front surface of the wafer 1. Compared to wet etching, dry etching has a stronger anisotropy, allowing alignment points 3 to be etched to the required depth in a very small area, thereby avoiding extensive damage to the front functional structures 2 already provided on the front surface of the wafer 1.

[0076] Referring to FIG. 7 , in this embodiment, multiple alignment points 3 are provided on a wafer 1. Therefore, this step may include etching multiple alignment points 3 at a predetermined depth on the front surface of the wafer 1 where the front functional structure 2 is provided. At this point, a line can be formed between each of the multiple alignment points 3. Compared to providing only one alignment point 3, the line formed by multiple alignment points 3 can more accurately reflect the position, orientation, and other information of the front functional structure 2, thereby ensuring more accurate alignment of the back functional structure 4 with the front functional structure 2.

[0077] Obviously, in this embodiment, the farther the distance between the two alignment points 3 of the connection line, that is, the longer the distance between the two alignment points 3 of the connection line, the more accurate the position information reflected by the connection line is, and the higher the precision is. Therefore, in this embodiment, it is usually necessary to ensure that the distance between the multiple alignment points 3 is not less than the radius of the wafer 1 to ensure the alignment accuracy. Of course, in this embodiment, only one alignment point 3 or more alignment points 3 can be set. The more alignment points 3 are set, the higher the alignment accuracy is, but it will occupy more area of ​​the wafer 1 and increase the preparation cost.

[0078] In this embodiment, the shape of the alignment site 3 is generally not specifically limited. The alignment site 3 can be circular, rectangular, cross-shaped or any polygonal shape, and is not specifically limited here.

[0079] It should be noted that the alignment point 3 setting method provided in this embodiment can be combined with other alignment point 3 setting methods, that is, the alignment point 3 provided in this embodiment and the alignment point 3 formed by other methods, including the alignment point 3 that is not ultimately exposed on the back side of the wafer, can be mixed and used. This embodiment does not limit the wafer 1 to only using the alignment point 3 provided in this embodiment. The specific content can be set according to actual conditions and is not specifically limited here.

[0080] S204: Filling PI glue on the front side of the wafer.

[0081] S205: Immerse gold on the front side of the wafer based on the ENIG process.

[0082] Referring to Figures 8 and 9 , steps S203 to S204 are part of the wafer-level advanced packaging process. PI (polyimide) adhesive 5 is a material composed of polyimide resin and filler. In this step, PI adhesive 5 is typically used to cover the non-metallic structure of the front functional structure 2. Then, an ENIG (electroless nickel-gold) process is used to electroplate a mixture of nickel and metal onto the metal structure on the front of wafer 1 to form a protective layer 6. For details regarding PI adhesive 5 and the ENIG process, reference can be made to the prior art and will not be repeated here.

[0083] S206: Bonding a substrate to the front side of the wafer.

[0084] Referring to Figure 10 , in this step, a substrate 8 is bonded to the front side of the packaged wafer 1. This substrate 8 can be used to provide support for the wafer 1 during subsequent thinning of the back side of the wafer 1. The specific material and thickness of the substrate 8 can be determined based on actual conditions and are not specifically limited here. The above bonding process can be achieved through direct bonding or through bonding with an adhesive layer 7 such as solder, both of which are not specifically limited here.

[0085] S207: After setting the alignment points and functional structures, the wafer is thinned from the back side of the wafer to expose the alignment points.

[0086] S208: Based on the exposed alignment points, a back functional structure is set on the back side of the wafer to complete the preparation of the semiconductor device.

[0087] 11 and 12 , the above S207 to S208 are substantially identical to S102 to S103 in the above invention embodiment. For details, please refer to the above invention embodiment, which will not be described in detail here.

[0088] Specifically, the step of setting up the functional structure on the other side in this step may include: setting up a back-gold array on the back side of the wafer 1; the back-gold array includes multiple back-gold modules, and the back-gold array is aligned with the alignment point 3 so that the back-gold module is aligned with the functional area.

[0089] The above-mentioned back-gold modules are equivalent to the small pieces of back-gold formed by patterning the entire back-gold surface, and the back-gold modules will be distributed in an array to form a back-gold array. At this time, a back-cutting path corresponding to the above-mentioned non-functional area can be formed between adjacent back-gold modules, and the back-gold modules need to be aligned with the functional area set on the front side of the wafer 1. In this embodiment, the back-gold module specifically needs to be aligned with the functional area set on the front side of the wafer 1 through the above-mentioned alignment point 3 exposed by the back side of the wafer 1, and the corresponding back-cutting paths between the back-gold modules and the above-mentioned non-functional area will also be aligned with each other.

[0090] Specifically, the above-mentioned setting of a back gold array on the back side of the wafer 1 can specifically include: setting a seed layer on the back side of the wafer 1; based on the position of the positioning point 3, setting an isolation layer corresponding to the back cutting path on the surface of the seed layer; plating a back gold module in the area of ​​the surface of the seed layer that is not shielded by the isolation layer to form a back gold array; after the back gold array is formed, the isolation layer is removed to expose the back cutting path.

[0091] In order to form the back-gold array of the above structure, in this embodiment, a thin seed layer can be generated first, and then an isolation layer is set on the surface of the seed layer. The isolation layer is a patterned isolation layer, and the isolation layer will correspond to the above-mentioned cutting path. After that, a back-gold module will be plated in the area on the surface of the seed layer that is not shielded by the isolation layer to form a back-gold array. Since the position corresponding to the cutting path is provided with an isolation layer in advance, it will not be provided with back-gold, and the back-side cutting path will eventually be retained. Finally, the isolation layer needs to be removed to expose the back-side cutting path and realize the patterning of the back-gold. The thickness of the above-mentioned seed layer is usually thin and will not affect the cutting of the wafer 1.

[0092] Of course, in this embodiment, other structures of the back functional structure 4 may also be provided, and the specific content thereof depends on the specific situation and is not specifically limited here.

[0093] In a method for fabricating a semiconductor device provided by an embodiment of the present invention, alignment points 3 are provided at a preset depth on the front surface of a wafer 1. This allows the front functional structure 2 of the wafer 1 to be aligned with the alignment points 3. After thinning the back surface of the wafer 1, the alignment points 3 are exposed. When the back functional structure 4 is subsequently provided, the back functional structure 4 needs to be aligned with the alignment points 3. Because the position of the alignment points 3 is fixed, alignment between the front functional structure 2 and the back functional structure 4 can be achieved.

[0094] A wafer structure provided by an embodiment of the present invention is introduced below. The wafer structure described below and the semiconductor device manufacturing method described above can be referred to accordingly.

[0095] In this embodiment, the functional area on the front side of the wafer 1 is provided with a front functional structure 2, the back side of the wafer 1 is provided with a back functional structure 4, and the non-functional area of ​​the wafer 1 is provided with an alignment point 3 extending from the front side to the back side. The distance between the bottom surface of the alignment point 3 and the initial back side of the wafer is less than the thinning thickness of the back side of the wafer 1. The initial back side of the wafer is the back surface before the back side of the wafer 1 is thinned, that is, the opening of the alignment point 3 on the back side of the wafer 1 can be exposed by thinning the back side of the wafer 1; the position of the front functional structure 2 is aligned with the position of the alignment point 3, and the position of the back functional structure 4 is aligned with the position of the alignment point 3.

[0096] The wafer structure disclosed in this embodiment is the overall structure of wafer 1 before cutting and separation. The front side of wafer 1 is provided with a front functional structure 2, and the back side of wafer 1 is provided with a back functional structure 4. At a preset position on wafer 1, an alignment point 3 extending from the front side to the back side is provided. The opening of the alignment point 3 on the back side of wafer 1 is specifically exposed by thinning the back side of wafer 1. In this embodiment, the front functional structure 2 and the back functional structure 4 are specifically aligned through the alignment point 3. The specific contents of the front functional structure 2, the back functional structure 4, and the alignment point 3 can be referred to the above-mentioned invention embodiment and will not be repeated here.

[0097] Specifically, in this embodiment, at least one layer of the back functional structure 4 is a graphic structure, and the graphic structure is aligned with the alignment point 3, so that the graphic structure on the back can be aligned with the graphic structure on the front.

[0098] Specifically, in this embodiment, the wafer 1 may be provided with a plurality of alignment points 3, and the distance between the corresponding plurality of alignment points 3 may be no less than the radius of the wafer 1. A packaging layer covering the front functional structure 2 may be further provided on the front side of the wafer 1. The packaging layer may be formed based on the PI glue 5 provided on the front side of the wafer 1 and the metal protective layer 6 formed by the ENIG process. The specific structure of the packaging layer can be referred to the prior art and will not be described in detail here. Accordingly, after the packaging layer is provided, a substrate 8 may be further bonded to the surface of the packaging layer.

[0099] The wafer structure of this embodiment is prepared based on the above-mentioned semiconductor device preparation method. Therefore, the specific implementation method of the wafer structure can be seen in the embodiment part of the semiconductor device preparation method in the previous text. Therefore, its specific implementation method can refer to the description of the corresponding embodiments of each part and will not be repeated here.

[0100] A semiconductor device provided by an embodiment of the present invention is introduced below. The semiconductor device described below and the semiconductor device manufacturing method described above can be referred to accordingly.

[0101] In this embodiment, the semiconductor device includes a substrate, a front functional structure 2 and a back functional structure 4 separated from a wafer. The front functional structure 2 and the back functional structure 4 are aligned with each other based on an alignment point 3. The alignment point 3 is arranged in a non-functional area of ​​the wafer 2 before the wafer 2 is separated. The alignment point 3 extends from the front to the back, and the distance between the bottom surface of the alignment point 3 and the initial back of the wafer is less than the thinning thickness of the back of the wafer 2.

[0102] The initial back side of the wafer mentioned above is the back surface before the back side of the wafer 2 is thinned, that is, the opening of the alignment point 3 on the back side of the wafer 1 is exposed by thinning the back side of the wafer 1. The semiconductor device disclosed in this embodiment is a device structure formed by the wafer 1 after cutting and separation. At this time, a front functional structure 2 is provided on the front side of the substrate, and a back functional structure 4 is provided on the back side of the substrate, and the front functional structure 2 and the back functional structure 4 are aligned with each other through the alignment point 3. The alignment point 3 is not directly reflected in the semiconductor device at this time, but is arranged in a non-functional area before the wafer is cut. For the specific contents of the front functional structure 2, the back functional structure 4 and the alignment point 3, please refer to the above-mentioned invention embodiment and will not be repeated here.

[0103] Specifically, in this embodiment, the edge of the back functional structure 4 and the edge of the substrate form a step structure, and the step structure is a step structure formed by cutting the wafer 1 based on the back cutting road formed on the back side of the wafer 1, and the back cutting road is aligned with the front cutting road of the wafer 1 through the alignment point 3.

[0104] Since the back functional structure 4 in this embodiment is a patterned structure, the corresponding embodiment can be cut along the back cutting path formed by the patterning of the back functional structure when dividing the wafer 1. Obviously, the width of the cutting path usually needs to be greater than the width of the cutting tool. Therefore, after cutting, a step structure will be formed between the edge of the back functional structure 4 and the edge of the substrate. This step structure is formed because the back cutting path is formed at the same time as the back functional structure 4 is patterned, and the wafer 1 is cut along the back cutting path. The back cutting path will be aligned with the cutting path of the wafer 1 through the above-mentioned alignment point 3, that is, aligned with the non-functional area on the front of the wafer 1.

[0105] Similarly, in this embodiment, the edge of the front functional structure 2 and the edge of the substrate generally form a step structure, which is a step structure formed by cutting the wafer 1 based on the front cutting road formed on the front side of the wafer 1.

[0106] The semiconductor device of this embodiment is prepared based on the above-mentioned semiconductor device preparation method. Therefore, the specific implementation method of the semiconductor device can be seen in the embodiment part of the semiconductor device preparation method in the previous text. Therefore, its specific implementation method can refer to the description of the corresponding embodiments of each part and will not be repeated here.

[0107] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0108] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0109] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0110] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0111] The above is a detailed introduction to the preparation method, wafer structure and semiconductor device of a semiconductor device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Obtaining a wafer having a functional area and a non-functional area formed on the front side, wherein the functional area is used to set the functional structure of the chip; An alignment point of a preset depth is etched in the non-functional area; the distance between the bottom surface of the alignment point and the back surface of the wafer is less than the thinning thickness of the back surface of the wafer; the position of the front functional structure can be aligned with the position of the alignment point; After setting the alignment points and the functional structure, thinning the wafer from the back side of the wafer to expose the alignment points; A back surface functional structure is provided on the back surface of the wafer to complete the preparation of the semiconductor device; the position of the back surface functional structure is aligned with the position of the alignment point.

2. The method according to claim 1, characterized in that Etching a predetermined depth of alignment points in the non-functional area includes: Setting photoresist on the front side of the wafer and exposing it to expose the preset alignment point position; An alignment point of a preset depth is etched at the alignment point position on the front side of the wafer by a plasma etching process.

3. The method according to claim 2, characterized in that Before setting photoresist on the front side of the wafer and exposing it to expose the preset alignment point position, the following steps are also included: A front functional structure is provided on the front side of the wafer.

4. The method according to claim 1, wherein Before thinning the wafer from the back side of the wafer to expose the alignment point, the method further includes: The front side of the wafer is packaged.

5. The method according to claim 4, characterized in that Packaging the front side of the wafer includes: Fill PI glue on the front side of the wafer; Immersion gold on the front side of the wafer based on the ENIG process.

6. The method according to claim 4, characterized in that After packaging the front side of the wafer, it also includes: A substrate is bonded to the front side of the wafer.

7. The method according to claim 1, characterized in that The alignment points for etching a preset depth on the front side of the wafer where the front side functional structure is provided include: A plurality of alignment points of preset depths are etched on the front side of the wafer where the front side functional structure is provided.

8. The method according to claim 7, characterized in that The distance between the plurality of alignment points is not less than the radius of the wafer.

9. The method according to claim 1, characterized in that Providing a back functional structure on the back side of the wafer includes: A back-gold array is provided on the back side of the wafer; the back-gold array includes a plurality of back-gold modules, and the back-gold array and the alignment points are aligned with each other, so that the back-gold modules and the functional areas are aligned with each other.

10. The method according to claim 9, characterized in that Providing a back-gold array on the back side of the wafer includes: providing a seed layer on the back side of the wafer; Based on the position of the positioning point, an isolation layer corresponding to the backside cutting line is provided on the surface of the seed layer; Plate a back-gold module on the area of ​​the seed layer surface not shielded by the isolation layer to form a back-gold array; After forming the back gold array, the isolation layer is removed to expose the backside cutting lanes.

11. A wafer structure, characterized in that: The functional area on the front side of the wafer is provided with a front functional structure, the back side of the wafer is provided with a back functional structure, and the non-functional area of ​​the wafer is provided with an alignment point extending from the front side to the back side, and the distance between the bottom surface of the alignment point and the initial back side of the wafer is less than the thinning thickness of the back side of the wafer; The position of the front functional structure and the position of the alignment point are aligned with each other, and the position of the back functional structure and the position of the alignment point are aligned with each other.

12. The wafer structure according to claim 11, wherein: The wafer is provided with a plurality of alignment points.

13. The wafer structure according to claim 11, wherein: At least one layer of the back functional structure is a graphic structure, and the graphic structure and the alignment points are aligned with each other.

14. A semiconductor device, characterized in that: It includes a substrate, a front functional structure and a back functional structure separated from a wafer. The front functional structure and the back functional structure are aligned with each other based on an alignment point. The alignment point is set in a non-functional area of ​​the wafer before the wafer is separated. The alignment point extends from the front to the back. The distance between the bottom surface of the alignment point and the initial back of the wafer is less than the thinning thickness of the back of the wafer.

15. The semiconductor device according to claim 14, wherein: The edge of the back functional structure and the edge of the substrate form a step structure, and the step structure is a step structure formed by cutting the wafer based on the back cutting road formed on the back of the wafer. The back cutting road is aligned with the front cutting road of the wafer through the alignment point.

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