Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises: a base substrate, a plurality of sub-pixels, and a light-shielding layer. The sub-pixels comprise a sub-pixel driving circuit. The sub-pixel driving circuit comprises a driving transistor and a compensation transistor. A first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the compensation transistor is coupled to a gate of the driving transistor by means of a first conductive connecting part. The light-shielding layer comprises a plurality of light-shielding patterns and a plurality of first light-shielding connecting parts. The orthographic projection of at least one of the plurality of light-shielding patterns on the base substrate at least partially overlaps the orthographic projection of a gate of a corresponding driving transistor on the base substrate. At least one of the plurality of first light-shielding connecting parts is coupled to a light-shielding pattern. The orthographic projection of at least one of the plurality of first light-shielding connecting parts on the base substrate at least partially overlaps the orthographic projection of the first conductive connecting part on the base substrate.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410339259.2 filed in China on March 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and consumers' demand for display quality is also increasing. To meet these higher consumer demands, the complexity of display film structures is increasing, and an increasing number of metal film layers are being used. However, metal film layers have poor transmittance. When the proportion of metal film layers in a limited layout space is too high, the transmittance of the display product decreases. Summary of the Invention

[0005] An object of the present disclosure is to provide a display substrate and a display device.

[0006] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0007] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of sub-pixels disposed on the base substrate, the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprising a driving transistor and a compensation transistor, a first electrode of the compensation transistor being coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor being coupled to a gate of the driving transistor via a first conductive connection;

[0008] The display substrate also includes a light-shielding layer, which includes a plurality of light-shielding patterns and a plurality of first light-shielding connection portions; the orthographic projection of at least one of the plurality of light-shielding patterns on the base substrate at least partially overlaps with the orthographic projection of the corresponding gate of the driving transistor on the base substrate; at least one of the plurality of first light-shielding connection portions is coupled to the light-shielding pattern, and the orthographic projection of at least one of the plurality of first light-shielding connection portions on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate.

[0009] Optionally, the display substrate further includes a first scan line, the first scan line including a first scan pattern and a second scan pattern alternately arranged, adjacent first scan patterns are coupled to the second scan patterns, a width of the first scan pattern along the first direction is greater than a width of the second scan pattern, and the first scan pattern is multiplexed as a gate of the corresponding compensation transistor;

[0010] The orthographic projection of the first light-shielding connection portion on the base substrate at least partially overlaps with the orthographic projection of the first scanning pattern on the base substrate.

[0011] Optionally, the first scanning line includes two stacked scanning layers, and each scanning layer includes the first scanning pattern and the second scanning pattern;

[0012] The orthographic projection of the first light-shielding connecting portion on the base substrate at least partially overlaps with the orthographic projection of the first scanning pattern in at least one scanning layer on the base substrate.

[0013] Optionally, the compensation transistor includes a compensation active layer, at least part of which is located between the two scanning layers; the compensation active layer includes an active layer main body and an active layer protrusion that are coupled to each other, the active layer main body is coupled to the second electrode of the driving transistor, the active layer protrusion is coupled to the first conductive connection part, and the positive projection of the active layer protrusion on the base substrate at least partially overlaps with the positive projection of the first light-shielding connection part on the base substrate.

[0014] Optionally, the sub-pixel driving circuit further includes a second conductive connection portion, a first reset transistor and a light emission control transistor; the second conductive connection portion is coupled to the second electrode of the first reset transistor, the first electrode of the light emission control transistor and the main portion of the active layer respectively;

[0015] The active layer main portion extends along a first direction, the second conductive connection portion extends along the first direction, and an orthographic projection of the second conductive connection portion on the base substrate at least partially overlaps with an orthographic projection of the active layer main portion on the base substrate.

[0016] Optionally, the display substrate further includes a second scan line, the second scan line including third scan patterns and fourth scan patterns that are alternately arranged, adjacent third scan patterns are coupled to the fourth scan patterns, and a width of the third scan pattern along the first direction is greater than a width of the fourth scan pattern;

[0017] The orthographic projection of the first light-shielding connection portion on the base substrate at least partially overlaps with the orthographic projection of the third scanning pattern on the base substrate.

[0018] Optionally, the first light-shielding connection portion includes a first sub-portion and a second sub-portion, the first sub-portion being coupled to the light-shielding pattern via the second sub-portion; a width of the first sub-portion in a direction perpendicular to its own extension direction is smaller than a width of the second sub-portion in a direction perpendicular to its own extension direction;

[0019] The orthographic projection of the first sub-portion on the base substrate does not overlap with the orthographic projection of the first conductive connection portion on the base substrate; the orthographic projection of the second sub-portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate.

[0020] Optionally, the display substrate further includes a first initialization signal transmission layer and a second initialization signal transmission layer;

[0021] The first initialization signal transmission layer includes a plurality of first initialization signal lines arranged along a first direction and a plurality of first initialization compensation lines arranged along a second direction, the first initialization signal lines include at least a portion extending along the second direction, the first initialization compensation lines include at least a portion extending along the first direction, and the first initialization compensation lines are respectively coupled to the first initialization signal lines;

[0022] The second initialization signal transmission layer includes a plurality of second initialization signal lines arranged along a first direction and a plurality of second initialization compensation lines arranged along a second direction, the second initialization signal lines include at least a portion extending along the second direction, the second initialization compensation lines include at least a portion extending along the first direction, and the second initialization compensation lines are respectively coupled to the second initialization signal lines;

[0023] The sub-pixel driving circuit further includes a first reset transistor and a second reset transistor; a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the second electrode of the driving transistor; a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to the anode of the light-emitting element;

[0024] The first initialization compensation lines and the second initialization compensation lines are alternately arranged along the second direction.

[0025] Optionally, the multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into a plurality of sub-pixel driving circuit columns arranged along the second direction, and each column of the sub-pixel driving circuit columns includes a plurality of the sub-pixel driving circuits arranged along the first direction; the multiple columns of sub-pixel driving circuit columns are divided into a plurality of column units arranged along the second direction, and each column unit includes at least three adjacent columns of sub-pixel driving circuit columns;

[0026] Each of the column units corresponds to a second initialization compensation line, and the second initialization compensation line is located in a layout area of ​​the corresponding column unit;

[0027] The odd-numbered column units correspond to one of the first initialization compensation lines, and the first initialization compensation lines are located within the layout area of ​​the corresponding odd-numbered column units; or, the even-numbered column units correspond to one of the first initialization compensation lines, and the first initialization compensation lines are located within the layout area of ​​the corresponding even-numbered column units.

[0028] Optionally, the display substrate further includes a third initialization signal transmission layer; the third initialization signal transmission layer includes a plurality of third initialization signal lines arranged along the first direction and a plurality of third initialization compensation lines arranged along the second direction, the third initialization signal lines include at least a portion extending along the second direction, the third initialization compensation lines include at least a portion extending along the first direction, and the third initialization compensation lines are respectively coupled to each of the third initialization signal lines;

[0029] The sub-pixel driving circuit further includes a third reset transistor, a first electrode of the third reset transistor is coupled to the corresponding third initialization signal line, and a second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

[0030] Optionally, the odd-numbered column units correspond to one of the third initialization compensation lines, and the third initialization compensation line is located within the layout area of ​​the corresponding odd-numbered column units; or, the even-numbered column units correspond to one of the third initialization compensation lines, and the third initialization compensation line is located within the layout area of ​​the corresponding even-numbered column units.

[0031] Optionally, the odd-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, and within the layout area of ​​the odd-numbered column units, the third initialization compensation line, the second initialization compensation line, and the first initialization compensation line are sequentially arranged along the second direction; or,

[0032] The even-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines. Within the layout area of ​​the even-numbered column units, the third initialization compensation line, the second initialization compensation line and the first initialization compensation line are sequentially arranged along the second direction.

[0033] Optionally, the first initialization signal transmission layer further includes a plurality of mutually independent first compensation patterns, wherein the first compensation pattern is coupled to at least one first initialization signal line, and a length of the first compensation pattern along the first direction is shorter than that of the first compensation signal line;

[0034] In the case where the odd-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the even-numbered column units includes at least one of the first compensation patterns;

[0035] In a case where the even-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the odd-numbered column units includes at least one of the first compensation patterns.

[0036] Optionally, the third initialization signal transmission layer further includes a plurality of independent third compensation patterns, wherein the third compensation patterns are coupled to at least one third initialization signal line, and the length of the third compensation patterns along the first direction is shorter than that of the third compensation signal line;

[0037] In the case where the odd-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the even-numbered column units includes at least one of the third compensation patterns;

[0038] In a case where the even-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the odd-numbered column units includes at least one of the third compensation patterns.

[0039] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0041] FIG1 is a circuit schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0042] FIG2 is a schematic cross-sectional view of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0043] FIG3 is a schematic diagram of the layout of the light shielding layer below the two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0044] FIG4 is a schematic diagram of the layout of polysilicon active layers in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0045] FIG5 is a schematic diagram of a layout with a light shielding layer added on the basis of FIG4 ;

[0046] FIG6 is a schematic diagram of the layout of the first gate metal layer in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0047] FIG7 is a schematic diagram of a layout in which a first gate metal layer is added on the basis of FIG4 ;

[0048] FIG8 is a schematic diagram of a layout with a light shielding layer added on the basis of FIG7;

[0049] FIG9 is a schematic diagram of the layout of the second gate metal layer in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0050] FIG10 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG8 ;

[0051] FIG11 is a schematic diagram of the layout of oxide active layers in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0052] FIG12 is a schematic diagram of a layout in which an oxide active layer is added based on FIG10;

[0053] FIG13 is a schematic diagram showing the layout of the third gate metal layer in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0054] FIG14 is a schematic diagram of a layout in which a third gate metal layer is added on the basis of FIG12;

[0055] FIG15 is a schematic diagram of the layout of vias on the first source / drain metal layer and the interlayer insulating layer in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0056] FIG16 is a schematic diagram of the layout of via holes on an interlayer insulating layer in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0057] FIG17 is a schematic diagram showing a layout of adding vias on the first source / drain metal layer and the interlayer insulating layer on the basis of FIG14;

[0058] FIG18 is a schematic diagram showing the layout of the second source and drain metal layers in two sub-pixel driving circuits provided by an embodiment of the present disclosure;

[0059] FIG19 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG17 ;

[0060] FIG20 is a schematic diagram of a first layout of an initialization signal transmission layer provided in an embodiment of the present disclosure;

[0061] FIG21 is a schematic diagram of a second layout of an initialization signal transmission layer provided in an embodiment of the present disclosure;

[0062] FIG22 is a schematic diagram of a third layout of the initialization signal transmission layer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0064] Referring to Figures 3 to 19 , an embodiment of the present disclosure provides a display substrate, including: a base substrate and a plurality of sub-pixels disposed on the base substrate. The sub-pixels include a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a driving transistor T3 and a compensation transistor T2. A first electrode of the compensation transistor T2 is coupled to a second electrode of the driving transistor T3. The second electrode of the compensation transistor T2 is coupled to a gate T3-g of the driving transistor T3 via a first conductive connection portion 11.

[0065] As shown in Figures 3, 15 and 17, the display substrate also includes a light-shielding layer LS, which includes a plurality of light-shielding patterns LS0 and a plurality of first light-shielding connection portions LS1; the orthographic projection of at least one of the plurality of light-shielding patterns LS0 on the base substrate at least partially overlaps with the orthographic projection of the corresponding gate T3-g of the driving transistor T3 on the base substrate; at least one of the plurality of first light-shielding connection portions LS1 is coupled to the light-shielding pattern LS0, and the orthographic projection of at least one of the plurality of first light-shielding connection portions LS1 on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 11 on the base substrate.

[0066] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. The plurality of columns of sub-pixel driving circuits are arranged along a second direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0067] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0068] The specific structure of the sub-pixel driving circuit varies, for example, a 7T1C circuit structure (i.e., 7 transistors and 1 capacitor) or an 8T1C circuit structure (i.e., 8 transistors and 1 capacitor), but is not limited thereto. The specific structure of the sub-pixel driving circuit will be described below using the 8T1C circuit structure as an example.

[0069] As shown in Figure 1, the display substrate includes a power line VDD, a data line DA, a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2, a third initialization signal transmission layer Vinit3, a first reset signal line Rst1, a second reset signal line Rst2, a first scan line G1, a second scan line G2, and a light emitting control signal line EM.

[0070] The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a third reset transistor T8, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emitting control transistor T6 and a storage capacitor Cst.

[0071] The gate of the first transistor T1 is coupled to the corresponding second reset signal line Rst2 , the first electrode of the first transistor T1 is coupled to the first initialization signal transmission layer Vinit1 , and the second electrode of the first transistor T1 is coupled to the second electrode of the third transistor T3 .

[0072] The gate of the second transistor T2 is coupled to the corresponding first scan line G1, the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3. The second transistor T2 includes an oxide transistor.

[0073] A gate of the fourth transistor T4 is coupled to the corresponding second scan line G2 , a first electrode of the fourth transistor T4 is coupled to the corresponding data line DA, and a second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3 .

[0074] A gate of the fifth transistor T5 is coupled to the corresponding light emitting control signal line EM, a first electrode of the fifth transistor T5 is coupled to the power layer VDD, and a second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor.

[0075] The gate of the sixth transistor T6 is coupled to the corresponding light-emitting control signal line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3, the second electrode of the sixth transistor T6 is coupled to the anode of the light-emitting element, and the cathode of the light-emitting element receives the negative power signal VSS.

[0076] A gate of the seventh transistor T7 is coupled to the corresponding first reset signal line Rst1 , a first electrode of the seventh transistor T7 is coupled to the second initialization signal transmission layer Vinit2 , and a second electrode of the seventh transistor T7 is coupled to the anode of the light emitting element.

[0077] A gate of the eighth transistor T8 is coupled to the corresponding first reset signal line Rst1 , a first electrode of the eighth transistor T8 is coupled to the third initialization signal transmission layer Vinit3 , and a second electrode of the eighth transistor T8 is coupled to the first electrode of the third transistor T3 .

[0078] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate T3 - g of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power layer VDD.

[0079] As shown in FIG2 , the display substrate exemplarily includes a buffer layer BF, a polysilicon active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, an oxide active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2. A passivation layer PVX may also be provided on the display substrate as needed. The passivation layer PVX may be located between the first source / drain metal layer SD1 and the first planarization layer PLN1, or between the first planarization layer PLN1 and the second source / drain metal layer SD2.

[0080] Exemplarily, the sub-pixel driving circuit further includes a first conductive connection portion 11, the first conductive connection portion 11 including at least a portion extending along the first direction, and configured to connect the second electrode of the compensation transistor T2 and the gate T3-g of the driving transistor T3.

[0081] As shown in Figure 3, the display substrate further includes a light-shielding layer LS, which is located on the side of the sub-pixel driving circuit facing the base substrate. The light-shielding layer LS includes a plurality of light-shielding patterns LS0 and a plurality of first light-shielding connecting portions LS1. The plurality of light-shielding patterns LS0 are arranged in an array, and the orthographic projections of the light-shielding patterns LS0 on the base substrate at least partially overlap with the orthographic projections of the corresponding gates T3-g of the driving transistors T3 on the base substrate. Furthermore, the orthographic projections of the light-shielding patterns LS0 on the base substrate can be configured to completely cover the orthographic projections of the corresponding gates T3-g of the driving transistors T3 on the base substrate.

[0082] As shown in Figure 3, illustratively, the first light-shielding connection portion LS1 includes at least a portion extending along the first direction, and the first light-shielding connection portion LS1 is coupled to the light-shielding pattern LS0 adjacent to the first direction. The light-shielding layer LS also includes a plurality of second light-shielding connection portions LS2, each of which includes at least a portion extending along the second direction, and is coupled to the light-shielding pattern LS0 adjacent to the second direction, so that the light-shielding layer LS forms a grid-like structure.

[0083] Exemplarily, the first conductive connection portion 11 is made of a metal material and can be provided in the same layer and material as the first source / drain metal layer. The first light-shielding connection portion LS1 is also made of a metal material, and the orthographic projection of the first light-shielding connection portion LS1 on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 11 on the base substrate. For example, at least the portion of the first light-shielding connection portion LS1 extending along the first direction can be completely covered by the orthographic projection of the first conductive connection portion 11 on the base substrate.

[0084] Based on the specific structure of the display substrate described above, the display substrate provided in the disclosed embodiment optimizes the design of the light-shielding layer LS by arranging the orthographic projection of the first light-shielding connection portion LS1 on the base substrate to at least partially overlap with the orthographic projection of the first conductive connection portion 11 on the base substrate. This reduces the proportion of the light-shielding area within the limited layout area blocked by the entire light-shielding film layer. This arrangement can improve transmittance by over 13%, effectively optimizing the transmittance of the display product. Furthermore, after a risk assessment, it was confirmed that this design eliminates other layout risks and can ensure the manufacturing yield and operational stability of the display substrate.

[0085] As shown in FIG3 and FIG9 to FIG14, in some embodiments, the display substrate further includes a first scan line G1, the first scan line G1 including a first scan pattern G101 and a second scan pattern G102 alternately arranged, adjacent first scan patterns G101 and second scan patterns G102 are coupled, a width of the first scan pattern G101 along a first direction is greater than a width of the second scan pattern G102, and the first scan pattern G101 is multiplexed as a gate of the corresponding compensation transistor T2;

[0086] The orthographic projection of the first light-shielding connection portion LS1 on the base substrate at least partially overlaps with the orthographic projection of the first scanning pattern G101 on the base substrate.

[0087] Exemplarily, the display substrate includes a plurality of first scan lines G1 arranged along the first direction, the first scan lines G1 include at least a portion extending along the second direction, the plurality of first scan lines G1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first scan lines G1 are respectively coupled to the gates of the compensation transistors T2 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0088] Illustratively, the orthographic projection of the first light-shielding connection portion LS1 on the base substrate at least partially overlaps with the orthographic projection of the second scanning pattern G102 on the base substrate.

[0089] The first light-shielding connection portion LS1 includes at least a portion extending along the first direction. The above-mentioned setting is that the width of the first scanning pattern G101 along the first direction is greater than the width of the second scanning pattern G102, and the orthographic projection of the first light-shielding connection portion LS1 on the base substrate and the orthographic projection of the first scanning pattern G101 on the base substrate at least partially overlap, which is beneficial to further reduce the proportion of the blocked area of ​​all light-shielding film layers with light-shielding effect in the limited layout area, thereby further optimizing the transmittance of the display product.

[0090] As shown in FIG3 and FIG9 to FIG14 , in some embodiments, the first scanning line G1 includes two stacked scanning layers G10 , and each scanning layer G10 includes the first scanning pattern G101 and the second scanning pattern G102 ;

[0091] The orthographic projection of the first light-shielding connecting portion LS1 on the base substrate at least partially overlaps with the orthographic projection of the first scanning pattern G101 in at least one scanning layer G10 on the base substrate.

[0092] Exemplarily, of the two scanning layers G10 , the scanning layer G10 close to the base substrate is provided in the same layer and material as the second gate metal layer, and the scanning layer G10 away from the base substrate is provided in the same layer and material as the third gate metal layer.

[0093] Illustratively, an orthographic projection of the first light-shielding connection portion LS1 on the base substrate at least partially overlaps with an orthographic projection of the second scanning pattern G102 in at least one scanning layer G10 on the base substrate.

[0094] The above-mentioned arrangement is conducive to further reducing the proportion of the blocked area of ​​all the light-shielding film layers with light-shielding function in the limited layout area, thereby further optimizing the transmittance of the display product.

[0095] As shown in Figures 11 and 12, in some embodiments, the compensation transistor T2 includes a compensation active layer 22, and at least a portion of the compensation active layer 22 is located between the two scanning layers G10; the orthographic projection of the compensation active layer 22 on the base substrate at least partially overlaps with the orthographic projection of the first light-shielding connection portion LS1 on the base substrate.

[0096] The above-mentioned arrangement is conducive to further reducing the proportion of the blocked area of ​​all the light-shielding film layers with light-shielding function in the limited layout area, thereby further optimizing the transmittance of the display product.

[0097] As shown in Figures 11 and 12, in some embodiments, the compensation transistor T2 includes a compensation active layer 22, at least part of which is located between the two scanning layers G10; the compensation active layer 22 includes an active layer main body 221 and an active layer protrusion 222 coupled to each other, the active layer main body 221 is coupled to the second electrode of the driving transistor T3, the active layer protrusion 222 is coupled to the first conductive connection portion 11, and the orthographic projection of the active layer protrusion 222 on the substrate at least partially overlaps with the orthographic projection of the first light-shielding connection portion LS1 on the substrate.

[0098] Exemplarily, the oxide active layer includes the compensation active layer 22. At least a portion of the compensation active layer 22 is located between the two scanning layers G10, so that the compensation transistor T2 is formed as an oxide transistor with a dual-gate structure.

[0099] Exemplarily, the compensation active layer 22 includes an active layer main portion 221 and an active layer protrusion 222 of an integrated structure, wherein the active layer main portion 221 includes at least a portion extending along the first direction, and the active layer protrusion 222 protrudes from the active layer main portion 221 along the second direction.

[0100] The above-mentioned setting of the orthographic projection of the active layer protrusion 222 on the base substrate and the orthographic projection of the first shading connection portion LS1 on the base substrate at least partially overlap is beneficial to further reduce the proportion of the blocked area of ​​all shading film layers with shading effect in the limited layout area, thereby further optimizing the transmittance of the display product.

[0101] As shown in FIG3 , FIG11 , FIG15 and FIG17 , in some embodiments, the sub-pixel driving circuit further includes a second conductive connection portion 12 , a first reset transistor T1 and a light emission control transistor T6 ; the second conductive connection portion 12 is respectively coupled to the second electrode of the first reset transistor T1 , the first electrode of the light emission control transistor T6 and the active layer main portion 221 ;

[0102] The active layer main portion 221 extends along a first direction, the second conductive connection portion 12 extends along the first direction, and the orthographic projection of the second conductive connection portion 12 on the base substrate at least partially overlaps with the orthographic projection of the active layer main portion 221 on the base substrate.

[0103] Exemplarily, the display substrate includes a plurality of second reset signal lines Rst2 arranged along the first direction, the second reset signal lines Rst2 including at least a portion extending along the second direction. The plurality of second reset signal lines Rst2 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and the second reset signal line Rst2 is respectively coupled to the gate of the first reset transistor T1 included in each sub-pixel driver circuit in a corresponding row of sub-pixel driver circuits.

[0104] Exemplarily, the display substrate includes a plurality of emission control signal lines EM arranged along the first direction, the emission control signal lines EM including at least a portion extending along the second direction. The plurality of emission control signal lines EM correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the emission control signal lines EM are respectively coupled to the gate of the emission control transistor T6 and the gate of the power control transistor T5 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0105] Exemplarily, the second conductive connection portion 12 is provided in the same layer and made of the same material as the first source / drain metal layer, and the second conductive connection portion 12 includes at least a portion extending along the first direction.

[0106] The above-mentioned setting of the orthographic projection of the second conductive connection part 12 on the base substrate at least partially overlaps with the orthographic projection of the active layer main part 221 on the base substrate, which is beneficial to further reduce the proportion of the blocked area of ​​all the shading film layers with shading effect in the limited layout area, thereby further optimizing the transmittance of the display product.

[0107] As shown in FIG6 to FIG8, in some embodiments, the display substrate further includes a second scan line G2, and the second scan line G2 includes third scan patterns G21 and fourth scan patterns G22 that are alternately arranged. Adjacent third scan patterns G21 are coupled to the fourth scan patterns G22. The width of the third scan pattern G21 along the first direction is greater than the width of the fourth scan pattern G22.

[0108] The orthographic projection of the first light-shielding connection portion LS1 on the base substrate at least partially overlaps with the orthographic projection of the third scanning pattern G21 on the base substrate.

[0109] Exemplarily, the display substrate includes a plurality of second scan lines G2 arranged along the first direction, each of the second scan lines G2 including at least a portion extending along the second direction. The plurality of second scan lines G2 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and the second scan lines G2 are respectively coupled to the gates of the data writing transistors T4 included in each sub-pixel driver circuit in a corresponding row of sub-pixel driver circuits.

[0110] Exemplarily, the display substrate further includes a plurality of data lines DA arranged along the second direction, the data lines DA including at least a portion extending along the first direction. The plurality of data lines DA correspond one-to-one to the plurality of sub-pixel drive circuit columns, and the data lines DA are respectively coupled to the first electrode of the data write transistor T4 included in each sub-pixel drive circuit in the corresponding column of sub-pixel drive circuits.

[0111] For example, the display substrate adopts FIP (Fanout In Panel) technology, which can achieve the purpose of reducing the frame.

[0112] For example, the display substrate adopts SIP (VSS In Panel) technology, which provides a more efficient space utilization and integration solution, and is conducive to realizing a more compact, higher performance, and more functional display device.

[0113] Exemplarily, the second scan line G2 is provided in the same layer and material as the first gate metal layer. The second scan line G2 includes a plurality of third scan patterns G21 and a plurality of fourth scan patterns G22, wherein the third scan patterns G21 and the fourth scan patterns G22 are alternately arranged, and adjacent third scan patterns G21 and fourth scan patterns G22 are coupled.

[0114] The first light-shielding connection portion LS1 includes at least a portion extending along the first direction, and the width of the third scanning pattern G21 along the first direction is greater than the width of the fourth scanning pattern G22; and the orthographic projection of the first light-shielding connection portion LS1 on the base substrate and the orthographic projection of the third scanning pattern G21 on the base substrate at least partially overlap, which is beneficial to further reduce the proportion of the blocked area of ​​all light-shielding film layers with light-shielding effect in the limited layout area. When the display substrate adopts the FIP design, the transmittance of the display product can be further optimized.

[0115] As shown in FIG3 and FIG17 , in some embodiments, the first light-shielding connection portion LS1 includes a first sub-portion LS11 and a second sub-portion LS12. The first sub-portion LS11 is coupled to the light-shielding pattern LS0 via the second sub-portion LS12. A width d1 of the first sub-portion LS11 in a direction perpendicular to its own extension direction is smaller than a width d2 of the second sub-portion LS12 in a direction perpendicular to its own extension direction.

[0116] The orthographic projection of the first sub-portion LS11 on the base substrate does not overlap with the orthographic projection of the first conductive connecting portion 11 on the base substrate; the orthographic projection of the second sub-portion LS12 on the base substrate at least partially overlaps with the orthographic projection of the first conductive connecting portion 11 on the base substrate.

[0117] Exemplarily, the second sub-portion LS12 includes at least a portion extending along the first direction, and the first sub-portion LS11 includes at least a portion extending along a third direction, where the third direction intersects both the first direction and the second direction.

[0118] The first sub-portion LS11 that does not overlap with the orthographic projection of the first conductive connection portion 11 on the base substrate has a smaller width, which is beneficial to further reduce the proportion of the blocked area of ​​all shading film layers with shading function in the limited layout area, thereby further optimizing the transmittance of the display product.

[0119] As shown in FIG. 20 and FIG. 21 , in some embodiments, the display substrate further includes a first initialization signal transmission layer Vinit1 and a second initialization signal transmission layer Vinit2;

[0120] The first initialization signal transmission layer Vinit1 includes a plurality of first initialization signal lines Vinit11 arranged along a first direction and a plurality of first initialization compensation lines Vinit12 arranged along a second direction, wherein the first initialization signal line Vinit11 includes at least a portion extending along the second direction, and the first initialization compensation line Vinit12 includes at least a portion extending along the first direction, and the first initialization compensation line Vinit12 is coupled to each of the first initialization signal lines Vinit11 respectively;

[0121] The second initialization signal transmission layer Vinit2 includes a plurality of second initialization signal lines Vinit21 arranged along a first direction and a plurality of second initialization compensation lines Vinit22 arranged along a second direction, wherein the second initialization signal line Vinit21 includes at least a portion extending along the second direction, and the second initialization compensation line Vinit22 includes at least a portion extending along the first direction, and the second initialization compensation line Vinit22 is coupled to each of the second initialization signal lines Vinit21 respectively;

[0122] The sub-pixel driving circuit further includes a first reset transistor T1 and a second reset transistor T7; a first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit11, and a second electrode of the first reset transistor T1 is coupled to the second electrode of the driving transistor T3; a first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit21, and a second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element;

[0123] The first initialization compensation lines Vinit12 and the second initialization compensation lines Vinit22 are alternately arranged along the second direction.

[0124] Exemplarily, the multiple first initialization signal lines Vinit11 correspond one-to-one to the multiple rows of sub-pixel driving circuits, and the first initialization signal line Vinit11 is respectively coupled to the first electrode of the first reset transistor T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0125] Exemplarily, the plurality of second initialization signal lines Vinit21 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second initialization signal line Vinit21 is respectively coupled to the first electrode of the second reset transistor T7 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0126] Exemplarily, the first initialization compensation lines Vinit12 and the second initialization compensation lines Vinit22 are alternately arranged along the second direction. The spacing between adjacent first initialization compensation lines Vinit12 and second initialization compensation lines Vinit22 is greater than or equal to the width of the layout area of ​​a column of sub-pixel driving circuits along the second direction.

[0127] The above-mentioned setting of the first initialization signal transmission layer Vinit1 includes the first initialization signal line Vinit11 and the first initialization compensation line Vinit12, so that the first initialization signal transmission layer Vinit1 forms a grid structure, which is beneficial to improving the signal transmission uniformity of the first initialization signal transmission layer Vinit1 and reducing the loading of the first initialization signal transmission layer Vinit1.

[0128] The above-mentioned setting of the second initialization signal transmission layer Vinit2 includes the second initialization signal line Vinit21 and the second initialization compensation line Vinit22, so that the second initialization signal transmission layer Vinit2 is formed into a grid structure, which is beneficial to improving the signal transmission uniformity of the second initialization signal transmission layer Vinit2 and reducing the loading of the second initialization signal transmission layer Vinit2.

[0129] As shown in FIG20 and FIG21 , in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of sub-pixel driving circuit columns Q arranged along the second direction, each of the sub-pixel driving circuit columns Q including a plurality of sub-pixel driving circuits arranged along the first direction; the plurality of sub-pixel driving circuit columns Q are divided into a plurality of column units LQ arranged along the second direction, each column unit LQ including at least three adjacent sub-pixel driving circuit columns Q;

[0130] Each of the column units LQ corresponds to a second initialization compensation line Vinit22 , and the second initialization compensation line Vinit22 is located in a layout area of ​​the corresponding column unit LQ;

[0131] The odd-numbered column units correspond to a first initialization compensation line Vinit12, and the first initialization compensation line Vinit12 is located in the layout area of ​​the corresponding odd-numbered column units; or, the even-numbered column units correspond to a first initialization compensation line Vinit12, and the first initialization compensation line Vinit12 is located in the layout area of ​​the corresponding even-numbered column units.

[0132] It should be noted that the layout area of ​​a column unit is the layout area occupied by all sub-pixel driving circuits in the column unit. The layout area occupied by each sub-pixel driving circuit can be an area that can accommodate the sub-pixel driving circuit. Exemplarily, this area can be a rectangular area, but is not limited to this.

[0133] It should be noted that the circular holes in Figure 20 represent connection holes, and the black dots in Figure 21 represent connection holes. The position distribution of these connection holes is not specifically limited, and is only illustrative in the figure.

[0134] Exemplarily, the plurality of first initialization compensation lines Vinit12 included in the first initialization signal transmission layer Vinit1 correspond one-to-one to the plurality of odd-numbered column units included in the display substrate, and the first initialization compensation line Vinit12 is located within the layout area of ​​the corresponding column of odd-numbered column units. Alternatively, the plurality of first initialization compensation lines Vinit12 included in the first initialization signal transmission layer Vinit1 correspond one-to-one to the plurality of even-numbered column units included in the display substrate, and the first initialization compensation line Vinit12 is located within the layout area of ​​the corresponding column of even-numbered column units.

[0135] Exemplarily, the second initialization signal transmission layer Vinit2 includes a plurality of second initialization compensation lines Vinit22 that correspond one-to-one to a plurality of column units included in the display substrate, and the second initialization compensation line Vinit22 is located in a layout area of ​​a corresponding column of the column units.

[0136] The above-mentioned setting method can ensure the routing density of the second initialization compensation line Vinit22 which has a greater impact on the display quality, while reducing the routing density of the first initialization compensation line Vinit12 which has a smaller impact on the product, thereby effectively reducing the light-blocking area formed by the first initialization compensation line Vinit12, thereby increasing the area ratio of the light-transmitting area of ​​the display substrate, and bringing at least 3% transmittance improvement effect to the product.

[0137] As shown in FIG20 and FIG21 , in some embodiments, the display substrate further includes a third initialization signal transmission layer Vinit3; the third initialization signal transmission layer Vinit3 includes a plurality of third initialization signal lines Vinit31 arranged along the first direction and a plurality of third initialization compensation lines Vinit32 arranged along the second direction, the third initialization signal lines Vinit31 including at least a portion extending along the second direction, the third initialization compensation lines Vinit32 including at least a portion extending along the first direction, and the third initialization compensation lines Vinit32 are respectively coupled to each of the third initialization signal lines Vinit31;

[0138] The sub-pixel driving circuit further includes a third reset transistor T8 , a first electrode of the third reset transistor T8 is coupled to the corresponding third initialization signal line Vinit31 , and a second electrode of the third reset transistor T8 is coupled to the first electrode of the driving transistor T3 .

[0139] Exemplarily, the plurality of third initialization signal lines Vinit31 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the third initialization signal line Vinit31 is respectively coupled to the first electrode of the third reset transistor T8 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0140] Exemplarily, the third initialization compensation lines Vinit32 and the second initialization compensation lines Vinit22 are alternately arranged along the second direction. The spacing between adjacent third initialization compensation lines Vinit32 and second initialization compensation lines Vinit22 is greater than or equal to the width of the layout area of ​​a column of sub-pixel driving circuits along the second direction.

[0141] The above-mentioned setting of the third initialization signal transmission layer Vinit3 includes the third initialization signal line Vinit31 and the third initialization compensation line Vinit32, so that the third initialization signal transmission layer Vinit3 is formed into a grid structure, which is beneficial to improving the signal transmission uniformity of the third initialization signal transmission layer Vinit3 and reducing the loading of the third initialization signal transmission layer Vinit3.

[0142] As shown in Figures 20 and 21, in some embodiments, the odd-numbered column units correspond to the third initialization compensation line Vinit32, and the third initialization compensation line Vinit32 is located in the layout area of ​​the corresponding odd-numbered column units; or, the even-numbered column units correspond to the third initialization compensation line Vinit32, and the third initialization compensation line Vinit32 is located in the layout area of ​​the corresponding even-numbered column units.

[0143] Exemplarily, the third initialization signal transmission layer Vinit3 includes a plurality of third initialization compensation lines Vinit32 that correspond one-to-one to the plurality of odd-numbered column cells included in the display substrate, and the third initialization compensation lines Vinit32 are located within the layout area of ​​the corresponding column of odd-numbered column cells. Alternatively, the third initialization signal transmission layer Vinit3 includes a plurality of third initialization compensation lines Vinit32 that correspond one-to-one to the plurality of even-numbered column cells included in the display substrate, and the third initialization compensation lines Vinit32 are located within the layout area of ​​the corresponding column of even-numbered column cells.

[0144] The above-mentioned setting method can ensure the routing density of the second initialization compensation line Vinit22 which has a greater impact on the display quality, while reducing the routing density of the third initialization compensation line Vinit32 which has a smaller impact on the product, thereby effectively reducing the area of ​​the light-blocking area formed by the third initialization compensation line Vinit32, thereby increasing the area ratio of the light-transmitting area of ​​the display substrate, and bringing at least 3% transmittance improvement effect to the product.

[0145] As shown in Figure 20, in some embodiments, the odd-numbered column units correspond to one of the first initialization compensation lines Vinit12 and one of the third initialization compensation lines Vinit32, and within the layout area of ​​the odd-numbered column units, the third initialization compensation line Vinit32, the second initialization compensation line Vinit22 and the first initialization compensation line Vinit12 are arranged in sequence along the second direction; or, the even-numbered column units correspond to one of the first initialization compensation lines Vinit12 and one of the third initialization compensation line Vinit32, and within the layout area of ​​the even-numbered column units, the third initialization compensation line Vinit32, the second initialization compensation line Vinit22 and the first initialization compensation line Vinit12 are arranged in sequence along the second direction.

[0146] More specifically, odd-numbered column units correspond to one first initialization compensation line Vinit12, one second initialization compensation line Vinit22, and one third initialization compensation line Vinit32. Even-numbered column units correspond to only one second initialization compensation line Vinit22. Alternatively, even-numbered column units correspond to one first initialization compensation line Vinit12, one second initialization compensation line Vinit22, and one third initialization compensation line Vinit32. Odd-numbered column units correspond to only one second initialization compensation line Vinit22.

[0147] Taking the example of each column unit including three adjacent columns of sub-pixel driver circuits, one first initialization compensation line Vinit12, two second initialization compensation lines Vinit22, and one third initialization compensation line Vinit32 are arranged in each of two adjacent column units. Exemplarily, within a column unit, the first initialization compensation line Vinit12, the second initialization compensation line Vinit22, and the third initialization compensation line Vinit32 correspond one-to-one to the three columns of sub-pixel driver circuits, and each initialization compensation line is located within the layout area of ​​the corresponding column of sub-pixel driver circuits.

[0148] As shown in FIG22 , in some embodiments, the display substrate adopts an RGBG pixel layout. Multiple sub-pixels in the display substrate include multiple light-emitting elements, each of which includes multiple anode patterns distributed in an array. The multiple anode patterns are divided into multiple columns of anode patterns, and the multiple columns of anode patterns are divided into anode column units arranged along the second direction.

[0149] Each column of anode column units includes a first column of green anode patterns G, a second column of mixed anode patterns, a third column of green anode patterns G and a fourth column of mixed anode patterns arranged in sequence. The green anode pattern G refers to the anode pattern included in the light-emitting element of the green sub-pixel. The mixed anode pattern includes a red anode pattern R and a blue anode pattern B. The red anode pattern R refers to the anode pattern included in the light-emitting element of the red sub-pixel. The blue anode pattern B refers to the anode pattern included in the light-emitting element of the blue sub-pixel.

[0150] The red anode patterns R and the blue anode patterns B in the second column of mixed anode patterns are alternately arranged along the first direction. The blue anode patterns B and the red anode patterns R in the fourth column of mixed anode patterns are alternately arranged along the first direction.

[0151] The orthographic projection of the first initialization compensation line Vinit12 on the base substrate overlaps with the orthographic projection of at least part of the green anode pattern G in a corresponding column of green anode patterns G on the base substrate; and / or, the orthographic projection of the second initialization compensation line Vinit22 on the base substrate overlaps with the orthographic projection of at least part of the green anode pattern G in a corresponding column of green anode patterns G on the base substrate; and / or, the orthographic projection of the third initialization compensation line Vinit32 on the base substrate overlaps with the orthographic projection of at least part of the green anode pattern G in a corresponding column of green anode patterns G on the base substrate.

[0152] As shown in FIG22 , in some embodiments, the first initialization signal transmission layer Vinit1 further includes a plurality of mutually independent first compensation patterns 61 , wherein the first compensation pattern 61 is coupled to at least one first initialization signal line Vinit11 , and the length of the first compensation pattern 61 along the first direction is shorter than that of the first compensation signal line;

[0153] In the case where the odd-numbered column units correspond to one of the first initialization compensation lines Vinit12 and one of the third initialization compensation lines Vinit32, the layout area of ​​the even-numbered column units includes at least one of the first compensation patterns 61.

[0154] When the even-numbered column units correspond to one of the first initialization compensation lines Vinit12 and one of the third initialization compensation lines Vinit32 , the layout area of ​​the odd-numbered column units includes at least one of the first compensation patterns 61 .

[0155] Illustratively, the orthographic projection of the first compensation pattern 61 on the base substrate at least partially overlaps with the orthographic projection of the green anode pattern on the base substrate.

[0156] Exemplarily, when the layout area of ​​the even-numbered column units includes at least one of the first compensation patterns 61, or the layout area of ​​the odd-numbered column units includes at least one of the first compensation patterns 61, the first compensation patterns 61 can be arranged in areas with dense metal wiring, while the first compensation patterns 61 are not arranged in areas with sparse metal wiring and high transmittance (such as the area between the red anode pattern R and the blue anode pattern B along the second direction).

[0157] The above layout can achieve the goal of minimizing the influence of the first signal transmission layer on the transmittance of the display substrate while ensuring the uniformity and low loading effect of the first initialization signal transmission layer Vinit1.

[0158] In some embodiments, the third initialization signal transmission layer Vinit3 further includes a plurality of independent third compensation patterns, wherein the third compensation patterns are coupled to at least one third initialization signal line Vinit31, and the length of the third compensation patterns along the first direction is shorter than that of the third compensation signal line;

[0159] In the case where the odd-numbered column units correspond to one of the first initialization compensation lines Vinit12 and one of the third initialization compensation lines Vinit32, the layout area of ​​the even-numbered column units includes at least one of the third compensation patterns;

[0160] In a case where the even-numbered column units correspond to one of the first initialization compensation lines Vinit12 and one of the third initialization compensation lines Vinit32 , the layout area of ​​the odd-numbered column units includes at least one of the third compensation patterns.

[0161] Illustratively, an orthographic projection of the third compensation pattern on the base substrate at least partially overlaps with an orthographic projection of the green anode pattern on the base substrate.

[0162] Exemplarily, when the layout area of ​​the even-numbered column units includes at least one of the third compensation patterns, or the layout area of ​​the odd-numbered column units includes at least one of the third compensation patterns, the third compensation patterns can be arranged in areas with dense metal wiring, while the third compensation patterns are not arranged in areas with sparse metal wiring and higher transmittance (such as the area between the red anode pattern and the blue anode pattern along the second direction).

[0163] The above layout can achieve the goal of minimizing the influence of the third initialization signal transmission layer on the transmittance of the display substrate while ensuring the uniformity and low loading effect of the third initialization signal transmission layer Vinit3.

[0164] It should be noted that, as shown in Figure 4, Figure 4 illustrates a first reset active layer 21, a driving active layer 23, a data writing active layer 24, a power control active layer 25, a light emitting control active layer 26, a second reset active layer 27, and a third reset active layer 28.

[0165] As shown in FIG. 5 to FIG. 19 , the first conductive connection portion 11 is coupled to the second electrode of the compensation transistor T2 through the fifth via hole Via5 , and is coupled to the gate electrode of the driving transistor T3 through the ninth via hole Via9 .

[0166] The second conductive connection portion 12 is coupled to the second electrode of the first reset transistor T1 through the fourth via Via4, the second conductive connection portion 12 is coupled to the first electrode of the compensation transistor T2 through the seventh via Via7, and the second conductive connection portion 12 is coupled to the second electrode of the driving transistor T3 through the eighth via Via8.

[0167] The third conductive connection portion 13 is coupled to the second initialization signal line Vinit21 through the third via Via3 , and the third conductive connection portion 13 is coupled to the first electrode of the second reset transistor T7 through the sixteenth via Via16 .

[0168] The fourth conductive connection portion 14 is coupled to the first initialization signal line Vinit11 through the first via Via1 , and the fourth conductive connection portion 14 is coupled to the first electrode of the first reset transistor T1 through the second via Via2 .

[0169] The fifth conductive connection portion 15 is coupled to the first electrode of the data writing transistor T4 through the sixth via hole Via6 , and the fifth conductive connection portion 15 is coupled to the data line DA through the eighteenth via hole Via18 .

[0170] The sixth conductive connection portion 16 is coupled to the second plate Cst2 of the storage capacitor Cst through the tenth via Via10, the sixth conductive connection portion 16 is coupled to the first electrode of the power control transistor T5 through the twelfth via Via12, and the sixth conductive connection portion 16 is coupled to the power line VDD through the nineteenth via Via19.

[0171] The seventh conductive connection portion 17 is coupled to the third initialization signal line Vinit31 through the thirteenth via hole Via13 , and the seventh conductive connection portion 17 is coupled to the first electrode of the third reset transistor T8 through the fourteenth via hole Via14 .

[0172] The eighth conductive connection portion 18 is coupled to the first electrode of the driving transistor T3 through the eleventh via hole Via11 , and the eighth conductive connection portion 18 is coupled to the second electrode of the third reset transistor T8 through the fifteenth via hole Via15 .

[0173] The ninth conductive connection portion 19 is coupled to the second electrode of the light emitting control transistor T6 through the seventeenth via hole Via17 . The ninth conductive connection portion 19 is coupled to the tenth conductive connection portion 50 through the twentieth via hole Via20 . The tenth conductive connection portion 50 is coupled to the corresponding anode.

[0174] As shown in FIG. 20 and FIG. 21 , an embodiment of the present disclosure further provides a display substrate, wherein the display substrate further includes a first initialization signal transmission layer Vinit1 and a second initialization signal transmission layer Vinit2 ;

[0175] The first initialization signal transmission layer Vinit1 includes a plurality of first initialization signal lines Vinit11 arranged along a first direction and a plurality of first initialization compensation lines Vinit12 arranged along a second direction, the first initialization signal line Vinit11 includes at least a portion extending along the second direction, the first initialization compensation line Vinit12 includes at least a portion extending along the first direction, the first direction intersects the second direction, and the first initialization compensation line Vinit12 is coupled to each of the first initialization signal lines Vinit11 respectively;

[0176] The second initialization signal transmission layer Vinit2 includes a plurality of second initialization signal lines Vinit21 arranged along a first direction and a plurality of second initialization compensation lines Vinit22 arranged along a second direction, wherein the second initialization signal line Vinit21 includes at least a portion extending along the second direction, and the second initialization compensation line Vinit22 includes at least a portion extending along the first direction, and the second initialization compensation line Vinit22 is coupled to each of the second initialization signal lines Vinit21 respectively;

[0177] The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, and a second reset transistor T7; a first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit11, and a second electrode of the first reset transistor T1 is coupled to the second electrode of the driving transistor T3; a first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit21, and a second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element;

[0178] The first initialization compensation lines Vinit12 and the second initialization compensation lines Vinit22 are alternately arranged along the second direction.

[0179] Exemplarily, the multiple first initialization signal lines Vinit11 correspond one-to-one to the multiple rows of sub-pixel driving circuits, and the first initialization signal line Vinit11 is respectively coupled to the first electrode of the first reset transistor T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0180] Exemplarily, the plurality of second initialization signal lines Vinit21 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second initialization signal line Vinit21 is respectively coupled to the first electrode of the second reset transistor T7 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0181] Exemplarily, the first initialization compensation lines Vinit12 and the second initialization compensation lines Vinit22 are alternately arranged along the second direction. The spacing between adjacent first initialization compensation lines Vinit12 and second initialization compensation lines Vinit22 is greater than or equal to the width of the layout area of ​​a column of sub-pixel driving circuits along the second direction.

[0182] In the display substrate provided by the embodiment of the present disclosure, the first initialization signal transmission layer Vinit1 is provided to include the first initialization signal line Vinit11 and the first initialization compensation line Vinit12, so that the first initialization signal transmission layer Vinit1 is formed into a grid structure, which is beneficial to improving the signal transmission uniformity of the first initialization signal transmission layer Vinit1 and reducing the loading of the first initialization signal transmission layer Vinit1.

[0183] In the display substrate provided by the embodiment of the present disclosure, the second initialization signal transmission layer Vinit2 is provided to include the second initialization signal line Vinit21 and the second initialization compensation line Vinit22, so that the second initialization signal transmission layer Vinit2 is formed into a grid structure, which is beneficial to improving the signal transmission uniformity of the second initialization signal transmission layer Vinit2 and reducing the loading of the second initialization signal transmission layer Vinit2.

[0184] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0185] Exemplarily, the display device includes an LTPO display device, but is not limited thereto.

[0186] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0187] In the display substrate provided in the above embodiment, by arranging the orthographic projection of the first light-shielding connection portion on the base substrate to at least partially overlap with the orthographic projection of the first conductive connection portion on the base substrate, the design of the light-shielding layer is optimized, reducing the proportion of the total light-shielding film layer shielding the limited layout area. This arrangement can improve transmittance by more than 13%, effectively optimizing the transmittance of the display product. Furthermore, after a risk assessment, it was confirmed that this design scheme does not pose any other layout risks and can ensure the manufacturing yield and operational stability of the display substrate.

[0188] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0189] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extended along the certain direction is greater than the length of the secondary part extended along other directions.

[0190] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, the film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then using the same mask to pattern the film layer through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0191] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0192] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0193] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. Terms such as "include" or "comprising" mean that the element or object preceding the term includes the elements or objects listed after the term and their equivalents, without excluding other elements or objects. Terms such as "connect," "couple," or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be "directly" "on" or "below" the other element, or there may be intervening elements. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any appropriate manner in any one or more embodiments or examples. The above description is only a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate, the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprising a driving transistor and a compensation transistor, a first electrode of the compensation transistor being coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor being coupled to a gate of the driving transistor via a first conductive connection; The display substrate further includes a light shielding layer, the light shielding layer including a plurality of light shielding patterns and a plurality of first light shielding connection portions; an orthographic projection of at least one of the plurality of light shielding patterns on the base substrate at least partially overlaps with an orthographic projection of a corresponding gate of the driving transistor on the base substrate; At least one of the plurality of first light-shielding connection portions is coupled to the light-shielding pattern, and an orthographic projection of at least one of the plurality of first light-shielding connection portions on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate.

2. The display substrate according to claim 1, wherein The display substrate further includes a first scan line, the first scan line including a first scan pattern and a second scan pattern alternately arranged, adjacent first scan patterns are coupled to the second scan patterns, a width of the first scan pattern along a first direction is greater than a width of the second scan pattern, and the first scan pattern is multiplexed as a gate of the corresponding compensation transistor; The orthographic projection of the first light-shielding connection portion on the base substrate at least partially overlaps with the orthographic projection of the first scanning pattern on the base substrate.

3. The display substrate according to claim 2, wherein: The first scanning line includes two stacked scanning layers, each scanning layer includes the first scanning pattern and the second scanning pattern; The orthographic projection of the first light-shielding connecting portion on the base substrate at least partially overlaps with the orthographic projection of the first scanning pattern in at least one scanning layer on the base substrate.

4. The display substrate according to claim 3, wherein: The compensation transistor includes a compensation active layer, at least a portion of which is located between the two scanning layers; The compensation active layer includes an active layer main body and an active layer protrusion coupled to each other, the active layer main body is coupled to the second electrode of the driving transistor, the active layer protrusion is coupled to the first conductive connection portion, and the positive projection of the active layer protrusion on the base substrate at least partially overlaps with the positive projection of the first light-shielding connection portion on the base substrate.

5. The display substrate according to claim 4, wherein: The sub-pixel driving circuit further includes a second conductive connection portion, a first reset transistor and a light emitting control transistor; the second conductive connection portion is coupled to the second electrode of the first reset transistor, the first electrode of the light emitting control transistor and the main portion of the active layer respectively; The active layer main portion extends along a first direction, the second conductive connection portion extends along the first direction, and an orthographic projection of the second conductive connection portion on the base substrate at least partially overlaps with an orthographic projection of the active layer main portion on the base substrate. The display substrate according to claim 1 , wherein: The display substrate further includes a second scan line, the second scan line including third scan patterns and fourth scan patterns alternately arranged, the adjacent third scan patterns are coupled to the fourth scan patterns, and a width of the third scan pattern along the first direction is greater than a width of the fourth scan pattern; The orthographic projection of the first light-shielding connection portion on the base substrate at least partially overlaps with the orthographic projection of the third scanning pattern on the base substrate.

7. The display substrate according to claim 1, wherein: The first light-shielding connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion being coupled to the light-shielding pattern via the second sub-portion; a width of the first sub-portion in a direction perpendicular to its own extension direction is smaller than a width of the second sub-portion in a direction perpendicular to its own extension direction; The orthographic projection of the first sub-portion on the base substrate does not overlap with the orthographic projection of the first conductive connection portion on the base substrate; the orthographic projection of the second sub-portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate.

8. The display substrate according to claim 1, wherein: The display substrate further includes a first initialization signal transmission layer and a second initialization signal transmission layer; The first initialization signal transmission layer includes a plurality of first initialization signal lines arranged along a first direction and a plurality of first initialization compensation lines arranged along a second direction, the first initialization signal lines include at least a portion extending along the second direction, the first initialization compensation lines include at least a portion extending along the first direction, and the first initialization compensation lines are respectively coupled to the first initialization signal lines; The second initialization signal transmission layer includes a plurality of second initialization signal lines arranged along a first direction and a plurality of second initialization compensation lines arranged along a second direction, the second initialization signal lines include at least a portion extending along the second direction, the second initialization compensation lines include at least a portion extending along the first direction, and the second initialization compensation lines are respectively coupled to each of the second initialization signal lines; The sub-pixel driving circuit further includes a first reset transistor and a second reset transistor; a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the second electrode of the driving transistor; a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to the anode of the light-emitting element; The first initialization compensation lines and the second initialization compensation lines are alternately arranged along the second direction.

9. The display substrate according to claim 8, wherein: The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of sub-pixel driving circuit columns arranged along the second direction, each of the sub-pixel driving circuit columns including a plurality of sub-pixel driving circuits arranged along the first direction; the plurality of sub-pixel driving circuit columns are divided into a plurality of column units arranged along the second direction, each column unit including at least three adjacent sub-pixel driving circuit columns; Each of the column units corresponds to a second initialization compensation line, and the second initialization compensation line is located in a layout area of ​​the corresponding column unit; The odd-numbered column units correspond to one of the first initialization compensation lines, and the first initialization compensation lines are located within the layout area of ​​the corresponding odd-numbered column units; or, the even-numbered column units correspond to one of the first initialization compensation lines, and the first initialization compensation lines are located within the layout area of ​​the corresponding even-numbered column units.

10. The display substrate according to claim 9, wherein: The display substrate further includes a third initialization signal transmission layer; the third initialization signal transmission layer includes a plurality of third initialization signal lines arranged along the first direction and a plurality of third initialization compensation lines arranged along the second direction, the third initialization signal lines include at least a portion extending along the second direction, the third initialization compensation lines include at least a portion extending along the first direction, and the third initialization compensation lines are respectively coupled to each of the third initialization signal lines; The sub-pixel driving circuit further includes a third reset transistor, a first electrode of the third reset transistor is coupled to the corresponding third initialization signal line, and a second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

11. The display substrate according to claim 10, wherein: The odd-numbered column units correspond to one of the third initialization compensation lines, and the third initialization compensation line is located within the layout area of ​​the corresponding odd-numbered column units; or, the even-numbered column units correspond to one of the third initialization compensation lines, and the third initialization compensation line is located within the layout area of ​​the corresponding even-numbered column units.

12. The display substrate according to claim 11, wherein: The odd-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines. Within the layout area of ​​the odd-numbered column units, the third initialization compensation line, the second initialization compensation line, and the first initialization compensation line are sequentially arranged along the second direction. Alternatively, The even-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines. Within the layout area of ​​the even-numbered column units, the third initialization compensation line, the second initialization compensation line and the first initialization compensation line are sequentially arranged along the second direction.

13. The display substrate according to claim 12, wherein: The first initialization signal transmission layer further includes a plurality of mutually independent first compensation patterns, wherein the first compensation patterns are coupled to at least one first initialization signal line, and the length of the first compensation patterns along the first direction is shorter than the first compensation signal line; In the case where the odd-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the even-numbered column units includes at least one of the first compensation patterns; In a case where the even-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the odd-numbered column units includes at least one of the first compensation patterns.

14. The display substrate according to claim 12, wherein: The third initialization signal transmission layer further includes a plurality of independent third compensation patterns, wherein the third compensation patterns are coupled to at least one third initialization signal line, and the length of the third compensation patterns along the first direction is shorter than that of the third compensation signal line; In the case where the odd-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the even-numbered column units includes at least one of the third compensation patterns; In a case where the even-numbered column units correspond to one of the first initialization compensation lines and one of the third initialization compensation lines, the layout area of ​​the odd-numbered column units includes at least one of the third compensation patterns.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

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