Substrate, imaging device, and method for manufacturing same

Abstract

A substrate 300 comprises: a semiconductor layer; an insulating layer 120 having a recess 130 in an upper surface 121 and provided on the semiconductor layer; pixel electrodes 50 provided on the insulating layer 120; and a light-shielding layer 210 positioned within the recess 130 and covering a side surface 131 of the recess 130. The recess 130 is provided at a position at which the recess does not overlap the pixel electrodes 50 in plan view. The uppermost surface 211 of the light-shielding layer 210 is positioned on the same plane as the upper surface 121 of the insulating layer 120.

Description

Substrate, imaging device, and methods for manufacturing the same

[0001] The present disclosure relates to a substrate, an imaging device, and a method for manufacturing the same.

[0002] Japanese Patent Application Laid-Open No. 2003-124222 discloses a method for manufacturing an electronic device, which includes a step of forming an alignment mark having a recess, and a step of aligning a photomask using the alignment mark.

[0003] Patent No. 6222989

[0004] When a photomask is aligned using an alignment mark having a recess, the alignment accuracy may be reduced, which may result in a decrease in the quality of the manufactured product.

[0005] Therefore, the present disclosure provides a high-quality substrate, a high-quality imaging device, and methods for manufacturing these.

[0006] A substrate according to one aspect of the present disclosure comprises a semiconductor layer, an insulating layer having a recess on its upper surface and provided on the semiconductor layer, an electrode provided on the insulating layer, and a first layer located within the recess and covering the side surface of the recess, wherein the recess is located at a position that does not overlap with the electrode in a planar view, the top surface of the first layer is located on the same plane as the upper surface of the insulating layer, and the substrate further comprises a second layer containing a photoelectric conversion material that converts light into electric charges, and the second layer covers the electrode and the first layer.

[0007] An imaging device according to one aspect of the present disclosure includes the substrate according to the above aspect and a signal processing circuit formed on the substrate.

[0008] A method for manufacturing a substrate according to one aspect of the present disclosure includes preparing a substrate having an insulating layer stacked on a semiconductor layer, forming a recess in an upper surface of the insulating layer, forming a first layer covering a side surface of the recess, forming an electrode in a position that does not overlap with the recess in a planar view, processing the first layer so that a top surface of the first layer and an upper surface of the insulating layer are located on the same plane, and forming a second layer containing a photoelectric conversion material that converts light into electric charges, so as to cover the first layer and the electrode.

[0009] A method for manufacturing a substrate according to one aspect of the present disclosure includes preparing a substrate including a semiconductor layer, an insulating layer having a recess on an upper surface and provided on the semiconductor layer, an electrode provided on the insulating layer, and a first layer located within the recess and covering a side surface of the recess, the first layer being provided at a position that does not overlap with the electrode in a planar view; and forming a second layer including a photoelectric conversion material that converts light into electric charges, so as to cover the first layer and the electrode.

[0010] A method for manufacturing an imaging device according to one aspect of the present disclosure includes cutting a substrate manufactured by a method for manufacturing a substrate according to the above aspect between the electrode and the recess, or at a position overlapping the recess.

[0011] According to the present disclosure, it is possible to provide a high-quality substrate, a high-quality imaging device, and methods for manufacturing these.

[0012] FIG. 1 is a diagram showing a circuit configuration of an imaging device according to an embodiment. FIG. 2 is a cross-sectional view showing a device structure of a unit cell of an imaging device according to an embodiment. FIG. 3A is a cross-sectional view of an imaging device according to an embodiment. FIG. 3B is a plan view of an imaging device according to an embodiment. FIG. 4 is a cross-sectional view showing the vicinity of an alignment mark and the vicinity of a pixel electrode of a substrate according to an embodiment. FIG. 5A is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 5B is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 5C is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 5D is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 5E is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 5F is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 5G is a cross-sectional view for explaining a step of a manufacturing method of a substrate according to an embodiment. FIG. 6A is a cross-sectional view for explaining an effect of a substrate according to an embodiment. FIG. 6B is a cross-sectional view for explaining an effect of a substrate according to an embodiment. FIG. 7 is a cross-sectional view showing the vicinity of an alignment mark and the vicinity of a pixel electrode of a substrate according to a first modification of the embodiment. FIG. 8A is a cross-sectional view illustrating one step of a method for manufacturing a substrate according to a first modification of the embodiment. FIG. 8B is a cross-sectional view illustrating one step of a method for manufacturing a substrate according to a first modification of the embodiment. FIG. 9 is a cross-sectional view illustrating the vicinity of an alignment mark and the vicinity of a pixel electrode on a substrate according to a second modification of the embodiment. FIG. 10A is a cross-sectional view illustrating one step of a method for manufacturing a substrate according to a second modification of the embodiment. FIG. 10B is a cross-sectional view illustrating one step of a method for manufacturing a substrate according to a second modification of the embodiment. FIG. 11 is a plan view illustrating one step of a method for manufacturing an imaging device according to a third modification of the embodiment.

[0013] (Summary of the Present Disclosure) A substrate according to a first aspect of the present disclosure comprises a semiconductor layer, an insulating layer having a recess on an upper surface and provided on the semiconductor layer, an electrode provided on the insulating layer, and a first layer located within the recess and covering a side surface of the recess, the recess being provided at a position that does not overlap with the electrode in a planar view, the top surface of the first layer being located on the same plane as an upper surface of the insulating layer, and further comprising a second layer containing a photoelectric conversion material that converts light into electric charges, the second layer covering the electrode and the first layer.

[0014] This allows for highly accurate alignment (i.e., positioning) based on the side surface of the recess. Since pattern misalignment is suppressed, a high-quality substrate can be achieved. Furthermore, since the second layer covers the first layer, diffusion of the material contained in the first layer can be suppressed. Since contamination of the substrate and manufacturing equipment due to material diffusion can be suppressed, the quality of the substrate can be improved.

[0015] A substrate according to a second aspect of the present disclosure is the substrate according to the first aspect, wherein the second layer completely covers the first layer.

[0016] This allows the second layer to completely cover the first layer, thereby enhancing the effect of suppressing the diffusion of the material contained in the first layer, thereby further improving the quality of the substrate.

[0017] A substrate according to a third aspect of the present disclosure is a substrate according to the first or second aspect, further comprising a third layer located within the recess and covering the first layer, the third layer comprising the same material as the material contained in the electrode.

[0018] In this way, the third layer covers the first layer, which can enhance the effect of suppressing the diffusion of the material contained in the first layer, thereby further improving the quality of the substrate.

[0019] A substrate according to a fourth aspect of the present disclosure is the substrate according to the third aspect, wherein the top surface of the third layer is located on the same plane as the top surface of the insulating layer and the top surface of the first layer.

[0020] This allows for highly accurate alignment using the side surface of the recess as a reference, suppressing pattern misalignment and achieving a high-quality substrate.

[0021] A substrate according to a fifth aspect of the present disclosure is a substrate according to the fourth aspect, further comprising a fourth layer located within the recess and covering the third layer, and the recess is planarized by the first layer, the third layer, and the fourth layer.

[0022] This allows for highly accurate alignment based on the side surface of the recess, even when the recess is flattened. This suppresses misalignment of the pattern, resulting in a high-quality substrate. Furthermore, flattening the recess improves the flatness and film quality of the film formed above, resulting in a higher-quality substrate.

[0023] A substrate according to a sixth aspect of the present disclosure is the substrate according to any one of the first to fifth aspects, wherein the first layer contains Cu.

[0024] As a result, the first layer covering the side surface of the recess contains visible Cu, allowing for accurate alignment based on the side surface of the recess. The Cu contained in the first layer precipitates during oxygen-based dry etching, causing contamination. Therefore, covering the first layer with a second layer or the like can suppress Cu precipitation, thereby preventing contamination of the substrate and manufacturing equipment.

[0025] A substrate according to a seventh aspect of the present disclosure is a substrate according to any one of the first to sixth aspects, comprising a wiring layer provided within the insulating layer, wherein the first layer contains the same conductive material as the wiring layer.

[0026] This allows the first layer to be formed in the same process as the wiring layer, reducing the number of steps in the manufacturing method and improving the quality of the substrate.

[0027] An imaging device according to an eighth aspect of the present disclosure includes a substrate according to any one of the first to seventh aspects, pixels formed on the substrate, and a signal processing circuit to which signals read out from the pixels are input.

[0028] This enables highly accurate alignment using the side surface of the recess as a reference, and suppresses pattern misalignment, resulting in a high-quality imaging device.

[0029] A method for manufacturing a substrate according to a ninth aspect of the present disclosure includes preparing a substrate having an insulating layer stacked on a semiconductor layer, forming a recess on an upper surface of the insulating layer, forming a first layer covering a side surface of the recess, forming an electrode in a position that does not overlap with the recess in a planar view, processing the first layer so that a top surface of the first layer and an upper surface of the insulating layer are located on the same plane, and forming a second layer containing a photoelectric conversion material that converts light into electric charges, so as to cover the first layer and the electrode.

[0030] This enables highly accurate alignment based on the side surface of the recess. Since pattern misalignment is suppressed, high-quality substrates can be manufactured. Furthermore, since the second layer covers the first layer, diffusion of the material contained in the first layer can be suppressed. Since contamination of the substrate and manufacturing equipment due to material diffusion can be suppressed, the quality of the substrate can be improved.

[0031] A substrate manufacturing method according to a tenth aspect of the present disclosure is a substrate manufacturing method according to the ninth aspect, further comprising patterning the second layer so as to leave at least the portions of the second layer on the first layer and the electrode.

[0032] In this way, the second layer covers the first layer, thereby suppressing diffusion of the material contained in the first layer, and thus preventing contamination of the substrate and manufacturing equipment due to the diffusion of the material, thereby improving the quality of the substrate.

[0033] A method for manufacturing a substrate according to an eleventh aspect of the present disclosure includes preparing a substrate including a semiconductor layer, an insulating layer having a recess on an upper surface and provided on the semiconductor layer, an electrode provided on the insulating layer, and a first layer located within the recess and covering a side surface of the recess, the first layer being provided at a position that does not overlap with the electrode in a planar view; and forming a second layer containing a photoelectric conversion material that converts light into an electric charge, so as to cover the first layer and the electrode.

[0034] This enables highly accurate alignment based on the side surface of the recess. Since pattern misalignment is suppressed, high-quality substrates can be manufactured. Furthermore, since the second layer covers the first layer, diffusion of the material contained in the first layer can be suppressed. Since contamination of the substrate and manufacturing equipment due to material diffusion can be suppressed, the quality of the substrate can be improved.

[0035] A substrate manufacturing method according to a twelfth aspect of the present disclosure is a substrate manufacturing method according to a thirteenth aspect, further comprising patterning the second layer so as to leave at least the portions of the second layer on the first layer and the electrode.

[0036] In this way, the second layer covers the first layer, thereby suppressing diffusion of the material contained in the first layer, and thus preventing contamination of the substrate and manufacturing equipment due to the diffusion of the material, thereby improving the quality of the substrate.

[0037] A method for manufacturing an imaging device according to a thirteenth aspect of the present disclosure includes cutting a substrate manufactured by a method for manufacturing a substrate according to any one of the ninth to twelfth aspects between the electrode and the recess, or at a position overlapping the recess.

[0038] This allows for highly accurate alignment based on the side of the recess. This suppresses misalignment of the pattern, allowing for the manufacture of high-quality imaging devices. Furthermore, if the recess is provided in an area that will be removed when the substrate is cut, it is possible to achieve a more compact imaging device.

[0039] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0040] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0041] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0042] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0043] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are used not only when two components are arranged with a gap between them and another component exists between them, but also when two components are arranged closely together and are in contact with each other.

[0044] In this specification and drawings, unless otherwise specified, the term "plan view" refers to the case where the main surface of a substrate is viewed from the front.

[0045] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0046] (Embodiment) First, an imaging device including a substrate according to the present embodiment will be generally described. FIG. 1 is a diagram showing the circuit configuration of an imaging device 500 according to the present embodiment. The imaging device 500 is also called an image sensor and includes a pixel array 101 including a plurality of unit pixel cells 14, and peripheral circuits. Note that, although an example in which the pixel array 101 and the peripheral circuits are provided on the same substrate will be described below, the peripheral circuits may be provided on a substrate separate from the pixel array 101. For example, a substrate on which the pixel array 101 is provided and a substrate on which the peripheral circuits are provided may be stacked.

[0047] A plurality of unit pixel cells 14 are arranged two-dimensionally, i.e., in row and column directions, on the substrate to form a pixel array 101. The pixel array 101 is also called a pixel region or a photosensitive region. Note that the imaging device 500 may be a line sensor in which a plurality of unit pixel cells 14 are arranged in a single row or column. In this specification, the row direction and column direction refer to the directions in which the rows and columns extend, respectively. In other words, the vertical direction is the column direction, and the horizontal direction is the row direction.

[0048] Each unit pixel cell 14 includes a photodetector 10, an amplifier transistor 11, a reset transistor 12, and an address transistor 13, which is a row selection transistor. The photodetector 10 includes a pixel electrode 50, a photoelectric conversion film 51, and a transparent electrode 52. The imaging device 500 includes a voltage control element for applying a predetermined voltage to the transparent electrode 52. The voltage control element may be, for example, a voltage control circuit, a voltage generation circuit such as a constant voltage source, or a voltage reference line such as a ground line. The voltage applied by the voltage control element is called a control voltage. The imaging device 500 according to this embodiment includes a voltage control circuit 60 as the voltage control element. The voltage control circuit 60 may generate a constant control voltage or multiple control voltages with different values. For example, the voltage control circuit 60 may generate control voltages of two or more different values, or may generate a control voltage that changes continuously within a predetermined range. The voltage control circuit 60 determines the value of the control voltage to be generated based on instructions from an operator operating the imaging device 500 or instructions from other control units, etc., included in the imaging device 500, and generates the control voltage of the determined value. The voltage control circuit 60 is provided outside the photosensitive area as part of the peripheral circuitry.

[0049] For example, the voltage control circuit 60 generates two or more different control voltages and applies the control voltages to the transparent electrode 52, thereby changing the spectral sensitivity characteristics of the photoelectric conversion film 51. Furthermore, this change in spectral sensitivity characteristics may include a spectral sensitivity characteristic in which the sensitivity of the photoelectric conversion film 51 becomes zero to light to be detected. As a result, for example, in the imaging device 500, while the unit pixel cells 14 read out detection signals row by row, the voltage control circuit 60 applies to the transparent electrode 52 a control voltage that makes the sensitivity of the photoelectric conversion film 51 zero, thereby making it possible to reduce the influence of incident light during readout of the detection signals to almost zero. Therefore, even when the detection signals are read out row by row, a global shutter operation can be achieved.

[0050] In this embodiment, as shown in FIG. 1 , the voltage control circuit 60 applies a control voltage to the transparent electrodes 52 of the unit pixel cells 14 arranged in the row direction via the counter electrode signal line 16. This changes the voltage between the pixel electrodes 50 and the transparent electrodes 52, thereby switching the spectral sensitivity characteristics of the photodetector unit 10. Alternatively, the voltage control circuit 60 may apply a control voltage to the pixel electrodes 50 so as to obtain spectral sensitivity characteristics in which sensitivity to light becomes zero at a predetermined timing during imaging. This enables electronic shutter operation. The voltage control circuit 60 may also apply a control voltage to the pixel electrodes 50. In order to irradiate the photodetector unit 10 with light and accumulate electrons as signal charges in the pixel electrodes 50, the pixel electrodes 50 are set to a relatively high potential with respect to the transparent electrode 52. At this time, the electrons move in the opposite direction to the hole movement, so a current flows from the pixel electrodes 50 to the transparent electrode 52. In addition, in order to irradiate the photodetector unit 10 with light and accumulate holes as signal charges in the pixel electrodes 50, the pixel electrodes 50 are set to a relatively low potential with respect to the transparent electrode 52. At this time, a current flows from the transparent electrode 52 to the pixel electrode 50 .

[0051] The pixel electrode 50 is connected to the gate electrode of the amplifier transistor 11, and the signal charge collected by the pixel electrode 50 is stored in a charge storage node 24 located between the pixel electrode 50 and the gate electrode of the amplifier transistor 11. In this embodiment, the case where the signal charge is a hole will be described, but the signal charge may also be an electron.

[0052] The signal charge accumulated in the charge accumulation node 24 is applied to the gate electrode of the amplifier transistor 11 as a voltage corresponding to the amount of signal charge. The amplifier transistor 11 constitutes a charge detection circuit 25 and amplifies the voltage applied to the gate electrode. One of the source and drain of the amplifier transistor 11 is connected to one of the source and drain of the address transistor 13. The address transistor 13 selectively reads out the amplified voltage as a signal voltage. One of the source and drain of the reset transistor 12 is connected to the pixel electrode 50 and resets the signal charge accumulated in the charge accumulation node 24. In other words, the reset transistor 12 resets the potentials of the gate electrode of the amplifier transistor 11 and the pixel electrode 50. The other of the source and drain of the reset transistor 12 is connected to a feedback line 23.

[0053] In order to selectively perform the above-described operations in the plurality of unit pixel cells 14, the imaging device 500 includes a power supply wiring 21, a vertical signal line 17, an address signal line 26, and a reset signal line 27, which are connected to the unit pixel cells 14, respectively. Specifically, the power supply wiring 21 is connected to the other of the source and drain of the amplification transistor 11. The vertical signal line 17 is connected to the other of the source and drain of the address transistor 13. The address signal line 26 is connected to the gate electrode of the address transistor 13. Furthermore, the reset signal line 27 is connected to the gate electrode of the reset transistor 12.

[0054] The peripheral circuits include a vertical scanning circuit 15, a horizontal signal readout circuit 20, a plurality of column signal processing circuits 19, a plurality of load circuits 18, and a plurality of differential amplifiers 22. The vertical scanning circuit 15 is also called a row scanning circuit. The horizontal signal readout circuit 20 is also called a column scanning circuit. The column signal processing circuit 19 is also called a row signal storage circuit. The differential amplifier 22 is also called a feedback amplifier.

[0055] The vertical scanning circuit 15 is connected to address signal lines 26 and reset signal lines 27. The vertical scanning circuit 15 selects a plurality of unit pixel cells 14 arranged in each row on a row-by-row basis, reads out a signal voltage, and resets the potential of the pixel electrode 50. A power supply wiring 21, which is a source follower power supply, supplies a predetermined power supply voltage to each unit pixel cell 14. The horizontal signal readout circuit 20 is electrically connected to a plurality of column signal processing circuits 19. The column signal processing circuits 19 are electrically connected to the unit pixel cells 14 arranged in each column via vertical signal lines 17 corresponding to each column. The load circuits 18 are electrically connected to each vertical signal line 17. The load circuits 18 and the amplification transistors 11 form a source follower circuit.

[0056] A plurality of differential amplifiers 22 are provided corresponding to each column. The negative input terminals of the differential amplifiers 22 are connected to the corresponding vertical signal lines 17. The output terminals of the differential amplifiers 22 are connected to the unit pixel cells 14 via feedback lines 23 corresponding to each column.

[0057] The vertical scanning circuit 15 applies a row selection signal that controls the on / off of the address transistor 13 to the gate electrode of the address transistor 13 via an address signal line 26. This scans and selects a row to be read out. A signal voltage is read out from the unit pixel cells 14 of the selected row to a vertical signal line 17. The vertical scanning circuit 15 also applies a reset signal that controls the on / off of the reset transistor 12 to the gate electrode of the reset transistor 12 via a reset signal line 27. This selects a row of unit pixel cells 14 that are the target of the reset operation. The vertical signal line 17 transmits the signal voltage read out from the unit pixel cells 14 selected by the vertical scanning circuit 15 to a column signal processing circuit 19.

[0058] The column signal processing circuit 19 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0059] The horizontal signal readout circuit 20 sequentially reads out signals from the plurality of column signal processing circuits 19 to a horizontal common signal line 28 .

[0060] The differential amplifier 22 is connected to the other of the source and drain of the reset transistor 12 via a feedback line 23. When the address transistor 13 and the reset transistor 12 are in a conductive state, the differential amplifier 22 receives the output value of the address transistor 13 at its negative terminal. The differential amplifier 22 performs a feedback operation so that the gate potential of the amplifying transistor 11 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 22 is 0 V or a positive voltage close to 0 V. The feedback voltage refers to the output voltage of the differential amplifier 22.

[0061] 2 is a cross-sectional view showing the device structure of a unit pixel cell 14 of an imaging device 500 according to the present embodiment. Note that in Fig. 2, the diagonal shading represents the cross section of the components included in the unit pixel cell 14. However, the diagonal shading representing the cross section is omitted for the interlayer insulating films 43A, 43B, and 43C.

[0062] Each unit pixel cell 14 includes a semiconductor substrate 31, a charge detection circuit 25, and a photodetector 10. The semiconductor substrate 31 is an example of a semiconductor layer of the present disclosure, and is, for example, a p-type silicon substrate. The charge detection circuit 25 is an example of a signal processing circuit, and is formed on the semiconductor substrate 31. It detects signal charges captured by the pixel electrode 50 and outputs a signal voltage. The charge detection circuit 25 includes an amplification transistor 11, a reset transistor 12, and an address transistor 13.

[0063] The amplifier transistor 11 includes n-type impurity regions 41C and 41D, a gate insulating layer 38B, and a gate electrode 39B. The n-type impurity regions 41C and 41D are formed in the semiconductor substrate 31 and function as a drain and a source, respectively. The gate insulating layer 38B is provided on the semiconductor substrate 31. The gate electrode 39B is provided on the gate insulating layer 38B.

[0064] The reset transistor 12 includes n-type impurity regions 41A and 41B, a gate insulating layer 38A, and a gate electrode 39A. The n-type impurity regions 41A and 41B are formed in the semiconductor substrate 31 and function as a source and a drain, respectively. The gate insulating layer 38A is provided on the semiconductor substrate 31. The gate electrode 39A is provided on the gate insulating layer 38A.

[0065] The address transistor 13 includes n-type impurity regions 41D and 41E, a gate insulating layer 38C, and a gate electrode 39C. The n-type impurity regions 41D and 41E are formed in the semiconductor substrate 31 and function as a drain and a source, respectively. The gate insulating layer 38C is provided on the semiconductor substrate 31. The gate electrode 39C is provided on the gate insulating layer 38C. The n-type impurity region 41D is shared by the amplifier transistor 11 and the address transistor 13. This connects the amplifier transistor 11 and the address transistor 13 in series.

[0066] The n-type impurity regions 41A, 41B, 41C, 41D, and 41E are each formed by implanting an n-type impurity such as phosphorus by ion implantation or the like. The gate insulating layers 38A, 38B, and 38C each have a single-layer or multilayer structure of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. The gate electrodes 39A, 39B, and 39C are each formed using a conductive material such as conductive polysilicon or a metal.

[0067] In the semiconductor substrate 31, an element isolation region 42 is provided between adjacent unit pixel cells 14 and between the amplification transistor 11 and the reset transistor 12. The element isolation region 42 electrically isolates adjacent unit pixel cells 14. In addition, leakage of signal charges accumulated in the charge accumulation node 24 is suppressed.

[0068] Interlayer insulating films 43A, 43B, and 43C are stacked in this order on the semiconductor substrate 31. The stacked structure of the interlayer insulating films 43A, 43B, and 43C is an example of an insulating layer according to the present disclosure.

[0069] Contact plugs 45A and 45B and a wiring 46A are buried in the interlayer insulating film 43A. The contact plug 45A is connected to the n-type impurity region 41B of the reset transistor 12. The contact plug 45B is connected to the gate electrode 39B of the amplifier transistor 11. The wiring 46A connects the contact plug 45A and the contact plug 45B. This electrically connects the n-type impurity region 41B of the reset transistor 12 to the gate electrode 39B of the amplifier transistor 11. The wiring 46A is also electrically connected to the pixel electrode 50 via a via 47A, a wiring 46B, a via 47B, a wiring 46C, and a via 47C.

[0070] The contact plugs 45A and 45B, the wirings 46A, 46B, and 46C, and the vias 47A, 47B, and 47C are examples of wiring layers according to the present disclosure. The contact plugs 45A and 45B, the wirings 46A, 46B, and 46C, and the vias 47A, 47B, and 47C are all formed using a conductive material. Examples of the conductive material include metal materials such as Cu, Ti, and Ta, but conductive polysilicon may also be used.

[0071] The photodetector 10 is provided on the interlayer insulating film 43C. The photodetector 10 includes a pixel electrode 50, a photoelectric conversion film 51, and a transparent electrode 52. The pixel electrode 50 is located closer to the semiconductor substrate 31 than the transparent electrode 52. The pixel electrode 50 is formed from a metal such as aluminum, copper, titanium, or tantalum, or polysilicon doped with impurities to provide conductivity.

[0072] The photoelectric conversion film 51 is sandwiched between the transparent electrode 52 and the pixel electrode 50. The specific structure of the photoelectric conversion film 51 will be described later.

[0073] The transparent electrode 52 is a counter electrode that faces the pixel electrode 50. The transparent electrode 52 is formed using a material that is translucent to the light to be detected and is conductive. For example, the transparent electrode 52 is made of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or the like, but other transparent conductive materials may also be used.

[0074] 2 , the unit pixel cell 14 includes an insulating film 53 formed on at least a portion of the upper surface of the transparent electrode 52, and a protective film 54 provided on the insulating film 53. The insulating film 53 and the protective film 54 each have a single layer or multilayer structure of an insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. The insulating film 53 and the protective film 54 may be insulating films formed using an organic material such as an insulating resin material. Note that the insulating film 53 and the protective film 54 do not necessarily have to be provided. When the insulating film 53 is provided, the protective film 54 may be a conductive film instead of an insulating film.

[0075] The unit pixel cell 14 also includes a color filter 55 provided on the protective film 54. The unit pixel cell 14 also includes a microlens 56 provided on the color filter 55. Note that the color filter 55 and the microlens 56 do not necessarily have to be provided.

[0076] In the present embodiment, the photoelectric conversion film 51 and transparent electrode 52 of each unit pixel cell 14 are integrally formed with the photoelectric conversion film 51 and transparent electrode 52 of the adjacent unit pixel cell 14. The photoelectric conversion film 51 may be separated for each unit pixel cell 14. The transparent electrode 52 may also be integrally formed for each row or column of unit pixel cells 14 arranged two-dimensionally. In contrast, the pixel electrode 50 of each unit pixel cell 14 is not connected to the pixel electrode 50 of the adjacent unit pixel cell 14 and is independent.

[0077] The imaging device 500 according to this embodiment may detect a change in the capacitance of the photoelectric conversion film rather than detecting charges generated by photoelectric conversion. That is, the photoelectric conversion film 51 may generate hole-electron pairs according to the intensity of incident light, or the capacitance may change according to the intensity of incident light. It is possible to detect light incident on the photoelectric conversion film 51 by detecting the generated charges or changes in capacitance.

[0078] [Structure of Imaging Device] Next, the overall structure of the imaging device 500 will be described with reference to FIGS. 3A and 3B.

[0079] FIG. 3A is a cross-sectional view of an imaging device 500 according to the present embodiment. FIG. 3B is a plan view of the imaging device 500 according to the present embodiment. Note that in FIG. 3A, the diagonal shading represents a cross section of the components included in the imaging device 500. However, the diagonal shading representing a cross section is omitted for the substrate layer 100. The substrate layer 100 collectively represents the semiconductor substrate 31 and the interlayer insulating films 43A, 43B, and 43C shown in FIG. 2. The upper surface 100a of the substrate layer 100 is the upper surface of the interlayer insulating film 43C shown in FIG. 2. In FIGS. 3A and 3B, the color filter 55 and the microlens 56 are omitted. In addition, in FIG. 3B, the protective film 54 shown in FIG. 2 is omitted.

[0080] The imaging device 500 includes the above-described plurality of pixel electrodes 50, photoelectric conversion film 51, and transparent electrode 52. The imaging device 500 also includes a control electrode 112 and a connection portion 115. The plurality of pixel electrodes 50 and the control electrode 112 form a circuit portion formed on the substrate layer 100. The connection portion 115 also forms a part of the counter electrode signal line 16.

[0081] The pixel electrodes 50 are arranged one-dimensionally or two-dimensionally and embedded in the substrate layer 100 so that the upper surface of each of the pixel electrodes 50 is exposed from the upper surface 100a of the substrate layer 100. Note that in Figure 3B, the sizes of the pixel electrodes 50, control electrodes 112, etc. are exaggerated and not accurate. Details will be described later, but for example, the pixel electrodes 50 are smaller than the recesses 130 used as alignment marks.

[0082] The photoelectric conversion film 51 is disposed on the upper surface 100a of the substrate layer 100 so as to cover the plurality of pixel electrodes 50. Furthermore, a transparent electrode 52 is disposed on the photoelectric conversion film 51. The transparent electrode 52 covers the upper surface 51a of the photoelectric conversion film 51 so as to cover at least the region of the photoelectric conversion film 51 where the pixel electrodes 50 are provided. In the present embodiment, the transparent electrode 52 is formed to cover the entire upper surface 51a of the photoelectric conversion film 51.

[0083] The insulating film 53 is formed to cover at least a part of the upper surface 52a of the transparent electrode 52. The insulating film 53 may cover the upper surface 52a so as to cover at least the region of the transparent electrode 52 where the pixel electrode 50 is provided.

[0084] The connection portion 115 is bonded to the control electrode 112 and the transparent electrode 52, electrically connecting them. Specifically, the connection portion 115 is bonded to the side surfaces 52s of the control electrode 112 and the transparent electrode 52 exposed on the substrate layer 100. The connection portion 115 also covers the side surfaces 51s of the photoelectric conversion film 51. The connection portion 115 also covers a portion of the upper surface 53a of the insulating film 53 except for the area above the region where the pixel electrode 50 is provided. The bonding area between the connection portion 115 and the control electrode 112 may be larger, smaller, or the same as the bonding area between the connection portion 115 and the transparent electrode 52.

[0085] In this embodiment, the photoelectric conversion film 51, the insulating film 53, and the transparent electrode 52 have a rectangular shape in a plan view, and the control electrode 112 is disposed adjacent to the sides 52e and 52f of the transparent electrode 52, among the four sides 52c, 52d, 52e, and 52f. Therefore, the imaging device 500 includes two connection portions 115. At positions adjacent to the sides 52e and 52f of the transparent electrode 52, the two connection portions 115 are joined to the control electrode 112 and a side surface 52s of the transparent electrode 52, respectively, thereby electrically connecting the control electrode 112 and the transparent electrode 52. In this embodiment, the side surface 53s of the insulating film 53 is located on the same plane as the side surface 52s of the transparent electrode 52, at each of the four sides 52c, 52d, 52e, and 52f of the transparent electrode 52.

[0086] The protective film 54 is provided on the upper surface 100 a of the substrate layer 100 , covering the connection portion 115 and the insulating film 53 .

[0087] The photoelectric conversion film 51 is made of, for example, an organic semiconductor. The photoelectric conversion film 51 may include one or more organic semiconductor layers. For example, the photoelectric conversion film 51 may include, in addition to a photoelectric conversion layer that generates hole-electron pairs, a carrier transport layer that transports electrons or holes, a blocking layer that blocks carriers, and the like. These organic semiconductor layers may be made of known organic p-type semiconductors or organic n-type semiconductors.

[0088] The control electrode 112 is made of a metal or a metal compound and has light-blocking properties. For example, the control electrode 112 is made of titanium, titanium nitride, aluminum, silicon and copper-added aluminum, copper, tungsten, or an alloy thereof. The control electrode 112 may be made of a single layer of the above-mentioned material, or may have a laminated structure including multiple layers. The control electrode 112 can be formed in the same process as the pixel electrode 50. In other words, the control electrode 112 may contain the same material as the pixel electrode 50.

[0089] The connection portion 115 is made of a metal or a metal compound. For example, the connection portion 115 is made of titanium, titanium nitride, aluminum, silicon, copper-added aluminum (AlSiCu), copper, tungsten, gold, silver, nickel, cobalt, or an alloy thereof. Like the control electrode 112, the connection portion 115 may be a single layer or a multilayer.

[0090] [Alignment Mark] As shown in Fig. 3B, the imaging device 500 according to this embodiment includes a recess 130 used as an alignment mark. The recess 130 is used to align a mask member when patterning each layer. In Fig. 3B, the recess 130 has a cross shape in plan view, but is not limited to this. The recess 130 may also have a linear, rectangular, triangular, or other shape in plan view.

[0091] The recess 130 is provided at a position that does not overlap the pixel electrode 50 in a plan view. The recess 130 also does not overlap the control electrode 112 in a plan view. Specifically, the recess 130 is provided in a peripheral region that is different from the photosensitive region of the imaging device 500. Alternatively, as in Modification 3 described below, the recess 130 may be provided in a region that is cut when the substrate is singulated.

[0092] The structure in the vicinity of the recess 130 will be described below with reference to Fig. 4. Fig. 4 is a cross-sectional view showing the vicinity of the alignment mark and the vicinity of the pixel electrode 50 of the substrate 300 according to this embodiment. Specifically, the left side of Fig. 4 shows the vicinity of the pixel electrode 50, and the right side of Fig. 4 shows the vicinity of the recess 130 used as the alignment mark.

[0093] The substrate 300 is used in manufacturing the imaging device 500. The substrate 300 shown in FIG. 4 corresponds to a stage during manufacturing of the imaging device 500, specifically, a stage after the photoelectric conversion film 51 is formed and before the connection portion 115 is formed. In FIG. 4, the transparent electrode 52 and the insulating film 53 are not shown. The imaging device 500 is manufactured by forming the connection portion 115 on the substrate 300 shown in FIG. 4 so as to contact the control electrode 112, and further by forming the protective film 54, the color filter 55, and the microlens 56 in this order so as to cover the insulating film 53 (not shown). That is, the imaging device 500 according to the present embodiment includes the substrate 300 shown in FIG. 4.

[0094] In FIG. 4 , the diagonal shading represents a cross section of the components of the substrate 300. The cross-sectional hatching of the insulating layers 120 and 150 and the transparent layers 230 and 240 is omitted. Also, the interlayer insulating films 43B and 43A shown in FIG. 2 and the semiconductor substrate 31 are provided below the insulating layer 120, but these are also omitted from the illustration. In other words, the substrate 300 shown in FIG. 4 includes a semiconductor substrate 31, which is an example of a semiconductor layer, and a layered structure of interlayer insulating films 43A, 43B, and 43C, which are insulating layers provided on the semiconductor layer and have a recess on the upper surface. The same illustration method as in FIG. 4 is also applied to the subsequent FIGS. 5A to 10B.

[0095] The configuration of the substrate 300 near the pixel electrodes 50 is the same as that described with reference to FIGS. 2 and 3A. While the interlayer insulating film 43C is illustrated as a single-layer structure in FIG. 2, the interlayer insulating film 43C is illustrated as having a laminated structure of insulating layers 120 and 150 in FIG. 4. The insulating layer 150 is provided to fill the spaces between the pixel electrodes 50 and the control electrodes 112. The upper surfaces of the insulating layer 150 and the pixel electrodes 50 are located on the same plane. This allows the lower surface of the photoelectric conversion film 51 to be planarized, resulting in a high-quality photoelectric conversion film 51 with good coverage. The interlayer insulating film 43C may have a single-layer structure instead of a laminated structure.

[0096] 4, the substrate 300 includes light-shielding layers 210 and 220, light-transmitting layers 230 and 240, and a photoelectric conversion film 51. The light-shielding layers 210 and 220 and the light-transmitting layers 230 and 240 are located in a recess 130 provided in the upper surface 121 of the insulating layer 120. Furthermore, the photoelectric conversion film 51 is provided so as to cover the recess 130. Note that the substrate 300 does not necessarily include the photoelectric conversion film 51.

[0097] 5A to 5G, a method for manufacturing the substrate 300 will be described, and a specific structure of the substrate 300 shown in FIG. 5A to 5G are cross-sectional views for explaining a step in the method for manufacturing the substrate 300 according to the present embodiment.

[0098] 5A, a substrate provided with an insulating layer 120 is prepared, and a recess 130 is formed on the upper surface of the insulating layer 120. In this embodiment, the recess 130 and a plurality of via holes 140 are formed simultaneously.

[0099] The insulating layer 120 has a single layer or multilayer structure of, for example, a tetraethoxysilane (TEOS) oxide film, a silicon nitride (SiN) film, or a silicon oxide (SiO) film, and is formed by a plasma chemical vapor deposition (CVD) method, etc. The recess 130 and the plurality of via holes 140 are simultaneously formed by, for example, dry etching.

[0100] The recess 130 is provided so as to penetrate the insulating layer 120. Although not shown in FIG. 5A , the interlayer insulating film 43B is present at the bottom of the recess 130. The bottom surface of the recess 130 is the upper surface of the interlayer insulating film 43B or the wiring 46C, but is not limited to this. The recess 130 may be formed so as to excavate a part of the interlayer insulating film 43B or the wiring 46C, or may penetrate the interlayer insulating film 43B or the wiring 46C.

[0101] The width W of the recess 130 is longer than the width d of the via hole 140. For example, the width W of the recess 130 is 10 times or more, and may be 50 times or more, the width d of the via hole 140. As an example, the width W is greater than 10 μm, while the width d is 0.2 μm. Note that, in the case of the cross-shaped recess 130 shown in FIG. 3B, the width W of the recess 130 corresponds to the line width of the cross. Furthermore, in the case of the via hole 140 being cylindrical, the width d of the via hole 140 corresponds to the diameter of the circle in a plan view.

[0102] Next, as shown in FIG. 5B , a light-shielding layer 210 is formed to cover the side surface 131 of the recess 130. The light-shielding layer 210 is an example of a first layer according to the present disclosure, and is located within the recess 130. In this embodiment, the via 47C provided within the via hole 140 and the light-shielding layer 210 are formed simultaneously. Therefore, the light-shielding layer 210 contains the same conductive material as the via 47C. For example, the light-shielding layer 210 contains Cu. Alternatively, the light-shielding layer 210 may contain Ti, Ta, or the like. The via 47C is an example of a wiring layer provided within the insulating layer 120.

[0103] For example, a Cu plating film is formed by plating the upper surface 121 of the insulating layer 120 with Cu. The Cu plating film fills the via hole 140 but does not completely fill the recess 130. This is due to the size difference between the recess 130 and the via hole 140. For this reason, as shown in FIG. 5B , the light-shielding layer 210 is formed to contact and cover the side surface 131 and bottom surface of the recess 130. Note that while FIG. 5B shows an example in which the light-shielding layer 210 has a uniform thickness, this is not limiting. The light-shielding layer 210 may be thicker at the corners of the recess 130.

[0104] Next, the light-shielding layer 210 is processed so that the top surface 211 of the light-shielding layer 210 and the top surface 121 of the insulating layer 120 are located on the same plane. Specifically, after a Cu plating film is embedded in the via hole 140, the Cu plating film remaining on the top surface 121 of the insulating layer 120 is removed by polishing such as CMP (Chemical Mechanical Polishing). As a result, the top surface of the via 47C and the top surface 121 of the insulating layer 120 are located on the same plane. Furthermore, the top surface 211 of the light-shielding layer 210 and the top surface 121 of the insulating layer 120 are located on the same plane.

[0105] Next, as shown in FIG. 5C , a conductive film 222 and an insulating film 232 are sequentially formed, and then a resist mask 250 is formed. The conductive film 222 is a conductive film that serves as the base for the pixel electrode 50 and the control electrode 112, which are examples of electrodes provided on the insulating layer 120. The conductive film 222 is formed using a material that is conductive and light-blocking. For example, the conductive film 222 has a single-layer or multi-layer structure containing Ti or Ta. The insulating film 232 is provided as a protective film for the conductive film 222 and serves as the base for the light-transmitting layer 230. The insulating film 232 has a single-layer or multi-layer structure made of, for example, a TEOS oxide film, a SiN film, or a silicon oxide SiO film.

[0106] The resist mask 250 is used to pattern the pixel electrode 50 and the control electrode 112. The resist mask 250 is, for example, a photosensitive photoresist, and is provided so as to overlap the via 47C and the recess 130 in a planar view. The resist mask 250 is formed by photolithography in an island shape so that the portion covering the via 47C matches the shape of the pixel electrode 50 or the control electrode 112 in a planar view. When forming the resist mask 250 with such a shape, alignment (positioning) is performed using the recess 130. Because the light-shielding layer 210 is covered by the light-shielding conductive film 222 in the recess 130, the underlying pattern including the light-shielding layer 210 itself cannot be seen. For this reason, alignment is performed based on the step of the recess 130.

[0107] Next, the portions of the insulating film 232 and the conductive film 222 that are not covered by the resist mask 250 are removed by dry etching, and then the resist mask 250 is removed by ashing or the like. As a result, as shown in Fig. 5D, the pixel electrode 50 and the control electrode 112 are formed by dry etching at positions that do not overlap the recess 130 in a plan view. Furthermore, the conductive film 222 and the insulating film 232 are left so as to cover the recess 130.

[0108] Next, an insulating film 242 is filled in so as to fill the gaps between adjacent pixel electrodes 50. The insulating film 242 is, for example, a TEOS oxide film.

[0109] Next, the upper surface of the substrate 300 is planarized by polishing such as CMP. As shown in Fig. 5F, the insulating layer 150 remains embedded between the adjacent pixel electrodes 50. Furthermore, the light-transmitting layer 240 remains in the recesses 130.

[0110] The polishing rate differs between the vicinity of the pixel electrode 50 and the vicinity of the recess 130. This is because a higher proportion of pixel electrodes 50, which are difficult to polish, are present near the pixel electrode 50. In other words, the polishing rate is higher near the recess 130 than near the pixel electrode 50. As a result, as shown in FIG. 5F , the conductive film 222 and insulating films 232 and 242 provided on the upper surface 121 of the insulating layer 120 are also removed near the recess 130, exposing the upper surface 121 of the insulating layer 120 and the top surface 211 of the light-shielding layer 210. The conductive film 222 and insulating films 232 and 242 remaining in the recess 130 become the light-shielding layer 220 and the light-transmitting layers 230 and 240, respectively.

[0111] The light-shielding layer 220 is an example of a third layer according to the present disclosure, and is located within the recess 130 and covers the light-shielding layer 210. A top surface 221 of the light-shielding layer 220 is located on the same plane as the top surface 211 of the light-shielding layer 210 and the top surface 121 of the insulating layer 120. The light-shielding layer 220 contains the same material as the material contained in the pixel electrode 50. For example, the light-shielding layer 220 has a single layer or a multilayer structure containing Ti, Ta, or the like.

[0112] Light-transmitting layers 230 and 240 are an example of a fourth layer according to the present disclosure, and are located within recess 130 and cover light-shielding layer 220. A top surface 231 of light-transmitting layer 230 is located on the same plane as a top surface 221 of light-shielding layer 220, a top surface 211 of light-shielding layer 210, and an upper surface 121 of insulating layer 120. Note that light-transmitting layer 240 does not necessarily have to be provided.

[0113] Through the above steps, the substrate 300 according to this embodiment is manufactured.

[0114] 5F , in the vicinity of the recess 130 of the substrate 300, the upper surface 121 of the insulating layer 120 and the top surface 211 of the light-shielding layer 210 are located on the same plane and are flush with each other. Furthermore, the light-shielding layer 220 does not cover the contact portion between the upper surface 121 and the top surface 211. In other words, the side surface 131 of the recess 130 is visible. This makes it possible to perform alignment using not only the step portion inside the recess 130 but also the side surface 131 of the recess 130.

[0115] A photoelectric conversion film 51 may further be formed on the substrate 300. After preparing the substrate 300 shown in Fig. 5F, a photoelectric conversion film 260 is formed so as to cover the light-shielding layer 220 and the pixel electrodes 50, as shown in Fig. 5G. Specifically, the photoelectric conversion film 260 is formed on the entire upper surface of the substrate 300 so as to cover the entire recess 130, the plurality of pixel electrodes 50, and the control electrodes 112.

[0116] Next, the photoelectric conversion film 260 is patterned into a predetermined shape by removing a portion thereof. Specifically, the photoelectric conversion film 260 is patterned so as to leave at least the portions thereof on the light-shielding layer 210 and the pixel electrodes 50. As a result, as shown in FIG. 4 , the control electrode 112 is exposed, and the photoelectric conversion film 51 is formed so as to cover across the plurality of pixel electrodes 50. Because the photoelectric conversion film 260 contains an organic photoelectric conversion material, the patterning is performed by, for example, oxygen-based dry etching.

[0117] The photoelectric conversion film 51 is an example of a second layer according to the present disclosure, contains a photoelectric conversion material that converts light into electric charges, and covers the pixel electrode 50 and the light-shielding layer 210. Specifically, the photoelectric conversion film 51 completely covers the light-shielding layer 210. The photoelectric conversion film 51 continuously covers the upper surface 121 of the insulating layer 120, the uppermost surface 211 of the light-shielding layer 210, the uppermost surface 221 of the light-shielding layer 220, the uppermost surface 231 of the light-transmitting layer 230, and the upper surface of the light-transmitting layer 240.

[0118] If the photoelectric conversion film 51 covering the recess 130 is not provided, i.e., if the portion covering the recess 130 is also removed during patterning of the photoelectric conversion film 260, Cu contained in the exposed light-shielding layer 210 will precipitate due to the influence of oxygen-based dry etching. As a result, the Cu will protrude outside the recess 130, reducing the visibility of the alignment mark. Furthermore, the precipitated Cu will remain in unnecessary locations on the substrate 300 and in the manufacturing equipment. In other words, so-called Cu contamination will occur, degrading the quality of the substrate 300 and the quality of the imaging device 500 manufactured using the substrate 300.

[0119] In contrast, in the present embodiment, the photoelectric conversion film 51 covers the light-shielding layer 210, thereby suppressing diffusion of the material (specifically, Cu) contained in the light-shielding layer 210. Since Cu contamination can be suppressed, the quality of the substrate 300 and the quality of the imaging device 500 manufactured using the substrate 300 can be improved.

[0120] [Alignment Accuracy] Next, the alignment accuracy using the recess 130 of the substrate 300 according to this embodiment will be described with reference to Figures 6A and 6B. Figures 6A and 6B are cross-sectional views for explaining the effects of the substrate 300 according to this embodiment.

[0121] 6A shows the vicinity of recess 130x of the substrate according to the comparative example and the vicinity of recess 130 of substrate 300 according to the example. In the comparative example, unlike the example, light-shielding layer 210x is provided instead of light-shielding layer 210. Light-shielding layer 210x is also provided outside recess 130x and covers upper surface 121 of insulating layer 120.

[0122] Because the light-shielding layer 210x is also provided outside the recess 130x, the side surface 131x of the recess 130x cannot be seen in the comparative example. Therefore, when performing alignment using the recess 130x, the center of the recess 130 (the "mark center" in the figure) is typically used as the reference position. The reference position can be confirmed from the wall surface of the light-shielding layer 220 (or the light-shielding layer 210x if the light-shielding layer 220 is not provided). Specifically, the position at an equal distance from the inner wall surface of the light-shielding layer 220 can be used as the reference position. Thus, in the case of the recess 130x according to the comparative example, alignment is possible by using the mark center as the reference position.

[0123] In contrast, in the recess 130 according to the embodiment, in addition to the center of the mark being used as the reference position, the side surface 131 of the recess 130 can also be used as the reference position. This is because the light-shielding layer 210 does not cover the upper surface 121 of the insulating layer 120. The ability to use the side surface 131 as the reference position can improve alignment accuracy. The reason for this will be explained using FIG. 6B .

[0124] Compared to FIG. 6A , FIG. 6B shows that a light-shielding layer 220x is provided instead of the light-shielding layer 220. The light-shielding layer 220x differs from the light-shielding layer 220 in that its thickness is not uniform. Film formation on the side surface 131x of the recess 130x or the side surface 131 of the recess 130 is unstable, and film thickness variations tend to be large. As a result, the light-shielding layer 220 becomes thicker or thinner in parts. Note that the light-shielding layer 210 may also have film thickness variations in the parts covering the side surface 131 or 131x.

[0125] In the comparative example, since the side surface 131x of the recess 130x cannot be seen, if the position where the distance from the inner wall surface of the light-shielding layer 220x is equal is used as the reference position, the mark will be shifted from its original center due to the difference in film thickness of the light-shielding layer 220x, making it impossible to achieve accurate alignment.

[0126] In contrast, in the embodiment, the side surface 131 of the recess 130 can be visually confirmed. Even if the film thickness of the light-shielding layer 210 or 220x varies within the recess 130, the position of the side surface 131 of the recess 130 does not change. Therefore, by using the side surface 131 as a reference position, alignment can be performed with high precision.

[0127] As described above, with the substrate 300 according to the present embodiment, the upper surface 121 of the insulating layer 120 and the top surface 211 of the light-shielding layer 210 in the recess 130 are located on the same plane and do not cover the side surface 131 of the recess 130. This enables alignment based on the side surface 131 of the recess 130, thereby enabling highly accurate alignment without being affected by variations in the film thickness of the light-shielding layer 210. Since pattern misalignment is suppressed, a high-quality substrate 300 and a high-quality imaging device 500 can be realized.

[0128] [Modifications] Next, a description will be given of modifications of the substrate 300 according to the present embodiment. The following description will focus on differences from the substrate 300 according to the embodiment, and description of commonalities will be omitted or simplified.

[0129] <Modification 1> First, Modification 1 will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing the vicinity of the alignment mark and the vicinity of the pixel electrode 50 on the substrate 301 according to this modification.

[0130] 7, the substrate 301 differs from the substrate 300 shown in Fig. 4 in that the light-shielding layer 220 and the light-transmitting layers 230 and 240 are not provided in the recess 130. The photoelectric conversion film 51 is provided in the recess 130 in contact with the inner wall surface 212 and the upper surface 213 of the light-shielding layer 210.

[0131] A method for manufacturing the substrate 301 shown in Fig. 7 will be described with reference to Fig. 8A and Fig. 8B. Fig. 8A and Fig. 8B are cross-sectional views for explaining one step of the method for manufacturing the substrate 301 according to this modification.

[0132] The manufacturing method of substrate 301 is the same as the manufacturing method of substrate 300 up to the step shown in Fig. 5E . After insulating film 242 is formed as shown in Fig. 5E , the upper surface of substrate 301 is planarized by polishing such as CMP. At this time, by increasing the polishing rate, insulating films 242 and 232 and conductive film 222 are removed from within recess 130 as shown in Fig. 8A . As a result, upper surface 213 and inner wall surface 212 of light-shielding layer 210 are exposed within recess 130.

[0133] As a result, a substrate 301 is manufactured in which only the light-shielding layer 210 remains in the recess 130. As with the substrate 300 according to the embodiment, no light-shielding layer is provided to cover the contact portion between the upper surface 121 of the insulating layer 120 and the uppermost surface 211 of the light-shielding layer 210, and the side surface 131 of the recess 130 is visible. This enables alignment using the side surface 131 of the recess 130. Note that at least one portion of the insulating films 242 and 232 and the conductive film 222 may remain without being removed.

[0134] A photoelectric conversion film 51 may further be formed on the substrate 301. After preparing the substrate 301 shown in Fig. 8A , a photoelectric conversion film 260 is formed to cover the light-shielding layer 220 and the pixel electrodes 50, as shown in Fig. 8B . Specifically, the photoelectric conversion film 260 is formed on the entire upper surface of the substrate 301 so as to cover the entire recess 130, the plurality of pixel electrodes 50, and the control electrodes 112. The photoelectric conversion film 260 contacts and covers the top surface 211, inner wall surface 212, and upper surface 213 of the light-shielding layer 210 in the recess 130.

[0135] Next, the photoelectric conversion film 260 is patterned into a predetermined shape by removing a portion of the photoelectric conversion film 260. As a result, the control electrode 112 is exposed, and the photoelectric conversion film 51 is formed so as to cover across the plurality of pixel electrodes 50, as shown in Fig. 7. In this way, the substrate 301 including the photoelectric conversion film 51 covering the light-shielding layer 210 can be manufactured.

[0136] In this modification, too, the photoelectric conversion film 51 covers the light-shielding layer 210, thereby suppressing diffusion of the material (specifically, Cu) contained in the light-shielding layer 210. Since Cu contamination can be suppressed, the quality of the substrate 301 and the quality of the imaging device 500 manufactured using the substrate 301 can be improved.

[0137] <Modification 2> Next, Modification 2 will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view showing the vicinity of the alignment mark and the vicinity of the pixel electrode 50 on the substrate 302 according to this modification.

[0138] 9, substrate 302 differs from substrate 300 shown in FIG. 4 in that the opening surface of recess 130 is planarized. Specifically, recess 130 is planarized by light-shielding layers 210 and 220 and light-transmitting layers 230 and 240. More specifically, the top surface of insulating layer 120 is located on the same plane as each of top surface 211 of light-shielding layer 210, top surface 221 of light-shielding layer 220, top surface 231 of light-transmitting layer 230, and top surface 241 of light-transmitting layer 240.

[0139] A method for manufacturing the substrate 302 shown in Fig. 9 will be described with reference to Fig. 10A and Fig. 10B. Fig. 10A and Fig. 10B are cross-sectional views for explaining one step of the method for manufacturing the substrate 302 according to this modification.

[0140] The manufacturing method of the substrate 302 is the same as the manufacturing method of the substrate 300 up to the step shown in Fig. 5D . After the pixel electrodes 50 and the control electrodes 112 are patterned as shown in Fig. 5D , the insulating film 242 is formed to a sufficient thickness as shown in Fig. 10A . Specifically, the insulating film 242 is formed so as to fill at least the entire recess 130. For example, the insulating film 242 may be formed to a thickness twice or more the depth of the recess 130 or half the width of the recess 130.

[0141] After forming the thick insulating film 242, the upper surface of the substrate 302 is planarized by polishing such as CMP, as shown in FIG. 10B . As a result, the recess 130 is planarized by the light-shielding layers 210 and 220 and the light-transmitting layers 230 and 240.

[0142] In this manner, a substrate 302 having a planarized recess 130 is manufactured. As with the substrate 300 according to the embodiment, no light-shielding layer is provided to cover the contact portion between the upper surface 121 of the insulating layer 120 and the uppermost surface 211 of the light-shielding layer 210, and the side surface 131 of the recess 130 is visible. This allows alignment using the side surface 131 of the recess 130.

[0143] As shown in FIG. 9 , a photoelectric conversion film 51 may be further formed on the substrate 302. The method for forming the photoelectric conversion film 51 is the same as in the embodiment and modified example 1. Covering the light-shielding layer 210 with the photoelectric conversion film 51 can suppress diffusion of the material (specifically, Cu) contained in the light-shielding layer 210. Since Cu contamination can be suppressed, the quality of the substrate 302 and the quality of the imaging device 500 manufactured using the substrate 302 can be improved. Since the recess 130 is planarized, the coverage of the portion of the photoelectric conversion film 51 that covers the recess 130 is improved, and the effect of suppressing Cu contamination can be enhanced.

[0144] <Modification 3> Next, Modification 3 will be described with reference to Fig. 11. Fig. 11 is a plan view for explaining one step of a manufacturing method for an imaging device 501 according to this modification.

[0145] The imaging device 501 shown in FIG. 11 differs from the imaging device 500 shown in FIG. 3B in that it does not include the recess 130. As described above, the recess 130 is used for alignment during manufacturing. That is, after the process requiring alignment is completed, the recess 130 is no longer necessary for the function of the imaging device 501. For this reason, as shown in FIG. 11 , the substrate layer 100 (i.e., the substrate 300, 301, or 302) is cut between the pixel electrode 50 and the recess 130 or at a position overlapping the recess 130. By arranging the recess 130 in the area to be cut or removed, the imaging device 501 can be made smaller.

[0146] A plurality of imaging devices 501 can be formed simultaneously on one wafer. Specifically, a plurality of imaging devices 501 are formed on one wafer in a two-dimensional array, and then the wafer is cut (also called dicing) to separate the imaging devices 501. A recess 130 may be formed in the region to be cut. That is, by cutting the wafer (i.e., the substrate 300, 301, or 302) at a position overlapping the recess 130, a plurality of small imaging devices 501 can be formed simultaneously.

[0147] While the substrate and imaging device according to one or more aspects, as well as the manufacturing methods thereof, have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0148] For example, in the above embodiment, the substrates 300, 301, and 302 are used in the manufacture of the imaging device 500 or 501, but this is not limiting. The substrates 300, 301, and 302 may also be used in the manufacture of other electronic devices such as memories. Alternatively, the substrates 300, 301, or 302 may be included in an electronic device. That is, the present disclosure may be realized as an electronic device including the substrates 300, 301, or 302. In this case, an electrode according to the present disclosure is formed on the upper surface 121 of the insulating layer 120 as a memory write electrode, a capacitor electrode, or the like, instead of the pixel electrode 50.

[0149] Furthermore, for example, the second layer covering the light-shielding layer 210 does not have to be the photoelectric conversion film 51 containing a photoelectric conversion material. In other words, the second layer does not have to contain a photoelectric conversion material. For example, the second layer may be formed using an organic material having a function other than photoelectric conversion. Alternatively, the second layer may be a dedicated film that covers the light-shielding layer 210.

[0150] Furthermore, for example, the logic circuit (peripheral circuit) of the imaging device 500 does not have to be provided on the substrate 300, 301, or 302. A separate substrate on which the logic circuit (peripheral circuit) is provided may be stacked on the substrate 300, 301, or 302. In other words, the imaging device 500 may have a stacked structure of two substrates.

[0151] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0152] The present disclosure can be used in electronic devices such as imaging devices, camera systems, and the like.

[0153] REFERENCE SIGNS LIST 10 Light detection section 11 Amplification transistor 12 Reset transistor 13 Address transistor 14 Unit pixel cell 15 Vertical scanning circuit 16 Counter electrode signal line 17 Vertical signal line 18 Load circuit 19 Column signal processing circuit 20 Horizontal signal readout circuit 21 Power supply wiring 22 Differential amplifier 23 Feedback line 24 Charge storage node 25 Charge detection circuit 26 Address signal line 27 Reset signal line 28 Horizontal common signal line 31 Semiconductor substrate 38A, 38B, 38C Gate insulating layer 39A, 39B, 39C Gate electrode 41A, 41B, 41C, 41D, 41E n-type impurity region 42 Element isolation region 43A, 43B, 43C Interlayer insulating film 45A, 45B Contact plug 46A, 46B, 46C Wiring 47A, 47B, 47C Via 50 Pixel electrode 51, 260 Photoelectric conversion film 51a, 52a, 53a, 100a, 121, 213, 241 Upper surface 51s, 52s, 53s, 131 Side surface 52 Transparent electrode 52c, 52d, 52e, 52f Side 53, 232, 242 Insulating film 54 Protective film 55 Color filter 56 Microlens 60 Voltage control circuit 100 Substrate layer 101 Pixel array 112 Control electrode 115 Connection portion 120, 150 Insulating layer 130 Recess 140 Via hole 210, 220 Light-shielding layer 211, 221, 231 Top surface 212 Inner wall surface 222 Conductive film 230, 240 Light-transmitting layer 250 Resist mask 300, 301, 302 Substrate 500, 501 Imaging device

Claims

1. A substrate comprising: a semiconductor layer; an insulating layer having a recess on its upper surface and provided on the semiconductor layer; an electrode provided on the insulating layer; and a first layer located within the recess and covering a side surface of the recess, wherein the recess is located at a position not overlapping with the electrode in a plan view; the top surface of the first layer is located on the same plane as an upper surface of the insulating layer; and further comprising a second layer containing a photoelectric conversion material that converts light into electric charges, wherein the second layer covers the electrode and the first layer.

2. The substrate of claim 1, wherein the second layer completely covers the first layer.

3. The substrate according to claim 1 or 2, further comprising a third layer located in the recess and covering the first layer, the third layer including the same material as that included in the electrode.

4. The substrate according to claim 3, wherein the top surface of said third layer is located on the same plane as the top surface of said insulating layer and the top surface of said first layer.

5. The substrate according to claim 4, further comprising a fourth layer located in the recess and covering the third layer, wherein the recess is planarized by the first layer, the third layer, and the fourth layer.

6. The substrate according to claim 1 or 2, wherein the first layer contains Cu.

7. The substrate according to claim 1 or 2, further comprising a wiring layer provided within the insulating layer, wherein the first layer contains the same conductive material as that contained in the wiring layer.

8. An imaging device comprising: a substrate according to claim 1 or 2; pixels formed on said substrate; and a signal processing circuit to which signals read out from said pixels are input.

9. A method for manufacturing a substrate, comprising: preparing a substrate having an insulating layer stacked on a semiconductor layer; forming a recess in an upper surface of the insulating layer; forming a first layer covering a side surface of the recess; forming an electrode in a position that does not overlap with the recess in a planar view; processing the first layer so that a top surface of the first layer and an upper surface of the insulating layer are located on the same plane; and forming a second layer containing a photoelectric conversion material that converts light into electric charges, so as to cover the first layer and the electrode.

10. The method for manufacturing a substrate according to claim 9, further comprising patterning the second layer so as to leave at least portions of the second layer that are on the first layer and the electrode.

11. A method for manufacturing a substrate, comprising: preparing a substrate comprising a semiconductor layer, an insulating layer having a recess on an upper surface and provided on the semiconductor layer, an electrode provided on the insulating layer, and a first layer located within the recess and covering a side surface of the recess, wherein the recess is provided at a position that does not overlap with the electrode in a plan view; and forming a second layer containing a photoelectric conversion material that converts light into electric charges, so as to cover the first layer and the electrode.

12. The method for manufacturing a substrate according to claim 11, further comprising patterning the second layer so as to leave at least portions of the second layer that are on the first layer and the electrode.

13. A method for manufacturing an imaging device, comprising cutting a substrate manufactured by the method for manufacturing a substrate according to any one of claims 9 to 12, between the electrode and the recess, or at a position overlapping the recess.

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