Lighting test method, lighting test system and electronic device

Abstract

The present disclosure relates to a lighting test method of a plurality of light-emitting elements, each including a second semiconductor layer, an active layer, a first semiconductor layer and an electrode unit, which are sequentially stacked on a growth substrate, and being spaced apart from each other. The lighting test method of the present disclosure comprises the steps of: forming an electric field between a probe card, which is in electrical contact with the electrode unit on the plurality of light-emitting devices, and a conductive plate disposed under the growth substrate so as to face the second semiconductor layer; and testing whether the plurality of light-emitting elements are turned on.

Description

Lighting inspection method, lighting inspection system, and electronic device

[0001] The present disclosure relates to a lighting inspection method for a light-emitting element applied to a display device, a lighting inspection system, and an electronic device including the display device.

[0002] The display device may include a light-emitting element. The light-emitting element may emit light, and the display device displays an image by combining the light emitted from the light-emitting element.

[0003] Micro LEDs can be used as these light-emitting devices. After being formed on a growth substrate, the micro LEDs can be separated from the growth substrate, transported, and ultimately bonded to electrodes of a display device.

[0004] It should be understood that this background is intended to provide a useful background for understanding the technology. However, this background may include ideas, concepts, or insights that were not known or appreciated by those skilled in the art prior to the effective filing date of the subject matter disclosed herein.

[0005] Multiple light-emitting elements can be formed simultaneously on a growth substrate. In this case, defects may occur in some of the multiple light-emitting elements.

[0006] The present disclosure provides a lighting inspection method and a lighting inspection system capable of inspecting whether a plurality of light-emitting elements formed on a growth substrate are defective before transfer and bonding are performed.

[0007] According to embodiments of the present disclosure, there is provided a method for inspecting the lighting of a plurality of light-emitting elements that are spaced apart from each other and include a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on a growth substrate: the method for inspecting the lighting includes: a step of forming an electric field between a probe card electrically contacting the electrode portion above the plurality of light-emitting elements and a conductive plate facing the second semiconductor layer under the growth substrate; and a step of inspecting whether the plurality of light-emitting elements are lit.

[0008] In one embodiment, the probe card may include a probe substrate disposed over the plurality of light-emitting elements; and a plurality of probe pins protruding from the probe substrate in a direction toward the plurality of light-emitting elements.

[0009] In one embodiment, the electrode portion of each of the plurality of light-emitting elements can be in electrical contact with a corresponding one of the plurality of probe pins.

[0010] In one embodiment, in the step of forming the electric field, the growth substrate may be placed between the conductive plate and the second semiconductor layer.

[0011] In one embodiment, in the step of forming the electric field, the conductive plate may be in direct contact with the lower surface of the growth substrate.

[0012] In one embodiment, the step of checking whether the plurality of light-emitting elements are lit may include the step of capturing an image of the plurality of light-emitting elements by an optical inspection unit; and the step of checking whether light is emitted in areas corresponding to the plurality of light-emitting elements in the image.

[0013] In one embodiment, the optical inspection unit can image the plurality of light-emitting elements on the probe card.

[0014] In one embodiment, the optical inspection unit captures the plurality of light-emitting elements under the conductive plate, wherein the conductive plate may include an optically transparent material.

[0015] In one embodiment, the lighting inspection method may further include, after the step of inspecting whether the plurality of light-emitting elements are lit, a step of removing a defective light-emitting element among the plurality of light-emitting elements from the growth substrate.

[0016] A lighting inspection system according to embodiments of the present disclosure comprises: a growth substrate; a plurality of light-emitting elements including a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on the growth substrate, the plurality of light-emitting elements being spaced apart from each other; a probe card disposed on the plurality of light-emitting elements and moving in a direction toward the plurality of light-emitting elements so as to make electrical contact with the electrode portion; a conductive plate disposed under the growth substrate and moving in a direction toward the growth substrate; and an optical inspection unit disposed on the probe card.

[0017] In one embodiment, the probe card may include a probe substrate disposed over the plurality of light-emitting elements; and a plurality of probe pins protruding from the probe substrate in a direction toward the plurality of light-emitting elements.

[0018] In one embodiment, the lighting inspection system may further include a power source electrically connected to each of the probe card and the conductive plate.

[0019] In one embodiment, the second semiconductor layer may be in direct contact with the upper surface of the growth substrate.

[0020] In one embodiment, the second semiconductor layer may include a first doped portion disposed below the active layer and having a first average doping concentration; a second doped portion disposed below the first doped portion and having a second average doping concentration lower than the first average doping concentration; and a third doped portion disposed below the second doped portion and having a third average doping concentration lower than the second average doping concentration.

[0021] In one embodiment, the electrode portion may further include an auxiliary electrode electrically contacting the first semiconductor layer on the first semiconductor layer; and a bonding electrode electrically connected to the auxiliary electrode on the auxiliary electrode.

[0022] In one embodiment, the auxiliary electrode may include a light-transmitting material.

[0023] In one embodiment, the planar surface area of ​​the bonding electrode may be smaller than the planar surface area of ​​the first semiconductor layer.

[0024] In one embodiment, the electrode portion may further include a reflective electrode disposed between the auxiliary electrode and the bonding electrode.

[0025] In one embodiment, the planar surface area of ​​the reflective electrode may be smaller than the planar surface area of ​​the first semiconductor layer.

[0026] A lighting inspection system according to embodiments of the present disclosure comprises: a growth substrate; a plurality of light-emitting elements including a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on the growth substrate, the plurality of light-emitting elements being spaced apart from each other; a probe card disposed on the plurality of light-emitting elements and moving in a direction toward the plurality of light-emitting elements so as to come into electrical contact with the electrode portion; a conductive plate disposed under the growth substrate and moving in a direction toward the growth substrate; and an optical inspection unit disposed on the conductive plate, wherein the conductive plate may include a light-transmitting material.

[0027] An electronic device according to embodiments of the present disclosure may include a processor that provides input image data; and a display device that displays an image based on the input image data. The display device may include a plurality of light-emitting elements, and the plurality of light-emitting elements may be manufactured by performing the lighting inspection method described above.

[0028] A lighting inspection method according to embodiments of the present disclosure provides a method for inspecting the lighting of a plurality of light-emitting elements formed directly on a growth substrate. Accordingly, lighting defects of the plurality of light-emitting elements can be sensed before the plurality of light-emitting elements are separated from the growth substrate and are transferred and bonded.

[0029] The foregoing and other aspects and features of the present disclosure will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings, in which:

[0030] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0031] FIG. 2 is a block diagram for explaining one of the sub-pixels included in the display device of FIG. 1.

[0032] FIG. 3 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0033] FIG. 4 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0034] FIG. 5 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0035] FIG. 6 is a schematic plan view illustrating a light emitting element array including a plurality of light emitting elements formed on a growth substrate.

[0036] Figure 7 is a schematic cross-sectional view taken along line I1-I1' of Figure 6.

[0037] FIG. 8 is a schematic cross-sectional view illustrating one embodiment of a lighting inspection system for performing lighting inspection of the light emitting element array of FIG. 6.

[0038] FIG. 9 is a schematic plan view for explaining an image captured by an optical inspection unit included in the lighting inspection system of FIG. 8.

[0039] Fig. 10 is a schematic cross-sectional view illustrating an embodiment of removing a light-emitting element determined to be defective based on the image of Fig. 9.

[0040] FIG. 11 is a schematic cross-sectional view illustrating one embodiment of a lighting inspection system for performing lighting inspection of the light emitting element array of FIG. 6.

[0041] Fig. 12 is a schematic plan view for explaining an image captured by an optical inspection unit included in the lighting inspection system of Fig. 11.

[0042] FIG. 13 is a schematic plan view illustrating an embodiment of one of the pixels of FIG. 3.

[0043] Fig. 14 is a schematic cross-sectional view taken along line X1-X1' of Fig. 13.

[0044] FIG. 15 is a schematic block diagram illustrating a display system according to one embodiment.

[0045] Figures 16 to 19 are schematic perspective views for explaining application examples of the display system of Figure 15.

[0046] Hereinafter, preferred embodiments according to the present disclosure will be described in detail with reference to the attached drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure will be described, and the description of other parts will be omitted so as not to obscure the gist of the present disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical concepts of the present disclosure in sufficient detail to enable those skilled in the art to easily implement them.

[0047] The size, thickness, proportion, and dimensions of elements in the drawings may be exaggerated for clarity and ease of explanation. Identical numbers represent identical elements throughout.

[0048] The singular expressions used herein are intended to include the plural expressions as well, unless the context clearly indicates otherwise.

[0049] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B." The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or."

[0050] In the specification and claims, the term "at least one" is intended to include, for purposes of meaning and interpretation, the meaning of "at least one selected from the group." For example, "at least one of A and B" can be understood to mean "A, B, or A and B."

[0051] Throughout this specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "indirectly connected" with other elements intervening. The terminology used herein is for the purpose of describing specific embodiments and is not intended to limit the present disclosure.

[0052] Throughout the specification, the terms "comprises," "comprising," "has," "having," and variations thereof specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0054] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features would instead be positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0055] The term "overlap" or "overlapping" means that the first object can be on top of, below, or next to the second object, or vice versa. The term "overlap" may also include layers, stacks, surfaces, or facing, extending, covering, or partially covering, or other appropriate terms understood and recognized by those skilled in the art.

[0056] The terms "face" and "face-to-face" imply that the first element can directly or indirectly replace the second element. If a third element intervenes between the first and second elements, the first and second elements can be understood as facing each other but indirectly replacing each other.

[0057] When elements are described as 'non-overlapping' or 'non-overlapping' with other elements, this may include the elements being spaced apart from each other, offset from each other, set separately from each other, or other appropriate terms that would be understood and recognized by one of ordinary skill in the art.

[0058] Various embodiments are described with reference to schematic drawings. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0059] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that value as determined by one of ordinary skill in the art, taking into account the measurement and the errors associated with measuring a particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0060] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries, for example, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0061] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0062] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0063] The display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0064] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, and the like within the scope and spirit of the present disclosure.

[0065] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. The pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included in the pixel (PXL).

[0066] The gate driver (120) may be connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) may output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) may include a start signal indicating the start of each frame, a horizontal synchronization signal, or the like within the scope and spirit of the present disclosure.

[0067] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and these drivers may be arranged on one side of the display panel (DP) and the other side opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0068] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, and the like within the spirit and scope of the present disclosure.

[0069] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn) using the received voltages. When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0070] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0071] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0072] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In another embodiment, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0073] The voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a selectable reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). In FIG. 1, the pixel control lines (PXCL) are illustrated as being connected between the voltage generator (140) and the display panel (DP), but embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0074] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0075] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by arranging the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0076] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0077] Fig. 2 is a block diagram for explaining one of the sub-pixels included in the display device of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated as an example.

[0078] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0079] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher level than the second power supply voltage.

[0080] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) is configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0081] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0082] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0083] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0084] FIG. 3 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0085] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned around the display area (DA).

[0086] A display panel (DP) may include sub-pixels (SP) arranged in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0087] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1, SP2, SP3), but the embodiments are not limited thereto. For example, the pixel (PXL) may also include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1, SP2, SP3).

[0088] Each of the first to third sub-pixels (SP1, SP2, SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. In the following, for clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) is configured to generate blue color light.

[0089] Each of the first to third sub-pixels (SP1, SP2, SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate red light, green light, and blue light, respectively.

[0090] As a display panel (DP), a self-luminous display panel can be used, such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements.

[0091] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0092] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0093] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed-loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0094] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In these cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0095] FIG. 4 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0096] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL, pixel element layer), a display element layer (DPL, display panel layer), and a light functional layer (LFL, light functional layer) that are sequentially stacked on the substrate (SUB) in a third direction (DR3) intersecting the first and second directions (DR1, DR2).

[0097] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. In another example, the substrate (SUB) may include a polyimide (PI) substrate. In another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0098] In the embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0099] A pixel circuit layer (PCL) may be disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, and the like within the scope and spirit of the present disclosure.

[0100] Circuit elements of the pixel circuit layer (PCL) can constitute a sub-pixel circuit (SPC) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) can be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0101] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines required to drive the display element layer (DPL).

[0102] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0103] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0104] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a given wavelength (or a given color). In some embodiments, the color filter layer may be omitted.

[0105] A window may be provided on the light-functional layer (LFL) to protect the exposed surface (or upper surface) of the display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded or connected to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0106] FIG. 5 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0107] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be configured to be substantially the same as (or similar to) the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4. Therefore, description of overlapping content will be omitted.

[0108] The input sensing layer (ISL) can detect a user's input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting an external object, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0109] Fig. 6 is a schematic plan view illustrating a light-emitting element array including a plurality of light-emitting elements formed on a growth substrate. Fig. 7 is a schematic cross-sectional view taken along line I1-I1' of Fig. 6.

[0110] Referring to FIGS. 6 and 7, a light emitting element array (LDAR) may be formed on a growth substrate (SSP). The light emitting element array (LDAR) may include a plurality of light emitting elements (e.g., LD_NOR, LD_DF). There is no limitation on the method for forming the light emitting element array (LDAR) on the growth substrate (SSP), and various known methods may be used. For example, an epitaxial growth process may be performed to form the plurality of light emitting elements.

[0111] The growth substrate (SSP) may include, for example, a sapphire substrate. However, the material of the growth substrate (SSP) is not limited thereto. The growth substrate (SSP) may include various known materials suitable for performing the aforementioned epitaxial growth process, etc.

[0112] The plurality of light emitting elements included in the light emitting element array (LDAR) may be spaced apart from each other and arranged on a growth substrate (SSP). One or more of the plurality of light emitting elements may have a defect. For example, the plurality of light emitting elements may include a normal light emitting element (LD_NOR) and a defective light emitting element (LD_DF). The normal light emitting element (LD_NOR) may be a light emitting element that normally emits light based on an electric signal provided from a pixel (PXL, see FIGS. 13 and 14) described below. The defective light emitting element (LD_DF) may be a light emitting element that does not emit light even when an electric signal is provided. The defective light emitting element (LD_DF) may be a light emitting element that has lost its function due to the intervention of a foreign substance during the above-described epitaxial process, for example.

[0113] The plurality of light-emitting elements may be separated from the growth substrate (SSP) and provided to the pixel (PXL) by various known transport means and methods. The plurality of light-emitting elements provided to the pixel (PXL) may be bonded to electrodes (e.g., AE1 to AE3, see FIG. 14). In this case, if a defective light-emitting element (LD_DF) is provided and bonded to the pixel (PXL), the pixel (PXL) may not be able to normally emit light. Accordingly, the display quality of the display device (DD, see FIG. 1) may deteriorate.

[0114] To prevent this, the present disclosure provides a method for performing an illumination inspection of a plurality of light emitting elements included in a light emitting element array (LDAR) after forming the light emitting element array (LDAR) on a growth substrate (SSP) and before the light emitting element array (LDAR) is separated, transferred, and bonded. This illumination inspection method and a system for performing the illumination inspection will be described in detail below with reference to FIGS. 8 to 12, and below, each of the plurality of light emitting elements included in the light emitting element array (LDAR) will be described in more detail with reference to FIG. 7.

[0115] A plurality of light-emitting elements included in a light-emitting element array (LDAR) may be configured substantially identically to each other. For example, two normal light-emitting elements (LD_NOR) and one defective light-emitting element (LD_DF) illustrated in FIG. 7 may be configured substantially identically to each other. Hereinafter, for clarity and conciseness, the description will be based on the normal light-emitting element (LD_NOR) illustrated on the left side of FIG. 7.

[0116] A normal light emitting element (LD_NOR) may include a light emitting layer (EST), an electrode portion (EE), and an insulating film (40).

[0117] The light-emitting stack (EST) may include a first semiconductor layer (10), an active layer (20), and a second semiconductor layer (30). The second semiconductor layer (30), the active layer (20), and the first semiconductor layer (10) may be sequentially stacked on a growth substrate (SSP) along a fourth direction (DR4). Here, the fourth direction (DR4) may be a direction opposite to the third direction (DR3, see FIGS. 3 to 5). In addition, in describing FIGS. 6 to 12, the fourth direction (DR4) may be referred to as an 'upward direction'.

[0118] The first semiconductor layer (10) may be configured to provide holes. The first semiconductor layer (10) may have a first polarity. For example, the first semiconductor layer (10) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (10) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), and the like within the spirit and scope of the present disclosure. However, the material constituting the first semiconductor layer (10) is not limited thereto, and various other materials may constitute the first semiconductor layer (10). In one embodiment of the present disclosure, the first semiconductor layer (10) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0119] The active layer (20) may be disposed between the first semiconductor layer (10) and the second semiconductor layer (30) to provide a region where electrons and holes recombine. As electrons and holes recombine in the active layer (20), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (20) may be formed in a single or multiple quantum well structure. When the active layer (20) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcement layer, and a well layer may be repeatedly stacked on each other to form the active layer (20). However, the active layer (20) is not limited to the above-described structure.

[0120] The second semiconductor layer (30) may be configured to provide electrons. The second semiconductor layer (30) may have a second polarity different from the first polarity. For example, the second semiconductor layer (30) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (30) may include any one of the semiconductor materials of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and the like, within the spirit and scope of the present disclosure. However, the material constituting the second semiconductor layer (30) is not limited thereto, and various other materials may constituting the second semiconductor layer (30). In one embodiment of the present disclosure, the second semiconductor layer (30) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0121] In embodiments, the second semiconductor layer (30) may include a first doped portion (31) disposed under the active layer (20), a second doped portion (32) disposed under the first doped portion (31), and a third doped portion (33) disposed under the second doped portion (32). The first doped portion (31) may be a portion doped with a dopant at a first average doping concentration. The second doped portion (32) may be a portion doped with a dopant at a second average doping concentration lower than the first average doping concentration. The third doped portion (33) may be a portion doped with a dopant at a third average doping concentration lower than the second average doping concentration. The first to third doped portions (31, 32, 33) may define the second semiconductor layer (30).

[0122] In the embodiments, the normal light emitting element (LD_NOR) may be formed directly on the growth substrate (SSP). Accordingly, the second semiconductor layer (30) may be in direct contact with the growth substrate (SSP). In other words, the lower surface of the second semiconductor layer (30) may be in direct contact with the upper surface of the growth substrate (SSP). In this case, other components such as a conductive layer may not be disposed between the second semiconductor layer (30) and the growth substrate (SSP).

[0123] In the embodiments, the light-emitting stack (EST) may have a columnar shape in which the second semiconductor layer (30), the active layer (20), and the first semiconductor layer (10) are sequentially stacked along the fourth direction (DR4). For example, the light-emitting stack (EST) may have a cylindrical shape, but the embodiments are not limited thereto.

[0124] An electrode unit (EE) may be disposed on a light-emitting stack (EST). The electrode unit (EE) may include an auxiliary electrode (SE), a reflective electrode (RE), and a bonding electrode (BDE) sequentially stacked along a fourth direction (DR4).

[0125] The auxiliary electrode (SE) may be disposed on the first semiconductor layer (10). The auxiliary electrode (SE) may be in electrical contact with the first semiconductor layer (10). In embodiments, the auxiliary electrode (SE) may be configured to be substantially transparent or translucent to satisfy selectable light transmittance. For example, the auxiliary electrode (SE) may include a conductive, light-transmitting material. For example, the auxiliary electrode (SE) may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the auxiliary electrode (SE) is not limited thereto.

[0126] The reflective electrode (RE) may be disposed on the auxiliary electrode (SE). The reflective electrode (RE) may be in electrical contact with the auxiliary electrode (SE). In embodiments, the reflective electrode (RE) may include a conductive material having a selectable reflectivity. For example, the reflective electrode (RE) may include a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. However, the material of the reflective electrode (RE) is not limited thereto. Since the reflective electrode (RE) has a selectable reflectivity, light emitted from the active layer (20) can be more effectively provided to the light functional layer (LFL, see FIG. 14) described below.

[0127] A bonding electrode (BDE) may be disposed on a reflective electrode (RE). The bonding electrode (BDE) may be in electrical contact with the reflective electrode (RE). In embodiments, the bonding electrode (BDE) may include a eutectic metal.

[0128] According to embodiments, at least one of the auxiliary electrode (SE) and the reflective electrode (RE) may be omitted. When both the auxiliary electrode (SE) and the reflective electrode (RE) are omitted, the bonding electrode (BDE) may be in electrical contact with the upper surface of the first semiconductor layer (10). When either the auxiliary electrode (SE) or the reflective electrode (RE) is omitted, the other electrode may be in electrical contact with the upper surface of the first semiconductor layer (10) and the lower surface of the bonding electrode (BDE), respectively.

[0129] In the embodiments, the auxiliary electrode (SE) may completely overlap with the first semiconductor layer (10). Each of the reflective electrode (RE) and the bonding electrode (BDE) may overlap with a portion of the first semiconductor layer (10). In other words, the planar area of ​​the auxiliary electrode (SE) may be substantially the same as the planar area of ​​the first semiconductor layer (10). Each of the planar area of ​​the reflective electrode (RE) and the planar area of ​​the bonding electrode (BDE) may be smaller than the planar area of ​​the first semiconductor layer (10).

[0130] The insulating film (40) may cover at least a portion of the outer surface of the light emitting stack (EST). For example, the insulating film (40) may cover at least a side surface of the active layer (20). The insulating film (40) may include a transparent insulating material. The insulating film (40) may prevent an electrical short circuit that may occur when the active layer (20) comes into contact with another conductive component. In embodiments, the insulating film (40) may have a multilayer structure composed of a plurality of layers including a transparent insulating material.

[0131] FIG. 8 is a schematic cross-sectional view illustrating one embodiment of a lighting inspection system for performing lighting inspection of the light emitting element array of FIG. 6.

[0132] Referring to FIG. 8, the lighting inspection system (SYS1) may include a growth substrate (SSP), a light emitting element array (LDAR), a probe card (PC), a conductive plate (MP), and an optical inspection unit (OU).

[0133] The growth substrate (SSP) and the light-emitting element array (LDAR) are described in the same manner as described with reference to FIGS. 6 and 7. Therefore, redundant descriptions are omitted.

[0134] A probe card (PC) may be placed on a plurality of light emitting elements (LD_NOR, LD_DF) included in a light emitting element array (LDAR). The probe card (PC) may be configured to be relatively movable in a direction toward the plurality of light emitting elements (LD_NOR, LD_DF). When the probe card (PC) is relatively moved in a direction toward the plurality of light emitting elements (LD_NOR, LD_DF), the probe card (PC) may electrically contact electrode portions (EE) of the plurality of light emitting elements (LD_NOR, LD_DF).

[0135] In embodiments, a probe card (PC) may include a probe substrate (PS) disposed on a plurality of light-emitting elements (LD_NOR, LD_DF), and a probe pin (PIN) protruding from the probe substrate (PS) in a direction toward the plurality of light-emitting elements (LD_NOR, LD_DF). A plurality of probe pins (PIN) may be provided so as to correspond one-to-one to the plurality of light-emitting elements (LD_NOR, LD_DF). For example, three probe pins (PINa, PINb, PINc) corresponding to three light-emitting elements (LD_NOR, LD_DF) illustrated in FIG. 8 may be provided. The probe pin (PIN) may be a portion that electrically contacts the electrode portions (EE) of the plurality of light-emitting elements (LD_NOR, LD_DF). In this case, the probe substrate (PS) may be electrically connected to the probe pin (PIN).

[0136] A conductive plate (MP) may be disposed under a growth substrate (SSP). The conductive plate (MP) may include a conductive material. For example, the conductive plate (MP) may include a metallic material. The conductive plate (MP) may be configured to be relatively movable in a direction toward the growth substrate (SSP). When the conductive plate (MP) is relatively movable in a direction toward the growth substrate (SSP), the conductive plate (MP) may directly contact a lower surface of the growth substrate (SSP).

[0137] An electric field may be formed between the probe card (PC) and the conductive plate (MP). For example, the lighting inspection system (SYS1) may further include a power source (PW) electrically connected to each of the probe card (PC) and the conductive plate (MP). By the power source (PW), an electric field may be formed between the probe card (PC) and the conductive plate (MP).

[0138] The above electric field can be formed when the probe card (PC) is in electrical contact with the electrode portion (EE) and the conductive plate (MP) is in contact with the lower surface of the growth substrate (SSP). In this case, the normal light-emitting element (LD_NOR) can emit light due to the electric field. However, the defective light-emitting element (LD_DF) may not emit light.

[0139] An optical inspection unit (OU) can be placed on a probe card (PC). The optical inspection unit (OU) can generate an image (IMG, see FIG. 9) of a plurality of light-emitting elements (LD_NOR, LD_DF) included in a light-emitting element array (LDAR) when an electric field is formed between the probe card (PC) and a conductive plate (MP).

[0140] FIG. 9 is a schematic plan view for explaining an image captured by an optical inspection unit included in the lighting inspection system of FIG. 8.

[0141] Referring to FIG. 9, images (IMG) of first to sixth areas (AA1, AA2, AA3, AA4, AA5, AA6) corresponding to the positions of a plurality of light-emitting elements (LD_NOR, LD_DF) included in the light-emitting element array (LDAR) of FIG. 6 can be generated.

[0142] First to sixth non-emission regions (NEA1, NEA2, NEA3, NEA4, NEA5, NEA6) may be defined in the center of the first to sixth regions (AA1, AA2, AA3, AA4, AA5, AA6). The first to sixth non-emission regions (NEA1, NEA2, NEA3, NEA4, NEA5, NEA6) may be regions corresponding to a bonding electrode (BDE) and a reflective electrode (RE) included in an electrode portion (EE) of a plurality of light-emitting elements (LD_NOR, LD_DF).

[0143] The first region (AA1) and the third to sixth regions (AA3, AA4, AA5, AA6) may be regions where normal light-emitting elements (LD_NOR) are located. Since the first region (AA1) and the third to sixth regions (AA3, AA4, AA5, AA6) are regions where light is emitted, they may be recognized as relatively bright regions on the image (IMG).

[0144] In contrast, the second area (AA2) may be an area where a defective light-emitting element (LD_DF) is located. Since the second area (AA2) is an area where no light is emitted, it may be recognized as a relatively dark area in the image (IMG). Accordingly, the defect (DF) of the defective light-emitting element (LD_DF) located in the second area (AA2) may be determined based on the image (IMG).

[0145] Fig. 10 is a schematic cross-sectional view illustrating an embodiment of removing a light-emitting element determined to be defective based on the image of Fig. 9.

[0146] Referring to Fig. 9, the defective light-emitting element (LD_DF) can be removed. Accordingly, only the normal light-emitting element (LD_NOR) can exist on the growth substrate (SSP). There is no limitation on the method for removing the defective light-emitting element (LD_DF), and various known methods can be used. For example, a method of selectively irradiating a laser to the area where the defective light-emitting element (LD_DF) is located can be used.

[0147] Referring again to FIGS. 8 to 10, the lighting inspection method of the present disclosure may include a step of forming an electric field between a probe card (PC) and a conductive plate (MP), and a step of inspecting whether a plurality of light-emitting elements included in a light-emitting element array (LDAR) are lit.

[0148] When the above electric field is formed, the probe card (PC) can make electrical contact with a plurality of light emitting elements included in the light emitting element array (LDAR). For example, the probe card (PC) can make electrical contact with the electrode portion (EE) that is in electrical contact with the first semiconductor layer (10). Alternatively, when the above electric field is formed, the conductive plate (MP) can be spaced apart from the plurality of light emitting elements included in the light emitting element array (LDAR). For example, the conductive plate (MP) can be non-contact with the second semiconductor layer (30). A growth substrate (SSP) can be disposed between the conductive plate (MP) and the second semiconductor layer (30), and the conductive plate (MP) can make contact with a lower surface of the growth substrate (SSP).

[0149] In this way, even if the conductive plate (MP) does not directly contact the second semiconductor layer (30), the normal light-emitting element (LD_NOR) among the plurality of light-emitting elements included in the light-emitting element array (LDAR) can emit light by the formation of the electric field. For example, even if the light-emitting element array (LDAR) is not separated from the growth substrate (SSP), it may be possible to check whether the light-emitting element array (LDAR) is turned on.

[0150] The inspection of whether lighting is on can be performed by checking whether areas corresponding to the plurality of light-emitting elements are lit in the image (IMG) based on the image (IMG) acquired by the optical inspection unit (OU).

[0151] FIG. 11 is a schematic cross-sectional view illustrating one embodiment of a lighting inspection system for performing lighting inspection of the light emitting element array of FIG. 6.

[0152] Below, the differences between the lighting inspection system (SYS2) and the lighting inspection system (SYS1) described with reference to Fig. 8 will be mainly explained, and any parts omitted will be replaced with the previous content.

[0153] Referring to FIG. 11, the lighting inspection system (SYS2) may include a growth substrate (SSP), a light emitting element array (LDAR), a probe card (PC), a conductive plate (MP'), and an optical inspection unit (OU').

[0154] The conductive plate (MP') can be configured to be substantially transparent or translucent to satisfy selectable light transmittance. For example, the conductive plate (MP') can include a light-transmitting material that is conductive. For example, the conductive plate (MP') can include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the conductive plate (MP') is not limited thereto.

[0155] An optical inspection unit (OU') can be placed under a conductive plate (MP'). The optical inspection unit (OU') can generate an image (IMG', see Fig. 12) of a plurality of light-emitting elements (LD_NOR, LD_DF) included in a light-emitting element array (LDAR) when an electric field is formed between the probe card (PC) and the conductive plate (MP').

[0156] Fig. 12 is a schematic plan view for explaining an image captured by an optical inspection unit included in the lighting inspection system of Fig. 11.

[0157] Referring to FIG. 12, images (IMG') of first to sixth areas (AA1', AA2', AA3', AA4', AA5', AA6') corresponding to positions of a plurality of light-emitting elements (LD_NOR, LD_DF) included in the light-emitting element array (LDAR) of FIG. 6 can be generated.

[0158] In this case, since the optical inspection unit (OU', see FIG. 11) captures a plurality of light-emitting elements (LD_NOR, LD_DF) under the conductive plate (MP'), the first to sixth non-light-emitting regions (NEA1, NEA2, NEA3, NEA4, NEA5, NEA6) described with reference to FIG. 9 may not be defined.

[0159] The first region (AA1') and the third to sixth regions (AA3', AA4', AA5', AA6') may be regions where the normal light-emitting element (LD_NOR) is located. Since the first region (AA1') and the third to sixth regions (AA3', AA4', AA5', AA6') are regions where light is emitted, they may be recognized as relatively bright regions on the image (IMG').

[0160] In contrast, the second area (AA2') may be an area where a defective light-emitting element (LD_DF) is located. Since the second area (AA2') is an area where no light is emitted, it may be recognized as a relatively dark area in the image (IMG'). Accordingly, the defect (DF') of the defective light-emitting element (LD_DF) located in the second area (AA2') may be determined based on the image (IMG').

[0161] FIG. 13 is a schematic plan view illustrating an embodiment of one of the pixels of FIG. 3.

[0162] Referring to FIG. 13, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0163] First to third anode electrodes (AE1, AE2, AE3) may be respectively disposed in the first to third sub-pixels (SP1, SP2, SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0164] One or more first light-emitting elements (LD1), one or more second light-emitting elements (LD2), and one or more third light-emitting elements (LD3) may be arranged on first to third anode electrodes (AE1, AE2, AE3). The first light-emitting elements (LD1) may be connected to the first anode electrode (AE1). The second light-emitting elements (LD2) may be connected to the second anode electrode (AE2). The third light-emitting elements (LD3) may be connected to the third anode electrode (AE3). When a plurality of light-emitting elements are provided in each sub-pixel, each anode electrode may have a shape extending in a given direction, such as the second direction (DR2), and the light-emitting elements connected thereto may be arranged in the same direction.

[0165] The first light-emitting elements (LD1) may be provided as light-emitting elements (LD, see FIG. 2) included in the first sub-pixel (SP1). The second light-emitting elements (LD2) may be provided as light-emitting elements (LD, see FIG. 2) included in the second sub-pixel (SP2). The third light-emitting elements (LD3) may be provided as light-emitting elements (LD, see FIG. 2) included in the third sub-pixel (SP3). When a plurality of light-emitting elements are provided in one sub-pixel, the plurality of light-emitting elements may be connected in parallel between the anode electrode and the cathode electrode to be provided as the light-emitting elements (LD) of FIG. 2.

[0166] Each of the first light-emitting elements (LD1), the second light-emitting elements (LD2), and the third light-emitting elements (LD3) can be configured substantially identically to the normal light-emitting element (LD_NOR) described with reference to FIG. 7.

[0167] Fig. 14 is a schematic cross-sectional view taken along line X1-X1' of Fig. 13.

[0168] Referring to FIGS. 13 and 14, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0169] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0170] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1, SP2, SP3) may include a sub-pixel circuit (SPC, see FIG. 2) of transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). The conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXLC) of FIG. 1.

[0171] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0172] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may include polyimide.

[0173] On a buffer layer (BFL), first to third transistors (T_SP1, T_SP2, T_SP3) corresponding to first to third sub-pixels (SP1, SP2, SP3) may be arranged, respectively. The first transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). The second transistor (T_SP2) may be any one of the transistors of the sub-pixel circuit (SPC) included in the second sub-pixel (SP2). The third transistor (T_SP3) may be any one of the transistors of the sub-pixel circuit (SPC) included in the third sub-pixel (SP3). Each of the first to third transistors (T_SP1, T_SP2, T_SP3) may be understood as a transistor connected to an anode electrode among the transistors of the corresponding sub-pixel.

[0174] A first transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0175] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the first transistor (T_SP1). The channel region may be a semiconductor pattern that is substantially not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurities, for example, p-type impurities may be used, but embodiments are not limited thereto.

[0176] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0177] Interlayer insulating layers (ILDs) sequentially stacked on a semiconductor pattern (SCP) may be disposed. The interlayer insulating layers (ILDs) may be inorganic insulating layers including inorganic materials. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0178] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the semiconductor pattern (SCP) is spaced apart from the gate electrode (GE). In embodiments, the gate insulating layer (GI) may be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL), thereby covering the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0179] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0180] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0181] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), the embodiments are not limited thereto. In the embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of the channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0182] In embodiments, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of each sub-pixel may include transistors of different types. For example, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and another transistor included in the sub-pixel circuit (SPC) of the first sub-pixel (SP1) may be formed of an oxide semiconductor transistor. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the first transistor (T_SP1) is formed.

[0183] In the embodiments, the first transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be a transistor having a bottom gate structure. The structure of the first transistor (T_SP1) may be changed in various ways.

[0184] Each of the second and third transistors (T_SP2, T_SP3) can be configured similarly to the first transistor (T_SP1). Therefore, description of overlapping content can be omitted.

[0185] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0186] A first passivation layer (PSV1) may be disposed over the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed beneath the first passivation layer (PSV1) and may provide a flat upper surface.

[0187] First to third connection patterns (CP1, CP2, CP3) may be arranged on a first passivation layer (PSV1). The first to third connection patterns (CP1, CP2, CP3) may penetrate the first passivation layer (PSV1) and be connected to first terminals (ET1) of the first to third transistors (T_SP1, T_SP2, T_SP3), respectively. The first to third connection patterns (CP1, CP2, CP3) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0188] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0189] A second passivation layer (PSV2) may be disposed on the first to third connection patterns (CP1, CP2, CP3) and the first passivation layer (PSV1). The second passivation layer (PSV2) may protect components disposed beneath the second passivation layer (PSV2) and provide a flat upper surface.

[0190] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0191] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0192] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include first to third anode electrodes (AE1, AE2, AE3), a first bank (BNK1), first to third light-emitting elements (LD1, LD2, LD3), an overcoat layer (OCL), a cathode electrode (CE), and a capping layer (CPL).

[0193] On the pixel circuit layer (PCL), first to third anode electrodes (AE1, AE2, AE3) can be arranged on the first to third sub-pixels (SP1, SP2, SP3), respectively.

[0194] The first anode electrode (AE1) may be electrically connected to the first connection pattern (CP1) through a contact hole penetrating the second passivation layer (PSV2). The second anode electrode (AE2) may be electrically connected to the second connection pattern (CP2) through another contact hole penetrating the second passivation layer (PSV2). The third anode electrode (AE3) may be electrically connected to the third connection pattern (CP3) through another contact hole penetrating the second passivation layer (PSV2). In this way, the first to third anode electrodes (AE1, AE2, AE3) may be electrically connected to the first to third transistors (T_SP1, T_SP2, T_SP3), respectively.

[0195] A first bank (BNK1) may be disposed on the first to third anode electrodes (AE1, AE2, AE3). The first bank (BNK1) may have first openings (OP1) exposing portions of the first to third anode electrodes (AE1, AE2, AE3). The first to third light-emitting elements (LD1, LD2, LD3) may be disposed in the first openings (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines areas where the first to third light-emitting elements (LD1, LD2, LD3) are positioned.

[0196] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material within the spirit and scope of the present disclosure, such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin. According to embodiments, in order to further improve light output efficiency, a reflective layer including a reflective material may be further disposed on a side of the first bank (BNK1) adjacent to the first openings (OP1).

[0197] The first to third light-emitting elements (LD1, LD2, LD3) may be respectively disposed on the first to third anode electrodes (AE1, AE2, AE3). The first to third light-emitting elements (LD1, LD2, LD3) may be bonded or connected to the first to third anode electrodes (AE1, AE2, AE3), respectively. The first to third light-emitting elements (LD1, LD2, LD3) may be configured substantially the same as the normal light-emitting element (LD_NOR) described with reference to FIG. 7. Therefore, description of overlapping content may be omitted.

[0198] The bonding electrode (BDE) of the first light-emitting element (LD1) may be connected to the first anode electrode (AE1). The bonding electrode (BDE2) of the second light-emitting element (LD2) may be connected to the second anode electrode (AE2). The bonding electrode (BDE3) of the third light-emitting element (LD3) may be connected to the third anode electrode (AE3). The upper surfaces of the second semiconductor layers (30) of the first to third light-emitting elements (LD1, LD2, LD3) may be connected to the cathode electrode (CE). Accordingly, the first light-emitting element (LD1) can be connected between the first anode electrode (AE1) and the cathode electrode (CE), the second light-emitting element (LD2) can be connected between the second anode electrode (AE2) and the cathode electrode (CE), and the third light-emitting element (LD3) can be connected between the third anode electrode (AE3) and the cathode electrode (CE).

[0199] An overcoat layer (OCL) may be disposed within the first openings (OP1) in which the first to third light-emitting elements (LD1, LD2, LD3) are disposed. The overcoat layer (OCL) may fix the first to third light-emitting elements (LD1, LD2, LD3) bonded to the first to third anode electrodes (AE1, AE2, AE3) so as not to move. The overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust and moisture. The overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0200] In embodiments, the overcoat layer (OCL) may not be disposed on the upper surfaces of the first to third light-emitting elements (LD1, LD2, LD3). The first to third light-emitting elements (LD1, LD2, LD3) may protrude into the light-functional layer (LFL). The first to third light-emitting elements (LD1, LD2, LD3) may be at least partially positioned within the second openings (OP2) of the second bank (BNK2). For example, the height of the upper surface (LTS) of each of the first to third light-emitting elements (LD1, LD2, LD3) from the substrate (SUB) may be higher than the lowermost end (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first to third light-emitting elements (LD1, LD2, LD3) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0201] A cathode electrode (CE) may be disposed on the first to third light-emitting elements (LD1, LD2, LD3). The cathode electrode (CE) may be disposed entirely on the first bank (BNK1), the first to third light-emitting elements (LD1, LD2, LD3), and the overcoat layer (OCL). The cathode electrode (CE) may contact the upper surface of the second semiconductor layer (30) of each of the first to third light-emitting elements (LD1, LD2, LD3). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. The second power voltage applied to the second power voltage node (VSSN) may be transmitted to the first to third light-emitting elements (LD1, LD2, LD3) through the cathode electrode (CE).

[0202] The cathode electrode (CE) may be configured to be substantially transparent or translucent to satisfy selectable light transmittance. In embodiments, the cathode electrode (CE) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like. However, the material of the cathode electrode (CE) is not limited thereto.

[0203] A capping layer (CPL) may be disposed on the cathode electrode (CE). The capping layer (CPL) may protect components under the capping layer (CPL), such as the cathode electrode (CE) and the first to third light-emitting elements (LD1, LD2, LD3), from external moisture and humidity. The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0204] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a third passivation layer (PSV3), first and second light conversion patterns (CCP1, CCP2), a light scattering pattern (LSP), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0205] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have second openings (OP2) that overlap the first openings (OP1).

[0206] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent pixels and the first to third sub-pixels (SP1, SP2, SP3). In embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material within the spirit and scope of the present disclosure, such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0207] A reflective layer (RFL) may be disposed on the side surfaces of the second bank (BNK2) adjacent to the second openings (OP2). The reflective layer (RFL) is configured to reflect incident light, and thus, light emission efficiency may be improved. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0208] It can be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the second bank (BNK2). The area overlapping the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). The area overlapping the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA).

[0209] A third passivation layer (PSV3) may be disposed on the capping layer (CPL) and within the second openings (OP2). The third passivation layer (PSV3) may protect components disposed beneath the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0210] On the third passivation layer (PSV3), first and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) can be arranged within the second openings (OP2).

[0211] The first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0212] In the embodiments, the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light output efficiency. Accordingly, the first to third sub-pixels (SP1, SP2, SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0213] In embodiments, the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit red, green, and blue light, respectively. In this case, each of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the color of the light emitted from the first to third light-emitting elements (LD1, LD2, LD3).

[0214] In the embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0215] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. The low-refractive-index layer (LRL) may provide light that has passed through the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) back to the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). Accordingly, the light conversion efficiency and light scattering efficiency of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) can be improved. In embodiments, the low refractive layer (LRL) may be omitted in the area corresponding to the third sub-pixel (SP3).

[0216] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0217] The first to third color filters (CF1, CF2, CF3) may overlap the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP), respectively. Each of the first to third color filters (CF1, CF2, CF3) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1, CF2, CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, the embodiments are not limited thereto, and the first to third color filters (CF1, CF2, CF3) may have a refractive index lower than or equal to that of the low refractive index layer (LRL).

[0218] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0219] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0220] Fig. 15 is a block diagram illustrating a display system according to one embodiment.

[0221] Referring to FIG. 15, the display system (1000) may include a processor (1100) and a display device (1200).

[0222] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), and the like, all within the scope and spirit of the present disclosure. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0223] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0224] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0225] Figures 16 to 19 are schematic perspective views for explaining application examples of the display system of Figure 15.

[0226] Referring to FIG. 16, the display system (1000) of FIG. 15 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0227] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0228] Referring to FIG. 17, the display system (1000) of FIG. 15 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0229] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0230] Referring to FIG. 18, the display system (1000) of FIG. 15 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0231] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0232] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0233] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or other materials within the scope and spirit of the present disclosure.

[0234] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0235] Referring to FIG. 19, the display system (1000) of FIG. 15 can be applied to a head-mounted display device (500).

[0236] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0237] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in a form within the spirit and scope of the present disclosure, such as a glasses frame form or a helmet form.

[0238] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0239] Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the claims below.

Claims

1. A method for inspecting the lighting of a plurality of light-emitting elements spaced apart from each other, the light-emitting elements including a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode part sequentially stacked on a growth substrate: A step of forming an electric field between a probe card in electrical contact with the electrode portion on the plurality of light-emitting elements and a conductive plate facing the second semiconductor layer under the growth substrate; and A lighting inspection method, comprising a step of inspecting whether the plurality of light-emitting elements are lit.

2. In the first paragraph, the probe card, a probe substrate disposed on the plurality of light-emitting elements; and A lighting inspection method comprising a plurality of probe pins protruding from the probe substrate in a direction toward the plurality of light-emitting elements.

3. In paragraph 2, A lighting inspection method, wherein the electrode portion of each of the plurality of light-emitting elements electrically contacts a corresponding one of the plurality of probe pins.

4. In paragraph 1, A lighting inspection method, wherein, in the step of forming the electric field, the growth substrate is placed between the conductive plate and the second semiconductor layer.

5. In paragraph 4, A lighting inspection method wherein, in the step of forming the electric field, the conductive plate is in direct contact with the lower surface of the growth substrate.

6. In the first paragraph, the step of checking whether the plurality of light-emitting elements are lit is, A step of acquiring an image by capturing the plurality of light-emitting elements with an optical inspection unit; and A lighting inspection method, comprising a step of checking whether light is emitted in areas corresponding to the plurality of light-emitting elements in the image.

7. In paragraph 6, A lighting inspection method in which the optical inspection unit captures images of the plurality of light-emitting elements on the probe card.

8. In paragraph 6, The optical inspection unit captures images of the plurality of light-emitting elements under the conductive plate, A lighting inspection method, wherein the conductive plate includes a light-transmitting material.

9. In the first paragraph, after the step of checking whether the plurality of light-emitting elements are lit, A lighting inspection method further comprising a step of removing a defective light-emitting element among the plurality of light-emitting elements from the growth substrate.

10. Growth substrate; A plurality of light-emitting elements including a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on the growth substrate, the plurality of light-emitting elements being spaced apart from each other; A probe card disposed on the plurality of light-emitting elements and moving in a direction toward the plurality of light-emitting elements so as to make electrical contact with the electrode portion; A conductive plate disposed under the growth substrate and moving in a direction toward the growth substrate; and A lighting inspection system comprising an optical inspection unit positioned on the probe card.

11. In the 10th paragraph, the probe card, a probe substrate disposed on the plurality of light-emitting elements; and A lighting inspection system comprising a plurality of probe pins protruding from the probe substrate in a direction toward the plurality of light-emitting elements.

12. In paragraph 10, A lighting inspection system further comprising a power source electrically connected to each of the probe card and the conductive plate.

13. In paragraph 10, A lighting inspection system in which the second semiconductor layer is in direct contact with the upper surface of the growth substrate.

14. In the 10th paragraph, the second semiconductor layer is A first doped portion disposed below the active layer and having a first average doping concentration; A second doping portion disposed below the first doping portion and having a second average doping concentration lower than the first average doping concentration; and A lighting inspection system comprising a third doping section disposed below the second doping section and having a third average doping concentration lower than the second average doping concentration.

15. In the 10th paragraph, the electrode part, An auxiliary electrode electrically contacting the first semiconductor layer on the first semiconductor layer; and A lighting inspection system further comprising a bonding electrode electrically connected to the auxiliary electrode on the auxiliary electrode.

16. In paragraph 15, A lighting inspection system, wherein the auxiliary electrode comprises a light-transmitting material.

17. In paragraph 15, A lighting inspection system wherein the planar surface area of ​​the above bonding electrode is smaller than the planar surface area of ​​the first semiconductor layer.

18. In the 15th paragraph, the electrode part, A lighting inspection system further comprising a reflective electrode disposed between the auxiliary electrode and the bonding electrode.

19. In paragraph 18, A lighting inspection system wherein the planar surface area of ​​the above reflective electrode is smaller than the planar surface area of ​​the first semiconductor layer.

20. Growth substrate; A plurality of light-emitting elements including a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on the growth substrate, the plurality of light-emitting elements being spaced apart from each other; A probe card disposed on the plurality of light-emitting elements and moving in a direction toward the plurality of light-emitting elements so as to make electrical contact with the electrode portion; A conductive plate disposed under the growth substrate and moving in a direction toward the growth substrate; and It includes an optical inspection unit placed on the conductive plate, A lighting inspection system, wherein the conductive plate comprises a light-transmitting material.

21. A processor providing input image data; and Includes a display device that displays an image based on the above input image data, The display device includes a plurality of light-emitting elements, An electronic device in which the plurality of light-emitting elements are manufactured by performing the lighting inspection method of claim 1.

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