Circuit board, and semiconductor package including same

Abstract

An embodiment of the present invention provides a circuit board including: a first insulating layer; a second insulating layer disposed on the first insulating layer; a dielectric layer disposed between the first insulating layer and the second insulating layer; and a first via electrode passing through the first insulating layer and the dielectric layer, wherein: the dielectric layer includes a first through-hole; the first via electrode is provided inside the first through-hole of the dielectric layer; a side surface of the first via electrode has a first inclination angle having a width becoming narrower toward an upper surface of the first insulating layer; a first inner side surface forming the first through-hole of the dielectric layer has an inclined surface having a second inclination angle becoming narrower toward the upper surface of the first insulating layer; the first inclination angle and the second inclination angle are different from each other; and a side surface of the first via electrode and the first inner side surface overlap each other along a horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantities. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of the circuit board, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, to eliminate power transmission noise and droop phenomenon, it is required to form a capacitor layer within the substrate.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which a capacitor layer is formed within a desired insulating layer to reduce an electrical connection path for the capacitor layer and suppress droop and power transmission noise.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved integration and increased input / output count through an embedded capacitor layer.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved structural reliability by preventing cracks from occurring at the interface between a heterogeneous insulating layer and a dielectric layer by arranging a via electrode having a different inclination angle from the through layer within the through layer and the through layer.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a dielectric layer disposed between the first insulating layer and the second insulating layer; and a first via electrode penetrating the first insulating layer and the dielectric layer, wherein the dielectric layer includes a first through hole, and the first via electrode is provided inside the first through hole of the dielectric layer, and a side surface of the first via electrode has a first inclination angle that narrows toward an upper surface of the first insulating layer, and a first inner surface forming the first through hole of the dielectric layer has an inclination surface having a second inclination angle that narrows toward an upper surface of the first insulating layer, and the first inclination angle and the second inclination angle are different from each other, and the side surface of the first via electrode and the first inner surface overlap along a horizontal direction.

[0012] The side surface of the first via electrode may be spaced apart from the first inner surface in the horizontal direction.

[0013] It may include a second via electrode penetrating the second insulating layer and the dielectric layer.

[0014] The first via electrode may penetrate the first through hole, and the dielectric layer may include a second through hole in which the second via electrode is disposed.

[0015] The side surface of the second via electrode may have a third inclination angle whose width increases as it approaches the upper surface of the second insulating layer.

[0016] The second inner side forming the second through hole of the dielectric layer has an inclined surface having a fourth inclined angle whose width increases as it goes from the first insulating layer toward the second insulating layer, and the fourth inclined angle and the third inclined angle are different from each other, and the side surface of the second via electrode and the second inner side can overlap along a horizontal direction.

[0017] The first via electrode, the second via electrode, the first through hole, and the second through hole may overlap in a horizontal direction.

[0018] A portion of the first insulating layer may be disposed between the first through hole and the first via electrode, and a portion of the second insulating layer may be disposed between the second through hole and the second via electrode.

[0019] A portion of the first via electrode, the dielectric layer and a portion of the second via electrode may overlap in a horizontal direction.

[0020] The width on the upper surface of the first via electrode may be smaller than the minimum width of the first through hole, and the width on the lower surface of the second via electrode may be smaller than the minimum width of the second through hole.

[0021] The length in the vertical direction of the dielectric layer may be less than the length in the vertical direction of at least one of the first via land and the second via land.

[0022] A portion of the first insulating layer may be disposed in the first through hole and may overlap a portion of the second via electrode in a horizontal direction.

[0023] The second insulating layer may be disposed in the second through hole and may overlap a portion of the first via electrode in a horizontal direction.

[0024] The length from the lower surface of the dielectric layer to the lower surface of the first insulating layer may be less than the length in the vertical direction of the first via electrode.

[0025] The length from the upper surface of the dielectric layer to the upper surface of the second insulating layer may be less than the length in the vertical direction of the second via electrode.

[0026] The length in the vertical direction of the first via electrode may be greater than the length in the vertical direction of the first via land, and the length in the vertical direction of the second via electrode may be greater than the length in the vertical direction of the second via land.

[0027] A capacitor structure may include a first via land disposed between the first insulating layer and the second insulating layer; a second via land disposed between the first via land and an upper surface of the second insulating layer; and the dielectric layer disposed between the first via land and the second via land.

[0028] A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a dielectric layer disposed between the first insulating layer and the second insulating layer; and a first via electrode penetrating the first insulating layer and the dielectric layer, wherein the dielectric layer includes a first through hole, the first via electrode is provided on an inner side of the first through hole of the dielectric layer, a side surface of the first via electrode is spaced apart from an inner side of the first through hole of the dielectric layer, and a first inner surface forming the first through hole of the dielectric layer overlaps a side surface of the first via electrode in a horizontal direction.

[0029] A second via electrode penetrating the second insulating layer and the dielectric layer is included, and the dielectric layer includes a second through hole in which the second via electrode is disposed, and a portion of the first insulating layer may be disposed between the first through hole and the first via electrode, and a portion of the second insulating layer may be disposed between the second through hole and the second via electrode.

[0030] A portion of the first insulating layer, a portion of the second insulating layer, the first through hole, and the second through hole may overlap in a horizontal direction.

[0031] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which a capacitor layer is formed within a desired insulating layer to reduce an electrical connection path for the capacitor layer and suppress droop and power transmission noise.

[0032] Additionally, the embodiment can provide a circuit board and a semiconductor package including the same with improved integration and increased input / output count through an embedded capacitor layer.

[0033] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved structural reliability by preventing cracks from occurring at the interface between a heterogeneous insulating layer and a dielectric layer by arranging a via electrode having a different inclination angle from the through layer within the through layer and the through layer.

[0034] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0035] Figure 1 is a plan view of a circuit board according to an embodiment of the present invention;

[0036] Figure 2 is a perspective view of a circuit board according to an embodiment of the present invention;

[0037] Figure 3 is a cross-sectional view of a circuit board according to the first embodiment of the present invention.

[0038] FIG. 4 is a perspective view of a dielectric layer, a first via electrode, and a second via electrode in a circuit board according to a first embodiment of the present invention.

[0039] Figure 5 is an enlarged view of K1 in Figure 3,

[0040] Figure 6 is an enlarged view of K2 in Figure 3,

[0041] Figure 7 is an enlarged view of K3 in Figure 3,

[0042] Fig. 8 is a preview of Fig. 5,

[0043] Fig. 9 is another example of Fig. 5,

[0044] FIGS. 10A to 10X are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0045] Fig. 11 is a cross-sectional view of a circuit board according to the second embodiment,

[0046] Figure 12 is an enlarged view of K4 in Figure 11,

[0047] Figures 13a to 13j are drawings explaining a method for manufacturing a circuit board according to the second embodiment.

[0048] Fig. 14 is a cross-sectional view of a circuit board according to the third embodiment;

[0049] Figure 15 is an enlarged view of K5 of Figure 14,

[0050] Figure 16 is an enlarged view of K6 of Figure 14,

[0051] Figure 17 is a cross-sectional view of a circuit board according to a modified example.

[0052] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0053] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0054] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0055] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0056] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0057] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0058] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0059] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0060] The circuit board may include a plurality of laminated insulating layers, circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the circuit patterns arranged within each of the insulating layers.

[0061] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of the above. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0062] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and can be placed between the semiconductor elements and the circuit board. For example, the connecting member can be embedded in the circuit board, or can be placed on the circuit board. When embedded in the circuit board, it can have the advantage of reducing the thickness of the semiconductor package. The connecting member can be formed of silicon, but is not limited thereto, and can be formed of an organic material, and since it functions to electrically interconnect a plurality of semiconductor elements, it can be referred to as a bridge.

[0063] Additionally, the connecting member may be placed on a circuit board. When placed on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a redistribution layer may be placed between the molding member and the semiconductor element.

[0064] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0065] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0066] Hereinafter, a circuit board according to an embodiment of the present invention may include a first build-up layer and a second build-up layer disposed on the first build-up layer. In addition, the first build-up layer and the second build-up layer may each include a plurality of laminated insulating layers. That is, the circuit board may be formed of insulating layers of the first build-up layer and the second build-up layer (or the first build-up layer and / or the second build-up layer). In addition, the upper build-up layer and the lower build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole may increase (increase) toward the upper side of the upper build-up layer. In addition, the width or area of ​​the via hole may decrease (increase) toward the upper side of the lower build-up layer. In addition, each build-up layer may correspond to an insulating layer other than the core layer. The first and second insulating layers described below may correspond to the first and second build-up layers. Furthermore, the build-up layer may be a different layer from the protective layer. A detailed description thereof will be provided below.

[0067] FIG. 1 is a plan view of a circuit board according to an embodiment of the present invention, FIG. 2 is a perspective view of a circuit board according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0068] Referring to FIGS. 1 to 3, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board (100) may include a protective layer (SR) disposed on the electrode portion (120). In addition, a semiconductor chip connected to a via electrode may be further disposed on the upper portion of the circuit board (100).

[0069] First, the insulating layer (110) may include multiple insulating layers. As an example, the insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113).

[0070] The second insulating layer (112) may be positioned on top of the first insulating layer (111). The lower surface (BS2) of the second insulating layer (112) may be in contact with the upper surface (US1) of the first insulating layer (111), and may form the same surface.

[0071] The third insulating layer (113) may be positioned on top of the first insulating layer (111). The upper surface of the third insulating layer (113) may be in contact with the lower surface (BS1) of the first insulating layer (111), and may form the same surface.

[0072] For example, the third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) can be sequentially arranged along the stacking direction or the vertical direction (X-axis direction).

[0073] Each build-up layer includes an insulating layer. For example, if a core layer exists in a circuit board, an upper build-up layer may be positioned above the core layer, and a lower build-up layer may be positioned below the core layer. In this case, the upper build-up layer and the lower build-up layer each include multiple insulating layers.

[0074] In addition, as described above, the build-up layer is a different layer from the above-described protective layer (SR), and the uppermost / lowest surface of the build-up layer (or insulating layer) corresponds to the uppermost / lowest surface of the build-up layer (insulating layer) placed on the top, and does not mean the uppermost / lowest surface of the protective layer (SR). In other words, the uppermost surface of the insulating layer of the circuit board means the uppermost / lowest surface of the build-up layer, not the protective layer.

[0075] And the insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0076] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0077] Each insulating layer may be made of the same or different materials. For example, the first to third insulating layers may be made of the same or different materials.

[0078] And the electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0079] In an embodiment, the electrode portion (120) may include a wiring electrode and a via electrode. The embryonic electrode may include a wiring (or circuit pattern, pattern) and a pad arranged in an insulating layer. The via electrode may be located within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0080] In addition, the pads arranged on the outside of the electrode portion (120) can be bonded to semiconductor elements, substrates, boards, etc. with solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern in order to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. In addition, the pads arranged on the inside function to connect the via electrodes and the circuit pattern. When the via electrodes are arranged with a width wider than the circuit pattern, pads having a width wider than the circuit pattern are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad directly in contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad directly in contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, but should also be understood as a concave or convex surface that may appear depending on various processes.

[0081] As an example, the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123). The electrode portion may include a wiring portion and a via electrode.

[0082] The first electrode portion (121) may include a first via electrode (121a), a first wiring portion (121b), and a first connection via electrode (121c). In addition, the second electrode portion (122) may include a second via electrode (122a), a second wiring portion (122b), and a second connection via electrode (122c). In addition, the third electrode portion (123) may include a third via electrode (123a) and a third wiring portion (123b).

[0083] The first electrode portion (121) may be positioned in the first insulating layer (111). In addition, the first via electrode (121a), the first wiring portion (121b), and the first connection via electrode (121c) may be positioned in the first insulating layer (111). The first via electrode (121a) may penetrate the first insulating layer (111). The first via electrode (121a) may be positioned between the second layer (L2) and the first wiring portion (121b). The first via electrode (121a) may be in contact with the second layer (L2) and the first wiring portion (121b). The first via electrode (121a) may electrically connect the second layer (L2) and the first wiring portion (121b). The first connecting via electrode (121c) can penetrate at least a portion of the first insulating layer (111). The first via electrode (121a) can be in contact with the second layer (L2) and the first wiring portion (121b). Accordingly, the first via electrode (121a) can be electrically connected to the second layer (L2) and the first wiring portion (121b).

[0084] The second electrode portion (122) includes a second via electrode (122a) and may be positioned on the dielectric layer (DLL). The second via electrode (122a) may penetrate the dielectric layer (DLL) and the second insulating layer (112). The second via electrode (122a) may be disposed between the first layer (L1) and the second wiring portion (122b). The second via electrode (122a) may be in contact with the first layer (L1) and the second wiring portion (122b). The second via electrode (122a) may electrically connect the first layer (L1) and the second wiring portion (122b). The second connection via electrode (122c) of the second electrode portion (122) may penetrate at least a portion of the second insulating layer (112). The second connection via electrode (122c) can be in contact with the second layer (L2) and the second wiring portion (122b) between the second layer (L2) and the second wiring portion (122b). The second connection via electrode (122c) can electrically connect the second layer (L2) and the second wiring portion (122b).

[0085] The third electrode portion (123) may be located on the third insulating layer (113). The third via electrode (123a) may be located between the first wiring portion (121b) and the third wiring portion (123b) and may electrically connect them.

[0086] In an embodiment, the first via electrode (121a) may penetrate a dielectric layer (DLL) and an insulating layer (e.g., a first insulating layer) in contact with the dielectric layer (DLL). For example, the first via electrode (121a) may penetrate the dielectric layer (DLL) and the first insulating layer (111). The dielectric layer (DLL) may include a first through hole (TH1). And, the first via electrode (121a) may be positioned inside the first through hole (TH1). For example, the first via electrode (121a) may be accommodated in the first through hole (TH1) and may penetrate the first through hole (TH1). For example, the first via electrode (121a) may penetrate the first insulating layer (111) within the first through hole (TH1).

[0087] And the second via electrode (122a) can penetrate the dielectric layer (DLL) and the insulating layer (e.g., the second insulating layer) in contact with the dielectric layer (DLL). For example, the second via electrode (122a) can penetrate the dielectric layer (DLL) and the second insulating layer (112). The dielectric layer (DLL) can include a second through hole (TH2). And the second via electrode (122a) can be positioned inside the second through hole (TH2). For example, the second via electrode (122a) can be accommodated in the second through hole (TH2) and penetrate the second through hole (TH2). For example, the second via electrode (122a) can penetrate the second insulating layer (112) within the second through hole (TH2).

[0088] Here, the dielectric layer (DLL) may be positioned between the first insulating layer (111) and the second insulating layer (112). For example, the dielectric layer (DLL) may be positioned between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112).

[0089] Additionally, the first via electrode (121a) may be positioned between the upper surface of the dielectric layer (DLL) and the lower surface (BS1) of the first insulating layer (111). And the first via electrode (121a) may penetrate the upper surface (US1) and the lower surface (BS1) of the first insulating layer (111).

[0090] Additionally, the second via electrode (122a) may be positioned between the lower surface of the dielectric layer (DLL) and the upper surface (US2) of the second insulating layer (112). And the second via electrode (122a) may penetrate the upper surface (US2) and the lower surface (BS2) of the second insulating layer (112).

[0091] The third via electrode (123a) may be placed between the lower surface of the third insulating layer (113) and the lower surface (BS1) of the first insulating layer (111). And the third via electrode (123a) may penetrate at least a portion of the third insulating layer (113).

[0092] Additionally, in this specification, the via electrode may be located within a via hole formed in each insulating layer, etc. This corresponds to the via electrode penetrating at least a portion of each insulating layer, etc. This is described as a reference in this specification.

[0093] The capacitor layer (CAL) may be located above, below, or within the insulating layer (110). For example, as described above, the capacitor layer (CAL) may be located between the first insulating layer (111) and the second insulating layer (112).

[0094] A capacitor layer (CAL) according to an embodiment may include a first layer (L1), a dielectric layer (DLL), and a second layer (L2). In the capacitor layer (CAL), the first layer (L1), the dielectric layer (DLL), and the second layer (L2) may be sequentially laminated or positioned along the vertical direction (X-axis direction). Accordingly, the dielectric layer (DLL) may be positioned between the first layer (L1) and the second layer (L2). A capacitance may be formed by the dielectric layer (DLL) between the first layer (L1) and the second layer (L2). The first layer (L1) may be positioned between the first insulating layer (111) and the second insulating layer (112). For example, the first layer (L1) may be positioned within the second insulating layer (112). The first layer (L1) may be positioned between the first insulating layer (111) and the second insulating layer (112). The second layer (L2) may be positioned on the dielectric layer (DLL). The second layer (L2) may be positioned between the first layer (L1) and the upper surface of the second insulating layer (112). Accordingly, the dielectric layer (DLL) may be positioned between the first layer (L1) and the second layer (L2).

[0095] The first and second layers (L1, L2) can be directly connected to the via electrode. Through the first and second layers (L1, L2), functions such as securing the positional alignment of the via electrode and the function of a circuit electrically connected to the via electrode can be implemented. In addition, the first and second layers here can serve as electrodes of a capacitor. In addition, the first and second layers can serve as wiring sections on the upper and lower surfaces of the dielectric layer (DLL).

[0096] The second layer (L2) may be positioned on the upper surface (US1) of the first insulating layer (111). Furthermore, the second layer (L2) may be positioned between the second protective layer and the first layer (or dielectric layer).

[0097] Additionally, at least a portion of the capacitor layer (CAL) may be embedded in the first insulating layer (111) or the second insulating layer (112).

[0098] In addition, in the present embodiment, the capacitor layer (CAL) may be a layer or structure that is continuously or connected on the second insulating layer (112). However, the present invention is not limited thereto, and the dielectric layer (DLL) of the capacitor layer (CAL) may be discontinuously disposed between the first insulating layer (111) and the second insulating layer (112). For example, the capacitor layer may be discontinuously disposed, multiple capacitor layers may be spaced apart from each other, or may be disposed within a portion of the insulating layer.

[0099] Furthermore, the first layer and the second layer may correspond to the first via land and the second via land described later. The first layer may be interchangeably referred to as 'first via land', 'first via land layer', 'first electrode layer', 'first electrode', etc. The second layer may be interchangeably referred to as 'second via land', 'second via land layer', 'second electrode layer', 'second electrode', etc. In addition, the capacitor layer may correspond to 'capacitor', 'capacitor structure', 'capacitor region', etc.

[0100] In addition, the first layer and the second layer refer to one electrode (layer) and the other electrode (layer) of the capacitor layer that perform the function of a capacitor. Furthermore, although the via electrode connected to each of the first layer and the second layer of the capacitor is illustrated as a single electrode, it may be connected singly or in multiples depending on the circuit connection (e.g., series connection, parallel connection, etc.).

[0101] A circuit board according to an embodiment can suppress droop and power transmission noise by embedding a capacitor layer therein. More specifically, when a processor of an electronic device or a package board continues to draw more power, the first droop and power transmission noise can be obstacles. Specifically, the first droop can occur when a circuit within a die or semiconductor device pulls power. To improve this first droop, a capacitor can be added to a circuit board on which a die or semiconductor device is provided, as in the embodiment. In particular, it may be desirable to add the capacitor near the die or semiconductor device, which is the source of the droop. In this case, when the capacitor is placed on the die side or the side land of the board, the electrical path between the capacitor on the die and the land side (or the die side) becomes longer, which may reduce the additional effect of the capacitor due to added parasitic inductance, etc. Additionally, interference with the interface of the circuit board or package substrate may occur due to the capacitor on the vialand side. Thus, the above-described problems can be easily solved by the capacitor layer.

[0102] In addition, a high-k dielectric layer can be applied to form a large capacitance capacity. Furthermore, in the embodiment, the capacitor layer can have any suitable shape and dimension. For example, the capacitor layer can have a rectangular or circular shape in plan view. Furthermore, the capacitor layer can be arranged at any position within the circuit board. For example, in order to reduce the electrical path, the capacitor layer can be located in a layer adjacent to the upper die within the circuit board. That is, the capacitor layer is located in an area adjacent to the die in the insulating layer, so that electrical performance degradation can be suppressed.

[0103] The protective layer (SR) may be further disposed on the uppermost or lowermost portion of the insulating layer (110). The protective layer (SR) may include a first protective layer (SR1) and a second protective layer (SR2). The first protective layer (SR1) may be positioned below the first insulating layer (111). And the second protective layer (SR2) may be positioned above the second insulating layer (112) or below the third insulating layer (113). As a variation, the second protective layer (SR2) may be disposed on the capacitor layer (CAL) to cover the capacitor layer (CAL). Accordingly, the protective layer may be in contact with the dielectric layer by penetrating the via land as a variation. For example, the second protective layer (SR2) may penetrate the second layer (L2), which is the second via land. And the second protective layer (SR2) may be in contact with the dielectric layer (DLL). The dielectric layer (DLL) may be located within the insulating layer (110) of the circuit board (100) or on the outermost side of the insulating layer. Accordingly, when forming the protective layer (SR), a portion of the second layer (L2) may be opened to expose the outermost dielectric layer (DLL).

[0104] The protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material that has insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. Furthermore, the insulating layer or protective layer (SR) located in the outer laminated region of the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, circuit boards, etc.

[0105] Additionally, the protective layer (SR) may include a connecting groove for electrical connection with each electrode portion, chip, die, etc. For example, there may be a plurality of connecting grooves (CG1, CG2, CG3). The connecting groove (CG1) may include a first connecting groove (CG1), a second connecting groove (CG2), and a third connecting groove (CG3).

[0106] A first connection groove (CG1) may include a first connection terminal (PP1) and a second connection terminal (PP2). The first connection terminal (PP1) and the second connection terminal (PP2) may be connected to a first layer (L1) and a second layer (L2), respectively. Furthermore, a chip may be mounted in the first connection groove (CG1). Accordingly, the first connection terminal (PP1) and the second connection terminal (PP2) may be electrically connected to one terminal and the other terminal of the chip, respectively. Accordingly, since a capacitance is formed between the first layer (L1) and the second layer (L2), the chip may be electrically connected to the capacitor.

[0107] The second connection home (CG2) may include a third connection terminal (PP3) and a fourth connection terminal (PP4). The third connection terminal (PP3) and the fourth connection terminal (PP4) may perform the same functions as the first connection terminal and the second connection terminal described above.

[0108] Additionally, as described above, when a dielectric layer (DLL) is placed on the outermost side of the insulating layer or build-up layer, the electrical connection distance between the semiconductor chip and the capacitor layer can be reduced. As a result, improved electrical performance can be provided.

[0109] Additionally, as described below, even if a dielectric layer (DLL) is placed between stacked insulating layers, electrical performance can be improved by reducing the electrical connection path with the capacitor by placing the dielectric layer (DLL) adjacent to the outermost insulating layer.

[0110] Additionally, the third connection home (CG3) may be a home where various elements other than capacitor connections are placed.

[0111] The outermost surface of the protective layer may be located on the inner side of the outermost surface of the dielectric layer (DLL) or the insulating layer (111, 112, 113). However, this is not limited to the case, and the outermost surface of the protective layer may be formed as the same surface as the outermost surface of the insulating layer (111, 112, 113) or the outermost surface of the dielectric layer (DLL).

[0112] Furthermore, the first layer (L1) may be exposed on the outermost side of the circuit board (100). When the first layer (L1) is exposed on the outermost side of the circuit board (100), the first layer (L1) exposed on the outermost side may be a dummy. Alternatively, the first layer (L1) may be covered by the second insulating layer (112). Accordingly, the first layer (L1) may not be exposed on the circuit board (100).

[0113] Additionally, the first wiring portion (121b) may be exposed on the outermost side of the circuit board (100). When the first wiring portion (121b) is exposed on the outermost side of the circuit board (100), the first wiring portion (121b) exposed on the outermost side may be a dummy portion. Alternatively, the first wiring portion (121b) may be covered by the first insulating layer (111). Accordingly, the first wiring portion (121b) may not be exposed on the circuit board (100). This may be equally applied to other wiring portions.

[0114] FIG. 4 is a perspective view of a dielectric layer, a first via electrode, and a second via electrode in a circuit board according to a first embodiment of the present invention, and FIG. 5 is an enlarged view of K1 in FIG. 3.

[0115] Referring to FIGS. 4 and 5, the side surface (S1) of the first via electrode (121a) becomes narrower as it approaches the upper surface of the first insulating layer (111) and may have a first inclination angle (θ1). The first via electrode (121a) may have a width that decreases in the vertical direction. The first inclination angle (θ1) may correspond to the angle formed by the upper surface (or lower surface) of the first via electrode (121a) and the side surface (S1).

[0116] In addition, the dielectric layer (DLL) may have a first inner side surface (IS1) forming a first through hole (TH1). A first insulating layer (111) may be positioned on the first inner side surface (IS1). Accordingly, the first inner side surface (IS1) may be in contact with the first insulating layer (111). In addition, the first inner side surface (IS1) may have a second inclination angle (θ2) in which the width thereof becomes narrower toward the upper surface of the first insulating layer (111). Correspondingly, the width (or diameter) of the first through hole (TH1) may narrow (or decrease) along the vertical direction. In an embodiment, the first inclination angle (θ1) may be different from the second inclination angle (θ2). Furthermore, the side surface (S1) of the first via electrode (121a) and the first inner side surface (IS1) may overlap in the horizontal direction (Y-axis direction).

[0117] At this time, the side surface (S1) of the first via electrode (121a) may be spaced apart from the first inner side surface (IS1) in the horizontal direction (Y-axis direction). The side surface (S1) of the first via electrode (121a) may have a first separation distance (gap1) in the horizontal direction (Y-axis direction) with the first inner side surface (IS1). By this configuration, the side surface (S1) of the first via electrode (121a) may not be in contact with both the dielectric layer (DLL) and the first insulating layer (111). That is, the first via electrode (121a) may not be in contact with the boundary surface of the different dielectric layers (DLL) and the first insulating layer (111). Accordingly, the occurrence of a groove at the boundary surface of the dielectric layer (DLL) and the first insulating layer (111) may be suppressed by a process such as a desmear process. Accordingly, the bonding strength to the first via electrode (121a) is improved and the occurrence of cracks such as grooves at the boundary between the dielectric layer (DLL) and the first insulating layer (111) is suppressed, so that the reliability of the circuit board (100) can be improved.

[0118] In addition, the side surface (S2) of the second via electrode (122a) may have an increasing width (or diameter) toward the upper surface of the second insulating layer (112). For example, the width (or diameter) of the second via electrode (122a) may increase in the vertical direction. The side surface (S2) of the second via electrode (122a) may increase toward the upper surface of the second insulating layer (112) and may have a third inclination angle (θ3). The third inclination angle (θ3) may correspond to an angle formed by the lower surface (or upper surface) of the second via electrode (122a) and the side surface (S2).

[0119] In addition, the dielectric layer (DLL) may have a second inner side surface (IS2) forming a second through hole (TH2). A second insulating layer (112) may be positioned on the second inner side surface (IS2). Accordingly, the second inner side surface (IS2) may be in contact with the second insulating layer (112). In addition, the second inner side surface (IS2) may have a fourth inclination angle (θ4) whose width increases toward the upper surface of the second insulating layer (112). Accordingly, the second through hole (TH2) may have a width (or diameter) that increases (or increases) along the vertical direction. In an embodiment, the third inclination angle (θ3) may be different from the fourth inclination angle (θ4). Furthermore, the side surface (S2) of the second via electrode (122a) and the second inner side surface (IS2) may overlap in the horizontal direction (Y-axis direction).

[0120] At this time, the side surface (S2) of the second via electrode (122a) may be spaced apart from the second inner surface (IS2) in the horizontal direction (Y-axis direction). The side surface (S2) of the second via electrode (122a) may have a second separation distance (gap2) in the horizontal direction (Y-axis direction) with the second inner surface (IS2). By this configuration, the occurrence of a groove at the boundary between the dielectric layer (DLL) and the second insulating layer (112) can be suppressed. Accordingly, the reliability of the circuit board (100) can be improved.

[0121] A first via electrode (121a) may be arranged in a first through hole (TH1) of a dielectric layer (DLL), and a second via electrode (121b) may be arranged in a second through hole (TH2). Accordingly, the first via electrode (121a), the second via electrode (122a), the first through hole (TH1), and the second through hole (TH2) may overlap in a horizontal direction (Y-axis direction). Furthermore, the first through hole (TH1) and the second through hole (TH2) may overlap with a side surface (S1) of the first via electrode (121a) and a side surface (S2) of the second via electrode (122a) in a horizontal direction (Y-axis direction).

[0122] Additionally, as described above, a portion of the first insulating layer (111) may be positioned between the first through hole (TH1) and the first via electrode (121a). Specifically, a portion of the first insulating layer (111) may be positioned between the first through hole (TH1) and the side surface (S1) of the first via electrode (121a).

[0123] Additionally, a portion of the second insulating layer (112) may be positioned between the second through hole (TH2) and the second via electrode (122a). Specifically, a portion of the second insulating layer (112) may be positioned between the second through hole (TH2) and the side surface (S2) of the second via electrode (122a).

[0124] Accordingly, a part of the first via electrode (121a), a part of the dielectric layer (DLL), and a part of the second via electrode (122a) may overlap in the horizontal direction (Y-axis direction). Specifically, a part of the first insulating layer (111) may be disposed in the first through hole (TH1), and a part of the second via electrode (122a) may be disposed in the second through hole (TH2). Accordingly, a part of the first insulating layer (111) may overlap a part of the second via electrode (122a) in the horizontal direction.

[0125] Additionally, a portion of the first via electrode (121a), a portion of the dielectric layer (DLL) and a portion of the second via electrode (122a) may also overlap horizontally with the first through hole (TH1) and the second through hole (TH2).

[0126] Accordingly, the first via electrode (121a) can penetrate the first through hole (TH1) and a part of the first insulating layer (111) within the first through hole (TH1). The second via electrode (122a) can penetrate the second through hole (TH2) and a part of the second insulating layer (112) within the second through hole (TH2). The first via electrode (121a) and the second via electrode (122a) can penetrate the dielectric layer (DLL). In addition, the first via electrode (121a) can penetrate the first through hole (TH1) of the dielectric layer (DLL). And the second via electrode (122a) can penetrate the dielectric layer (DLL). In addition, the second via electrode (122a) can penetrate the second through hole (TH2) of the dielectric layer (DLL).

[0127] In response to this, the width (W1) of the first through hole (TH1) within the first through hole (TH1) may be greater than the width (W2) of the first via electrode (121a). In addition, the width (W3) of the second through hole (TH2) within the second through hole (TH2) may be greater than the width (W4) of the second via electrode (122a).

[0128] In addition, the width (or diameter) of the first via electrode (121a) may gradually increase from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112). Conversely, the width (or diameter) of the second via electrode (122a) may gradually decrease from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112). In this way, the expanding directions of the diameters of the first via electrode (121a) and the second via electrode (122a) may be opposite to each other. In other words, the increasing directions of the widths of the first via electrode (121a) and the second via electrode (122a) may be opposite to each other. In an embodiment, the width of the second via electrode (122a) may gradually decrease from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112). In contrast, the width of the first via electrode (121a) may gradually increase as it moves from the top of the second insulating layer (112) toward the bottom of the second insulating layer (112).

[0129] Additionally, the width (or diameter) of the first through hole (TH1) may increase as it moves from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112). Correspondingly, the width (or diameter) of the second through hole (TH2) may decrease as it moves from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112).

[0130] In addition, as an embodiment, the first via electrode (121a) and the second via electrode (122a) may not overlap at least partly in the vertical direction (X-axis direction). In addition, the third via electrode may not overlap with the first via electrode (121a) and the second via electrode (122a) in the horizontal direction (Y-axis direction). And the third via electrode (123a) may not overlap with the capacitor layer (CAL) in the horizontal direction (Y-axis direction).

[0131] Meanwhile, the first via electrode (121a) may overlap at least a portion of the capacitor layer (CAL) in the horizontal direction (Y-axis direction). The first via electrode (121a) may overlap the dielectric layer (DLL) and the first layer (L1) of the capacitor layer (CAL) in the horizontal direction (Y-axis direction).

[0132] In addition, the second via electrode (122a) and the first via electrode (121a) can overlap the dielectric layer (DLL) in the horizontal direction (Y-axis direction).

[0133] The outer surfaces of the first via electrode (121a) and the second via electrode (122a) that horizontally overlap with the dielectric layer (DLL) may be arranged at different angles. For example, the angle (first inclination angle) formed by the first via electrode (121a) and the upper surface of the dielectric layer (DLL) may be different from the angle (second inclination angle) formed by the via electrode (122a) and the upper surface of the dielectric layer (DLL).

[0134] In addition, a dielectric layer (DLL) may be interposed between the first layer (L1) and the second layer (L2) to form a storage capacity or capacitance. In other words, as described above, a capacitance may be formed by the dielectric layer (DLL) between the second via land (L2) and the first via land (L1). In addition, the capacitor layer (CAL) may function as a 'capacitor'. The size of such a capacitor layer or capacitor needs to be further reduced in order to meet the needs of substrates and semiconductor devices requiring increased integration.

[0135] Methods for improving the storage capacity of such capacitors include increasing the effective area of ​​the first and second layers (via lands, electrodes), reducing the thickness of the dielectric film, and using a high-k material as the dielectric film. In particular, when the high-k material is used as the dielectric film, it is possible to sufficiently reduce the leakage current that frequently occurs between the first layer, which is the lower electrode, and the second layer, which is the upper electrode, while maintaining a thin equivalent oxide thickness. In an embodiment, a high-k material may be used as the dielectric film. For example, the high-k material may include, for example, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, etc.

[0136] In addition, the circuit board according to the embodiment can solve the problems of reduced circuit board integration and input / output count due to the volume of the capacitor as described above when mounting a high-capacity capacitor. In other words, the capacitor layer according to the embodiment can increase the circuit board integration and input / output count while providing improved storage capacity.

[0137] A capacitance can be formed in a region where a first via land (L1), a dielectric layer (DLL), and a second via land (L2) overlap in a vertical direction (X-axis direction). Furthermore, a size of the capacitance can correspond to a size of a region where the first via land (L1), a dielectric layer (DLL), and a second via land (L2) overlap in a vertical direction (X-axis direction).

[0138] And the areas of the first layer (L1) and the second layer (L2) may be the same or different. For example, the area of ​​the first layer (L1) may be smaller than the area of ​​the second layer (L2). After the first layer (or the second layer) and the dielectric layer (DLL) are formed, the second layer (or the first layer) may be formed by etching. For example, the area of ​​the upper surface of the first layer (L1) may be smaller than the area of ​​the upper surface of the second layer (L2). In addition, the area of ​​the lower surface of the first layer (L1) may be smaller than the area of ​​the lower surface of the second layer (L2). In addition, the planar area of ​​the dielectric layer (DLL) may be larger than the area of ​​the first layer (L1) or the second layer (L2). Accordingly, capacitance can be formed by controlling the formation area of ​​the second layer (L2). In addition, a decrease in the size of the capacitance due to the dielectric layer can be easily prevented. Therefore, capacitance deviation and error occurrence can be suppressed depending on the difference in overlapping area.

[0139] Figure 6 is an enlarged view of K2 in Figure 3, and Figure 7 is an enlarged view of K3 in Figure 3.

[0140] Referring to FIGS. 6 and 7, the first via electrode (121a) can at least partially overlap the second connection via electrode (122c) in the vertical direction (X-axis direction).

[0141] Furthermore, the first through hole (TH1) may have a minimum width (W1a) on the upper surface of the first through hole (TH1). The second through hole (TH2) may have a minimum width (W3a) on the lower surface of the second through hole (TH2). In addition, the first via electrode (121a) may have a minimum width (W2a) on the upper surface. And the second via electrode (122a) may have a minimum width (W4a) on the lower surface.

[0142] In an embodiment, the minimum width (W2a) on the upper surface of the first via electrode (121a) may be smaller than the minimum width (W1a) of the first through hole (TH1). Accordingly, the first via electrode (121a) may be spaced apart from the inner surface of the first through hole (TH1). In addition, the minimum width (W4a) on the lower surface of the second via electrode (122a) may be smaller than the minimum width (W3a) of the second through hole (TH2). Accordingly, the second via electrode (122a) may be spaced apart from the inner surface of the second through hole (TH2). Accordingly, cracks or splitting occurring at the interface between the dielectric layer (DLL), which is a heterogeneous insulating layer, and the first insulating layer (or the second insulating layer) may be suppressed.

[0143] Furthermore, the length (H1) in the vertical direction of the first via electrode (121a) may be greater than the length (H2) from the lower surface of the dielectric layer (DLL) to the lower surface of the first insulating layer (111). In other words, the length (H2) from the lower surface of the dielectric layer (DLL) to the lower surface of the first insulating layer (111) may be less than the length (H1) in the vertical direction of the first via electrode (121a). Alternatively, the maximum length in the vertical direction of the first insulating layer (111) may be greater than the length (H2) from the lower surface of the dielectric layer (DLL) to the lower surface of the first insulating layer (111).

[0144] And the length (H3) in the vertical direction from the upper surface of the dielectric layer (DLL) to the upper surface of the second insulating layer (112) may be less than the length (H4) in the vertical direction of the second via electrode (122a). In other words, the length (H4) in the vertical direction of the second via electrode (122a) may be greater than the length (H3) from the upper surface of the dielectric layer (DLL) to the upper surface of the second insulating layer (112). Alternatively, the maximum length in the vertical direction of the second insulating layer (112) may be greater than the length (H3) from the upper surface of the dielectric layer (DLL) to the upper surface of the second insulating layer (112).

[0145] In addition, the length in the vertical direction of the dielectric layer (DLL) may be smaller than the length in the vertical direction of at least one of the first via land (L1), the second via land (L2), the first via electrode (121a), and the second via electrode (122b). For example, the length in the vertical direction (X-axis direction) of the dielectric layer (DLL) may be smaller than the length in the vertical direction of the first via land (L1) or the second via land (L2). Accordingly, even if the capacitor layer is embedded in the circuit board, a compact or thin circuit board can be provided.

[0146] Additionally, the vertical length of the first via electrode (121a) or the second via land (122a) may be greater than the vertical length of the first via land (L1) or the second via land (L2).

[0147] And, among the plurality of via electrodes in the circuit board (100), the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may have different positions in the vertical direction. Among them, the first via electrode (121a) and the second via electrode (122a) and the third via electrode (123a) may not overlap in the horizontal direction (Y-axis direction).

[0148] In addition, the first connection via electrode (121c) may partially overlap with the first via electrode (121a) in the vertical direction, but may not vertically overlap with the second via electrode (122a). And the second connection via electrode (122c) may partially overlap with the second via electrode (122a) in the vertical direction, but may not vertically overlap with the first via electrode (121a).

[0149] Furthermore, the first connection via electrode (121c) may have a length in the vertical direction that is smaller than the length in the vertical direction of the first insulating layer (111) or the length in the vertical direction of the second via electrode (122a). And the second connection via electrode (122c) may have a length in the vertical direction that is smaller than the length in the vertical direction of the second insulating layer (112) or the length in the vertical direction of the first via electrode (121a).

[0150] In an embodiment, the thickness of the first via electrode (121a), the thickness of the second via electrode (122a), and the thickness of the third via electrode (123a) may be the same as or different from each other. For example, the thickness of the first via electrode (121a) may be greater than the thickness of the second via electrode (122a). And the thickness of the third via electrode (123a) may be greater than the thickness of at least one of the first via electrode (121a) and the second via electrode (122a). For example, the thickness of the third via electrode (123a) may be greater than the thickness of the second via electrode (122a). By this configuration, at least one die (or semiconductor element) disposed on the circuit board (100) can be easily connected to the capacitor.

[0151] Even if the first via electrode (121a) and the first connection via electrode (121c) have the same minimum width (or area), the first via electrode (121a) and the first connection via electrode (121c) may have different maximum areas based on the same height. Similarly, even if the second via electrode (122a) and the second connection via electrode (122c) have the same minimum width (or area), the second via electrode (122a) and the second connection via electrode (122c) may have different maximum areas based on the same height.

[0152] And the first insulating layer (111) and the second insulating layer (112) may have a vertically longer length than the dielectric layer (DLL). For example, the vertically longer length of the first insulating layer (111) may be greater than the vertically longer length of the dielectric layer (DLL). In addition, the vertically longer length of the second insulating layer (112) may be greater than the vertically longer length of the dielectric layer (DLL).

[0153] Figure 8 is a preview of Figure 5, and Figure 9 is another example of Figure 5.

[0154] In an embodiment, the first inclination angle (θ1) may be different from the second inclination angle (θ2). And the third inclination angle (θ3) may be different from the fourth inclination angle (θ4).

[0155] Referring to Fig. 8, the first inclination angle (θ1) may be smaller than the second inclination angle (θ2). They may be different. And the third inclination angle (θ3) may be smaller than the fourth inclination angle (θ4).

[0156] Accordingly, the first separation distance (gap1) between the first inner side (IS1) of the first through hole (TH1) and the side surface (S1) of the first via electrode (121a) may decrease from the upper surface to the lower surface of the first insulating layer (111).

[0157] Additionally, the second separation distance (gap2) between the second inner side (IS2) of the second through hole (TH2) and the side surface (S2) of the second via electrode (122a) may increase from the upper surface to the lower surface of the first insulating layer (111).

[0158] Accordingly, when the first layer (L1) or the second layer (L2) is adjacent to the first via electrode (121a) or the second via electrode (122a), the capacitance reduction due to the capacitor layer can be reduced.

[0159] Referring to FIG. 9, in this example, the first inclination angle (θ1) may be greater than the second inclination angle (θ2). They may be different. And the third inclination angle (θ3) may be greater than the fourth inclination angle (θ4).

[0160] Accordingly, the first separation distance (gap1) between the first inner side (IS1) of the first through hole (TH1) and the side surface (S1) of the first via electrode (121a) may increase from the upper surface to the lower surface of the first insulating layer (111).

[0161] Additionally, the second separation distance (gap2) between the second inner side (IS2) of the second through hole (TH2) and the side surface (S2) of the second via electrode (122a) may decrease from the upper surface to the lower surface of the first insulating layer (111).

[0162] FIGS. 10A to 10X are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0163] Referring to FIG. 10A, a carrier board (310) may be prepared. The carrier board (310) may be a copper clad laminate (CCL). Accordingly, the carrier board (310) may include a carrier insulating layer (311) and a copper foil layer (312) disposed on both sides of the carrier insulating layer (311). The carrier insulating layer (311) may be made of PPG.

[0164] Additionally, an additional insulating layer (320) may be placed on both sides or one side of the carrier board (310). The structure in which each layer is placed on both sides will be described below.

[0165] In addition, a dielectric layer (DLL'), a first base layer (LL1), and a second base layer (LL2) for a capacitor layer, which will be described later, may be arranged on both sides or one side of the carrier board (310). The dielectric layer (DLL') may correspond to the 'dielectric layer' described above. The first base layer (LL1) may correspond to the 'first layer' or the 'first via land' described above. The second base layer (LL2) may correspond to the 'second layer' or the 'second via land' described above.

[0166] And a separation layer (330) for separation may be arranged on the first base layer (LL1) and the second base layer (LL2). The separation layer (330) may be a copper foil. Accordingly, the bonding force between the dielectric layer and the first base layer (LL1) and the second base layer (LL2) may be greater than the bonding force between the dielectric layer and the separation layer (330).

[0167] Referring to FIG. 10b, a carrier board (310), an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a dielectric layer (DLL'), and a first base layer (LL1) can be laminated and pressed. At this time, pressing can be performed with the outermost separation layer (330) removed. Accordingly, an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a dielectric layer (DLL'), and a first base layer (LL1) can be sequentially laminated on both sides of the carrier board (310).

[0168] Referring to FIG. 10c, a mask (350) can be formed on the first base layer (LL1). For example, the mask (350) can be a dry film. Then, exposure and development, etc. can be performed on the mask (350).

[0169] Referring to FIG. 10d, an open area (OP) may be formed in the mask (350) on the first base layer (LL1) by exposure and development of the mask (350). In other words, patterning of the dry film may be performed. The mask (350) may be positioned in an area other than a location where the first via land is formed. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure or the like. This mask formation may be applied to other mask formations in the same manner.

[0170] Referring to FIG. 10e, plating may be performed on the open area of ​​the mask (350). That is, a plating layer (EE1) may be formed corresponding to the position of the first via land. For example, various processes such as chemical plating may be applied to the plating layer.

[0171] Referring to FIG. 10f, the mask (350) can be removed. The mask (350) can be removed by various etching methods. And etching can be performed on the plating layer and the first base layer. Etching can be performed on a part or the entire area corresponding to the first via land. Etching on a part of the area can be performed using an additional mask, etc. In addition, when etching on the entire area is performed, both the plating layer and the first base layer can be etched. By etching, the plating layer and the first base layer can remain at a desired position corresponding to the mask of FIG. 10c. That is, the first via land (L1) can be formed.

[0172] Referring to FIG. 10g, etching of the dielectric layer (DLL) can be performed. Accordingly, a first through hole (TH1) can be formed in the dielectric layer (DLL).

[0173] Referring to FIG. 10h, a first insulating layer (111) can be formed. The first insulating layer (111) can be formed on the first via land and the dielectric layer. In addition, a plating layer (EE2) for the third electrode portion can be formed on the first insulating layer (111).

[0174] Referring to FIG. 10i, a first via (V1) in which a first via electrode is to be provided can be formed. The first via (V1) can be formed within the first through hole (TH1) described above. That is, the first via (V1) can penetrate the first through hole (TH1). In addition, a second via (V2) can also be formed that penetrates the first insulating layer (111) to expose the first via land (L1). The first via (V1) can penetrate the dielectric layer (DLL) and the first insulating layer (111). In addition, the first via (V1) can also penetrate a plating layer on the first insulating layer (111).

[0175] At this time, the first via (V1) and the second via (V2) can be formed by various methods. For example, via formation can be performed by a laser. For example, the first via (V1) and the second via (V2) can be formed by a carbon dioxide (CO2) laser drill.

[0176] Referring to FIG. 10j, a desmear process can be performed on the formed first via and second via. For example, since the boundary between the first insulating layer and the dielectric layer (DLL) is eliminated by the desmear process, cracks and gaps can be suppressed from occurring at the interface of the laminated insulating layers by the desmear process.

[0177] And a plating layer (EE3) may be formed on the first via and the second via. The plating layer (EE3) formed on the first via (V1) and the second via (V2) may be connected to the plating layer and the second base layer (LL2) located on the upper surface of the first insulating layer (111). At this time, the plating layer may be located on the outside of the first via electrode as a seed layer. Furthermore, the seed layer may be disposed on the outside of the above-described extension portion (the first extension portion) or may be located on the entire extension portion. That is, the above-described seed layer may be located on the outermost side of the first via electrode, and the plating layer described later may be located on the inside of the first via electrode or the inside of the seed layer. At this time, the seed layer and the plating layer may be made of different metal materials, such as the first metal and the second metal described above. Accordingly, by using a more elastic metal as the seed layer, the reliability of the brittle characteristic of the dielectric layer can be improved more effectively.

[0178] Referring to FIGS. 10k and 10l, a mask (350') may be formed on the first insulating layer (111) and the aforementioned plating layer. For example, the mask (350') may be a dry film. Then, exposure and development, etc. may be performed on the mask (350') to form an open area. In other words, patterning may be performed on the dry film. The mask (350') may be placed in an area other than a position where the first electrode portion is formed. Furthermore, a curing process of the mask may be performed after the open area (OP1) is formed by exposure, etc.

[0179] Referring to FIG. 10m, plating may be performed on the open area (OP1) of the mask (350'). That is, a plating layer (EE4) may be formed corresponding to the position of the first electrode portion. For example, various processes such as chemical plating may be applied to the plating layer (EE4).

[0180] Referring to FIG. 10n, the mask (350') can be removed.

[0181] And referring to FIG. 10o, etching can be performed on the plating layer. Accordingly, the connected plating layers (EE3, EE4) formed on the first insulating layer (111) can be electrically separated corresponding to the position of the first electrode portion (121). Accordingly, the first via electrode (121a), the first wiring portion (121b), and the first connection via electrode (121c) of the first electrode portion (121) can be formed.

[0182] Referring to FIG. 10p, a third insulating layer (113) may be formed on the first electrode portion (121). In addition, a plating layer (EE5) may be formed on the third insulating layer (113). Here, the third electrode portion may be formed on the third insulating layer (113) like the first electrode portion. However, as described below, the third electrode portion may be formed simultaneously with the formation of the second electrode portion on the second insulating layer. The following description will be based on this.

[0183] Referring to FIG. 10q, the second base layer (LL2) and the layer above the second base layer (LL2) can be separated from the aforementioned carrier board and additional insulating layer.

[0184] Referring to FIG. 10r, a plating layer can be formed on the second base layer (LL2). A mask (350") can be formed on the plating layer formed on the second base layer (LL2). In addition, a mask (350") can also be formed under the third via and the third insulating layer (113). For example, the mask (350") can be a dry film. And an open area can be formed by performing exposure and development on the mask (350"). In other words, patterning can be performed on the dry film. The mask (350") can be placed in an area other than a position where the second electrode portion is formed. Furthermore, a curing process of the mask can be performed after the open area is formed by exposure and development.

[0185] Referring to FIG. 10s, a plating layer can be performed on the open area of ​​the aforementioned mask (350''). Accordingly, a plating layer can be formed. And the mask (350'') can be removed. The mask (350) can be removed by various etching methods. And etching can be performed on the plating layer and the second base layer. Etching can be performed on a part or the entire area corresponding to the second via land. Etching on a part of the area can be performed using an additional mask, etc. In addition, when etching is performed on the entire area, both the plating layer and the second base layer can be etched. By etching, the plating layer and the first base layer can remain at a desired position corresponding to the mask. That is, the second via land (L2) can be formed.

[0186] Referring to FIG. 10t, etching of the dielectric layer (DLL) can be performed. Accordingly, a second through hole (TH2) can be formed in the dielectric layer (DLL).

[0187] Referring to FIG. 10u, a second insulating layer (112) may be formed on a dielectric layer (DLL). The second insulating layer (112) may be formed on the second via land and the dielectric layer. In addition, a portion of the second insulating layer (112) may be positioned within the second through hole (TH2).

[0188] Referring to FIG. 10v, a third via (V3) in which a second via electrode is to be provided can be formed. The third via (V3) can be formed within the second through hole (TH2) described above. That is, the third via (V3) can penetrate the second through hole (TH2). In addition, a fourth via (V4) that penetrates the second insulating layer (112) to expose the second via land can also be formed. The third via (V3) can penetrate the dielectric layer (DLL) and the second insulating layer (112). In addition, the third and fourth vias can also penetrate the plating layer on the second insulating layer (112).

[0189] At this time, the third via (V3) and the fourth via (V4) can be formed by various methods. For example, via formation can be performed by a laser.

[0190] Furthermore, a via corresponding to the third via electrode of the third electrode section can also be formed.

[0191] And the above-described desmear and other methods can be applied to the third via (V3) and the fourth via (V4).

[0192] Referring to FIG. 10w, similarly to the formation of the first via and the second via described above, a plating layer may be formed on the third via (V3) and the fourth via (V4). The plating layer formed on the third via (V3) and the fourth via (V4) may be connected to the plating layer located on the upper surface of the second insulating layer and the first via land (or the second via land). Then, a mask may be formed on the second insulating layer (112) and the plating layer described above. For example, the mask may be a dry film. Then, exposure and development, etc. may be performed on the mask to form an open area. In other words, patterning may be performed on the dry film. The mask may be placed in an area other than a position where the second electrode portion is formed. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure, etc. And plating may be performed on the open area of ​​the mask. That is, the plating layer may be formed corresponding to the position of the second electrode portion. For example, various processes such as chemical plating may be applied to the plating layer. Next, the mask can be removed. In addition, the third electrode portion (123) can also be formed through the plating process described above.

[0193] Referring to FIG. 10x, a protective layer (SR) can be formed on the second electrode portion and the third electrode portion. Furthermore, an opening area can be formed in the protective layer (SR) for electrical connection with a chip or substrate, etc.

[0194] Fig. 11 is a cross-sectional view of a circuit board according to the second embodiment, and Fig. 12 is an enlarged view of K4 in Fig. 11.

[0195] Referring to FIGS. 11 and 12, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board (100A) may also include a protective layer (SR) disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0196] In this embodiment, the insulating layer (110) in the circuit board (100A) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). And the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123).

[0197] At this time, the second electrode portion (122) may not have a second via electrode (122a).

[0198] That is, only the first through hole (TH1) exists based on the dielectric layer (DLL), and the second through hole (TH2) described above may not exist.

[0199] Accordingly, the second electrode portion (122) may include a second wiring portion and a second connection via electrode. Accordingly, the first via electrode (121a) may overlap with the dielectric layer (DLL) (the first through hole (TH1) and a portion of the first insulating layer (111) in the horizontal direction. And the first via electrode (121a) may not overlap with the second insulating layer (112) in the horizontal direction. Furthermore, a portion of the first insulating layer (111) may not overlap with the second insulating layer (112) in the horizontal direction.

[0200] Additionally, the number of lower and upper insulating layers based on the dielectric layer (DLL) on the circuit board may be different or the same.

[0201] For example, the number of insulating layers below the dielectric layer (DLL) may be 2n (where n is a natural number). In addition, the number of insulating layers above the dielectric layer (DLL) may be 2m-1 (where m is a natural number). That is, the upper and lower insulating layers based on the dielectric layer (DLL) may be composed of different numbers, and if one of the upper and lower insulating layers is composed of an even number of insulating layers, the other may be composed of an odd number of insulating layers.

[0202] In addition, the number of insulating layers below the dielectric layer (DLL) may be 2n (n is a natural number). In addition, the number of insulating layers above the dielectric layer (DLL) may be 2m (m is a natural number). That is, the upper and lower insulating layers based on the dielectric layer (DLL) may be formed with the same or different numbers, and if one of the upper and lower insulating layers is formed with an even (odd) number of insulating layers, the other may be formed with an even (odd) number of insulating layers. Accordingly, the number of insulating layers above and below the dielectric layer (DLL) can be easily set to a desired number based on the dielectric layer (DLL).

[0203] Figures 13a to 13j are drawings explaining a method for manufacturing a circuit board according to a second embodiment.

[0204] The manufacturing method according to the present embodiment can be applied to the manufacturing method described above, except for the contents described below.

[0205] Referring to FIG. 13A, a carrier board (310) may be provided. The carrier board (310) may be a copper clad laminate (CCL). Accordingly, the carrier board may include a carrier insulating layer and a copper foil layer disposed on both sides of the carrier insulating layer. The carrier insulating layer may be made of PPG. The carrier board may be omitted in the drawing.

[0206] Additionally, an additional insulating layer may be placed on both sides or one side of the carrier board (310). The structure in which each layer is placed on both sides will be described below.

[0207] In addition, a dielectric layer (DLL'), a first base layer (LL1), and a second base layer (LL2) for a capacitor layer, which will be described later, may be arranged on both sides or one side of the carrier board (310). The dielectric layer (DLL') may correspond to the 'dielectric layer' described above. The first base layer (LL1) may correspond to the 'first layer' or the 'first via land' described above. The second base layer (LL2) may correspond to the 'second layer' or the 'second via land' described above.

[0208] And a separation layer for separation may be arranged on the first base layer (LL1) and the second base layer (LL2). The separation layer may be a copper foil. Accordingly, the bonding force between the first base layer (LL1) and the second base layer (LL2) and the dielectric layer may be greater than the bonding force between the first base layer (LL1) and the second base layer (LL2) and the separation layer.

[0209] A carrier board, an additional insulating layer, a separation layer, a second base layer (LL2), a dielectric layer (DLL'), and a first base layer (LL1) can be laminated and pressed. At this time, the pressing can be performed with the outermost separation layer removed. Accordingly, an additional insulating layer, a separation layer, a second base layer (LL2), a dielectric layer (DLL'), and a first base layer (LL1) can be sequentially laminated on both sides of the carrier board.

[0210] Referring to FIG. 13B, a mask may be formed on the first base layer (LL1). For example, the mask may be a dry film. Exposure and development, etc. may be performed on the mask. By exposing and developing the mask, an open area may be formed in the mask on the first base layer. In other words, patterning may be performed on the dry film. The mask may be placed in an area other than a location where the first via land is formed. Furthermore, a curing process may be performed on the mask after the formation of the open area by exposure, etc. This mask formation may be applied to the formation of other masks in the same manner. Plating may be performed on the open area of ​​the mask. That is, a plating layer may be formed corresponding to the location of the first via land. For example, various processes such as chemical plating may be applied to the plating layer. Next, the mask may be removed. The mask may be removed by various etching methods. Etching may be performed on the plating layer and the first base layer. Etching may be performed on a portion or the entire area corresponding to the first via land. Etching of some areas may be performed using an additional mask, etc. Additionally, when etching is performed on the entire area, both the plating layer and the first base layer (LL1) may be etched. By etching, the plating layer and the first base layer may remain at a desired location corresponding to the mask. In other words, a first via land (L1) may be formed.

[0211] Referring to FIG. 13c, etching of the dielectric layer (DLL) can be performed. Accordingly, a first through hole (TH1) can be formed in the dielectric layer (DLL).

[0212] Referring to FIG. 13d, a first insulating layer (111) can be formed. The first insulating layer (111) can be formed on the first via land and the dielectric layer. In addition, a plating layer for the third electrode portion can be formed on the first insulating layer (111).

[0213] Referring to FIG. 13e, a first via (V1) in which a first via electrode is to be provided can be formed. The first via (V1) can be formed within the first through hole (TH1) described above. That is, the first via can penetrate the first through hole (TH1). In addition, a second via can also be formed that penetrates the first insulating layer (111) to expose the first via land. The first via (V1) can penetrate the dielectric layer (DLL) and the first insulating layer (111). In addition, the first via can also penetrate a plating layer on the first insulating layer (111).

[0214] At this time, the first via (V1) and the second via can be formed by various methods. For example, via formation can be performed by a laser. For example, the first via and the second via can be formed by a carbon dioxide (CO2) laser drill.

[0215] Referring to FIG. 13F, a mask can be formed on the first insulating layer (111) and the plating layer. Similarly, exposure and development, etc. can be performed on the mask to form an open area. In other words, patterning can be performed on the dry film. The mask can be placed in an area other than a position where the first electrode portion is formed. Furthermore, a curing process of the mask can be performed after the open area is formed by exposure, etc. Then, plating can be performed on the open area of ​​the mask. That is, a plating layer can be formed corresponding to the position of the first electrode portion. For example, various processes such as chemical plating can be applied to the plating layer. Next, the mask can be removed, and etching can be performed on the plating layer. Accordingly, the connected plating layer formed on the first insulating layer (111) can be electrically isolated corresponding to the position of the first electrode portion. Accordingly, the first via electrode (121a), the first wiring portion (121b), and the first connection via electrode of the first electrode portion can be formed.

[0216] Referring to FIG. 13g, a third insulating layer (113) can be formed on the first electrode portion. Additionally, a plating layer (EE6) can be formed on the third insulating layer (113). As described above, the third electrode portion can be formed simultaneously with the formation of the second electrode portion in the second insulating layer.

[0217] Referring to FIG. 13h, the second base layer (LL2) and the layer above the second base layer (LL2) can be separated from the carrier board and the additional insulating layer.

[0218] Referring to FIG. 13i, a second via land (L2) can be formed by performing exposure, development, and peeling on a mask. A via corresponding to a third via electrode can be formed on the third insulating layer (113). The via described above can be formed by etching or etching. In addition, a third electrode portion can be formed by forming a via and performing plating or the like. The third electrode portion can be formed by forming a mask, exposure, development and curing, peeling, and plating as described above.

[0219] Referring to FIG. 13j, a protective layer (SR) can be formed on the second electrode portion and the third electrode portion. Furthermore, an opening area can be formed in the protective layer (SR) for electrical connection with a chip or substrate, etc.

[0220] Fig. 14 is a cross-sectional view of a circuit board according to the third embodiment, Fig. 15 is an enlarged view of K5 of Fig. 14, and Fig. 16 is an enlarged view of K6 of Fig. 14.

[0221] A circuit board (100B) according to the third embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board (100A) may also include a protective layer (SR) disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0222] According to the present embodiment, as described above, the first via electrode (121a) can penetrate the dielectric layer (DLL) and the insulating layer (e.g., the first insulating layer) in contact with the dielectric layer (DLL). In addition, the first via electrode (121a) can penetrate the first additional insulating layer (111') arranged within the through hole of the first insulating layer. For example, the first additional insulating layer (111') can be penetrated by the first via electrode (121a). And, the first additional insulating layer (111') can penetrate the first insulating layer (111). Accordingly, the first additional insulating layer (111') and the first insulating layer (111) can be sequentially arranged toward the outside based on the center of the first via electrode (121a).

[0223] Furthermore, the dielectric layer (DLL) may include a first through hole (TH1). And a first via electrode (121a) may be positioned inside the first through hole (TH1). In addition, a first additional insulating layer (111') may also be positioned inside the first through hole (TH1). In addition, a first insulating layer (111) may also be disposed inside the first through hole (TH1). For example, the first via electrode (121a), the first additional insulating layer (111'), and the first insulating layer (111) may be accommodated in the first through hole (TH1) and may be sequentially positioned toward the outside with respect to the center. That is, the first via electrode (121a), the first additional insulating layer (111'), and the first insulating layer (111) may overlap with the first through hole (TH1) or the dielectric layer (DLL) in the horizontal direction. In addition, as another example, the first insulating layer (111) may be arranged parallel to the inclined surface of the dielectric layer (DLL). Accordingly, the first via electrode (121a), the first additional insulating layer (111'), and the first insulating layer (111) may be sequentially positioned in the outer direction of the first via electrode (121a).

[0224] However, a first additional insulating layer (111') and a first via electrode (121a) may be positioned in the first through hole (TH1) penetrating the dielectric layer (DLL). Accordingly, the first insulating layer (111) may not overlap the dielectric layer (DLL) in the horizontal direction.

[0225] By means of this first additional insulating layer (111'), the occurrence of cracks such as grooves at the boundary between the dielectric layer (DLL) and the first insulating layer (111) is suppressed, and as a result, the reliability of the circuit board can be improved.

[0226] In addition, an additional insulating layer (second additional insulating layer) may be positioned on the second via electrode (122a) and the second insulating layer (112). First, the second via electrode (122a) may penetrate the dielectric layer (DLL) and the insulating layer (e.g., the first insulating layer) in contact with the dielectric layer (DLL). In addition, the second via electrode (122a) may penetrate the second additional insulating layer (112') positioned within the through hole of the first insulating layer. For example, the second additional insulating layer (112') may be penetrated by the second via electrode (122a). And the second additional insulating layer (112') may penetrate the second insulating layer (112). Accordingly, the second additional insulating layer (112') and the second insulating layer (112) may be sequentially positioned outward with respect to the center of the second via electrode (122a).

[0227] Furthermore, the dielectric layer (DLL) may include a second through hole (TH2). And a second via electrode (122a) may be positioned inside the second through hole (TH2). In addition, a second additional insulating layer (112') may also be positioned inside the second through hole (TH2). In addition, a second insulating layer (112) may also be disposed inside the second through hole (TH2). For example, the second via electrode (122a), the second additional insulating layer (112'), and the second insulating layer (112) may be accommodated in the second through hole (TH2) and may be sequentially positioned toward the outside with respect to the center. That is, the second via electrode (122a), the second additional insulating layer (112'), and the second insulating layer (112) may overlap with the second through hole (TH2) or the dielectric layer (DLL) in the horizontal direction. In addition, as another example, the second insulating layer (112) may be arranged parallel to the inclined surface of the dielectric layer (DLL). Accordingly, the second via electrode (122a), the second additional insulating layer (112'), and the second insulating layer (112) may be sequentially positioned in the outer direction of the second via electrode (122a).

[0228] However, a second additional insulating layer (112') and a second via electrode (122a) may be positioned in the second through hole (TH2) penetrating the dielectric layer (DLL). Accordingly, the second insulating layer (112) may not overlap the dielectric layer (DLL) in the horizontal direction.

[0229] By this second additional insulating layer (112'), the occurrence of cracks such as grooves at the boundary between the dielectric layer (DLL) and the second insulating layer (112) is suppressed, and as a result, the reliability of the circuit board can be improved.

[0230] Figure 17 is a cross-sectional view of a circuit board according to a modified example.

[0231] Referring to FIG. 17, a circuit board according to a modified example may include an insulating layer (110), an electrode portion (120), and a capacitor layer (CAL). Furthermore, the circuit board may include a protective layer (SR) disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0232] According to this example, as described above, the first via electrode (121a) can penetrate the dielectric layer (DLL) and the insulating layer (e.g., the first insulating layer) in contact with the dielectric layer (DLL). The first via electrode (121a) may be in a form in which a portion thereof is combined with the third via electrode. That is, the first via electrode (121a) can penetrate both the first insulating layer (111) and the third insulating layer (113). Furthermore, the first via electrode (121a) can also penetrate the dielectric layer (DLL).

[0233] Specifically, the third insulating layer (113) can penetrate the first insulating layer (111). Accordingly, the first insulating layer (111) can penetrate the first through hole (TH1) of the dielectric layer (DLL). And the third insulating layer (113) can penetrate the first through hole (TH1) of the dielectric layer (DLL). The first via electrode (121a) can penetrate the third insulating layer (113). In addition, the third insulating layer (113) can be disposed within the first through hole (TH1). Accordingly, the first through hole (TH1) can overlap the first insulating layer (111) and the third insulating layer (113) in the horizontal direction. Accordingly, the third insulating layer (113) and the first insulating layer (111) can be sequentially disposed toward the outside with respect to the center of the first via electrode (121a) or the first through hole (TH1). With this configuration, a via electrode can penetrate all sequentially laminated insulating layers while still making contact with a single insulating layer. Consequently, the via electrode can be prevented from forming with the interface between the laminated insulating layers exposed. Consequently, reliability issues arising at the laminated interface can be resolved.

[0234] In addition, the via electrode can be applied equally to an additional insulating layer disposed under the third insulating layer in addition to the first insulating layer and the third insulating layer. That is, the additional insulating layer disposed under the third insulating layer can be located within the first through hole (TH1) of the dielectric layer (DLL).

[0235] Furthermore, the configuration of the dielectric layer (DLL), the first insulating layer (111), the third insulating layer (113) and the via electrode penetrating the first and third insulating layers can be equally applied to the laminated insulating layer, dielectric layer and via electrode of the circuit board.

[0236] For example, when an additional insulating layer is disposed on the second insulating layer (112), a via electrode penetrating the additional insulating layer and the second insulating layer (112) (including the dielectric layer) may be in contact with a through hole of the additional insulating layer. That is, the additional insulating layer may penetrate both the second insulating layer (112) and the dielectric layer, and in particular, may be located within the through hole of the second insulating layer (112).

[0237] In addition, the semiconductor package may include a connecting member. The connecting member may be referred to as a bridge substrate. For example, the connecting member may include a redistribution layer. The connecting member may function to horizontally electrically connect a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device must have is generally very large, the connecting member may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0238] In an embodiment, the connecting member may be an organic bridge. For example, the connecting member may comprise an organic material. For example, the connecting member may comprise an organic substrate instead of a silicon substrate. The connecting member may be embedded within the circuit board.

[0239] To this end, the circuit board may include a cavity, and a connecting member may be positioned within the cavity of the circuit board. The connecting member may horizontally connect a plurality of semiconductor elements positioned on the circuit board.

[0240] Furthermore, the circuit board according to the embodiment can be divided into a package board and an interposer corresponding to the lower board according to the function of the circuit board, and applied thereto. The package board has a function for mounting semiconductor devices and / or interposers. As the area of ​​the circuit board increases due to the increase in data, or as the number of laminated insulating layers increases, the yield of the circuit board may be greatly reduced. Therefore, in order to improve the yield of a circuit board with a high number of laminated layers, the yield of the circuit board can be improved by separating it into an interposer and a package board. In addition, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads of the package board having an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0241] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0242] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0243] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0244] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0245] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0246] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer; A dielectric layer disposed between the first insulating layer and the second insulating layer; and including a first via electrode penetrating the first insulating layer and the dielectric layer; The above dielectric layer includes a first through hole, The above first via electrode is provided on the inside of the first through hole of the dielectric layer, The side surface of the first via electrode has a first inclination angle that becomes narrower as it approaches the upper surface of the first insulating layer, The first inner surface forming the first through hole of the dielectric layer has a slope having a second slope angle whose width becomes narrower as it approaches the upper surface of the first insulating layer, The first slope angle and the second slope angle are different from each other, A circuit board in which the side surface of the first via electrode and the first inner surface overlap along a horizontal direction.

2. In paragraph 1, The side surface of the first via electrode is spaced apart from the first inner surface in the horizontal direction of the circuit board.

3. In paragraph 1, A circuit board including a second via electrode penetrating the second insulating layer and the dielectric layer.

4. In paragraph 3, The above first via electrode penetrates the above first through hole, A circuit board including a second through hole in which the second via electrode is arranged, wherein the dielectric layer is.

5. In paragraph 4, A circuit board having a third inclination angle in which the side surface of the second via electrode increases in width as it approaches the upper surface of the second insulating layer.

6. In paragraph 5, The second inner surface forming the second through hole of the dielectric layer has a slope having a fourth slope angle whose width increases as it moves from the first insulating layer toward the second insulating layer, The above fourth slope angle and the above third slope angle are different from each other, A circuit board in which the side surface of the second via electrode and the second inner surface overlap along a horizontal direction.

7. In paragraph 4, A circuit board in which the first via electrode, the second via electrode, the first through hole, and the second through hole overlap in a horizontal direction.

8. In paragraph 4, A portion of the first insulating layer is disposed between the first through hole and the first via electrode, A circuit board in which a portion of the second insulating layer is disposed between the second through hole and the second via electrode.

9. In paragraph 3, A circuit board in which a portion of the first via electrode, the dielectric layer, and a portion of the second via electrode overlap in a horizontal direction.

10. In paragraph 4, The width on the upper surface of the first via electrode is smaller than the minimum width of the first through hole, A circuit board having a width on the lower surface of the second via electrode smaller than the minimum width of the second through hole.

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