Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. In a sub-pixel of the display substrate, a connecting structure is electrically connected to a first part of a first electrode and a second part of the first electrode, and comprises a first extension portion, a second extension portion and a connecting portion, wherein a first end of the first extension portion is electrically connected to the first part of the first electrode, a first end of the second extension portion is electrically connected to the second part of the first electrode, and the connecting portion is located in a non-light-emitting region and is connected to a second end of the first extension portion and a second end of the second extension portion; and a first transfer electrode is electrically connected to a first electrode of a driving transistor, and comprises a strip-shaped portion extending from a display region to the non-light-emitting region in a first direction and a connecting pad located in the non-light-emitting region, connected to the strip-shaped portion and located at the end of the strip-shaped portion away from the display region in the first direction, wherein the connecting portion is connected to the connecting pad through a via hole in the non-light-emitting region, and the connecting pad is separately spaced apart from the first extension portion and the second extension portion in a second direction intersecting the first direction.

Description

Display substrate and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, OLED technology is increasingly being used in transparent displays. Transparent displays are a key area of ​​personalized display technology, representing the display of images in a transparent state. Viewers can see not only the image on the display device, but also the scene behind it. Transparent displays using AMOLED technology typically divide each pixel into a display area and a non-luminous area. The display area is equipped with pixel driver circuits and light-emitting devices to display images, while the non-luminous area allows light to pass through.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising a display unit including a display area and a non-luminescent area; the display area including sub-pixels, each sub-pixel including a driving transistor and a light-emitting device; the driving transistor configured to control the magnitude of a driving current flowing through the light-emitting device and including a gate, a first electrode, and a second electrode; the light-emitting device configured to receive the driving current and be driven by the driving current to emit light, and including a first electrode including a first portion and a second portion spaced apart from each other. The display unit further includes a connecting structure and a first switching electrode. The connecting structure electrically connects the first part of the first electrode and the second part of the first electrode, and includes a first extension portion, a second extension portion and a connecting portion; the first extension portion and the second extension portion extend from the display area to the non-luminous area along the first direction, respectively, the first end of the first extension portion is electrically connected to the first part of the first electrode, the first end of the second extension portion is electrically connected to the second part of the first electrode, and the connecting portion is located in the non-luminous area and connects the second end of the first extension portion and the second end of the second extension portion; the first switching electrode is electrically connected to the first pole of the driving transistor and includes a strip portion extending from the display area to the non-luminous area along the first direction, and a connection pad located in the non-luminous area, connected to the strip portion and located at one end of the strip portion away from the display area in the first direction, the connection portion is connected to the connection pad in the non-luminous area through a via, and the connection pad is spaced apart from the first extension portion and the second extension portion in a second direction intersecting the first direction.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the interval between the connecting pad and the first extension portion in the second direction is a first interval, and the interval between the connecting pad and the second extension portion in the second direction is a second interval; the length of at least one of the first interval and the second interval in the second direction is greater than or equal to the line width of the first extension portion in the second direction, or greater than or equal to the line width of the second extension portion in the second direction, or greater than or equal to the line width of the portion of the connecting portion extending along the second direction in the first direction.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display unit is provided on the base substrate; and the first transfer electrode is located on a side of the driving transistor close to the base substrate.

[0007] For example, in at least one embodiment of the present disclosure, the display substrate further comprises a base substrate, the display unit is disposed on a major surface of the base substrate, and the first transfer electrode comprises a first transfer portion and a second transfer portion. The first transfer portion is located in the display area and electrically connected to the first electrode of the driving transistor; the second transfer portion is located in the non-luminescent area and electrically connected to the first transfer portion; the second transfer portion comprises the connection pad and a portion of the strip portion located in the non-luminescent area; the display unit further comprises a second transfer electrode located in the non-luminescent area, the second transfer electrode being located between the connection portion and the second transfer portion in a direction perpendicular to the major surface of the base substrate; the connection portion and the second transfer portion are disposed in different layers, the connection portion being electrically connected to the second transfer electrode in the non-luminescent area via a first via hole, the second transfer electrode being electrically connected to the second transfer portion of the first transfer electrode via a second via hole, the first via hole and the second via hole being spaced apart in the first direction, and the second via hole being located on a side of the first via hole and the first and second sub-portions of the connection structure that is closer to the display area.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display unit further includes a flat layer, which is located between the first electrode and the second switching electrode in a direction perpendicular to the base substrate; the flat layer covers the second via hole and does not cover the first via hole.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the length of the connection pad in the second direction is less than or equal to the length of the connection pad in the first direction.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is connected to the second end of the first extension portion, the second sub-portion is connected to the second end of the second extension portion, and the first sub-portion and the second sub-portion are both located on the side of the connection pad between the first via hole and the first transfer electrode away from the display area; the distance between the first via hole and the second via hole in the first direction is greater than the line width of the first sub-portion or the second sub-portion in the first direction.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the width of the second via hole in the second direction is less than or equal to the width of the second via hole in the first direction.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate also includes a base substrate, and the display unit is arranged on the main surface of the base substrate; the connecting portion includes a first sublayer, a second sublayer and a third sublayer stacked in a direction perpendicular to the main surface of the base substrate, the second sublayer is located between the first sublayer and the third sublayer, and the third sublayer is located on the side of the second sublayer away from the base substrate; the area of ​​the orthographic projection of the third sublayer on the main surface of the base substrate is smaller than at least one of the orthographic projection of the second sublayer on the main surface of the base substrate and the orthographic projection of the first sublayer on the main surface of the base substrate, and is located within the range of at least one of the orthographic projection of the second sublayer on the main surface of the base substrate and the orthographic projection of the first sublayer on the main surface of the base substrate.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate also includes a base substrate, and the display unit is arranged on the main surface of the base substrate; the connecting portion includes a first sub-portion, a second sub-portion and a protrusion, and the first sub-portion, the second sub-portion and the protrusion are all located in the non-luminous area, the first sub-portion and the second sub-portion are respectively connected to the second end of the first extension portion and the second end of the second extension portion and extend respectively along a second direction intersecting with the first direction, the protrusion is connected to the first sub-portion and the second sub-portion, and protrudes from the first sub-portion and the second sub-portion along the first direction toward the display area; the first transfer electrode includes: a first transfer portion and a second transfer portion. The first transfer portion is located in the display area and is electrically connected to the first electrode of the driving transistor; the second transfer portion is located in the non-luminous area and has the connection pad at one end away from the display area in the first direction, wherein the connection pad is connected to the protrusion in the non-luminous area, and the direction perpendicular to the first direction is the second direction; the display unit also includes a second transfer electrode located in the non-luminous area, and the second transfer electrode is located between the protrusion and the first transfer portion in a direction perpendicular to the main surface of the base substrate; the protrusion and the second transfer portion are arranged in different layers, and the protrusion is electrically connected to the second transfer electrode in the non-luminous area via a third via hole, and the second transfer electrode is electrically connected to the connection pad of the first transfer electrode via a fourth via hole; the first sub-portion and the second sub-portion are both located on the side of the connection pad of the first transfer electrode, the third via hole and the fourth via hole away from the display area.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, the third via hole and the fourth via hole are spaced apart in the second direction, and the length of the second connecting electrode in the first direction is smaller than the length in the second direction.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display unit further includes a flat layer, which is located between the first electrode and the second switching electrode in a direction perpendicular to the base substrate; the flat layer does not cover the third via hole and the fourth via hole.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, the length of the second switching electrode in the second direction is greater than the length of the second switching electrode in the first direction.

[0017] For example, the display substrate provided in at least one embodiment of the present disclosure includes: a scanning signal line and a sensing signal line. The scanning signal line includes at least one annular outer ring portion, including a portion extending as a whole along the first direction, passing through the non-luminous area and the display area, transmitting a sensing scanning signal, and including a sensing scanning signal line, the sensing scanning signal line including an annular first outer ring portion, the at least one annular outer ring portion including the first outer ring portion; the sensing signal line transmits a sensing signal, the sub-pixel also includes a sensing transistor, the sensing scanning signal line is configured to provide the sensing scanning signal to the sensing transistor, the sensing transistor is configured to detect the electrical characteristics of the sub-pixel using the sensing signal under the control of the sensing scanning signal, the second electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the first electrode of the light-emitting element; the sub-pixel also includes an intermediate connecting portion extending along the first direction, the sensing signal line is connected to the intermediate connecting portion through a first connecting via, and the second electrode of the sensing transistor is connected to the intermediate connecting portion through a second connecting via; the intermediate connecting portion is located in the annular space inside the first outer ring portion.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the non-luminous area of ​​the display unit includes a first non-luminous area and a second non-luminous area, the first non-luminous area is located on the first side of the display area in the first direction, and the second non-luminous area is located on the second side of the display area in the first direction opposite to the first side thereof; the first outer ring portion extends from the first non-luminous area to the display area and then extends to the second non-luminous area.

[0019] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a base substrate and a longitudinal signal line, and the display unit is arranged on the main surface of the base substrate; the longitudinal signal line is arranged on the base substrate and is located in the display area, and extends as a whole along a second direction intersecting with the first direction; each of the at least one outer ring portion includes a first wire and a second wire; the first wire extends as a whole along the first direction and extends from the non-luminous area to the display area; the second wire extends as a whole along the first direction and extends from the non-luminous area to the display area, and is spaced apart from the first wire in the second direction; the first wire and the second wire both overlap with the longitudinal signal line in a direction perpendicular to the main surface of the base substrate.

[0020] For example, the display substrate provided by at least one embodiment of the present disclosure includes a first power line, which is connected to the first voltage terminal and is configured to provide a first power voltage to the sub-pixel, and includes a longitudinal portion extending as a whole along the second direction, and the longitudinal signal line includes the longitudinal portion of the first power line; the first conductor of the first outer ring portion and the second conductor of the first outer ring portion overlap with the longitudinal portion of the first power line in a direction perpendicular to the base substrate.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the scan signal line further includes: a data scan signal line and a data signal line. The data scan signal line includes a portion extending as a whole along the first direction, transmitting a data scan signal; a data signal line, transmitting a data signal; the sub-pixel further includes a data write transistor, the data scan signal line is configured to provide the data scan signal to the gate of the data write transistor, and the data write transistor is configured to transmit the data signal to the drive transistor under the control of the data scan signal; the longitudinal signal line includes the data signal line, and the first and second conductors of the first outer ring portion both overlap with the data signal line in a direction perpendicular to the base substrate.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the data scanning signal line includes a second outer ring portion in a ring shape, and the first conductive wire and the second conductive wire of the second outer ring portion both overlap with the longitudinal portion of the first power line in a direction perpendicular to the base substrate.

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a base substrate, and the display unit is arranged on the main surface of the base substrate; the intermediate connecting portion and the first part and the second part of the first electrode do not overlap in a direction perpendicular to the main surface of the base substrate.

[0024] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a second direction intersecting with the first direction, there is a first distance between the intermediate connection portion and the first conductive wire of the first outer ring portion, and there is a second distance between the intermediate connection portion and the second conductive wire of the first outer ring portion, and the first distance is greater than the second distance.

[0025] For example, in the display substrate provided in at least one embodiment of the present disclosure, the sub-pixel includes an upper sub-pixel and a lower sub-pixel arranged in the second direction, the first electrode of the upper sub-pixel overlaps with the first wire of the first outer ring portion in a direction perpendicular to the base substrate and includes a first protrusion located within the ring shape of the first outer ring portion, the first electrode of the lower sub-pixel overlaps with the second wire of the first outer ring portion in a direction perpendicular to the base substrate and includes a second protrusion located within the ring shape of the first outer ring portion, the length of the first protrusion in the second direction is greater than the length of the second protrusion in the second direction; the intermediate connecting portion is located between the first protrusion and the second protrusion and does not overlap with the first protrusion and the second protrusion in the direction perpendicular to the base substrate.

[0026] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a base substrate, and the display unit is arranged on the main surface of the base substrate; the first electrode is located on the side of the intermediate connecting portion away from the base substrate, and the intermediate connecting portion and the first switching electrode are arranged on the same layer.

[0027] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a base substrate, and the display unit is arranged on the base substrate; the active layer of the sensing transistor is located between the intermediate connection portion and the second electrode of the sensing transistor, and the second electrode of the sensing transistor is also electrically connected to the active layer of the sensing transistor through a second connection via; the active layer of the sensing transistor and the intermediate connection portion at least partially overlap in a direction perpendicular to the base substrate, and the second connection via is a through hole formed by a first depth via and a second depth via penetrating each other, and the second connection via exposes the upper surface of the active layer of the sensing transistor away from the base substrate and the side surface of the active layer of the sensing transistor intersecting with the upper surface, and exposes the intermediate connection portion; the second electrode of the sensing transistor contacts both the upper surface and the side surface of the active layer of the sensing transistor through the second connection via, and contacts the intermediate connection portion through the second connection via.

[0028] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second electrode of the sensing transistor includes an outer portion close to the non-luminous area in the first direction and an inner portion away from the non-luminous area, and the outer portion and the inner portion are connected to each other; the active layer of the sensing transistor overlaps with the inner portion of the second electrode of the sensing transistor in a direction perpendicular to the base substrate, and the second connecting via exposes the end of the upper surface of the active layer of the sensing transistor close to the non-luminous area in the first direction and the first side surface of the active layer of the sensing transistor, and the first side surface faces the non-luminous area in the first direction.

[0029] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second electrode of the sensing transistor includes an outer portion close to the non-luminous area in the first direction and an inner portion away from the non-luminous area, and the outer portion and the inner portion are connected to each other; the active layer of the sensing transistor overlaps with the outer portion of the second electrode of the sensing transistor in a direction perpendicular to the base substrate, and the second connecting via exposes the end of the upper surface of the active layer of the sensing transistor away from the non-luminous area in the first direction and the second side surface of the active layer of the sensing transistor, and the second side surface is away from the non-luminous area in the first direction.

[0030] At least one embodiment of the present disclosure provides a display substrate, which includes a display unit, the display unit including a display area and a non-luminous area, the display area including sub-pixels, the sub-pixels including a driving transistor and a light-emitting device, the driving transistor being configured to control the magnitude of a driving current flowing through the light-emitting device, and including a gate, a first electrode, and a second electrode; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode including a first portion and a second portion spaced apart from each other; the display unit also includes a sub-pixel, the sub-pixel including: a connecting structure and a first switching electrode; the connecting structure electrically connects the first portion of the first electrode and the second portion of the first electrode, and includes a first extending portion, a second extending portion, a first sub-portion, a second sub-portion, and a protrusion, the first extending portion and the second extending portion respectively extending from the first electrode in a first direction to the second electrode. The display area extends to the non-luminous area, the first end of the first extension portion is electrically connected to the first part of the first electrode, and the first end of the second extension portion is electrically connected to the second part of the first electrode; the first sub-portion, the second sub-portion and the protrusion are all located in the non-luminous area, the first sub-portion and the second sub-portion are respectively connected to the second end of the first extension portion and the second end of the second extension portion and extend respectively along a second direction intersecting with the first direction, the protrusion is connected to the first sub-portion and the second sub-portion, and protrudes from the first sub-portion and the second sub-portion toward the display area along the first direction; the first transfer electrode is electrically connected to the first pole of the driving transistor and includes a portion located in the non-luminous area, and the protrusion is connected to the portion of the first transfer electrode located in the non-luminous area via a via in the non-luminous area.

[0031] At least one embodiment of the present disclosure provides a display substrate, which includes a display unit, a scanning signal line, and a sensing signal line. The display unit includes a display area and a non-luminous area, the display area includes sub-pixels, the sub-pixels include a driving transistor and a light-emitting device, the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device, and includes a gate, a first pole, and a second pole; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the scanning signal line includes at least one annular outer ring portion, a portion extending along a first direction as a whole, passing through the non-luminous area and the display area, transmitting a sensing scanning signal, and includes a sensing scanning signal line, the sensing scanning signal line includes a portion extending along a second direction intersecting with the first direction as a whole, passing through the non-luminous area and the display area, and transmitting a sensing scanning signal, the sensing scanning signal line includes a first annular portion. An outer ring portion, wherein the at least one annular outer ring portion includes the first outer ring portion; a sensing signal line transmits a sensing signal, the sub-pixel also includes a sensing transistor, the sensing scan signal line is configured to provide the sensing scan signal to the sensing transistor, and the sensing transistor is configured to use the sensing signal to detect the electrical characteristics of the sub-pixel under the control of the sensing scan signal, the second electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the first electrode of the light-emitting element; the sub-pixel also includes an intermediate connecting portion extending along the first direction, the sensing signal line is connected to the intermediate connecting portion through a first connecting via, and the second electrode of the sensing transistor is connected to the intermediate connecting portion through a second connecting via; the intermediate connecting portion is located in the annular space inside the first outer ring portion.

[0032] At least one embodiment disclosed herein further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0034] FIG1A is a schematic overall plan view of a display substrate provided by one embodiment of the present disclosure;

[0035] FIG1B is a block diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0036] FIG2A is an equivalent circuit diagram of a pixel circuit of a display unit of a display substrate provided by an embodiment of the present disclosure;

[0037] 2B-2D are signal timing diagrams of a driving method for a pixel circuit provided by an embodiment of the present disclosure;

[0038] FIG3A is a schematic plan view of a display unit of a display substrate provided by at least one embodiment of the present disclosure;

[0039] FIG3B is a schematic diagram of the first sub-pixel in FIG3A ;

[0040] FIG3C is an enlarged view of a portion including a connection structure in FIG3B ;

[0041] FIG4A is a schematic cross-sectional view along line AA' in FIG3B;

[0042] FIG4B is a schematic cross-sectional view along line BB' and line CC' in FIG3B ;

[0043] FIG4C is a schematic cross-sectional view along line DD' in FIG3A;

[0044] FIG4D is a schematic diagram showing a cross section of a display substrate provided by another embodiment of the present disclosure taken along line DD' in FIG3A;

[0045] FIG4E is a schematic diagram showing a cross section of a display substrate provided by another embodiment of the present disclosure taken along line AA′ in FIG3B ;

[0046] FIG5A is a schematic plan view of the first conductive layer of the display unit shown in FIG3A ;

[0047] 5B is a schematic plan view of the first insulating layer of the display unit shown in FIG3A ;

[0048] FIG5C is a schematic plan view of the semiconductor layer of the display unit shown in FIG3A ;

[0049] 5D is a schematic plan view of the second conductive layer of the display unit shown in FIG3A ;

[0050] 5E is a schematic plan view of the third insulating layer of the display unit shown in FIG3A ;

[0051] FIG5F is a schematic plan view of the third conductive layer of the display unit shown in FIG3A ;

[0052] 5G is a plan view of the fourth insulating layer of the display unit shown in FIG3A ;

[0053] 5H is a schematic plan view of the fifth insulating layer of the display unit shown in FIG3A ;

[0054] FIG5I is a schematic plan view of the fourth conductive layer of the display unit shown in FIG3A ;

[0055] FIG5J is a schematic plan view of the fifth conductive layer of the display unit shown in FIG3A ;

[0056] FIG5K is a schematic plan view of the sixth conductive layer of the display unit shown in FIG3A ;

[0057] FIG5L is a schematic plan view of a pixel definition layer of the display unit shown in FIG3A ;

[0058] 6A is a schematic diagram of a first sub-pixel of a display unit of another display substrate provided by at least one embodiment of the present disclosure;

[0059] FIG6B is an enlarged view of a portion including a connection structure in FIG6A;

[0060] FIG6C is a schematic cross-sectional view along line AA′ in FIG6A ;

[0061] 7A-7L are plan views of various film layers of the display unit where the sub-pixel shown in FIG6A is located;

[0062] FIG8 is a schematic diagram of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used herein should have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0065] In this disclosure, descriptions such as "structure A and structure B form a continuous, integrated structure" mean that structure A and structure B are made of the same material, have no seams between them, and form a uniform, integrated structure, for example, formed through the same patterning process. The letters A and B are used to refer to the corresponding structures described herein.

[0066] It should be noted that in the disclosed embodiment, the longitudinal portion of the first power line and the second power line are spaced apart in the first direction and are located at a first edge of the display area in the first direction and a second edge of the display area opposite the first edge in the first direction, respectively. The area between the edge of the longitudinal portion of the first power line away from the second power line and the edge of the second power line away from the longitudinal portion of the first power line constitutes the display area. The area outside the display area constitutes a non-luminous area.

[0067] The display substrate provided by the present disclosure can be used in transparent display devices, such as large-scale transparent display devices, including, for example, display panels larger than 55 inches. Transparent display devices display images in a transparent state, allowing viewers to see not only the image displayed on the display device but also the scene behind the display device.

[0068] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as luminescence, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, and extremely high response speed. Depending on the driving method, OLEDs can be divided into two types: Passive Matrix (PM) and Active Matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to be continuously and independently driven to emit light. Transparent display devices using AMOLED technology typically divide each pixel into a display area and a non-luminous area. The display area is equipped with a pixel driving circuit and a light-emitting device 20 to display images, while the non-luminous area allows light to pass through.

[0069] During the manufacturing process of a display device circuit, a thin film transistor, or an organic light emitting diode, characteristic degradation or an internal short circuit failure of the thin film transistor may occur.

[0070] If the thin film transistor is not driven properly, a pixel or sub-pixel may become a dark spot because current or voltage is not applied to the organic light-emitting diode connected to the thin film transistor. Alternatively, if the source and drain electrodes of the driving thin film transistor are short-circuited, the driving thin film transistor cannot be driven properly, and the voltage applied to the source electrode is directly applied to the drain electrode without turning it on / off. As a result, the sub-pixel remains in the on state at all times, and a bright spot appears.

[0071] Because bright spots are easily visible to the user due to their high visibility, they degrade display quality. Consequently, even a single bright spot within the display area is considered a defect, preventing the display device from being manufactured as a final product. In particular, since dark spots or bright spots in transparent displays or large-scale top-emission displays can be visible to the user, solutions are needed to avoid or minimize them.

[0072] In a transparent display device, since sufficient non-luminous areas need to be reserved, the display area for arranging pixel driving circuits has limited space, and circuit wiring in the display area needs to be reduced as much as possible.

[0073] At least one embodiment of the present disclosure provides a display substrate, comprising a display unit including a display area and a non-luminescent area; the display area including sub-pixels, each sub-pixel including a driving transistor and a light-emitting device; the driving transistor configured to control the magnitude of a driving current flowing through the light-emitting device and including a gate, a first electrode, and a second electrode; the light-emitting device configured to receive the driving current and be driven by the driving current to emit light, and including a first electrode including a first portion and a second portion spaced apart from each other. The display unit further includes a connecting structure and a first switching electrode. The connecting structure electrically connects the first part of the first electrode and the second part of the first electrode, and includes a first extension portion, a second extension portion and a connecting portion; the first extension portion and the second extension portion extend from the display area to the non-luminous area along the first direction, respectively, the first end of the first extension portion is electrically connected to the first part of the first electrode, the first end of the second extension portion is electrically connected to the second part of the first electrode, and the connecting portion is located in the non-luminous area and connects the second end of the first extension portion and the second end of the second extension portion; the first switching electrode is electrically connected to the first pole of the driving transistor and includes a strip portion extending from the display area to the non-luminous area along the first direction, and a connection pad located in the non-luminous area, connected to the strip portion and located at one end of the strip portion away from the display area in the first direction, the connection portion is connected to the connection pad in the non-luminous area through a via, and the connection pad is spaced apart from the first extension portion and the second extension portion in a second direction intersecting the first direction.

[0074] At least one embodiment of the present disclosure provides a display substrate, which includes a display unit, the display unit including a display area and a non-luminous area, the display area including sub-pixels, the sub-pixels including a driving transistor and a light-emitting device, the driving transistor being configured to control the magnitude of a driving current flowing through the light-emitting device, and including a gate, a first electrode, and a second electrode; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode including a first portion and a second portion spaced apart from each other; the display unit also includes a sub-pixel, the sub-pixel including: a connecting structure and a first switching electrode; the connecting structure electrically connects the first portion of the first electrode and the second portion of the first electrode, and includes a first extending portion, a second extending portion, a first sub-portion, a second sub-portion, and a protrusion, the first extending portion and the second extending portion respectively extending from the first electrode in a first direction to the second electrode. The display area extends to the non-luminous area, the first end of the first extension portion is electrically connected to the first part of the first electrode, and the first end of the second extension portion is electrically connected to the second part of the first electrode; the first sub-portion, the second sub-portion and the protrusion are all located in the non-luminous area, the first sub-portion and the second sub-portion are respectively connected to the second end of the first extension portion and the second end of the second extension portion and extend respectively along a second direction intersecting with the first direction, the protrusion is connected to the first sub-portion and the second sub-portion, and protrudes from the first sub-portion and the second sub-portion toward the display area along the first direction; the first transfer electrode is electrically connected to the first pole of the driving transistor and includes a portion located in the non-luminous area, and the protrusion is connected to the portion of the first transfer electrode located in the non-luminous area via a via in the non-luminous area.

[0075] At least one embodiment of the present disclosure provides a display substrate, which includes a display unit, a scanning signal line, and a sensing signal line. The display unit includes a display area and a non-luminous area, the display area includes sub-pixels, the sub-pixels include a driving transistor and a light-emitting device, the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device, and includes a gate, a first pole, and a second pole; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the scanning signal line includes at least one annular outer ring portion, a portion extending along a first direction as a whole, passing through the non-luminous area and the display area, transmitting a sensing scanning signal, and includes a sensing scanning signal line, the sensing scanning signal line includes a portion extending along a second direction intersecting with the first direction as a whole, passing through the non-luminous area and the display area, and transmitting a sensing scanning signal, the sensing scanning signal line includes a first annular portion. An outer ring portion, wherein the at least one annular outer ring portion includes the first outer ring portion; a sensing signal line transmits a sensing signal, the sub-pixel also includes a sensing transistor, the sensing scan signal line is configured to provide the sensing scan signal to the sensing transistor, and the sensing transistor is configured to use the sensing signal to detect the electrical characteristics of the sub-pixel under the control of the sensing scan signal, the second electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the first electrode of the light-emitting element; the sub-pixel also includes an intermediate connecting portion extending along the first direction, the sensing signal line is connected to the intermediate connecting portion through a first connecting via, and the second electrode of the sensing transistor is connected to the intermediate connecting portion through a second connecting via; the intermediate connecting portion is located in the annular space inside the first outer ring portion.

[0076] At least one embodiment disclosed herein further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0077] For example, FIG1A is a schematic overall plan view of a display substrate provided by an embodiment of the present disclosure. As shown in FIG1A , the display substrate 10 includes a base substrate 1 and a display unit P disposed on the base substrate, for example, including a plurality of display units P, for example, the plurality of display units P are arranged in an array. Each display unit P includes a display area 11 and a non-luminous area 12. The display area 11 includes sub-pixels. For example, the display unit P includes a plurality of sub-pixels arranged in an array, the array including a first pixel row extending along a first direction D1 and a second pixel row extending along the first direction D1; the first pixel row includes adjacently arranged first sub-pixels P1 and second sub-pixels P2, and the second pixel row includes adjacently arranged third sub-pixels P3 and fourth sub-pixels P4. FIG1A takes the example of the display area 11 of each display unit P including a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Of course, in other embodiments, the display area 11 of each display unit P also includes more than four or less than four sub-pixels.

[0078] For example, the first subpixel P1 can be a red subpixel (R) that emits red light, the second subpixel P2 can be a green subpixel (G) that emits green light, the second subpixel P2 can be a white subpixel (W) that emits white light, and the fourth subpixel P4 can be a blue subpixel (B) that emits blue light. Of course, the emission colors of the first subpixel P1, the second subpixel P2, the second subpixel P2, and the fourth subpixel P4 are not limited to the above, and the embodiments of the present disclosure do not limit this.

[0079] In some embodiments, the shape of each sub-pixel can be rectangular, diamond, pentagonal, or hexagonal. In one exemplary embodiment, four sub-pixels can be arranged in a horizontal parallel manner to form a RWBG pixel arrangement. In other embodiments, the four sub-pixels can be arranged in a square, diamond, or vertically parallel manner, which is not limited in this disclosure.

[0080] FIG2A is a schematic diagram of an equivalent circuit of a pixel circuit of four sub-pixels of a display unit P shown in FIG1A . In conjunction with FIG1A and FIG2A , each of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 includes a pixel circuit, and the pixel circuit includes a driving transistor T1 and a light-emitting device 20; the display area 11 is a light-emitting area for displaying images; the non-light-emitting area is a non-light-emitting area that is not used for displaying images and can see through the environment on the non-display side. The driving transistor T1 is configured to control the magnitude of the driving current flowing through the light-emitting device 20, and includes a gate, a first electrode, and a second electrode. The light-emitting device 20 is configured to receive a driving current and be driven by the driving current to emit light. For example, the display substrate is an organic light-emitting diode (OLED) display substrate, and the light-emitting device 20 is an OLED.

[0081] FIG1B is a block diagram of a display substrate provided by at least one embodiment of the present disclosure. As shown in FIG1B , for example, each of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 includes a pixel circuit that drives the light-emitting device 20 to emit light. The display substrate may also include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels. As needed, the display substrate may further include power lines, detection lines, etc.

[0082] The pixel circuit includes a driving subcircuit for driving the light emitting device 20 to emit light and a detection subcircuit for detecting the electrical characteristics of the subpixel to achieve external compensation. The embodiment of the present disclosure does not limit the specific structure of the pixel circuit.

[0083] FIG1B shows a schematic diagram of a 3T1C pixel circuit for the display substrate. As needed, the pixel circuit may further include a compensation circuit, a reset circuit, and the like. For example, the pixel circuit may also have a 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. The embodiments of the present disclosure are not limited thereto.

[0084] As shown in Figures 2A and 1A, in an exemplary embodiment, each display unit P further includes a first scan signal line G1, a second scan signal line G2, a first power line vdd, a second power line vss, four data signal lines D (in Figure 2A, the four data signal lines D are the first data signal line D1 to the fourth data signal line D4, the first subpixel P1 is connected to the first data signal line D1, the second subpixel P2 is connected to the second data signal line D2, the third subpixel P3 is connected to the third data signal line D3, and the fourth subpixel P4 is connected to the fourth data signal line D4), a detection signal line S and four pixel circuits corresponding to the four word pixels P1\P2\P3\P4 respectively.

[0085] For example, the first scan signal line G1 and the second scan signal line G2 extend along a first direction D1 and are arranged along a second direction D2. The first direction D1 intersects the second direction D2, for example, the first direction is perpendicular to the second direction D2. The first power line VDD, the data signal lines D1, D2, D3, and D4, and the detection signal line S can extend along the second direction D2 and be arranged along the first direction D1.

[0086] For example, four data signal lines D and one detection signal line S are arranged between a first power line vdd and a second power line vss. Two of the four data signal lines D1, D2, D3, and D4 are located between the detection signal line S and the first power line vdd, and the other two of the four data signal lines D, D1 and D2, are located between the detection signal line S and the second power line vss. Thus, four sub-pixels are formed between the first power line vdd and the second power line vss by arranging the four data signal lines D1, D2, D3, and D4 and the detection signal line S. Correspondingly, four sub-pixels are also formed between the two detection signal lines S by arranging the first power line vdd, the second power line vss, and the four data signal lines D1, D2, D3, and D4.

[0087] Figures 2B-2D are signal timing diagrams of a driving method for a pixel circuit provided in an embodiment of the present disclosure. Referring to Figures 2A and 2B, for example, the pixel circuit of each of the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4 includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. A first scan signal line G1 is connected to the gate electrode of the second transistor T2 in each subpixel, and a second scan signal line G2 is connected to the gate electrode of the third transistor T3 in each subpixel. In each sub-pixel, the first electrode of the second transistor T2 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the first transistor T1, the data signal line is connected to the second electrode of the second transistor T2, the second electrode of the second transistor T2 is configured to receive the data signal GT, the second transistor T2 is a data transistor, and is configured to write the data signal DT into the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal G1; the first electrode of the first transistor T1 is electrically connected to the second capacitor electrode of the storage capacitor Cst, and is configured to be electrically connected to the first electrode of the light-emitting element 20, the first power line VDD is connected to the second electrode of the first transistor T1, and the second electrode of the first transistor T1 is configured to receive the first power supply voltage V1 (for example, the high power supply voltage V DD), the first transistor T1 is a driving transistor and is configured to control the current used to drive the light-emitting element under the control of the voltage of the gate of the first transistor T1; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second capacitor electrode of the storage capacitor Cst, the detection signal line S is connected to the second electrode of the third transistor T3, and the second electrode of the third transistor T3 is configured to be connected to the first detection line S to be connected to the external detection circuit 11. The third transistor T3 is a detection transistor and is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element. The external detection circuit 11 is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and the embodiments of the present disclosure are not described in detail.

[0088] The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as an example. The source and drain of the transistors used here may be symmetrical in structure, so their source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole as the second pole. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that, in the following description, the transistor in FIG. 1B is an N-type transistor as an example, but this is not intended to limit the present disclosure.

[0089] The working principle of the pixel circuit shown in Figure 2A is explained below in conjunction with the signal timing diagrams shown in Figures 2B-2D, where Figure 2B shows the signal timing diagram of the pixel circuit during the display process, and Figures 2C and 2D show the signal timing diagrams of the pixel circuit during the detection process.

[0090] For example, as shown in FIG2B , the display process of each frame of image includes a data writing and reset phase 1 and a light-emitting phase 2. FIG2B shows the timing waveforms of each signal in each phase. An operation process of the 3T1C pixel circuit includes: in the data writing and reset phase 1, the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2, the first switch K1 is closed, the analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (e.g., the anode of the OLED) through the first detection line 130 and the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the operating voltage; in the light-emitting phase 2, the first control signal G1 and the second control signal G2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in a saturated state and the current remains unchanged, and drives the light-emitting element to emit light.

[0091] For example, Figure 2C shows a signal timing diagram of the pixel circuit when detecting the threshold voltage. One operating process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2; the first switch K1 is closed, the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the first detection line 130 and the third transistor T3, the first transistor T1 is turned on and charges the node S until the first transistor is turned off, and the digital-to-analog converter samples the voltage on the first detection line 130 to obtain the threshold voltage of the first transistor T1. This process can be performed, for example, when the display device is turned off.

[0092] For example, FIG2D shows a signal timing diagram of the pixel circuit when performing threshold voltage detection. An operation process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; for example, the external detection circuit writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the first detection line 130 and the third transistor T3; in the second stage, the first control signal G1 is an off signal, the second control signal G1 is an on signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the first detection line 130 is floated; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in a saturated state and the current remains unchanged and drives the light-emitting element to emit light, and then the digital-to-analog converter samples the voltage on the first detection line 130 and calculates the carrier mobility in the first transistor T1 in combination with the magnitude of the light-emitting current. For example, this process can be performed in the blanking stage between display stages.

[0093] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented.

[0094] For example, as shown in FIG1B , the display substrate 10 may further include a data driver circuit 03 and a scan driver circuit 04. The data driver circuit 03 is configured to issue a data signal, such as the aforementioned data signal DT, as needed (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the gate of the first transistor. The scan driver circuit 04 is configured to output various scan signals, such as the aforementioned first control signal G1 and second control signal G2, and is, for example, an integrated circuit chip (IC) or a gate driver circuit (GOA) directly fabricated on the display substrate.

[0095] For example, the display substrate 10 further includes a control circuit 02. For example, the control circuit 02 is configured to control the data drive circuit 03 to apply data signals and to control the gate drive circuit to apply scan signals. An example of the control circuit 02 is a timing control circuit (T-con). The control circuit 02 can be in various forms, for example, including a processor 021 and a memory 022, the memory 022 including executable code, and the processor 021 running the executable code to perform the above-described detection method.

[0096] For example, the processor 021 may be a central processing unit (CPU) or other forms of processing devices with data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0097] For example, the memory 022 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 021 may execute the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as the electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0098] Figure 3A is a schematic plan view of a display unit P of a display substrate 10 provided in at least one embodiment of the present disclosure; Figure 3B is a schematic view of the first subpixel P1 in Figure 3A ; Figure 3C is an enlarged view of a portion L including a connection structure in Figure 3B ; and Figure 4A is a schematic cross-sectional view taken along line AA' in Figure 3B . Referring to Figures 3A-3C and Figure 4A , the light-emitting device 20 includes a first electrode 2, which includes a first portion 21 and a second portion 22 spaced apart from each other. The display unit P also includes a connection structure 3 and a first transfer electrode 4. The connection structure 3 electrically connects the first portion 21 of the first electrode and the second portion 22 of the first electrode, and includes a first extension portion 31, a second extension portion 32, and a connection portion 30. The first extension portion 31 and the second extension portion 32 extend from the display area 11 to the non-luminous area 12 along the first direction D1, respectively. The first extension portion 31 is electrically connected to the first portion 21 of the first electrode at a first end, and the first end of the second extension portion 32 is electrically connected to the second portion 22 of the first electrode; the connection portion 30 is located in the non-luminous area 12 and connects the second end of the first extension portion 31 and the second end of the second extension portion 32; in conjunction with Figures 3C, 4A, and 5 A. The first transfer electrode 4 is electrically connected to the first electrode T1s of the driving transistor T1. The first transfer electrode 4 includes a strip portion 42a extending from the display area 11 to the non-luminescent area 12 along the first direction D1, and a connection pad 42b located in the non-luminescent area 12, connected to the strip portion 42a, and located at an end of the strip portion 42a farther from the display area 11 in the first direction D1. The connection portion 30 is connected to the connection pad 42b in the non-luminescent area 12 via a via. A gap exists between the connection pad 42b and each of the first extension portion 31 and the second extension portion 32 in a second direction D2 intersecting the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1.

[0099] In the display substrate 10 provided by the embodiment of the present disclosure, multiple parts of the first electrode 22, such as the first part 21 and the second part 22, are connected to the first electrode T1s of the driving transistor T1 through the connecting portion 30 and the first switching electrode 4. In this way, the opening area of ​​a sub-pixel (taking the first sub-pixel P1 as an example) includes a first sub-opening 601 and a second sub-opening 602 (as shown in Figure 5L). The first sub-opening 601 and the second sub-opening 602 are the areas corresponding to the first part 21 of the first electrode and the second part 22 of the first electrode, respectively. For example, the first part 21 of the first electrode covers the first sub-opening 601, and the second part 22 of the first electrode covers the second sub-opening 602. Furthermore, the first portion 21 of the first electrode and the second portion 22 of the first electrode are electrically connected to the connection portion 30 located in the non-luminescent region 12 in the non-luminescent region 12, and are then connected to the first electrode T1s of the driving transistor T1 via the portion of the first transfer electrode 4 located in the display region 11. When a display defect such as a dark spot occurs in one of the two portions of the sub-pixel opening area, that is, when a display defect such as a dark spot occurs in one of the regions corresponding to the first portion 21 of the first electrode or the second portion 22 of the first electrode in the opening area of ​​a sub-pixel, the first portion 21 or the second portion 22 of the first electrode corresponding to the region where the dark spot occurs can be disconnected by cutting off one of the first extension portion 31 and the second extension portion 32 corresponding to the region where the dark spot occurs. For example, the first extension portion 31 can be cut off along the cutoff line CUT in Figures 3B-3C. This prevents the dark spot from performing a display function in the region where the dark spot occurs, reduces the sub-pixel dark spot defect, achieves sub-pixel repair, and improves image quality, thereby ensuring an excellent display effect for the product. Furthermore, since the first portion 21 and the second portion 22 of the first electrode are electrically connected to the connecting portion 30 located in the non-luminescent region 12, and then connected to the first electrode T1s of the driving transistor T1 through the portion of the first transfer electrode 4 located in the display region 11, a via hole for connecting the connecting portion 30 to the first transfer electrode 4 can be easily formed in the non-luminescent region 12. Compared to a solution in which the first portion 21 and the second portion of the first electrode are connected to the first transfer electrode 4 in the display region 11, since no signal lines for the pixel circuit are provided in the non-luminescent region 12, in the disclosed embodiment, the alignment process for forming the via hole for connecting the connecting portion 30 to the first transfer electrode 4 at the position corresponding to the connecting portion 30 in the non-luminescent region 12 is easier, significantly improving the yield rate.

[0100] Furthermore, since there is a gap between the connection pad 42b of the first switching electrode 4 and the first extension portion 31 and the second extension portion 32 in the second direction D2, the distance between the connection pad 42b and the first extension portion 31 and the second extension portion 32 (i.e., the two anode connection lines) can be increased, so that the first extension portion 31 or the second extension portion 32 can be cut off during the repair of defective pixels, which provides a larger space and reduces the difficulty of the cutting operation, thereby facilitating faster and more accurate cutting of the target structure to complete pixel repair.

[0101] Referring to Figure 5A, in order to facilitate the connection of the connecting pad 42b to the connecting portion 30 via the via (described below), the width of the connecting pad 42b in the second direction D2 is greater than the width of the strip portion 42a in the second direction D2, so that there is a gap between the connecting pad 42b and the first extension portion 31 and the second extension portion 32 in the second direction D2. It is also beneficial to minimize the size of the connecting pad 42b, avoid the size of the connecting pad 42b being too large, and help reduce the blocking of the transparent non-luminous area by the connecting pad 42b to increase the aperture ratio.

[0102] For example, referring to FIG3C , the spacing between the connection pad 42 b and the first extension portion 31 is a first spacing, and the spacing between the connection pad 42 b and the second extension portion 32 is a second spacing. The length of the first spacing in the second direction D2 is L1, and the length of the second spacing in the second direction D2 is L2. The length of at least one of the first spacing and the second spacing in the second direction D2 is greater than the line width of the first extension portion 31 in the second direction D2, or greater than the line width of the second extension portion 32 in the second direction D2, or greater than the line width of the portion of the connection portion 30 extending along the second direction D2 in the first direction D1. For example, both L1 and L2 are greater than the line width of the first extension portion 31 in the second direction D2; for example, both L1 and L2 are greater than the line width of the portion of the connection portion 30 extending along the second direction D2 in the first direction D1. This further increases the spacing between the first extension portion 31 and the second extension portion 32, allowing for faster and more accurate severing of the first extension portion 31 or the second extension portion 32, thereby completing pixel repair.

[0103] For example, referring to FIG3C , the second end of the first extending portion 31 has a first cuttable portion 310, and the second end of the second extending portion 32 has a second cuttable portion 320. At a location on the side of the first cuttable portion 310 facing the first cuttable portion 310 on the side closest to the substrate 1, no conductive layer overlaps with the first cuttable portion 310 in a direction perpendicular to the main surface of the substrate 1. At least at a location on the side of the second cuttable portion 320 facing the second cuttable portion 320 on the side closest to the substrate 1, no conductive layer overlaps with the second cuttable portion 320 in a direction perpendicular to the main surface of the substrate 1. This allows for the removal of the first or second cuttable portion 310, 320, from a display defect such as a dark spot in a sub-pixel without damaging the other conductive layers. This facilitates the removal process, enabling sub-pixel repair and improving display quality.

[0104] For example, the display substrate includes a base substrate 1 , and the display unit P is provided on the base substrate 1 . The first switching electrode 4 is located on a side of the driving transistor T1 close to the base substrate 1 .

[0105] For example, referring to Figures 3C and 4A , the first transition electrode 4 includes a first transition portion 41 and a second transition portion 42. The first transition portion 41 is located in the display area 11, i.e., the portion of the first transition electrode 4 located in the display area, and is electrically connected to the first electrode T1s of the driving transistor T1. The second transition portion 42 is located in the non-luminescent area 12, and includes the aforementioned connection pad 42b and the portion of the strip portion 42a located in the non-luminescent area, and is electrically connected to the first transition portion 41. For example, referring to Figure 5A , the first transition portion 41 and the second transition portion 42 are disposed on the same layer and form a continuous, integrated structure. As shown in Figure 4A, for example, the display unit P also includes a second transfer electrode 5 located in the non-luminous area 12, and the second transfer electrode 5 is located between the connecting portion 30 and the second transfer portion 42 in a direction perpendicular to the main surface of the base substrate 1; the connecting portion 30 and the second transfer portion 42 are arranged in different layers, and the connecting portion 30 is electrically connected to the second transfer electrode 5 via the first via hole V01 in the non-luminous area 12, and the second transfer electrode 5 is electrically connected to the second transfer portion 42 of the first transfer electrode 4 via the second via hole V02, so as to achieve segmented connection, reduce the hole depth of the connecting portion 30 directly connected to the second transfer portion 42 through a via hole, and improve the manufacturing yield of the display substrate.

[0106] For example, referring to Figures 3B-3C and 4A , the first via hole V01 and the second via hole V02 are spaced apart in the first direction D1, with the second via hole V02 located on the side of the first via hole V01 and the first and second sub-portions 30a, 30b of the connecting structure 30 that is closer to the display area 11. The orthographic projection of the first via hole V01 on the main surface of the base substrate 1 and the orthographic projection of the second via hole V02 on the main surface of the base substrate 1 do not overlap (do not have any overlap). This allows the non-luminous area 12, which has more ample space relative to the display area, to be utilized. The distance between the first via hole V01 and the second via hole V02 in the first direction D1 is increased, reducing manufacturing difficulty. This also facilitates increasing the length of the first and second extension portions 31, 32 in the first direction D1, reducing the difficulty of the cutting operation during the pixel repair process and facilitating faster and more accurate cutting of the target structure to complete the pixel repair.

[0107] For example, the first via V01 and the second via V02 overlap in the first direction D1. That is, if a straight line is drawn along the first direction D1, the orthographic projection of the straight line on the main surface of the substrate 1 passes through the orthographic projections of the first via V01 and the second via V02 on the main surface of the substrate 1. For example, the centers of the two vias lie on the same straight line extending along the first direction D1. This helps to increase the space occupied in the second direction D2 by structures such as the first via V01 and the second via V02, as well as the connecting portion and the second transition portion 42 connected to each other by the two vias, thereby maximizing the spacing between the first extension portion 31 and the second extension portion 32 and these structures, facilitating faster and more accurate severing of the target structure to complete pixel repair.

[0108] Referring to FIG3C and FIG5I , for example, the connecting portion 30 includes a first sub-portion 30a and a second sub-portion 30b. The first sub-portion 30a connects to the second end of the first extending portion 31, and the second sub-portion 30b connects to the second end of the second extending portion 32. The first sub-portion 30a and the second sub-portion 30b are both located on a side of the first via hole V01 and the connection pad 42b of the first switching electrode 4 that is away from the display area 11. For example, L1 and L2 are both greater than the line width of the first sub-portion 30a and the second sub-portion 30b in the first direction D1. Furthermore, for example, referring to FIG5I , the first sub-portion 30a and the second sub-portion 30b are connected to form a strip extending in the second direction D2, and the strip has a narrow portion and a wide portion. The narrow portion has a smaller width in the first direction D1 than the wide portion. For example, in some embodiments, L1 and L2 are both greater than the width of the narrow portion in the first direction D1. Furthermore, in some embodiments, for example, L1 and L2 are both greater than the width of the wide portion in the first direction D1.

[0109] For example, as shown in FIG4A , the display substrate 10 further includes a first insulating layer 101, a second insulating layer 102 located on a side of the first insulating layer 101 away from the base substrate 1, a third insulating layer 103 located on a side of the second insulating layer 102 away from the base substrate 1, a fourth insulating layer 104 located on a side of the second transition electrode 5 away from the third insulating layer 103 in a direction perpendicular to the main surface of the base substrate 1, and a planar layer 105 located on a side of the fourth insulating layer 104 away from the third insulating layer 103 in a direction perpendicular to the main surface of the base substrate 1. A second via hole V02 penetrates the first insulating layer 101 and the third insulating layer 103, and the second transition electrode 5 is connected to the connection pad 42b of the second transition portion 42 through the second via hole V02. A first via hole V01 penetrates the fourth insulating layer 104, and the connection portion 30 is connected to the second transition electrode 5 through the first via hole V01, thereby achieving a connection between the connection portion 30 and the connection pad 42b of the second transition portion 42 through multiple vias.

[0110] For example, in some embodiments, the material of the first transfer electrode 4 is a light-shielding material, such as a metal material, such as copper, aluminum, chromium, copper alloy, aluminum alloy, chromium alloy, manganese alloy, etc. For example, in some embodiments, it may also include an organic material, such as a black light-shielding layer, etc., but is not limited to the types listed above.

[0111] For example, in conjunction with Figures 3C, 4A, and 5F, the length l1 of the second transition electrode 5 in the second direction D2 is greater than the length l2 of the first transition electrode 4 in the first direction D1. This allows for the space occupied by the second transition electrode 5 in the first direction D1 to be reduced while achieving connection to both the electrodes in the third via hole V03 and the fourth via hole V04 via the second transition electrode 5. This helps reduce the obstruction of the transparent non-luminescent area by the second transition electrode 5 (e.g., a light-opaque material such as a metal material, a light-shielding layer including an organic material, a black light-shielding layer, etc.), thereby increasing the aperture ratio.

[0112] For example, referring to FIG4A , the planar layer 105 includes a portion located in the display area 11 and a portion located in the non-luminous area 12. In a direction perpendicular to the main surface of the base substrate 1, the planar layer 105 is located between the first electrode 2 and the second transfer electrode 5; for example, the planar layer 105 covers the second via V02 and does not cover the first via V01. On the one hand, the process of forming the first electrode 2 (e.g., an anode) above the planar layer 105 typically requires multiple etching steps. The fourth insulating layer 104, for example, an inorganic layer, is typically relatively thin, making it difficult to maintain the second via V0 covered by it during these multiple etching steps. Therefore, covering the second via V02 with the planar layer 105 can prevent the etching solution from corroding the portion of the second transfer electrode 42 located in the second via V02 during these multiple etching steps, thereby preventing poor contact through the second via V02. 4A and 5H , the planar layer 105 includes an opening area OP located in the non-luminescent region 12 and a raised portion 105a covering the second via hole V02. Corresponding to the location of the second via hole V02, the raised portion 105a protrudes from the portion of the planar layer 105 located in the display region 11 along a first direction D1 toward the non-luminescent region 12. The raised portion 105a is located within the non-luminescent region 12. Furthermore, the planar layer 105 is relatively thick and has a relatively low light transmittance. Positioning the second via hole V02 below the planar layer 105 prevents the second via hole V02 from forming an additional barrier in the transparent non-luminescent region, thereby improving the light transmittance of the non-luminescent region 12 and, consequently, the entire display substrate 10.

[0113] For example, the thickness of the planarization layer 105 in a direction perpendicular to the base substrate 1 is greater than 6000 angstroms to meet its insulation and planarization functions. For example, the material of the planarization layer 105 is an organic insulating material, such as a resin material or an acrylic material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc., but not limited to the above. The planarization layer 105 also serves to form a flat surface to facilitate the fabrication of the first electrode, light-emitting layer, and second electrode of the light-emitting device thereon.

[0114] For example, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 may be inorganic insulating layers, such as silicon oxide, silicon nitride, or silicon oxynitride, or insulating materials including metal oxynitrides, such as aluminum oxide and titanium nitride. For example, the first insulating layer 101 may be a buffer layer to prevent debris from the base substrate 1 from invading the film layer above it during the display substrate manufacturing process.

[0115] For example, referring to Figure 5A, the length S2 of the connecting pad 42b in the second direction D2 is less than or equal to the length S1 of the connecting pad 42b in the first direction D1, so that on the basis of exerting the connecting function of the connecting pad 42b, the space occupied by the first transfer electrode 4 in the second direction D2 in the non-luminous area 12 can be minimized, thereby maximizing the distance between the first extension portion 31 and the second extension portion 32 and the first transfer electrode 4, which is conducive to faster and more accurate cutting off of the target structure to complete pixel repair.

[0116] For example, referring to Figures 3C and 5I, the connecting portion 30 includes a first sub-portion 30a and a second sub-portion 30b, the first sub-portion 30a is connected to the second end of the first extension portion 31, and the second sub-portion 30b is connected to the second end of the second extension portion 32, and the first sub-portion 30a and the second sub-portion 30b are both located on the side of the first via hole V01 and the connection pad 42b of the first switching electrode 4 away from the display area 11; the distance between the first via hole V01 and the second via hole V02 in the first direction D1 (for example, the distance between the geometric centers or approximate geometric centers of the first via hole V01 and the second via hole V02) is greater than the line width of the first sub-portion 30a in the first direction D1, or greater than the line width of the second sub-portion 30b in the first direction D1, so as to increase the distance between the first via hole V01 and the second via hole V02 in the first direction D1.

[0117] For example, the width of the second via hole V02 in the second direction D2 is less than or equal to the width of the second via hole V02 in the first direction D1, which is beneficial to increasing the interval between the first via hole V01 and the second via hole V02 and the first extension portion 31 and the second extension portion 32 in the second direction D2 within a limited space. Therefore, when repairing defective pixels, in the process of cutting off the first extension portion 31 or the second extension portion 32, the difficulty of the cutting operation is reduced, which is beneficial to faster and more accurate cutting of the target structure to complete the pixel repair.

[0118] For example, referring to FIG4A , the connection portion 30 includes a first sublayer 3a, a second sublayer 3b, and a third sublayer 3c stacked in a direction perpendicular to the main surface of the base substrate 1. The second sublayer 3b is located between the first sublayer 3a and the third sublayer 3c, and the third sublayer 3c is located on the side of the second sublayer 3b away from the base substrate 1. The orthographic projection of the third sublayer 3c on the main surface of the base substrate 1 is smaller than at least one of the orthographic projections of the second sublayer 3b and the first sublayer 3a, and is located within the range of at least one of the orthographic projections of the second sublayer 3b and the first sublayer 3a. In other words, the topmost first sublayer 3a is indented relative to at least one of the second sublayer 3b and the first sublayer 3a. This prevents the connection portion 30 from having a rib structure. The term "rib structure" herein means that the first sublayer 3a, the second sublayer 3b, and the third sublayer 3c can be formed using the same mask and the same patterning process, for example, by an etching process such as a wet etching process, so as to simplify the manufacturing process of the display substrate 10; and the material of the second sublayer 3b is different from that of the third sublayer 3c, so that the two have different etching rates, thereby easily causing the edge of the second sublayer 3b to be retracted relative to the third sublayer 3c, i.e., forming a "rib structure". This structure is very likely to cause a gap in the PDL at the rib structure, thereby preventing the cathode from being electrically connected to the rib structure through the gap during the subsequent cathode formation process (i.e., the cathode and anode are electrically connected). Therefore, in the embodiment shown in FIG4A , by making the pattern of the third sublayer 3c significantly retracted relative to the first sublayer 3a or the second sublayer 3b during patterning, the dimensional effect caused by the different etching rates of the second sublayer 3b and the third sublayer 3c is covered, thereby preventing the formation of a rib structure, thereby preventing display abnormalities caused by the cathode and anode at this location.

[0119] It should be noted that, in at least one embodiment of the present disclosure, the longitudinal portion vdd1 of the first power line vdd and the second power line vss are arranged at intervals in the first direction D1, and are respectively located at the first edge of the display area 11 in the first direction D1 and the second edge of the display area 11 opposite to the first edge in the first direction D1; the area between the edge of the longitudinal portion vdd1 of the first power line vdd away from the second power line vss and the edge of the longitudinal portion vdd1 of the second power line vss away from the first power line vdd is the display area 11.

[0120] For example, as shown in FIG4A , the light-emitting element may be an organic light-emitting diode, comprising a first electrode 2, a second electrode 24, and a light-emitting layer 23 located between the first electrode 2 and the second electrode 24. For example, the first electrode is a material with a high work function to act as an anode, such as an ITO / Ag / ITO laminate structure, or an ITO / Al / ITO laminate structure (sandwich structure), or an ITO / (Al+Ag) / ITO laminate structure (sandwich structure). Of course, the first electrode is not limited to the above-mentioned sandwich structure, and the material of the first electrode is not limited to the types listed above. The second electrode 24 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material. For example, the light-emitting element is a top emission structure, the first electrode 2 is reflective, and the second electrode 122 is transmissive or semi-transmissive.

[0121] For example, as shown in FIG3A , the display substrate 10 further includes scan signal lines G1 / G2 and data signal lines D1-D4 disposed on the base substrate 1. The scan signal lines G1 / G2 transmit scan signals. For example, the scan signal lines include a data scan signal line G1 and a sensing scan signal line G2. The data scan signal line G1 transmits a data scan signal, and the sensing scan signal line G2 transmits a sensing scan signal. For example, the data scan signal and the sensing scan signal can be row-by-row scan signals, such as the data scan signal and the sensing scan signal are the same scan signal, as shown in FIG2B . Alternatively, in other embodiments, the data scan signal and the sensing scan signal are different signals. For example, the data signal lines D1-D4 transmit a data signal DT. The scan signal lines include portions extending generally along a first direction D1, and the data signal lines D1-D4 include portions extending generally along a second direction D2 intersecting the first direction D1. The sub-pixel further includes a data write transistor T2, which is configured to transmit the data signal to the drive transistor T1 under the control of the data scan signal.

[0122] It should be noted that "extending overall along the first direction D1" includes extending substantially along the first direction D1, or at least overall along the first direction D1. For example, in some examples, the scan signal line extending overall along the first direction D1 may have a certain curvature, or in some examples, the edge of the strip extending overall along the second direction D2 may not be a smooth line, for example, its edge may have burrs or jagged edges. In short, as long as the overall extension trend is along the first direction D1, it is sufficient. The same applies to "extending overall along the second direction D2." Similarly, the same applies to all references to "extending overall along a certain direction" in this disclosure.

[0123] For example, as shown in Figures 3A-3B, each subpixel further includes a first power line vdd, which is connected to the first voltage terminal VDD and configured to provide a first power supply voltage to the subpixel. The first power line vdd is disposed on the same layer as the first electrode of the driving transistor T1 and includes a vertical portion vdd1. The vertical portion vdd1 extends entirely along the second direction D2 and is connected to adjacent subpixels. For example, the first power line vdd further includes a transverse portion vdd2, which is electrically connected to the vertical portion and extends entirely along the first direction D1 to connect to each subpixel in the display unit, thereby providing the first power supply voltage to each subpixel in the display unit. For example, the transverse portion vdd2 in Figure 3B is connected to the third subpixel P3 and the fourth subpixel P4. Figure 3A also includes another transverse portion vdd2 connected to the vertical portion vdd2 and to the first subpixel P1 and the second subpixel P2, thereby providing the first power supply voltage from the vertical portion vdd1 to each subpixel in the display unit. For example, the first extension portion 31 and the second extension portion 32 extend to the non-luminous region 12 across the first power line vdd and the data signal line to be connected to the connection portion 30 located in the non-luminous region 12 .

[0124] For example, referring to FIG3A , the non-luminescent region 12 and the display region 11 are arranged in the second direction D2, the first portion 21 of the first electrode and the second portion 22 of the first electrode are arranged in the second direction D2, and the first extension portion 31 and the second extension portion 32 both extend entirely along the first direction D1. This arrangement coordinates the positions of the first portion 21 of the first electrode and the second portion 22 of the first electrode with the non-luminescent regions corresponding to the sub-pixels in which they are located, thereby facilitating the extension of the first extension portion 31 and the second extension portion 32 from the first portion 21 of the first electrode and the second portion 22 of the first electrode, respectively, to the non-luminescent region 12, thereby facilitating the connection of the connection portion 30 in the non-luminescent region 12 with the first portion 21 of the first electrode and the second portion 22 of the first electrode.

[0125] For example, the non-luminous region 12 includes a first non-luminous region 12A and a second non-luminous region 12B, the first non-luminous region 12A is located on a first side of the display region 11 in the first direction D1, and the second non-luminous region 12B is located on a second side of the display region 11 opposite to the first side in the first direction D1; the first sub-pixel P1 and the third sub-pixel P3 are adjacent to the first non-luminous region 12A, and the second sub-pixel P2 and the fourth sub-pixel P4 are adjacent to the first non-luminous region 12A; a connection structure 3 is provided for each of the plurality of sub-pixels, and the connection structure 3 connects the first portion 21 of the first electrode and the second portion 22 of the first electrode of the sub-pixel adjacent thereto; the first sub-pixel P1 and the third sub-pixel P3 are adjacent to the first non-luminous region 12A, and the second sub-pixel P2 and the fourth sub-pixel P4 are adjacent to the first non-luminous region 12A; The connection portion 30 of the connection structure 3 of P1 and the connection portion 30 of the connection structure 3 corresponding to the third sub-pixel P3 are located in the first non-luminous area 12A; the connection portion 30 of the connection structure 3 corresponding to the second sub-pixel P2 and the connection portion 30 of the connection structure 3 corresponding to the fourth sub-pixel P4 are located in the second non-luminous area 12B, so that the first electrode of each sub-pixel of the display unit P includes a first part and a second part, and the first part and the second part of the first electrode of each sub-pixel can be connected to the first pole T1s of the driving transistor T1 located in the display area 11 through the connection portion located in the corresponding non-luminous area and the first switching electrode (or, the first switching electrode and the second switching electrode).

[0126] For example, as shown in Figure 3A, the scanning signal line G1 / G2 that provides scanning signals to the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 is located in the intersection area of ​​the first pixel row and the second pixel row, so as to provide scanning signals to the first pixel row and the second pixel row on both sides of the intersection area.

[0127] For example, the planar patterns of the first sub-pixel P1 and the second sub-pixel P2 are symmetrical with respect to the symmetry axis extending along the second direction D2, the planar patterns of the third sub-pixel P3 and the fourth sub-pixel P4 are symmetrical along the symmetry axis, and the planar patterns of the first non-luminous area 12A and the second non-luminous area 12B are symmetrical with respect to the symmetry axis, so as to rationally utilize space, improve the uniformity of the display substrate, thereby improving the uniformity of display in the display area, and reducing the difficulty of manufacturing the display substrate.

[0128] For example, referring to Figures 3B and 5L, the display unit P further includes a pixel defining layer 6, which includes a first portion 61 and a second portion 62. The first portion 61 is located between the first electrodes 2 of adjacent sub-pixels to define an opening region 60 of the sub-pixel. The light-emitting layer 23 of the light-emitting device 20 is at least located in the opening region 60. The second portion 62 is located between the first portion 21 of the first electrode and the second portion 22 of the first electrode to separate the first portion 21 of the first electrode from the second portion 22 of the first electrode.

[0129] For example, as shown in Figure 4A, the orthographic projection of the connecting portion 30 on the base substrate 1 is located within the orthographic projection of the first portion 61 of the pixel defining layer 6 on the base substrate 1, so as to avoid the connecting portion 30 and the first portion 61 of the pixel defining layer 6 occupying independent spaces respectively, saving space, and utilizing the first portion 61 of the pixel defining layer 6 to protect the connecting portion 30.

[0130] For example, the light-emitting element of the display substrate 10 provided in some embodiments of the present disclosure may adopt a top emission structure.

[0131] For example, as shown in FIG4A , each sub-pixel, taking the first sub-pixel P1 as an example, further includes a first capacitor C1; the first capacitor C1 includes a first plate Ca and a second plate Cb; the first plate Ca is electrically connected to the gate T1g of the driving transistor T1 and is disposed on the same layer as the gate of the driving transistor T1, for example, the first plate Ca and the gate T1g of the driving transistor T1 are continuously integrally formed; the orthographic projection of the second plate Cb on the base substrate 1 at least partially overlaps with the orthographic projection of the first plate Ca on the base substrate 1.

[0132] For example, as shown in FIG4A , a subpixel, taking the first subpixel P1 as an example, further includes a second capacitor C2. The second capacitor C2 includes a first plate Ca and a third plate Cc. The third plate Cc includes an overlapping portion and a non-overlapping portion. The orthographic projection of the overlapping portion on the substrate 1 overlaps with the orthographic projection of the first plate Ca on the substrate 1. The orthographic projection of the non-overlapping portion on the substrate 1 does not overlap with the orthographic projection of the first plate Ca on the substrate 1 and at least partially overlaps with the orthographic projection of the second plate Cb on the substrate 1. FIG4B is a schematic cross-sectional view along lines BB' and CC' in FIG3B . As shown in FIG4B , the non-overlapping portion is connected to the second plate Cb via a second via V2. The third plate Cc is also used as the first adapter 41. That is, the first adapter 41 is connected to the second plate Cb via the second via V2. This simplifies the structure and manufacturing process of the display substrate 10.

[0133] For example, as shown in FIG4B , the second electrode plate Cb is disposed on the same layer as the first electrode T1s of the driving transistor T1. For example, the second electrode plate Cb and the first electrode T1s of the driving transistor T1 are continuously integrated to electrically connect the second electrode plate Cb to the first electrode T1s of the driving transistor T1, thereby electrically connecting the first adapter 41 to the first electrode T1s of the driving transistor T1. The third electrode plate Cc is reused as the first adapter 41, and the second electrode plate Cb is continuously integrated with the first electrode T1s of the driving transistor T1, which greatly simplifies the structure and manufacturing process of the display substrate 10.

[0134] For example, as shown in FIG4B , the first electrode T1s of the driving transistor T1 is connected to the active layer T1a of the driving transistor T1 via a via V9, and the via V9 extends through the second insulating layer 102 and the third insulating layer 103. Of course, the number of vias is not limited to one and can be designed as needed. For example, in other embodiments, the first electrode T1s of the driving transistor T1 can also be connected to the active layer T1a of the driving transistor T1 via multiple vias to reduce contact resistance.

[0135] Figure 5A is a plan schematic diagram of the first conductive layer of the display unit shown in Figure 3A; Figure 5B is a plan schematic diagram of the first insulating layer of the display unit shown in Figure 3A; Figure 5C is a plan schematic diagram of the semiconductor layer of the display unit shown in Figure 3A; Figure 5D is a plan schematic diagram of the second conductive layer of the display unit shown in Figure 3A; Figure 5E is a plan schematic diagram of the third insulating layer of the display unit shown in Figure 3A; Figure 5F is a plan schematic diagram of the third conductive layer of the display unit shown in Figure 3A; Figure 5G is a plan schematic diagram of the fourth insulating layer of the display unit shown in Figure 3A; Figure 5H is a plan schematic diagram of the fifth insulating layer of the display unit shown in Figure 3A; Figure 5I is a plan schematic diagram of the fourth conductive layer of the display unit shown in Figure 3A; Figure 5J is a plan schematic diagram of the fifth conductive layer of the display unit shown in Figure 3A; and Figure 5K is a plan schematic diagram of the sixth conductive layer of the display unit shown in Figure 3A. 5A-5K and FIG4A , the display substrate 10 includes a first conductive layer 100, a first insulating layer 101, a semiconductor layer 600, a second insulating layer 102, a second conductive layer 200, a third insulating layer 103, a third conductive layer 300, a fourth insulating layer 104, a fifth insulating layer 105, a fourth conductive layer 401 and a sixth conductive layer 403 stacked sequentially on the base substrate 1 in a direction from close to the base substrate 1 to away from the base substrate 1. The fifth insulating layer is also the above-mentioned flat layer 105.

[0136] For example, the material of the semiconductor layer 600 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0137] As shown in conjunction with Figures 4A and 5A-5K, the first conductive layer 100 includes a first transition portion 41, a second transition portion 42, and a third electrode Cc; the semiconductor layer 600 includes an active layer T1a of the driving transistor T1, an active layer T2a of the data transistor T2, and an active layer T3a of the sensing transistor T3; the second conductive layer 200 includes a data scanning signal line G1 and a sensing scanning signal line G2, a gate T1g of the driving transistor T1, a gate T2g of the data transistor T2, and a gate T3g of the sensing transistor T3, a first electrode Ca, and a lateral portion v of the first power line vdd. The auxiliary power line vdd2 and the auxiliary power line vdd3 extend in the second direction D2, corresponding to the vertical portion vdd1 of the first power line vdd. The auxiliary power line vdd3 is electrically connected to the vertical portion vdd1 of the first power line vdd through a plurality of vias V4 extending through the third insulating layer 103. This allows the auxiliary power line vdd3 to be connected in parallel with the vertical portion vdd1 of the first power line vdd, thereby reducing the resistance of the first power line vdd. Furthermore, as shown in FIG5D , the auxiliary power line vdd3 is electrically connected to the horizontal portion vdd2, thereby electrically connecting the horizontal portion vdd2 to the vertical portion vdd1. For example, the auxiliary power line vdd3 and the horizontal portion vdd2 are disposed on the same layer, both located in the second conductive layer 200. For example, the auxiliary power line vdd3 and the horizontal portion vdd2 are formed as a continuous, integrated structure. The third conductive layer 300 includes the first electrode T1s and the second electrode T1d of the driving transistor T1, the first electrode T2s and the second electrode T2d of the data transistor T2, the first electrode T3s and the second electrode T3d of the sensing transistor T3, the data lines D1\D2\D3\D4, the detection signal line S, and the vertical portion vdd1 of the first power line vdd.

[0138] For example, in combination with Figure 4A and Figures 5I-5K, the first part 21 of the first electrode, the second part 22 of the first electrode, the first extension portion 31, the second extension portion 32 and the connecting portion 30 are a continuous one-piece molding structure to simplify the structure of the display substrate. The above-mentioned continuous one-piece molding structure can be formed by performing the same patterning process on the same material layer, thereby simplifying the manufacturing process of the display substrate.

[0139] For example, referring to Figures 4A and 5I-5K , the first portion 21 of the first electrode and the second portion 22 of the first electrode are connected to the first electrode T1s of the driving transistor T1. Furthermore, the first portion 21 of the first electrode and the second portion 22 of the first electrode respectively include a first sub-electrode layer 2a, a second sub-electrode layer 2b, and a third sub-electrode layer 2c, which are stacked sequentially in a direction perpendicular to the main surface of the base substrate 1 and from a direction closer to the base substrate 1 to a direction farther away from the base substrate 1. The first sub-layer 3a, the second sub-layer 3b, and the third sub-layer 3c of the connecting portion 30 are respectively made of the same material and disposed in the same layer as the first sub-electrode layer 2a, the second sub-electrode layer 2b, and the third sub-electrode layer 2c of the first electrode 2. For example, the same layer arrangement is formed through a single patterning process, thereby simplifying the manufacturing process of the display substrate.

[0140] The patterning process in the present disclosure includes, for example, a photolithography process, and certainly may also be other patterning processes.

[0141] For example, the second sub-electrode layer 2b of the first portion 21 of the first electrode, the third sub-electrode layer 2c of the first portion 21, the second sub-electrode layer 2b of the second portion 22 of the first electrode, and the third sub-electrode layer 2c of the second portion 22 of the first electrode can be formed using the same mask and the same patterning process, such as an etching process such as a wet etching process, to simplify the manufacturing process of the display substrate 10. In addition, the material of the second sub-electrode layer 2b is different from that of the third sub-electrode layer 2c, so that the two have different etching rates, thereby obtaining the structure shown in FIG4A in which the second sub-electrode layer 2b is indented relative to the third sub-electrode layer 2c. Of course, in other embodiments of the present disclosure, the first electrode is not limited to this structure, and the second sub-electrode layer 2b can also be non-indented.

[0142] For example, the material of the first sub-electrode layer 2a of the first portion 21 and the first sub-electrode layer 2a of the second portion 22 is a transparent conductive material, the material of the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22 is a metal material, and the material of the third sub-electrode layer 2c of the first portion 21 and the third sub-electrode layer 2c of the second portion 22 is a transparent conductive material. For example, the material of the second sub-electrode layer 2b may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials composed of the above metals. For example, the material of the first sub-electrode layer 2a and the material of the third sub-electrode layer 2c are conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc. Of course, the materials of the first sub-electrode layer 2a, the second sub-electrode layer 2b, and the third sub-electrode layer 2c are not limited to the types listed above, and the embodiments of the present disclosure are not limited to this.

[0143] For example, referring to FIG. 5I , the fourth conductive layer 401 includes the first sublayer 3a of the connection portion 30 , the first extension portion 31 , the second extension portion 32 , the first subelectrode layer 2a of the first portion 21 , and the first subelectrode layer 2a of the second portion 22 .

[0144] 5J , the fifth conductive layer 402 is located between the fourth conductive layer 401 and the sixth conductive layer 403 in a direction perpendicular to the main surface of the base substrate 1. The fifth conductive layer 402 includes the second sub-layer 3b of the connecting portion 30. For example, in some embodiments, the fifth conductive layer 402 may further include the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22.

[0145] 5K , the sixth conductive layer 403 includes the third sub-layer 3 c of the connection part 30 , the third sub-electrode layer 2 c of the first portion 21 , and the third sub-electrode layer 2 c of the second portion 22 .

[0146] Figure 4C is a schematic cross-sectional view along line DD' in Figure 3A. In conjunction with Figure 5A and Figure 4C, Figure 4C uses the first subpixel P1 and the second subpixel P2 as an example. The first conductive layer 100 further includes an intermediate connecting portion 43, for example, located at the junction of the first pixel row and the second pixel row. The detection signal line S is connected to the intermediate connecting portion 43 via a first connecting via V31 that penetrates the third insulating layer 103 and the first insulating layer 101, thereby connecting the detection signal line S to the second electrode T3d of the sensing transistor T3.

[0147] Referring to Figure 4C, for example, in a direction perpendicular to the main surface of the base substrate 1, the active layer T3a of the sensing transistor T3 (taking the sensing transistor T3 of the first sub-pixel P1 as an example) is located between the intermediate connection portion 43 and the first electrode of the sensing transistor T3; the second electrode T3d of the sensing transistor T3 is also electrically connected to the active layer T3a of the sensing transistor T3 through the second connection via V32; the active layer T3a of the sensing transistor T3 and the intermediate connection portion 43 at least partially overlap in a direction perpendicular to the main surface of the base substrate 1, and the second connection via V32 is a through hole formed by the first depth via V321 and the second depth via V322 penetrating each other. The second connection via V32 exposes the upper surface of the active layer T3a of the sensing transistor T3 away from the base substrate 1 and the side surface of the active layer T3a of the sensing transistor T3 intersecting with the upper surface, and exposes the intermediate connection portion 43. The depth of the first deep via V321 is less than that of the second deep via V322. Both the depths of the first and second deep vias refer to depths in a direction perpendicular to the main surface of the substrate 1. For example, the first deep via V321 penetrates the third insulating layer 103 to expose the side surface of the active layer T3a of the sensing transistor T3 that intersects the upper surface, while the second deep via V322 penetrates the third insulating layer 103 and the first insulating layer 101 to expose the intermediate connection portion 43. The second electrode T3d of the sensing transistor T3 contacts both the upper and side surfaces of the active layer T3a of the sensing transistor T3 through the second connection via V32, and contacts the intermediate connection portion 43 through the second connection via V32. This electrically connects the second electrode T3d of the sensing transistor T3 in the first subpixel P1 to the active layer T3a of the sensing transistor T3, and the second electrode T3d of the sensing transistor T3 is electrically connected to the detection signal line S via the intermediate connection portion 43.

[0148] Similarly, the second electrode T3d' of the sensing transistor of the second subpixel P2 is electrically connected to the active layer T3a' of the sensing transistor of the second subpixel P2 through a third connection via V33. The active layer T3a' of the sensing transistor at least partially overlaps with the intermediate connection portion 43 in a direction perpendicular to the main surface of the base substrate 1. The third connection via V33 is a through-hole formed by a third deep via V331 and a fourth deep via V332 extending through each other. The third connection via V33 exposes the upper surface of the active layer T3a' of the sensing transistor away from the base substrate 1, the side surface of the active layer T3a' of the sensing transistor intersecting with the upper surface, and the intermediate connection portion 43. The depth of the third deep via V331 is less than the depth of the fourth deep via V332. The depths of the third and fourth deep vias refer to the depths in a direction perpendicular to the main surface of the base substrate 1. For example, a third depth via V331 penetrates the third insulating layer 103 to expose the side surface of the active layer T3a' of the sensing transistor that intersects the upper surface. A fourth depth via V332 penetrates the third insulating layer 103 and the first insulating layer 101 to expose the intermediate connection portion 43. The second electrode T3d' of the sensing transistor of the second subpixel P2 contacts both the upper and side surfaces of the active layer T3a' of the sensing transistor through the third connection via V33, and contacts the intermediate connection portion 43 through the third connection via V33. This electrically connects the second electrode T3d' of the sensing transistor of the second subpixel P2 to the active layer T3a' of the sensing transistor, and the second electrode T3d' of the sensing transistor to the detection signal line S via the intermediate connection portion 43. Consequently, the second electrode T3d of the sensing transistor of the first subpixel P1 and the second electrode T3d' of the sensing transistor of the second subpixel P2 are connected to the same detection signal line S via the same intermediate connection portion 43, simplifying the structure and manufacturing process of the display substrate 10.

[0149] For example, as shown in FIG4C , the second electrode T3d of the sensing transistor T3 includes an outer portion proximal to the non-luminescent region 12 in the first direction D1 and an inner portion distal to the non-luminescent region 12, with the outer and inner portions connected to each other. The active layer T3a of the sensing transistor T3 overlaps the inner portion of the second electrode T3d of the sensing transistor T3 in a direction perpendicular to the main surface of the substrate 1. A second connection via V32 exposes the end of the upper surface of the active layer T3a of the sensing transistor T3 proximal to the non-luminescent region 12 in the first direction D1, as well as a first side surface of the active layer T3a of the sensing transistor T3, which faces the non-luminescent region 12 in the first direction D1. The second electrode T3d of the sensing transistor T3 contacts both the upper surface and the first side surface of the active layer T3a of the sensing transistor T3 through the second connection via V32. The same is true for the active layer T3a' of the sensing transistor. In the embodiment shown in FIG4C , for a sub-pixel, the active layer T3a of the sensing transistor T3 is located on the inner side of the second connection via V32 near the middle connection portion 43, which facilitates reducing the size of the sub-pixel in the first direction D1 and achieving a higher PPI. For example, the active layers of the sensing transistors of two adjacent sub-pixels in the first direction D1 are located on the inner side of the corresponding second connection via V32 near the middle connection portion 43 and the inner side of the fourth connection via V33 near the middle connection portion 43, respectively. This further facilitates reducing the size of the entire display unit P in the first direction D1 and achieving a higher PPI.

[0150] Alternatively, in another embodiment, as shown in FIG4D , the active layer T3a of the sensing transistor T3 overlaps the outer portion of the second electrode T3d of the sensing transistor T3 in a direction perpendicular to the main surface of the substrate 1. The second connection via V32 exposes the end of the upper surface of the active layer T3a of the sensing transistor T3 that is distal from the non-luminescent region 12 in the first direction D1, as well as the second side surface of the active layer T3a of the sensing transistor T3, which faces away from the non-luminescent region 12 in the first direction D1. The second electrode T3d of the sensing transistor T3 contacts both the upper surface and the second side surface of the active layer T3a of the sensing transistor T3 through the second connection via V32. This also enables the second electrode T3d of the sensing transistor T3 to be electrically connected to the active layer T3a of the sensing transistor T3, and the second electrode T3d of the sensing transistor T3 to be electrically connected to the detection signal line S via the intermediate connection portion 43.

[0151] For example, in combination with Figures 4C and 5C, the second electrode T3d of the sensing transistor T3 of the first sub-pixel P1 (i.e., the upper sub-pixel hereinafter) and the second electrode T3d of the sensing transistor T3 of the third sub-pixel P3 (i.e., the lower sub-pixel hereinafter) constitute a continuous integrally formed electrode, and the active layer T3a of the sensing transistor T3 of the first sub-pixel P1 and the active layer T3a of the sensing transistor T3 of the third sub-pixel P3 are integrally formed into an active layer IAL, and the integrally formed electrode is electrically connected to the integrally formed active layer IAL through the middle via V33.

[0152] For example, as shown in FIG4A , the third electrode plate Cc is located on a side of the first electrode plate Ca close to the base substrate 1 .

[0153] For example, in conjunction with Figures 4A and 5A, the display substrate 10 further includes a light shielding layer 7, which is located on the side of the semiconductor layer 200 that is adjacent to the base substrate 1. The orthographic projection of the active pattern of the driving transistor T1 (i.e., the active layer T1a or the channel region) on the base substrate 1 is located within the orthographic projection of the light shielding layer 7 on the base substrate 1. Thus, the light shielding layer 7 blocks top light from the side of the active pattern of the driving transistor T1 that is away from the base substrate 1, preventing the top light from irradiating the channel region of the driving transistor T1, thereby preventing the light from degrading the performance of the driving transistor T1. For example, if the light-emitting device 20 is a top-emitting device, light emitted by the light-emitting layer 23 is emitted from the side of the light-emitting device 20 that is away from the base substrate 1. Of course, the light-emitting device 20 can also be a bottom-emitting device, with light emitted by the light-emitting layer 23 being emitted through the base substrate 1. For example, the light shielding layer 7 can be reused as the first adapter 41, i.e., the two are the same structure, thereby simplifying the structure and manufacturing process of the display substrate 10.

[0154] The embodiment of the present disclosure also provides a display substrate, as shown in Figures 1 and 3A, the display substrate 10 includes a display unit P, the display unit P includes a display area and a non-luminous area, the display area includes a sub-pixel, the sub-pixel includes a driving transistor T1 and a light-emitting device, the driving transistor is configured to control the magnitude of the driving current flowing through the light-emitting device, and includes a gate, a first electrode, and a second electrode; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. Referring to Figures 3A and 5D, the display substrate 10 includes: a scanning signal line and a sensing signal line S, the scanning signal line includes at least one annular outer ring portion; the sensing scanning signal line G1 includes a portion extending along the first direction D1 as a whole, passing through the non-luminous area 12 and the display area 11, transmitting a sensing scanning signal, and including a sensing scanning signal line G1, the sensing scanning signal line G1 includes a first annular outer ring portion R1, and at least one annular outer ring portion includes the first outer ring portion R1; the sensing signal line S transmits a sensing signal, the sub-pixel also includes a sensing transistor T3, the sensing scanning signal line G1 is configured to supply a sensing signal to the sensing transistor S. Transistor T3 provides a sensing scan signal. Sensing transistor T3 is configured to detect the electrical characteristics of the sub-pixel using the sensing signal under the control of the sensing scan signal. The second electrode T3d of sensing transistor T3 is electrically connected to the first electrode T1s of driving transistor T1 and the first electrode 2 of the light-emitting element. The sub-pixel also includes an intermediate connecting portion 43 extending along the first direction D1. The sensing signal line S is connected to the intermediate connecting portion 43 through a first connecting via, and the second electrode T3d of sensing transistor T3 is connected to the intermediate connecting portion 43 through a second connecting via V32. The intermediate connecting portion 43 is located in the annular space within the first outer ring portion R1. For example, the circuit structure of the sub-pixel is the same as that of the previously described embodiment, and reference may be made to the circuit structures in Figures 2A and 3A. For example, the connection relationships of the various transistors, capacitors, and signal lines (data line, first power line, second power line, etc.) may refer to those shown in Figures 2A and 3A.

[0155] For example, a vertical signal line is disposed on the base substrate 1 and is located in the display area 11, including a portion extending as a whole along a second direction D2 intersecting the first direction D1 (for example, the second direction D2 is perpendicular to the first direction D1), and each of the at least one outer ring portion includes a first conductor and a second conductor, the first conductor and the second conductor both extending as a whole along the first direction D1 and both extending from the non-luminous area 12 to the display area 11, and the second conductor being spaced apart from the first conductor in the second direction D2. For example, the display substrate 10 further includes the base substrate 1, and the display unit is disposed on the main surface of the base substrate 1. The first conductor and the second conductor both overlap with the vertical signal line in a direction perpendicular to the main surface of the base substrate 1. Thus, at least one outer ring portion can effectively reduce the load (or resistance) of the scanning signal line while avoiding excessive overlap with the longitudinal signal line; and, the first wire and the second wire of at least one outer ring portion extend from the non-luminous area to the display area, so that they can overlap with the longitudinal signal line located at the edge of the display area close to the non-luminous area in a direction perpendicular to the base substrate. Thus, when a short circuit or other problem occurs at the point where the longitudinal signal line overlaps with one of the first wire and the second wire of the same outer ring portion, the short-circuited one of the first wire and the second wire can be cut off to stop working, thereby avoiding affecting the display effect of the display unit where it is located, thereby achieving pixel repair of the display unit.

[0156] For example, referring to FIG3A and FIG5D , the first outer ring portion R1 includes a first conductive line R11 and a second conductive line R12. The first outer ring portion R1 overlaps with a signal line extending along a second direction D2 in a direction perpendicular to the main surface of the base substrate 1. When a short circuit or other problem occurs at the intersection of the signal line extending in the second direction and one of the first conductive line R11 and the second conductive line R12 of the first outer ring portion R1, the short-circuited conductive line can be severed, causing the severed conductive line to stop functioning, thereby preventing it from affecting the display effect of the display unit P. This allows pixel repair of the display unit P. The unsevered conductive line can then continue to provide sensing scanning signals to the multiple sub-pixels P1 to P4 of the display unit P, thereby maintaining normal operation of the multiple sub-pixels P1 to P4 of the display unit P and reducing the impact of the short circuit on the display effect. In the display substrate provided in an embodiment of the present disclosure, the intermediate connection portion 43 is located inside the first outer ring portion R1. The annular design of the first outer ring portion R1 can be combined with the position design of the intermediate connection portion 43 to fully utilize the sufficient space inside the annular portion of the first outer ring portion R1 to set the intermediate connection portion 43. The setting of the first outer ring portion R1 does not occupy too much extra space, so that the intermediate connection portion 43 will not be too close to the first wire R11 of the first outer ring portion R1 and the second wire R12 of the first outer ring portion R1. Therefore, it is possible to avoid a short circuit between the intermediate connection portion 43 and the sensing scanning signal line G1 during the process of cutting the first wire R11 of the first outer ring portion R1 or the second wire R12 of the first outer ring portion R1 when performing pixel repair.

[0157] For example, the non-luminous area 12 of the display unit P includes a first non-luminous area 12A and a second non-luminous area 12B, the first non-luminous area 12A is located on the first side of the display area 11 in the first direction D1, and the second non-luminous area 12B is located on the second side of the display area 11 in the first direction D1 opposite to the first side thereof; the first outer ring portion R1 extends from the first non-luminous area 12A to the display area 11 and then to the second non-luminous area 12B, that is, the first conductive wire R11 of the first outer ring portion R1 or the second conductive wire R12 of the first outer ring portion R1 extends from the first non-luminous area 12A to the display area 11 and then to the second non-luminous area 12B. That is, the first wire R11 of the first outer ring portion R1 or the second wire R12 of the first outer ring portion R1 passes through the first non-luminous area 12A, the display area 11 and the second non-luminous area 12B in sequence and passes through the entire display area 11 along the first direction D1. Among the outer ring portions of each scanning signal line, the first outer ring portion R1 is the ring with the largest span in the first direction D1. Therefore, it can not only overlap with all the longitudinal signal lines extending along the second direction D2 in the display area 11 as a whole in the direction perpendicular to the main surface of the base substrate 1, so as to solve the above-mentioned pixel repair when short circuit occurs for all longitudinal signal lines, but also can utilize the larger space inside the larger ring, which is more conducive to setting the intermediate connection portion 43 inside the first outer ring portion R1, so as to avoid the intermediate connection portion 43 and the sensing scanning signal line G1 being short-circuited during the cutting operation of the first wire R11 of the first outer ring portion R1 or the second wire R12 of the first outer ring portion R1 when performing pixel repair.

[0158] For example, as shown in Figures 3A and 5D , the first conductive line R11 of the first outer loop portion R1 and the second conductive line R12 of the first outer loop portion R1 both overlap with the data signal line in a direction perpendicular to the main surface of the base substrate 1, overlap with the longitudinal portion vdd1 of the first power line vdd in a direction perpendicular to the main surface of the base substrate 1, and overlap with the second power line vss in a direction perpendicular to the main surface of the base substrate 1. For example, the data signal lines include a first data line D1 that provides a data signal to the first subpixel P1, a second data line D2 that provides a data signal DT to the second subpixel P2, a third data line D3 that provides a data signal DT to the third subpixel P3, and a fourth data line D4 that provides a data signal DT to the fourth subpixel P4; the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 are arranged alternately in the first direction D1. For example, the first conductive line R11 and the second conductive line R12 of the first outer loop portion R1 are both connected to the data signal lines D1 to D4 of the plurality of sub-pixels P1 to P4 of the display unit P. Thus, the pixel repair in the event of a short circuit can be solved for the data signal lines D1 to D4, the longitudinal portion vdd1 of the first power line vdd, and the second power line vss.

[0159] For example, the longitudinal signal line also includes a detection signal line S, which transmits a detection signal. The sub-pixel also includes a sensing transistor T3, and the sensing scan signal line G2 is configured to provide a sensing scan signal to the sensing transistor T3. The sensing transistor T3 is configured to detect the electrical characteristics of the sub-pixel using the detection signal under the control of the sensing scan signal to achieve external compensation. For example, as shown in Figures 3A and 5D, the first wire R11 of the first outer ring portion R1 and the second wire R12 of the first outer ring portion R1 both overlap with the detection signal line S in a direction perpendicular to the main surface of the base substrate 1. Therefore, the pixel repair when a short circuit occurs can also be solved for the detection signal line S.

[0160] For example, the display substrate 10 includes a first power line vdd. As described above, the first power line vdd is connected to the first voltage terminal and is configured to provide a first power supply voltage to the subpixel. The first power line vdd includes a longitudinal portion vdd1 extending generally along the second direction D2. The longitudinal signal line includes the longitudinal portion vdd1 of the first power line vdd. The first conductive line R11 and the second conductive line R12 of the first outer ring portion R1 both overlap with the longitudinal portion vdd1 of the first power line in a direction perpendicular to the main surface of the base substrate 1. In this way, the first conductive line R11 and the second conductive line R12 of the first outer ring portion R1 extend from the non-luminous region 12A to the display region 11, thereby overlapping with longitudinal signal lines, such as the first power line vdd, located at an edge of the display region 11 near the non-luminous region 12A in a direction perpendicular to the main surface of the base substrate 1. Thus, the first outer ring portion R1 can effectively reduce the load (or resistance) of the data scanning signal line G1, and when a short circuit occurs at the intersection of the longitudinal portion vdd1 and one of the first wire R11 of the first outer ring portion R1 and the second wire R12 of the first outer ring portion R1, the one of the first wire R11 of the first outer ring portion R1 and the second wire R12 of the first outer ring portion R1 that has a short circuit can be cut off. For example, the first wire R11 of the first outer ring portion R1 and the second wire R12 of the first outer ring portion R1 can be cut off at the first side or the second side opposite to each other in the first direction D1 of the longitudinal portion vdd1. The short-circuited one of the first wire R11 and the second wire R12 of the first outer ring portion R1 is cut off, so that the cut wire stops working, avoids affecting the display effect of the display unit P where it is located, and realizes pixel repair of the display unit P. The uncut one of the first wire R11 of the first outer ring portion R1 and the second wire R12 of the first outer ring portion R1 continues to provide data scanning signals to the multiple sub-pixels P1~P4 of the display unit P, keeps the multiple sub-pixels P1~P4 of the display unit P working normally, and reduces the influence of the above-mentioned short-circuit problem on the display effect.

[0161] For example, referring to Figures 3A and 5D , the scan signal lines further include a data scan signal line G2 and data signal lines D1-D4. The data scan signal line G2 includes a portion extending generally along a first direction D1 and transmits a data scan signal; the data signal lines D1-D4 transmit data signals DT. As described above, the subpixel further includes a data write transistor T2. The data scan signal line G2 is configured to provide a data scan signal to the gate of the data write transistor T2. For example, the data scan signal line G1 provides a data scan signal to multiple subpixels P1-P4 of the display unit P; the data write transistor T2 is configured to transmit the data signal DT to the drive transistor T1 under the control of the data scan signal. The longitudinal signal lines include at least one data signal line, for example, at least one data signal line from the multiple data signal lines D1-D4 that provide data signals to multiple subpixels of a display unit P. The first conductive line R11 and the second conductive line R12 of the first outer ring portion R1 both overlap with the at least one data signal line in a direction perpendicular to the main surface of the base substrate 1.

[0162] For example, the data scan signal line G2 includes a second outer ring portion R2 in a ring shape, and the first conductive line R21 and the second conductive line R22 of the second outer ring portion R2 both overlap with the longitudinal portion vdd1 of the first power line in a direction perpendicular to the main surface of the base substrate 1. In this way, the first conductive line R21 and the second conductive line R22 of the second outer ring portion R2 extend from the non-luminous area 12A to the display area 11, thereby facilitating overlap with longitudinal signal lines, such as the first power line vdd, located at an edge of the display area 11 near the non-luminous area 12A in a direction perpendicular to the base substrate 1. Thus, the second outer ring portion R2 can effectively reduce the load (or resistance) of the data scanning signal line G1, and when a short circuit occurs at the intersection of the longitudinal portion vdd1 and one of the first wire R21 of the second outer ring portion R2 and the second wire R22 of the second outer ring portion R2, the short-circuited one of the first wire R21 of the second outer ring portion R2 and the second wire R22 of the second outer ring portion R2 can be cut off. For example, the first wire R21 of the second outer ring portion R2 can be cut off at the first side or the second side of the longitudinal portion vdd1 opposite to each other in the first direction D1. The short-circuited one of the first wire R21 and the second wire R22 of the second outer ring portion R2 is cut off, causing the cut wire to stop working, avoiding affecting the display effect of the display unit P where it is located, and realizing pixel repair of the display unit P. The uncut one of the first wire R21 of the second outer ring portion R2 and the second wire R22 of the second outer ring portion R2 continues to provide data scanning signals to the multiple sub-pixels P1~P4 of the display unit P, maintaining the normal operation of the multiple sub-pixels P1~P4 of the display unit P, and reducing the impact of the above-mentioned short-circuit problem on the display effect.

[0163] For example, in the embodiment shown in FIG3A , the first conductive line R21 of the second outer ring portion R2 and the second conductive line R22 of the second outer ring portion R2 overlap with the first data signal line D1 in a direction perpendicular to the base substrate 1. Of course, in other embodiments, the first conductive line R21 of the second outer ring portion R2 and the second conductive line R22 of the second outer ring portion R2 may also overlap with the second data signal line D2 in a direction perpendicular to the base substrate 1, or overlap with the third data signal line D3 in a direction perpendicular to the base substrate 1, or overlap with the fourth data signal line D4 in a direction perpendicular to the base substrate 1. For example, in other embodiments, the first conductive line R21 of the second outer ring portion R2 and the second conductive line R22 of the second outer ring portion R2 may also overlap with multiple data signal lines of the display unit P. The positional relationship between the data line and the second outer ring portion may be designed according to the specific pixel structure and needs.

[0164] For example, as shown in Figures 3A and 5D, the data scan signal line G1 further includes a third outer loop portion R3, and the at least one outer loop portion includes the third outer loop portion R3. The longitudinal signal line includes a second power line vss, which is connected to the second voltage terminal and configured to provide a second power voltage different from the first power voltage to the sub-pixel, and extends in a second direction D2. The first conductor R31 and the second conductor R32 of the third outer loop portion R3 overlap with the second power line vss in a direction perpendicular to the main surface of the base substrate 1. In this way, the third outer ring portion R3 can further reduce the load (or resistance) of the data scanning signal line G1, and when a short circuit occurs at the intersection of the longitudinal portion vdd1 and one of the first wire R31 of the third outer ring portion R3 and the second wire R32 of the third outer ring portion R3, the short-circuited one of the first wire R31 of the third outer ring portion R3 and the second wire R32 of the third outer ring portion R3 can be cut off. For example, the third outer ring portion R3 can be connected to the first side or the second side of the second power line vss in the first direction D1. The short-circuited one of the first wire R31 and the second wire R32 of the third outer ring portion R3 is cut off, causing the cut wire to stop working, thereby avoiding affecting the display effect of the display unit P where it is located, and realizing pixel repair of the display unit P. The uncut one of the first wire R31 of the third outer ring portion R3 and the second wire R32 of the third outer ring portion R3 continues to provide data scanning signals to the multiple sub-pixels P1~P4 of the display unit P, thereby maintaining the normal operation of the multiple sub-pixels P1~P4 of the display unit P and reducing the impact of the above-mentioned short-circuit problem on the display effect.

[0165] For example, the first power supply voltage is a high power supply voltage VDD, and the second power supply voltage is a low power supply voltage VSS. For example, the horizontal portion vdd2 of the first power supply line vdd is provided on the same layer as the data scan signal line G1 and the sense scan signal line G2, and is provided on a different layer from the vertical portion vdd1 of the first power supply line vdd and is electrically connected to the vertical portion vdd1 through a via (as described above).

[0166] For example, as shown in FIG3A and FIG5D , the third outer ring portion R3 and the second outer ring portion R2 are spaced apart from each other in the first direction D1. In the embodiment of the present disclosure, since the signal lines between the third outer ring portion R3 and the second outer ring portion R2 are densely packed, this can avoid the problems of frequent short circuits and reduced manufacturing yield caused by the third outer ring portion R3 and the second outer ring portion R2 overlapping with too many signal lines extending along the second direction D2. Of course, depending on different layout structures, the lengths of the third outer ring portion R3 and the second outer ring portion R2 in the first direction D1 can be designed as needed to determine which signal lines extending along the second direction D2 the third outer ring portion R3 and the second outer ring portion R2 overlap with in the normal analysis perpendicular to the substrate 1. The embodiment of the present disclosure is not limited to this.

[0167] For example, a longitudinal portion vdd1 of the first power line vdd is located at a first edge of the display area 11 in the first direction D1, and a second power line vss is located at a second edge of the display area 11 opposite the first edge in the first direction D1. Thus, the first and second conductive lines R11 and R12 of the second outer ring portion R2 extend from the first non-luminous area 12A to the display area 11 so as to overlap with the longitudinal portion vdd1 of the first power line vdd, and the first and second conductive lines R21 and R22 of the third outer ring portion R3 extend from the second non-luminous area 12B to the display area 11 so as to overlap with the second power line vss.

[0168] For example, the data scan signal line G1 is configured to provide a data scan signal to the data transistors T2 of the first to fourth sub-pixels P1 to P4; the first conductive line R11 of the first outer ring portion R1 provides a sensing scan signal to the sensing transistor T3 of the first sub-pixel P1 and the sensing transistor T3 of the second sub-pixel P2; and the second conductive line R32 of the first outer ring portion R1 is configured to provide a sensing scan signal to the sensing transistor T3 of the third sub-pixel P3 and the sensing transistor T3 of the fourth sub-pixel P4. For example, the first conductive line R31 of the first outer ring portion R1 and the second conductive line R32 of the first outer ring portion R1 both overlap with the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 in a direction perpendicular to the base substrate 1, so as to fully utilize the first outer ring portion R1 to cooperate with all the data lines, thereby being able to address pixel repair issues caused by short circuits between all the data lines and the sensing signal lines.

[0169] For example, in combination with Figure 3A and Figure 5D, the parts of the first wire R11 of the first outer ring portion R1 that overlap with the channel regions of the sensing transistors T3 of the third sub-pixel P3 and the fourth sub-pixel P4 respectively constitute the gate T3g-3 of the sensing transistor T3 of the third sub-pixel P3 and the gate T3g-4 of the sensing transistor T3 of the fourth sub-pixel P4, and the parts of the second wire R12 of the first outer ring portion R1 that overlap with the channel regions of the sensing transistors T3 of the first sub-pixel P1 and the second sub-pixel P2 respectively constitute the gate T3g-1 of the sensing transistor T3 of the first sub-pixel P1 and the gate T3g-2 of the sensing transistor T3 of the second sub-pixel P2.

[0170] 5D , the data scan signal line G1 and the sensing scan signal line G2 are located in the same layer, for example, in the second conductive layer 200 . Therefore, the outer ring portions, for example, the first outer ring portion R1 , the second outer ring portion R2 , and the third outer ring portion R3 are all located in the same conductive layer, for example, the second conductive layer 200 .

[0171] 3A and 5D , the annular area of ​​the first outer ring portion R1 is greater than the annular area of ​​the third outer ring portion R3 and greater than the annular area of ​​the second outer ring portion R2. For example, the length of the first outer ring portion R1 in the first direction D1 is greater than the length of the second outer ring portion R2 in the first direction D1 and greater than the length of the third outer ring portion R3 in the first direction D1, and the width of the first outer ring portion R1 in the second direction D2 is greater than the width of the second outer ring portion R2 in the second direction D2 and greater than the width of the third outer ring portion R3 in the second direction D2. The first outer ring portion R1 extends from a non-display area 12A on a first side of the display area 11 of a display unit along the first direction D1 into the display area 11, and penetrates the display area 11 along the first direction D1 to enter the non-display area 12B on a second side of the display area 11. However, the third outer ring portion R3 and the second outer ring portion R2 do not span the entire display area 11 of a display unit P along the first direction.

[0172] For example, the portion of the data scan signal line G1 that overlaps with the channel region of the data transistor of the third sub-pixel P3 constitutes the gate of the data transistor T2 of the third sub-pixel P3, and the portion that overlaps with the channel region of the data transistor of the fourth sub-pixel P4 constitutes the gate of the data transistor T2 of the fourth sub-pixel P4.

[0173] For example, as shown in Figures 3B and 5F, the display unit P further includes: an auxiliary scan line G3, a first connection line CL1, and a second connection line CL2. The auxiliary scan line G3 extends along a first direction D1; the first connection line CL1 connects the auxiliary scan line G3 with the data scan signal line G1; the second connection line CL2 is spaced apart from the first connection line CL1 in a second direction D2 and connects the auxiliary scan line G3 with the data scan signal line G1; the auxiliary scan line G3 is configured to provide a first scan signal to the data transistor T2 of the first subpixel P1 and the data transistor T2 of the second subpixel P2; the first conductive line R11 of the first outer ring portion R1 and the second conductive line R12 of the first outer ring portion R1 both overlap with the first connection line CL1 and the second connection line CL2 in a direction perpendicular to the base substrate 1. Thus, the above-mentioned pixel repair in the event of a short circuit can be solved for both the first connection line CL1 and the second connection line CL2.

[0174] 5D , the data scan signal line G1 and the auxiliary scan line G3 are disposed on the same layer, and are also disposed on the same layer as the gate T1g of the driving transistor T1, and are both located in the second conductive layer 200. The first connection line CL1 and the second connection line CL2 are located in the third conductive layer 300, and are disposed in a different layer from the data scan signal line G1.

[0175] For example, as shown in Figures 5D and 5F, the auxiliary scanning line G3 has a first end and a second end opposite to each other in the first direction D1; the first connecting line CL1 connects the first end and the second outer ring portion R2 of the auxiliary scanning line G3, and the second connecting line CL2 connects the second end and the third outer ring portion R3 of the auxiliary scanning line G3.

[0176] For example, in conjunction with Figures 5E-5F and Figures 3A-3B , the first end of the auxiliary scan line G3 is connected to the first end of the first connection line CL1 via a via V71 penetrating the third insulating layer 103, and the second end of the first connection line CL1 is connected to the data scan signal line G1 via a via V61 penetrating the third insulating layer 103. The second end of the auxiliary scan line G3 is connected to the first end of the second connection line CL2 via a via V72 penetrating the third insulating layer 103, and the second end of the second connection line CL2 is connected to the data scan signal line G1 via a via V62 penetrating the third insulating layer 103. For example, the second end of the first connection line CL1 is connected to the second outer ring portion R2 via a via V61, and the second end of the second connection line CL2 is connected to the third outer ring portion R3 via a via V62.

[0177] Figure 5L is a schematic plan view of the pixel-defining layer of the display unit shown in Figure 3B . For example, referring to Figures 3B and 5L , the pixel-defining layer 6 includes a portion located in the non-display area 12A. The portion of the pixel-defining layer 6 located in the non-display area 12A includes a groove 63 that is recessed away from the display area. The orthographic projection of the connecting portion 30 on the base substrate 1 is at least partially located within the orthographic projection of the groove 63 on the base substrate 1. The groove 63 has an edge 631 facing the connecting portion 30. A gap exists between the edge 301 of the connecting portion 30 that is away from the display area 11 in the first direction D1 and the edge 631 of the groove 63. In other words, the edge 631 of the groove 63 is located on the side of the edge 301 of the connecting portion 30 that is away from the display area 11.

[0178] For example, referring to FIG3A , the intermediate connector 43 does not overlap with the first portion 21 and the second portion of the first electrode in a direction perpendicular to the main surface of the base substrate 1. Therefore, when a conventional laser is used to cut the wire adjacent to the intermediate connector 43 that is short-circuited to the intermediate connector 43 during pixel repair, short circuits caused by contact between the first electrode 2 and the intermediate connector 43 after melting can be avoided.

[0179] For ease of illustration, the approximate location of the intermediate connecting portion 43 is indicated by a dashed line in FIG5D . For example, referring to FIG5D , the second conductive line R21 of the first outer ring portion R1 is located on a side of the first conductive line R11 of the first outer ring portion R1 in the second direction D2, away from the data scan signal line G1. For example, in the second direction D2, a first distance d1 exists between the intermediate connecting portion 43 and the first conductive line R11 of the first outer ring portion R1, and a second distance d2 exists between the intermediate connecting portion 43 and the second conductive line R12 of the first outer ring portion R1, where the second distance d2 is greater than the first distance d1. For example, in the embodiments shown in Figures 3A and 5D, the sensing scan signal line G2 includes a main line G20 extending along the first direction D1, the first outer ring portion R1 is connected to the main line G20 and protrudes from the main line G20 in the second direction D2 in a direction away from the data scan signal line G1, so that the second wire R21 of the first outer ring portion R1 goes deeper into the area of ​​the first sub-pixel P1 and the second sub-pixel P2 located on the side of the sensing scan signal line G2 away from the data scan signal line G1 in the second direction D1, so that the anodes of the first sub-pixel P1 and the second sub-pixel P2 are more easily extended to the annular area of ​​the first outer ring portion R1. Therefore, making the second distance d2 greater than the first distance d1 is beneficial to ensure that the first electrode (for example, the second portion 22 of the first electrode) extending from the area of ​​the first sub-pixel P1 or the second sub-pixel P2 to the annular area of ​​the first outer ring portion R1 is avoided from overlapping with the intermediate connection portion 43, so as to ensure that the above-mentioned problem of short circuit between the intermediate connection portion 43 and the first electrode during the pixel repair process is avoided.

[0180] The first distance d1 refers to the distance from any position 1 on the edge of the first conductive wire R11 of the intermediate connecting portion 43 close to the first outer ring portion R1 to the edge of the second conductive wire R12 of the first outer ring portion R1 close to the first outer ring portion R1. The second distance d2 refers to the distance from any position 2 on the edge of the second conductive wire R12 of the intermediate connecting portion 43 close to the first outer ring portion R1 to the edge of the first conductive wire R11 of the first outer ring portion R1 close to the first outer ring portion R1. Position 1 and position 2 are located on the same straight line perpendicular to the first direction D1 (i.e., perpendicular to the extension direction of the edge of the second conductive wire R12 of the first outer ring portion R1 close to the first outer ring portion R1).

[0181] For example, the sub-pixel includes an upper sub-pixel and a lower sub-pixel arranged in the second direction D2. Taking the upper sub-pixel and the lower sub-pixel as an example, the first sub-pixel P1 and the third sub-pixel P3 are respectively used. Referring to Figure 3B, the first electrode 2 of the first sub-pixel P1 overlaps with the first wire R11 of the first outer ring portion R1 in a direction perpendicular to the main surface of the base substrate 1 and includes a first protrusion 21a located within the ring of the first outer ring portion R1. The first electrode 2 of the third sub-pixel P3 overlaps with the second wire R12 of the first outer ring portion R1 in a direction perpendicular to the main surface of the base substrate 1 and includes a second protrusion 22a located within the ring of the first outer ring portion R1. The length of the first protrusion 21a in the second direction D2 is greater than the length of the second protrusion 22a in the second direction D2. The intermediate connecting portion 43 is located between the first protrusion 21a and the second protrusion 22a and does not overlap with the first protrusion 21a and the second protrusion 22a in the direction perpendicular to the main surface of the base substrate 1. Thus, when the above-mentioned length of the first protruding portion 21a of the first electrode extending from the area of ​​the first sub-pixel P1 or the second sub-pixel P2 to the annular area of ​​the first outer ring portion R1 is greater than the above-mentioned length of the second protruding portion 22a of the first electrode extending from the area of ​​the third sub-pixel P3 or the fourth sub-pixel P4 to the annular area of ​​the first outer ring portion R1, it is ensured that the first electrodes of each sub-pixel are avoided from overlapping with the intermediate connecting portion 43, so as to ensure that the above-mentioned problem of short circuit between the intermediate connecting portion 43 and the first electrode during the pixel repair process is avoided.

[0182] For example, referring to Figures 4A, 5A, and 5I-5K, in a direction perpendicular to the main surface of the base substrate 1, the first electrode 2 is located on the side of the intermediate connecting portion 43 away from the base substrate 1, and the intermediate connecting portion 43 is provided in the same layer as the first transfer electrode 4. Therefore, if the intermediate connecting portion 43 overlaps with the first electrode 2, cutting the wire near the intermediate connecting portion 43 that is short-circuited to the intermediate connecting portion 43 to repair the pixel will also cut the first electrode 2 located above the intermediate connecting portion 43. The two can easily fuse and contact with each other, causing a short circuit. The design solution of the above-mentioned embodiment of the present disclosure that avoids the overlap of the intermediate connecting portion 43 and the first electrode 2 can avoid this problem.

[0183] Figure 6A is a schematic diagram of a first subpixel of a display unit of another display substrate provided in at least one embodiment of the present disclosure; Figure 6B is an enlarged view of a portion of Figure 6A including the connection structure; and Figure 6C is a schematic cross-sectional view taken along line AA' in Figure 6A. The embodiment shown in Figures 6A-6C differs from the embodiment shown in Figure 3B in the following ways.

[0184] FIG7A is a schematic plan view of the first conductive layer of the display unit where the sub-pixel shown in FIG6A is located; FIG7B is a schematic plan view of the first insulating layer of the display unit where the sub-pixel shown in FIG6A is located; FIG7C is a schematic plan view of the semiconductor layer of the display unit where the sub-pixel shown in FIG6A is located; FIG7D is a schematic plan view of the second conductive layer of the display unit where the sub-pixel shown in FIG6A is located; FIG7E is a schematic plan view of the third insulating layer of the display unit where the sub-pixel shown in FIG6A is located; FIG7F is a schematic plan view of the third conductive layer of the display unit where the sub-pixel shown in FIG6A is located; and FIG7G is a schematic plan view of the fourth insulating layer of the display unit where the sub-pixel shown in FIG6A is located;

[0185] Figure 7H is a plan schematic diagram of the fifth insulating layer of the display unit where the sub-pixel shown in Figure 6A is located; Figure 7I is a plan schematic diagram of the fourth conductive layer of the display unit where the sub-pixel shown in Figure 6A is located; Figure 7J is a plan schematic diagram of the fifth conductive layer of the display unit where the sub-pixel shown in Figure 6A is located; Figure 7K is a plan schematic diagram of the sixth conductive layer of the display unit where the sub-pixel shown in Figure 6A is located; Figure 7L is a plan schematic diagram of the pixel defining layer of the display unit where the sub-pixel shown in Figure 6A is located.

[0186] 6A-6B , at least one embodiment of the present disclosure further provides a display substrate, comprising a display unit P (as shown in FIG1 ), the display unit P comprising a sub-pixel, the sub-pixel comprising a connection structure 30 and a first transfer electrode 4, the connection structure 30 electrically connecting the first portion 21 of the first electrode and the second portion 22 of the first electrode, and comprising a first extension portion 31, a second extension portion 32, a first sub-portion 30a, a second sub-portion 30b, and a third sub-portion 30c, the third sub-portion 30c being also the protrusion, the first extension portion 31 and the second extension portion 32 respectively extending from the display area 11 to the non-luminous area 12 along a first direction D1, the first end of the first extension portion 31 being electrically connected to the first portion 21 of the first electrode, and the first end of the second extension portion 32 being electrically connected to the second portion 22 of the first electrode; the first sub-portion 30a The second sub-portion 30b and the third sub-portion 30c are all located in the non-luminescent area 12. The first sub-portion 30a and the second sub-portion 30b are connected to the second ends of the first extension portion 31 and the second extension portion 32, respectively, and extend along a second direction D2 that intersects the first direction D1. For example, the first direction D1 is perpendicular to the second direction D2. The third sub-portion 30 connects the first sub-portion 30a and the second sub-portion 30b and protrudes from the first sub-portion 30a and the second sub-portion 30b toward the display area 11 along the first direction D1. The portion of the first transfer electrode 4 located in the display area 11 is electrically connected to the first electrode T1s of the drive transistor T1 and includes a portion located in the non-luminescent area 12. The third sub-portion 30c (i.e., the protruding portion) is connected to the portion of the first transfer electrode 4 located in the non-luminescent area 12 via a via in the non-luminescent area 12. The first sub-portion 30a and the second sub-portion 30b are both located on the side of the connection pad 42b of the first transfer electrode 4, the third via V03, and the fourth via V04 that is away from the display area 11. That is, in this embodiment of the present disclosure, the first extension portion 31 connected to the first portion 21 of the first electrode, the second extension portion 32 connected to the second portion 22 of the first electrode, the first sub-portion 30a, the second sub-portion 30b and the third sub-portion 30 (i.e., the protrusion) are connected to each other to form an overall structure, which first goes around to the outside of the connection pad 42b, the third via V03 and the fourth via V04 in the first direction D1 away from the display area 11, and then turns back toward the display area 11 through the protrusion. The protrusion is electrically connected to the connection pad 42b of the first transfer electrode 4 through the third via V03 and the fourth via V04 in sequence, and the portion of the first transfer electrode 4 located in the display area 11 is electrically connected to the first electrode of the driving transistor T1. As a result, the first portion 21 of the first electrode and the second portion 22 of the first electrode are both electrically connected to the first electrode of the driving transistor T1.

[0187] 6A-6B and 7I , the first sub-portion 30 a and the second sub-portion 30 b are both located on a side of the connection pad 42 b of the first switching electrode 4 away from the display area 11 ; the first sub-portion 30 a is connected to the second end of the first extension portion 31 , the second sub-portion 30 b is connected to the second end of the second extension portion 32 , and the third sub-portion 30 c is connected to the first sub-portion 30 a and the second sub-portion 30 b .

[0188] The first transfer electrode 4 includes: a first transfer portion 41 and a second transfer portion 42. The first transfer portion 41 is located in the display area 11 and is electrically connected to the first electrode T1s of the driving transistor T1; the second transfer portion 42 is located in the non-luminous area 12 and is electrically connected to the first transfer portion 41. The display unit also includes a second transfer electrode 5 located in the non-luminous area 12. The second transfer electrode 5 is located between the connecting portion 30 and the first transfer portion 41 in a direction perpendicular to the main surface of the base substrate 1. In conjunction with Figures 6C, 7B, 7E and 7G, the connecting portion 3 0 is provided in a different layer from the second transition portion 42, the third sub-portion 30c is electrically connected to the second transition electrode 5 via the third via hole V03 in the non-luminous area 12, and the second transition electrode 5 is electrically connected to the second transition portion 42 of the first transition electrode 4 via the fourth via hole V04, that is, electrically connected to the connection pad 42b of the second transition portion 42; the extension direction of the first extension portion 31 and the second extension portion 32 is the first direction D1, and the direction perpendicular to the first direction D1 is the second direction D2, and the third via hole V03 and the fourth via hole V04 are arranged at intervals in the second direction D2. Therefore, arranging the third via hole V03 and the fourth via hole V04 at intervals in the second direction D2 is beneficial to reducing the space occupied by the whole formed by the third via hole V03 and the fourth via hole V04 for realizing the electrical connection between the connecting portion 30 and the second adapter portion 42 in the first direction D1, thereby reducing the length of the overlapping portion between the whole formed by the third via hole V03 and the fourth via hole V04 and the first extension portion 31 and the second extension portion 32 extending along the first direction D1, so that there are relatively few structures around the first extension portion 31 or the second extension portion 32, which provides sufficient space for the operation of cutting off the first extension portion 31 or the second extension portion 32 to realize pixel repair, reduces the difficulty of the cutting operation, and improves the accuracy of the cutting operation.

[0189] For example, referring to Figures 6A-6B and 7I, the first sub-section 30a and the second sub-section 30b are spaced apart from each other in the second direction D2 and connected via the third sub-section 30c (i.e., the protrusion). For example, the first sub-section 30a, the second sub-section 30b, and the third sub-section 30c form a continuous, one-piece structure. Alternatively, in other embodiments, the first sub-section 30a and the second sub-section 30b can also be directly connected to each other to form a continuous, one-piece structure.

[0190] For example, referring to Figures 6A and 6C, the orthographic projections of the third via V03 and the fourth via V04 on the main surface of the base substrate do not overlap. For example, in some embodiments, the third via V03 and the fourth via V04 may overlap in the second direction D2, that is, if a straight line is drawn along the second direction D2 on the main surface of the base substrate 1, the orthographic projection of the straight line passes through the orthographic projections of the third via V03 and the fourth via V04 on the main surface of the base substrate 1; further, for example, the centers (geometric centers) of the orthographic projections of the third via V03 and the fourth via V04 on the main surface of the base substrate 1 are located on the same straight line extending along the second direction D2.

[0191] For example, referring to Figures 6C and 7H , the display unit P further includes a planar layer 105. In a direction perpendicular to the main surface of the base substrate 1, the planar layer 105 is located between the first electrode 2 and the second transfer electrode 5. The material of the planar layer 105 is the same as that of the previous embodiment. The planar layer 105 does not cover the third via hole V03 and the fourth via hole V04, thereby facilitating connection of the connecting portion 30 to the second transfer electrode 5 via the third via hole V03 in the non-luminescent area. This avoids the problem of low via hole production yield and significant impact on surrounding structures caused by space limitations when drilling holes in the insulating layer in the display area 11. The opening O of the planar layer 105 located in the non-luminescent area 12A exposes the third via hole V03 and the fourth via hole V04. Because the planarization layer 105 is relatively thick in a direction perpendicular to the substrate 1 (e.g., greater than 6000 angstroms in a direction perpendicular to the substrate 1 ) to meet its insulation and planarization function, if a via hole is formed through the planarization layer 105 to connect the connection portion 30 to the second transfer electrode 5 , the via hole will have different dimensions parallel to the substrate than other via holes in the planarization layer 105 . For example, the via hole will be required to have a larger dimension parallel to the substrate. Consequently, when forming multiple via holes through the planarization layer 105 using the same patterning process, it is difficult to simultaneously meet these different dimensions, ensuring mask alignment is difficult. Furthermore, the planarization layer 105 is relatively thick, making it difficult to accurately meet these different dimensions during etching. However, the above-described solution of the disclosed embodiment avoids the need to form a via hole through the planarization layer 105 to connect the connection portion 30 to the second transfer electrode 5 , thereby avoiding the aforementioned problems.

[0192] For example, referring to FIG. 7F , the length l1 of the second transition electrode 5 in the second direction D2 is greater than the length l2 of the second transition electrode 5 in the first direction D1. This allows the second transition electrode 5 to be connected to both the electrodes in the third via hole V03 and the fourth via hole V04 via the second transition electrode 5, thereby reducing the space occupied by the second transition electrode 5 in the first direction D1. This helps, on the one hand, reduce the shading of the transparent non-luminous area by the second transition electrode 5 (e.g., made of an opaque material such as a metal material, a light-shielding layer including an organic material, a black light-shielding layer, etc.), thereby improving the aperture ratio. On the other hand, it reduces the length of the overlap between the second transition electrode 5 and the first extension portion 31 and the second extension portion 32 extending along the first direction D1, thereby reducing the number of structures surrounding the first extension portion 31 or the second extension portion 32. This provides ample space for severing the first extension portion 31 or the second extension portion 32 to perform pixel repair, thereby reducing the difficulty of the severing operation and improving the accuracy of the severing operation.

[0193] Other features not mentioned in the embodiments shown in FIG. 6A-6C and FIG. 7A-7L are the same as those in FIG. 5A-5L , and reference may be made to the previous description, which will not be repeated here.

[0194] As shown in FIG8 , at least one embodiment of the present disclosure further provides a display device 1000. As shown in FIG8 , the display device 1000 includes any one of the display substrates 10 provided in the embodiments of the present disclosure. The display device 1000 may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other types of devices having a display function. The embodiments of the present disclosure are not limited thereto.

[0195] The structure, function, and technical effects of the display device provided by the embodiment of the present disclosure can refer to the corresponding description of the display substrate 10 provided by the above embodiment of the present disclosure, and will not be repeated here.

[0196] For example, the display device 1000 provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, and the embodiments of the present disclosure are not limited thereto.

[0197] There are a few points to note:

[0198] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0199] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0200] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0201] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the scope defined in the claims.

Claims

1. A display substrate, comprising: A display unit comprising a display area and a non-luminescent area, wherein the display area includes a sub-pixel, the sub-pixel includes a driving transistor and a light-emitting device, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device, and includes a gate, a first electrode, and a second electrode; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode including a first portion and a second portion spaced apart from each other; The display unit further includes: a connecting structure electrically connecting a first portion of the first electrode and a second portion of the first electrode, and comprising a first extension portion, a second extension portion, and a connecting portion, wherein the first extension portion and the second extension portion respectively extend from the display area to the non-luminescent area along a first direction, a first end of the first extension portion is electrically connected to the first portion of the first electrode, a first end of the second extension portion is electrically connected to the second portion of the first electrode, and the connecting portion is located in the non-luminescent area and connects the second end of the first extension portion and the second end of the second extension portion; and A first switching electrode is electrically connected to the first pole of the driving transistor and includes a strip portion extending from the display area to the non-luminous area along the first direction, and a connection pad located in the non-luminous area, connected to the strip portion and located at one end of the strip portion away from the display area in the first direction, the connection portion is connected to the connection pad in the non-luminous area through a via, and the connection pad is spaced apart from the first extension portion and the second extension portion in a second direction intersecting the first direction.

2. The display substrate according to claim 1, wherein The distance between the connection pad and the first extension portion in the second direction is a first distance, and the distance between the connection pad and the second extension portion in the second direction is a second distance; A length of at least one of the first interval and the second interval in the second direction is greater than or equal to a line width of the first extension portion in the second direction, or greater than or equal to a line width of the second extension portion in the second direction, or greater than or equal to a line width of a portion of the connecting portion extending along the second direction in the first direction.

3. The display substrate according to claim 2, further comprising a base substrate, wherein The display unit is arranged on the base substrate; The first switching electrode is located on a side of the driving transistor close to the base substrate.

4. The display substrate according to any one of claims 1 to 3, wherein: The display substrate further comprises a base substrate, and the display unit is arranged on a main surface of the base substrate; The first switching electrode includes: a first transfer portion, located in the display area and electrically connected to the first electrode of the driving transistor; and The second transfer portion is located in the non-luminous area and is electrically connected to the first transfer portion, wherein the second transfer portion includes the connection pad and the portion of the strip portion located in the non-luminous area, and the display unit further includes a second transfer electrode located in the non-luminous area, the second transfer electrode is perpendicular to the main surface of the base substrate Directionally located between the connecting portion and the second transition portion; The connecting portion and the second transition portion are arranged in different layers, the connecting portion is electrically connected to the second transition electrode via a first via hole in the non-luminous area, the second transition electrode is electrically connected to the second transition portion of the first transition electrode via a second via hole, the first via hole and the second via hole are arranged at intervals in the first direction, and the second via hole is located on the side of the first via hole and the first sub-portion and the second sub-portion of the connecting structure close to the display area.

5. The display substrate according to claim 4, wherein: The display unit further includes a planar layer, wherein the planar layer is located between the first electrode and the second switching electrode in a direction perpendicular to the base substrate; The planar layer covers the second via hole and does not cover the first via hole.

6. The display substrate according to claim 4 or 5, wherein: The length of the connection pad in the second direction is less than or equal to the length of the connection pad in the first direction.

7. The display substrate according to any one of claims 4 to 6, wherein: The connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is connected to the second end of the first extending portion, the second sub-portion is connected to the second end of the second extending portion, and the first sub-portion and the second sub-portion are both located on a side of the connection pad between the first via hole and the first transfer electrode away from the display area; A distance between the first via hole and the second via hole in the first direction is greater than a line width of the first sub-portion or the second sub-portion in the first direction.

8. The display substrate according to any one of claims 4 to 7, wherein: The width of the second via hole in the second direction is less than or equal to the width of the second via hole in the first direction.

9. The display substrate according to any one of claims 4 to 7, wherein: The display substrate further includes a base substrate, the display unit is provided on a main surface of the base substrate; the connecting portion includes a first sublayer, a second sublayer, and a third sublayer stacked in a direction perpendicular to the main surface of the base substrate, the second sublayer is located between the first sublayer and the third sublayer, and the third sublayer is located on a side of the second sublayer away from the base substrate; The area of ​​the orthographic projection of the third sublayer on the main surface of the base substrate is smaller than at least one of the orthographic projection of the second sublayer on the main surface of the base substrate and the orthographic projection of the first sublayer on the main surface of the base substrate, and is located within the range of at least one of the orthographic projection of the second sublayer on the main surface of the base substrate and the orthographic projection of the first sublayer on the main surface of the base substrate.

10. The display substrate according to any one of claims 1 to 3, wherein: The display substrate further comprises a base substrate, and the display unit is arranged on a main surface of the base substrate; The connecting portion includes a first sub-portion, a second sub-portion, and a protruding portion, wherein the first sub-portion, the second sub-portion, and the protruding portion are all located in the non-luminous area, the first sub-portion and the second sub-portion are respectively connected to the second end of the first extending portion and the second end of the second extending portion and extend along a second direction intersecting the first direction, and the protruding portion is connected to the first sub-portion and the second sub-portion and protrudes from the first sub-portion and the second sub-portion along the first direction toward the display area; The first switching electrode includes: a first transfer portion, located in the display area and electrically connected to the first electrode of the driving transistor; and A second transition portion is located in the non-luminous area and has the connection pad at one end away from the display area in the first direction, wherein the connection pad is connected to the protrusion in the non-luminous area, and a direction perpendicular to the first direction is a second direction; The display unit further includes a second switching electrode located in the non-luminous area, wherein the second switching electrode is located between the protruding portion and the first switching portion in a direction perpendicular to the main surface of the base substrate; The protrusion and the second transfer portion are provided in different layers, the protrusion is electrically connected to the second transfer electrode via a third via hole in the non-luminous area, and the second transfer electrode is electrically connected to the connection pad of the first transfer electrode via a fourth via hole; The first sub-portion and the second sub-portion are both located on a side of the connection pad of the first switching electrode, the third via hole, and the fourth via hole away from the display area.

11. The display substrate according to claim 10, wherein: The third via hole and the fourth via hole are arranged at intervals in the second direction, and the length of the second connecting electrode in the first direction is shorter than the length in the second direction.

12. The display substrate according to claim 10 or 11, wherein: The display unit further includes a planar layer, wherein the planar layer is located between the first electrode and the second switching electrode in a direction perpendicular to the base substrate; The planar layer does not cover the third via hole and the fourth via hole.

13. The display substrate according to any one of claims 10 to 12, wherein: The length of the second switching electrode in the second direction is greater than the length of the second switching electrode in the first direction.

14. The display substrate according to any one of claims 1 to 13, comprising: a scanning signal line, comprising at least one annular outer ring portion, including a portion extending as a whole along a first direction, passing through the non-luminous area and the display area, transmitting a sensing scanning signal, and comprising a sensing scanning signal line, wherein the sensing scanning signal line comprises an annular first outer ring portion, and the at least one annular outer ring portion comprises the first outer ring portion; and a sensing signal line for transmitting a sensing signal, wherein the sub-pixel further includes a sensing transistor, the sensing scanning signal line is configured to provide the sensing scanning signal to the sensing transistor, the sensing transistor is configured to detect an electrical characteristic of the sub-pixel using the sensing signal under the control of the sensing scanning signal, and the second electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the first electrode of the light-emitting element; The sub-pixel further includes a middle connection portion extending along a first direction, the sensing signal line is connected to the middle connection portion through a first connection via hole, and the second electrode of the sensing transistor is connected to the middle connection portion through a second connection via hole; The intermediate connecting portion is located in the annular space inside the first outer ring portion.

15. The display substrate according to claim 14, wherein: The non-luminescent area of ​​the display unit includes a first non-luminescent area and a second non-luminescent area, the first non-luminescent area is located on a first side of the display area in the first direction, and the second non-luminescent area is located on a second side of the display area in the first direction opposite to the first side; The first outer ring portion extends from the first non-luminous area to the display area and then to the second non-luminous area.

16. The display substrate according to any one of claims 14-15, further comprising: a base substrate, wherein the display unit is provided on a main surface of the base substrate; A longitudinal signal line is provided on the base substrate and located in the display area, and extends as a whole along a second direction intersecting with the first direction, wherein each of the at least one outer ring portion includes: a first conductive line extending along the first direction as a whole and extending from the non-luminescent area to the display area; and The second conductive line extends along the first direction as a whole and extends from the non-luminous area to the display area, and is spaced apart from the first conductive line in the second direction, wherein: The first conductive line and the second conductive line both overlap the vertical signal line in a direction perpendicular to the main surface of the base substrate.

17. The display substrate according to claim 16, comprising: a first power line connected to the first voltage terminal and configured to provide a first power voltage to the sub-pixel, and comprising a longitudinal portion extending entirely along the second direction, wherein the longitudinal signal line comprises the longitudinal portion of the first power line; The first conductive line of the first outer loop portion and the second conductive line of the first outer loop portion overlap with a longitudinal portion of the first power line in a direction perpendicular to the base substrate.

18. The display substrate according to claim 17, wherein: The scanning signal line further includes: a data scanning signal line, comprising a portion extending entirely along the first direction, for transmitting a data scanning signal; and Data signal line, transmits data signal, wherein The sub-pixel further includes a data writing transistor, the data scanning signal line is configured to provide the data scanning signal to the gate of the data writing transistor, and the data writing transistor is configured to transmit the data signal to the driving transistor under the control of the data scanning signal; The longitudinal signal line includes the data signal line, and the first conductive line and the second conductive line of the first outer ring portion both overlap with the data signal line in a direction perpendicular to the base substrate.

19. The display substrate according to claim 18, wherein: The data scanning signal line includes a second outer ring portion in a ring shape, and the first conductive line and the second conductive line of the second outer ring portion both overlap with a longitudinal portion of the first power line in a direction perpendicular to the base substrate.

20. The display substrate according to any one of claims 14 to 19, wherein: The display substrate further comprises a base substrate, and the display unit is arranged on a main surface of the base substrate; The intermediate connection portion does not overlap with the first portion and the second portion of the first electrode in a direction perpendicular to the main surface of the base substrate.

21. The display substrate according to claim 20, wherein: In a second direction intersecting the first direction, there is a first distance between the intermediate connection portion and the first conductive wire of the first outer ring portion, and a second distance between the intermediate connection portion and the second conductive wire of the first outer ring portion, and the first distance is greater than the second distance.

22. The display substrate according to claim 21, wherein The subpixel includes an upper subpixel and a lower subpixel arranged in the second direction, the first electrode of the upper subpixel overlaps with the first conductive line of the first outer ring portion in a direction perpendicular to the base substrate and includes a first protruding portion located within a ring shape of the first outer ring portion, the first electrode of the lower subpixel overlaps with the second conductive line of the first outer ring portion in a direction perpendicular to the base substrate and includes a second protruding portion located within a ring shape of the first outer ring portion, and a length of the first protruding portion in the second direction is greater than a length of the second protruding portion in the second direction; The intermediate connecting portion is located between the first protruding portion and the second protruding portion and does not overlap with the first protruding portion and the second protruding portion in a direction perpendicular to the base substrate.

23. The display substrate according to any one of claims 14 to 22, wherein: The display substrate further comprises a base substrate, and the display unit is arranged on a main surface of the base substrate; The first electrode is located on a side of the intermediate connecting portion away from the base substrate, and the intermediate connecting portion and the first switching electrode are provided on the same layer.

24. The display substrate according to any one of claims 14 to 23, wherein: The display substrate further comprises a base substrate, and the display unit is arranged on the base substrate; The active layer of the sensing transistor is located between the intermediate connecting portion and the second electrode of the sensing transistor, and the second electrode of the sensing transistor is also electrically connected to the active layer of the sensing transistor through a second connecting via; The active layer of the sensing transistor at least partially overlaps with the intermediate connection portion in a direction perpendicular to the substrate; the second connection via is a through hole formed by a first deep via and a second deep via penetrating each other; the second connection via exposes an upper surface of the active layer of the sensing transistor away from the substrate and a side surface of the active layer of the sensing transistor intersecting with the upper surface, and exposes the intermediate connection portion; The second electrode of the sensing transistor contacts both the upper surface and the side surface of the active layer of the sensing transistor through the second connection via, and contacts the intermediate connection portion through the second connection via.

25. The display substrate according to claim 24, wherein: The second electrode of the sensing transistor includes an outer portion close to the non-luminous region and an inner portion away from the non-luminous region in the first direction, the outer portion and the inner portion being connected to each other; The active layer of the sensing transistor overlaps with an inner portion of the second electrode of the sensing transistor in a direction perpendicular to the base substrate, and the second connecting via exposes an end portion of an upper surface of the active layer of the sensing transistor close to the non-luminous region in the first direction and a first side surface of the active layer of the sensing transistor, and the first side surface faces the non-luminous region in the first direction.

26. The display substrate according to claim 24, wherein: The second electrode of the sensing transistor includes an outer portion close to the non-luminous region and an inner portion away from the non-luminous region in the first direction, the outer portion and the inner portion being connected to each other; The active layer of the sensing transistor and the outer portion of the second electrode of the sensing transistor are perpendicular to the substrate. The second connecting vias overlap in the direction of the substrate, and expose the end of the upper surface of the active layer of the sensing transistor away from the non-luminous area in the first direction and the second side surface of the active layer of the sensing transistor, and the second side surface is away from the non-luminous area in the first direction.

27. A display substrate comprising: A display unit comprising a display area and a non-luminescent area, wherein the display area includes a sub-pixel, the sub-pixel includes a driving transistor and a light-emitting device, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device, and includes a gate, a first electrode, and a second electrode; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode including a first portion and a second portion spaced apart from each other; The display unit further includes a sub-pixel, the sub-pixel including a connection structure, the connection structure electrically connecting a first portion of the first electrode and a second portion of the first electrode, and including a first extension portion, a second extension portion, a first sub-portion, a second sub-portion, and a protrusion, wherein the first extension portion and the second extension portion respectively extend from the display area to the non-luminescent area along a first direction, a first end of the first extension portion is electrically connected to the first portion of the first electrode, and a first end of the second extension portion is electrically connected to the second portion of the first electrode; The first sub-portion, the second sub-portion, and the protrusion are all located in the non-luminous area, the first sub-portion and the second sub-portion are respectively connected to the second end of the first extension portion and the second end of the second extension portion and extend along a second direction intersecting the first direction, and the protrusion is connected to the first sub-portion and the second sub-portion and protrudes from the first sub-portion and the second sub-portion toward the display area along the first direction; and The first switching electrode is electrically connected to the first electrode of the driving transistor and includes a portion located in the non-luminous area, wherein the protrusion is connected to the portion of the first switching electrode located in the non-luminous area via a via hole.

28. A display substrate comprising: A display unit comprising a display area and a non-luminescent area, wherein the display area comprises sub-pixels, the sub-pixels comprising a driving transistor and a light-emitting device, the driving transistor being configured to control the magnitude of a driving current flowing through the light-emitting device and comprising a gate, a first electrode, and a second electrode; the light-emitting device being configured to receive the driving current and be driven by the driving current to emit light; a scanning signal line, comprising at least one annular outer ring portion, a portion extending as a whole along a first direction, passing through the non-luminous area and the display area, and transmitting a sensing scanning signal, and comprising a sensing scanning signal line, wherein the sensing scanning signal line comprises a portion extending as a whole along a second direction intersecting with the first direction, passing through the non-luminous area and the display area, and transmitting a sensing scanning signal, the sensing scanning signal line comprises a first annular outer ring portion, and the at least one annular outer ring portion comprises the first outer ring portion; and A sensing signal line transmits a sensing signal, wherein the sub-pixel further comprises a sensing transistor, the sensing scanning signal line is configured to provide the sensing scanning signal to the sensing transistor, the sensing transistor is configured to detect the electrical characteristics of the sub-pixel using the sensing signal under the control of the sensing scanning signal, the second electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the first electrode of the light-emitting element; the sub-pixel further comprises a sensing transistor along the first sensing scanning signal line. An intermediate connecting portion extending in one direction, the sensing signal line is connected to the intermediate connecting portion through a first connecting via, and the second electrode of the sensing transistor is connected to the intermediate connecting portion through a second connecting via; the intermediate connecting portion is located in an annular space inside the first outer ring portion.

29. A display device comprising the display substrate according to any one of claims 1 to 28.

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