Instruction scheduling method and apparatus, and processor, electronic apparatus and storage medium

Abstract

Provided in the embodiments of the present disclosure are an instruction scheduling method and apparatus for a simultaneous multithreading processor, and a processor, an electronic apparatus and a non-transitory storage medium. The instruction scheduling method comprises: in response to there being a plurality of instructions belonging to a plurality of threads in a current pipeline stage and a priority thread scheduling policy being enabled, acquiring a priority thread from among the plurality of threads; and on the basis of the priority thread, selecting a target instruction from among the plurality of instructions of the plurality of threads to enter the current pipeline stage.

Description

Instruction scheduling method and device, processor, electronic device and storage medium

[0001] This application claims priority to Chinese Patent Application No. 202410355692.5 filed on March 26, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an instruction scheduling method and apparatus, a processor, an electronic device, and a storage medium. Background Art

[0003] Simultaneous Multithreading (SMT) technology enables a single physical CPU core to process multiple threads in parallel, improving resource utilization and overall performance. When a single thread is running, multiple execution units within the CPU may be idle due to stalls such as cache misses. With SMT, even when a thread is paused, other threads can continue to use these hardware resources, avoiding idling and improving multithreaded throughput and performance-per-watt ratio. The thread scheduling policy affects SMT performance, energy consumption, and fairness between threads. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides an instruction scheduling method for a simultaneous multi-threaded processor, comprising: in response to a current pipeline stage having multiple instructions belonging to multiple threads and enabling a priority thread scheduling policy, obtaining a priority thread among the multiple threads; and selecting a target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage based on the priority thread.

[0005] For example, the instruction scheduling method provided by an embodiment of the present disclosure further includes: in response to the priority thread register being a first value, determining to enable the priority thread scheduling policy and the priority thread.

[0006] For example, the instruction scheduling method provided by an embodiment of the present disclosure further includes: in response to the priority thread register being a second value different from the first value, determining to stop the priority thread scheduling policy.

[0007] For example, in the instruction scheduling method provided in an embodiment of the present disclosure, the target instruction is selected from multiple instructions of the multiple threads according to the priority thread to enter the current pipeline stage, including: when the priority thread meets the preset conditions, the instruction belonging to the priority thread is selected from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage, or, when the priority thread does not meet the preset conditions, a non-priority thread scheduling strategy is adopted to select the target instruction from multiple instructions of the multiple threads to enter the current pipeline stage.

[0008] For example, the instruction scheduling method provided by an embodiment of the present disclosure also includes: in response to the priority thread being inactive in the current pipeline stage, when the priority thread does not meet the preset conditions, a non-priority thread scheduling strategy is used to select a target instruction from multiple instructions of the multiple threads to enter the current pipeline stage, including: using the non-priority thread scheduling strategy to select an instruction that does not belong to the priority thread from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage.

[0009] For example, in the instruction scheduling method provided in an embodiment of the present disclosure, the non-priority thread scheduling strategy includes a polling scheduling strategy.

[0010] For example, in the instruction scheduling method provided in an embodiment of the present disclosure, the preset conditions include the quantitative relationship between the number of instructions belonging to the priority thread and a preset threshold, and the priority thread is active in the current pipeline stage.

[0011] For example, in the instruction scheduling method provided in one embodiment of the present disclosure, the current pipeline stage includes a branch prediction stage, an instruction fetch stage, an instruction decoding stage, an instruction dispatch and renaming stage, an instruction execution stage or an instruction end stage.

[0012] For example, an embodiment of the present disclosure provides an instruction scheduling method, wherein, when there are multiple priority threads among the multiple threads, one priority thread among the multiple priority threads is selected as the target priority thread, wherein the target instruction belongs to the target priority thread.

[0013] At least one embodiment of the present disclosure provides an instruction scheduling device for a simultaneous multi-threaded processor, comprising: an acquisition module, configured to acquire a priority thread among the multiple threads in response to a current pipeline stage having multiple instructions belonging to multiple threads and enabling a priority thread scheduling policy; and a processing module, configured to select a target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage according to the priority thread.

[0014] For example, the instruction scheduling device provided by an embodiment of the present disclosure further includes a priority thread register, wherein the processing module is further configured to: in response to the priority thread register being a first value, determine to enable the priority thread scheduling policy and the priority thread, or, in response to the priority thread register being a second value different from the first value, determine to stop the priority thread scheduling policy.

[0015] For example, in the instruction scheduling device provided in one embodiment of the present disclosure, the processing module is further configured to: when the priority thread meets the preset conditions, select the instruction belonging to the priority thread from the multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage; or, when the priority thread does not meet the preset conditions, adopt a non-priority thread scheduling strategy to select the target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage.

[0016] For example, in the instruction scheduling device provided in one embodiment of the present disclosure, the processing module is further configured to: in response to the priority thread being inactive in the current pipeline stage, when the priority thread does not meet the preset conditions, adopt the non-priority thread scheduling strategy to select an instruction that does not belong to the priority thread from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage.

[0017] For example, in the instruction scheduling device provided in one embodiment of the present disclosure, the processing device is further configured to: when there are multiple priority threads among the multiple threads, select one of the multiple priority threads as the target priority thread, wherein the target instruction belongs to the target priority thread.

[0018] At least one embodiment of the present disclosure provides an instruction scheduling device, comprising: a processing unit; and a storage unit storing computer-executable instructions; wherein, when the computer-executable instructions are executed by the processing unit, the instruction scheduling method provided by any embodiment of the present disclosure is executed.

[0019] At least one embodiment of the present disclosure provides a simultaneous multi-threaded processor, including the instruction scheduling device provided by any embodiment of the present disclosure.

[0020] At least one embodiment of the present disclosure provides a simultaneous multi-threaded processor, comprising a pipeline, wherein the pipeline includes a current pipeline stage, the current pipeline stage having multiple instructions belonging to multiple threads, the pipeline being configured to enable a priority thread scheduling policy, obtain a priority thread among the multiple threads, and being configured to select a target instruction from multiple instructions of the multiple threads to enter the current pipeline stage according to the priority thread.

[0021] For example, the simultaneous multi-threaded processor provided by an embodiment of the present disclosure further includes: a priority thread register configured to mark a priority thread among the multiple threads when the priority thread register is a first value.

[0022] At least one embodiment of the present disclosure provides an electronic device including the simultaneous multi-threaded processor provided by any embodiment of the present disclosure.

[0023] At least one embodiment of the present disclosure provides a non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a computer, the instruction scheduling method provided by any embodiment of the present disclosure is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0025] FIG1 shows a schematic diagram of a pipeline of a processor core;

[0026] FIG2 shows a flow chart of an instruction scheduling method for a simultaneous multi-threaded processor provided by at least one embodiment of the present disclosure;

[0027] FIG3 shows a flowchart illustrating an application example of an instruction scheduling method for a simultaneous multi-threaded processor provided by at least one embodiment of the present disclosure;

[0028] FIG4 shows a schematic block diagram of an instruction scheduling device provided by at least one embodiment of the present disclosure;

[0029] FIG5 shows a schematic block diagram of another instruction scheduling device provided by at least one embodiment of the present disclosure;

[0030] FIG6 shows a schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure; and

[0031] FIG7 shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0034] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0035] In order to improve the performance of the processor core, the processor core can use a pipeline approach, that is, the entire process of an instruction from extraction, decoding, execution, to result writing is divided into multiple pipeline stages, and one instruction can only be in one of the pipeline stages per clock; and the processor core can make multiple instructions run in different pipeline stages.

[0036] FIG1 shows a schematic diagram of a pipeline of a processor core, where the dashed line with an arrow represents a redirected instruction flow.

[0037] As shown in Figure 1, the processor core (e.g., CPU core) of a single-core or multi-core processor uses pipelining technology to improve instruction-level parallelism. The processor core internally includes multiple pipeline stages. For example, after the pipeline inputs program counters from various sources and the multiplexer (Mux) selects the next program counter (PC), the instruction corresponding to that PC undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retirement. Waiting queues are set up between each pipeline stage as needed. These queues are typically first-in, first-out (FIFO) queues. For example, after the branch prediction unit, there's a branch prediction (BP) FIFO queue to store branch prediction results; after the instruction fetch unit, there's an instruction cache (IC) FIFO to cache fetched instructions; after the instruction decode unit, there's a decode (DE) FIFO to cache decoded instructions; and after the instruction dispatch and rename unit, there's a finish (RT) FIFO to cache instructions waiting for completion confirmation. The processor core's pipeline also includes an instruction queue to cache instructions waiting for execution by the instruction execution unit after dispatch and renaming.

[0038] To support high operating frequencies, each pipeline stage may contain multiple pipeline stages (operation cycles), with each pipeline stage performing limited operations to further improve the performance of the processor core. Although each pipeline stage performs limited operations, this allows each clock to be kept to a minimum, thereby improving the performance of the CPU core by increasing the CPU's operating frequency. Each pipeline stage can also further improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology). Superscalar refers to a method of executing multiple instructions in parallel within a cycle. A processor with increased instruction-level parallelism that can process multiple instructions within a cycle is called a superscalar processor. Superscalar processors add additional resources to conventional scalar processors, creating multiple pipelines, each of which executes its own assigned instructions to achieve parallelism.

[0039] Similarly, to improve the parallelism of instruction execution in the processor, the processor can also adopt simultaneous multi-threading (SMT) technology. The processor's pipeline structure for instruction execution (also referred to as "pipeline") can support the simultaneous execution of two or more (hardware) threads, such as SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads), or SMT8 (supporting up to eight concurrent threads). In the pipeline of a processor that supports simultaneous multi-threading technology, the processor's computing resources are shared by multiple threads. For example, each thread can have its own independent logical register; in the queues of various control functions of the pipeline, they can be shared by multiple threads, such as the instruction scheduling queue, or they can be statically divided among multiple threads, such as the instruction reordering queue. Simultaneous multi-threading technology can use the parallelism between threads to improve pipeline resource utilization.

[0040] Processors that use Simultaneous Multithreading (SMT) can operate in either SMT or single-threaded mode. For example, in SMT mode, when one thread encounters a wait state, other threads can continue executing. This effectively improves hardware resource utilization, thereby enhancing the CPU core's multithreading capabilities, overall performance, and performance-per-watt ratio.

[0041] The inventors of the present disclosure have noticed that in the SMT scenario of dynamic resource sharing, since multiple threads compete for hardware resources in the processor in their respective pipeline stages, SMT may affect the performance of a single thread.

[0042] Embodiments of the present disclosure provide an instruction scheduling method, apparatus, processor, chip, and non-transitory storage medium for a simultaneous multithreaded processor. The instruction scheduling method includes: in response to multiple instructions belonging to multiple threads in a current pipeline stage and the activation of a priority thread scheduling policy, obtaining a priority thread among the multiple threads; and selecting a target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage based on the priority thread. This instruction scheduling method can improve the scheduling and execution efficiency of instructions from multiple threads and enhance the performance of the processor core.

[0043] In this disclosure, an operation cycle can be, for example, a clock cycle or a machine cycle, or any other time period in a processor's instruction pipeline that is used to complete a single operation. The execution of an instruction consists of several stages, each of which completes a basic operation (e.g., instruction fetch, memory read, memory write, etc.). The time required to complete a basic operation is called a machine cycle, also known as a CPU cycle.

[0044] FIG2 shows a flowchart of an instruction scheduling method for a simultaneous multi-threaded processor provided by at least one embodiment of the present disclosure.

[0045] As shown in FIG. 2 , the instruction scheduling method provided by this embodiment may include steps S100 to S110 .

[0046] Step S100: In response to a current pipeline stage having multiple instructions belonging to multiple threads and enabling a priority thread scheduling policy, obtaining a priority thread among the multiple threads.

[0047] For step S100, "current pipeline stage" refers to the pipeline stage of the processor as the description object among multiple pipeline stages. For example, the current pipeline stage may include any currently described pipeline stage in the pipeline stages such as the branch prediction stage, the instruction fetch stage, the instruction decoding stage, the instruction distribution and renaming stage, the instruction execution stage or the instruction retirement stage. The embodiments of the present disclosure do not limit this.

[0048] Here, the "priority thread scheduling policy" aims to sort or schedule multiple instructions in the processor pipeline according to the priority assigned to the threads, so as to optimize the execution efficiency of critical tasks or high-priority threads.

[0049] In a simultaneous multi-threaded processor, when there are multiple pending instructions from multiple threads in a pipeline stage (such as the instruction fetch stage, instruction decoding stage, instruction dispatch stage, or instruction execution stage), the processor operates differently depending on whether the priority thread scheduling policy is enabled.

[0050] For example, the processor can determine whether the priority thread scheduling policy is enabled based on the settings of the software being run; for example, when compiling the software, it can determine whether the priority thread scheduling policy is enabled for some or all instructions based on the mode or requirements of the instructions (for example, for real-time control). When it is determined that the priority thread scheduling policy is enabled, the processor can be notified by changing the hardware settings. For example, the processor can include at least one priority thread register, which can be configured to mark whether the priority thread scheduling policy is enabled, and can be further configured to mark a priority thread among multiple threads executed in the processor when the priority thread scheduling policy is enabled, and the priority thread is the thread that needs priority scheduling.

[0051] For example, the priority of each thread can be adjusted based on runtime workload, performance monitoring data, or user input. For example, the priority of each thread can be adjusted based on the thread's task type, urgency, historical performance, preset priority, and other relevant factors. For example, these adjustments can be made in near real time, for example, checking whether an adjustment is needed based on a certain period (e.g., every 1 second).

[0052] Step S110: According to the priority thread, a target instruction is selected from multiple instructions of multiple threads to enter the current pipeline stage.

[0053] For step S110, for example, if the priority thread is active in the current pipeline stage, the instruction belonging to the priority thread can be preferentially selected from multiple instructions of multiple threads as the target instruction to enter the current pipeline stage. For example, the target instruction is decoded in the instruction decoding stage, the target instruction is distributed in the instruction distribution stage, or the target instruction is sent to the execution unit (such as the logic operation unit, ALU unit or LSU unit, etc.) for execution in the instruction execution stage.

[0054] On the other hand, for example, among multiple threads, if the priority thread is inactive in the current pipeline stage, the conventional non-priority thread scheduling strategy can still be used to select corresponding instructions from multiple threads to enter the current pipeline stage.

[0055] On the other hand, for example, for reasons of fairness and system stability or reliability, if the priority thread itself has a large number of instructions to be scheduled (for example, more than 1 / 2 or 3 / 4 of the number of instructions that the instruction queue of the current pipeline stage can accommodate), the non-priority thread scheduling strategy can still be used to select corresponding instructions from multiple threads to enter the current pipeline stage, so that non-priority threads will not be deprived of resources due to not being scheduled for a long time.

[0056] On the other hand, for example, when the instructions in a non-priority thread are a prerequisite for the continued execution of instructions in a priority thread, the instructions of the non-priority thread can be selected as the target instructions to enter the current pipeline stage, and then the instructions belonging to the priority thread can be selected to enter the current pipeline stage.

[0057] In the embodiments of the present disclosure, whether a thread is "active" or "inactive" in the current pipeline stage refers to whether the thread is in a state where it can be executed immediately. For example, a thread is considered "active" when it is in a ready state (rather than waiting or being paused). For example, a thread is considered "inactive" in the current pipeline stage when it has no instructions available for execution.

[0058] Therefore, in the embodiments of the present disclosure, the processor can select an appropriate instruction from multiple instructions in multiple threads as the target instruction based on the specific state or situation of the priority thread and send it to the current pipeline stage. In this way, the processor can ensure that when multiple threads are running simultaneously, while improving the processing efficiency of the priority thread, it also takes into account the fairness, stability, and reliability of multi-thread processing, thereby improving overall processing efficiency.

[0059] In some embodiments of the present disclosure, the above instruction scheduling method may further include step S120 (not shown in the figure).

[0060] Step S120: In response to the priority thread register being at the first value, determining to enable the priority thread scheduling policy and the priority thread.

[0061] For step S120, for example, the priority thread register can be configured to mark whether the priority thread scheduling policy is enabled and record the priority threads among multiple threads. When the priority thread register is the first value, it is determined to enable the priority thread scheduling policy and start the marked priority thread. For example, the priority thread register can use whether the 0th bit is "1" to mark whether the priority thread scheduling policy is enabled. For the SMT4 processor, bits 1-4 are used to record the priority threads among multiple threads. For example, "0001" indicates that the thread labeled 1 is the priority thread, for example, "0100" indicates that the thread labeled 3 is the priority thread, for example, "0101" indicates that the threads labeled 1 and 3 are priority threads; or, for the SMT4 processor, bits 0-3 are used to simultaneously mark whether the priority thread scheduling policy is enabled and record the priority threads among multiple threads. As long as there is "1" in these 4 bits, it means that the priority thread scheduling policy is enabled and the corresponding thread is the priority thread. For example, "0101" indicates that the priority thread scheduling policy is enabled and the threads labeled 1 and 3 are priority threads.

[0062] For example, the “first value” may also include any preset numerical value or any identifier, which is not limited in the embodiments of the present disclosure.

[0063] In some embodiments of the present disclosure, the above instruction scheduling method may further include step S121 (not shown in the figure).

[0064] Step S121: In response to the priority thread register being a second value different from the first value, determining to stop the priority thread scheduling policy.

[0065] In step S121, for example, if the priority thread register is at the second value, it is determined that the priority thread scheduling policy is disabled, and the marked priority thread can be treated as a normal thread (i.e., a non-priority thread), and the non-priority thread scheduling policy can be used to select a target instruction from multiple instructions of multiple threads to enter the current pipeline stage. Here, the "second value" may include a preset numerical value or identifier different from the "first value."

[0066] For example, when it is determined based on the running situation that the priority thread scheduling policy is no longer needed, the priority thread register can be modified from the first value to the second value, thereby notifying the processor to adjust the scheduling policy (eg, switch the scheduling policy).

[0067] In some embodiments of the present disclosure, the above step S110 may further include step S111 or step S112 (not shown in the figure).

[0068] Step S111: when the priority thread meets a preset condition, an instruction belonging to the priority thread is selected from multiple instructions of multiple threads as a target instruction to enter the current pipeline stage.

[0069] In step S111, if the priority thread meets the preset conditions, an instruction belonging to the priority thread may be preferentially selected from multiple instructions of multiple threads as the target instruction to enter the current pipeline stage. Subsequently, instructions belonging to non-priority threads may be selected to enter the current pipeline stage. For example, a non-priority thread scheduling strategy may be used to select instructions from multiple non-priority threads to enter the current pipeline stage.

[0070] Step S112: When the priority thread does not meet the preset conditions, a non-priority thread scheduling strategy is used to select a target instruction from multiple instructions of multiple threads to enter the current pipeline stage.

[0071] For step S112, if the priority thread does not meet the preset conditions, the priority thread is regarded as a non-priority thread to participate in instruction scheduling, and a non-priority thread scheduling strategy can be used to select a target instruction from multiple instructions of multiple threads to enter the current pipeline stage.

[0072] For example, the preset conditions for different pipeline stages may be different. For example, in the instruction distribution stage, the preset conditions may include that the number of instructions belonging to the priority thread among multiple threads is smaller than the number of instructions of other non-priority threads (for example, the number of instructions belonging to the priority thread is less than 1 / 2 of the number of instructions that the instruction queue in the instruction distribution stage can accommodate); in the instruction execution stage, the preset conditions may include that the number of instructions belonging to the priority thread in the instruction queue is larger (for example, the number of instructions belonging to the priority thread is greater than 1 / 2 of the number of instructions that the instruction queue in the instruction execution stage can accommodate or is greater than 1 / 2 of the number of instructions in the instruction queue in the instruction execution stage). It should be noted that those skilled in the art can set specific thresholds for the preset conditions according to actual needs.

[0073] In some embodiments of the present disclosure, the preset conditions include a quantitative relationship between the number of instructions belonging to the priority thread and a preset threshold, and the priority thread being active in the current pipeline stage.

[0074] For example, different “preset thresholds” can be set for different pipeline stages.

[0075] For example, when the current pipeline stage is the instruction dispatch stage, the preset threshold may be 1 / 2 or 3 / 4 of the total number of instructions that the instruction queue can accommodate. The preset conditions for the instruction dispatch stage may include that the number of instructions belonging to the priority thread does not exceed the preset threshold and the priority thread is active in the instruction dispatch stage.

[0076] Exemplarily, when the priority thread is active in the instruction distribution phase, if the number of instructions belonging to the priority thread exceeds the preset threshold, the priority thread will not be considered, that is, the priority thread will be treated as a non-priority thread, and the non-priority thread scheduling strategy will be used to select the target instruction from multiple instructions of multiple threads to enter the instruction queue; if the number of instructions belonging to the priority thread does not exceed the preset threshold, the priority thread scheduling strategy will be used to preferentially select the instruction belonging to the priority thread from multiple instructions of multiple threads as the target instruction to enter the instruction queue of the instruction distribution phase, and then select the instruction belonging to the non-priority thread to enter the instruction queue of the instruction distribution phase.

[0077] For example, when the current pipeline stage is the instruction execution stage, the preset threshold may include 1 / 4, 1 / 3, or 1 / 2 of the total number of instructions that the instruction queue can accommodate. The preset condition for the instruction execution stage may include that the number of instructions belonging to the priority thread in the instruction queue exceeds the preset threshold, and the priority thread is active in the instruction execution stage.

[0078] Exemplarily, when the priority thread is active in the instruction execution stage, if the number of instructions belonging to the priority thread in the instruction queue does not exceed the preset threshold, the priority thread loses its priority and is regarded as a non-priority thread. The non-priority thread scheduling strategy is used to select the target instruction from the instruction queue for execution. Furthermore, the instructions in the instruction queue that are in a ready state (i.e., ready instructions) can be executed first; if the number of instructions belonging to the priority thread in the instruction queue exceeds the preset threshold, the instructions in the instruction queue that belong to the priority thread are executed first. Furthermore, the instructions in the instruction queue that belong to the priority thread and are in a ready state can be executed first, and then the instructions in the instruction queue that belong to the non-priority thread and are in a ready state are executed.

[0079] In some embodiments of the present disclosure, the above-mentioned step S112 may further include step S1121 (not shown in the figure).

[0080] Step S1121: In response to the priority thread being inactive in the current pipeline stage, a non-priority thread scheduling strategy is used to select an instruction not belonging to the priority thread from multiple instructions of multiple threads as a target instruction to enter the current pipeline stage.

[0081] For step S1121, the non-priority thread scheduling strategy may include a round-robin scheduling strategy, a best-candidate selection scheduling strategy, etc., which is not limited in the embodiments of the present disclosure.

[0082] For example, the SMT4 architecture can simultaneously maintain the processing flow of four threads including T0, T1, T2 and T3. For each pipeline stage (such as the execution stage), when adopting a non-priority thread scheduling strategy, the processor can adopt a polling scheduling strategy to start checking from the first thread (such as T0), and loop in the order of T0→T1→T2→T3→T0 to check whether the instructions in the queue meet the requirements of entering the pipeline stage for processing (such as execution). For example, if the instructions of all four threads do not meet the execution conditions, the CPU will stall during that operation cycle, that is, no valid instructions will be executed, waiting for at least one thread to be ready; if only one thread's instructions meet the execution conditions, the instructions of this thread will be directly selected to enter the current pipeline stage for execution; when multiple threads (for example, at least two of T0, T1, T2, and T3) all meet the execution conditions, the thread to be executed will be selected in the established order. For example, in the order of T0→T1→T2→T3→T0, if T0 was selected in the previous operation cycle, then T1 can be selected in the current operation cycle, then T2 can be selected, then T3 can be selected, and then back to T0, and so on.

[0083] In at least one embodiment of the present disclosure, a round-robin scheduling strategy is employed to ensure fairness among multiple concurrent threads by allocating processor execution resources in a cyclic manner. Each thread has the opportunity to take turns obtaining CPU time slices for instruction execution in a preset order, thus avoiding the problem of starvation of other threads caused by a single thread monopolizing resources for a long time. Its simple and intuitive design makes implementation cost-effective and easy to understand and maintain, helping to simplify system architecture and debugging. When the multi-threaded task load is relatively balanced, the round-robin scheduling strategy also helps to achieve efficient utilization of hardware resources and improve the throughput of the overall system.

[0084] For example, when selecting the next executable thread to enter the current pipeline stage, the best candidate selection scheduling strategy can consider the status of multiple threads (such as whether the thread is active, whether there are pending non-conflicting instructions between multiple threads, the thread with the least impact on overall performance, etc.), so as to select a suitable thread as the source of the target instruction among multiple threads.

[0085] In some embodiments of the present disclosure, the instruction scheduling method may further include step S130 (not shown in the figure).

[0086] Step S130: When there are multiple priority threads among the multiple threads, select one of the multiple priority threads as a target priority thread, wherein the target instruction belongs to the target priority thread.

[0087] For step S130, for example, when there are more than two threads among multiple threads that are marked as priority threads, for each cycle, one of the multiple priority threads can be selected as the target priority thread using, for example, a polling strategy, and the other unselected priority threads in the cycle can be regarded as non-priority threads, so as to further avoid the situation where multiple priority threads occupy resources and affect processing efficiency. For example, the status of the multiple priority threads can also be comprehensively considered to select the better thread as the target priority thread. For example, in a multi-core architecture, other threads marked as priority threads can also be transferred to other CPU cores for execution to improve the overall processing efficiency of the processor.

[0088] FIG3 shows a flowchart illustrating an application example of an instruction scheduling method for a simultaneous multi-threaded processor provided by at least one embodiment of the present disclosure.

[0089] As shown in FIG3 , the instruction scheduling method of a simultaneous multi-threaded processor is described below by taking the instruction scheduling method of the pipeline stage of instruction distribution as an example.

[0090] For example, the instruction scheduling method for a simultaneous multi-threaded processor in the instruction dispatching phase may include steps S200 to S293. The following steps are directed to the scheduling operations performed on the instructions waiting to be scheduled in one operation cycle.

[0091] Step S200: Initialization, i=0, P=-1.

[0092] For step S200, i is an integer, and P represents the thread number selected after the above scheduling method is executed in the operation cycle.

[0093] For example, under the SMT4 architecture, four threads including T0, T1, T2 and T3 are maintained simultaneously. P=0 can indicate that thread T0 will be selected later, and the initial value is -1, indicating that no selection has been made yet.

[0094] Step S210: Determine whether the priority thread scheduling policy is enabled. If it is determined that the priority thread scheduling policy is enabled, proceed to step S220; otherwise, proceed to step S240.

[0095] Regarding step S210 , for example, whether the priority thread scheduling policy is enabled is determined by reading the value of the priority thread register.

[0096] If the value of the priority thread register indicates that the priority thread scheduling policy is enabled, then the process proceeds to step S220, otherwise the process proceeds to step S240. For example, please refer to the above description of steps 120 and S121, which will not be repeated here.

[0097] Step S220: Determine whether the priority thread meets the preset conditions. If the priority thread meets the preset conditions for selection, proceed to step S230; otherwise, proceed to step S240 (described later).

[0098] Regarding step S220 , when it is determined that the priority thread scheduling policy is enabled, it is further determined whether the priority thread meets the preset conditions. If so, the process proceeds to step S230 , otherwise, the process proceeds to step S240 .

[0099] For example, in the instruction distribution pipeline stage, the preset condition includes whether the number of instructions belonging to the priority thread among the multiple threads does not exceed 1 / 2 of the number of instructions that the instruction queue can accommodate.

[0100] Step S230: Let P = PTR[Tid].

[0101] For step S230, PTR[Tid] represents the priority thread among multiple threads, so P is assigned to the thread number of PTR[Tid], that is, the priority thread is set as the selected thread, and then step S291 is entered (to be described later).

[0102] Step S240: Tid=(NextTid+i)%numThread.

[0103] For step S240, when scheduling is performed with a priority thread scheduling policy, Tid represents the ID of the thread currently being considered (referred to as the "current thread"), NextTid represents the starting thread ID in the polling of the current operation cycle (because the initial value of i is 0, and NextTid is determined in the operation cycle before the current operation cycle, refer to step 290 described below), and numThread represents the maximum number of active threads supported by the CPU core (for example, for SMT4, the value of this parameter is 4).

[0104] Step S250: Determine whether S[Tid]>0.

[0105] In step S250, it is determined whether the current thread meets the scheduling conditions and can be scheduled. If S[Tid]>0, it means that the current thread meets the scheduling conditions and can be selected and thus enters step S260, otherwise enters step S270.

[0106] Step S260: Let P = Tid.

[0107] For step S260, P is assigned to Tid, that is, the thread number of the current thread, that is, the current thread is selected. For example, in step S250, it is determined that thread 0 meets the scheduling conditions, Tid=0, then P=0 in step S260.

[0108] Step S270: I=i+1. This implements the polling operation in the scheduling method of this operation cycle.

[0109] Step S280: Determine whether P=-1.

[0110] For step S280, determine whether a selection has been made in the current operation cycle (i.e., the target thread is obtained). If P is not equal to -1 (i.e., a selection has been made), enter step S290, otherwise enter step S292 (to be described later).

[0111] Step S290: NextTid=(P+1)%numThread.

[0112] For step S290, it is determined that the starting thread that needs to be checked for whether the scheduling conditions are met in the polling of the next operation cycle is the thread immediately following the selected thread P (i.e., the thread whose thread number is incremented by 1). Thus, polling is performed between multiple operation cycles, which is more conducive to fair scheduling of each thread.

[0113] Step S291: Select P. That is, in the current operation cycle, select the instruction of thread P as the target instruction to enter the current pipeline stage.

[0114] In step S291, an instruction of thread P (ie, a target instruction) is selected from the instruction queue for execution. The instruction of the thread corresponding to the thread ID determined in step S260 or step S230 is selected and entered into the instruction queue.

[0115] Step S292: Determine i <numThread。

[0116] In step S292, determine whether i is less than the maximum number of active threads supported by the CPU core. For example, in the SMT4 architecture, if i is greater than 3 (i.e., greater than or equal to 4), proceed to step S293. If i is less than 4, return to step S240 and begin determining whether the next thread meets the scheduling conditions.

[0117] Step S293: None, that is, no thread is selected in the current operation cycle, and thus no target instruction is obtained to enter the current pipeline stage.

[0118] FIG4 shows a schematic block diagram of an instruction scheduling device provided by at least one embodiment of the present disclosure.

[0119] As shown in FIG. 4 , the instruction scheduling device 300 includes an acquisition module 310 and a processing module 320 .

[0120] The acquisition module 310 is configured to acquire a priority thread among the multiple threads in response to the current pipeline stage having multiple instructions belonging to multiple threads and enabling a priority thread scheduling policy. The acquisition module 310 may, for example, execute step S100 described in FIG1 .

[0121] The processing module 320 is configured to select a target instruction from multiple instructions of multiple threads to enter the current pipeline stage according to the priority thread. The processing module 320 can, for example, execute step S110 described in FIG1 .

[0122] In some embodiments of the present disclosure, the instruction scheduling apparatus 300 may further include a priority thread register 330. The processing module 320 may further be configured to, in response to the priority thread register being at a first value, determine to enable the priority thread scheduling policy and the priority thread; or, in response to the priority thread register being at a second value different from the first value, determine to disable the priority thread scheduling policy. The processing module 320 may further, for example, execute steps S120 or S121 above.

[0123] In some embodiments of the present disclosure, the processing module 320 may also be configured to select an instruction belonging to the priority thread from multiple instructions of multiple threads as the target instruction to enter the current pipeline stage when the priority thread meets a preset condition. The processing module 320 may also perform the above-mentioned step S111.

[0124] In some embodiments of the present disclosure, the processing module 320 may also be configured to, if the priority thread does not meet the preset conditions, use a non-priority thread scheduling strategy to select a target instruction from multiple instructions of multiple threads to enter the current pipeline stage. The processing module 320 may also perform the above-mentioned step S112, for example.

[0125] In some embodiments of the present disclosure, the processing module 320 may also be configured to, in response to the priority thread being inactive in the current pipeline stage, select an instruction not belonging to the priority thread from multiple instructions of multiple threads using a non-priority thread scheduling strategy as a target instruction to enter the current pipeline stage if the priority thread does not meet a preset condition. The processing module 320 may also, for example, perform step S1121 described above.

[0126] In some embodiments of the present disclosure, the processing module 320 may also be configured to, when there are multiple priority threads among the multiple threads, select one of the multiple priority threads as the target priority thread, wherein the target instruction belongs to the target priority thread. The processing module 320 may also perform the above-mentioned step S130, for example.

[0127] In the embodiments of the present disclosure, for example, the acquisition module 310 and the processing module 320 may be hardware, software, firmware, or any feasible combination thereof. For example, the acquisition module 310 and the processing module 320 may be dedicated or general-purpose circuits, chips, or devices, or may be a combination of a processor and memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above-mentioned units.

[0128] It should be noted that in the embodiments of the present disclosure, the various modules of the instruction scheduling device 300 correspond to the various steps of the aforementioned instruction scheduling method. For the specific functions of the instruction scheduling device 300, reference can be made to the relevant description of the aforementioned instruction scheduling method, and no further description is given here. The components and structure of the instruction scheduling device 300 shown in FIG4 are merely exemplary and non-restrictive. The instruction scheduling device 300 may also include other components and structures as needed.

[0129] FIG5 shows a schematic block diagram of another instruction scheduling device provided by at least one embodiment of the present disclosure.

[0130] For example, as shown in Figure 5, the instruction scheduling apparatus 400 includes a storage unit 410 and a processing unit 420. For example, the storage unit 410 is used to non-temporarily store computer-executable instructions, and the processing unit 420 is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processing unit 420, the instruction scheduling method provided by any embodiment of the present disclosure is executed.

[0131] For example, the storage unit 410 is coupled to the processing unit 420. For example, in some examples, as shown in FIG5 , the instruction scheduling device 400 may further include a system bus 430, and the storage unit 410 and the processing unit 420 may communicate with each other through the system bus 430. For example, the processing unit 420 may access the storage unit 410 through the system bus 430.

[0132] For example, the processing unit 420 may control other components in the instruction dispatching apparatus to perform desired functions. For example, the processing unit 420 may include a circuit or module with certain instruction processing capabilities.

[0133] For example, the storage unit 410 may include a volatile memory and / or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory. The non-volatile memory may include, for example, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, etc. The embodiments of the present disclosure are not limited in this regard.

[0134] For example, one or more computer instructions may be stored on the storage unit 410, and the processing unit 420 may execute the computer instructions to implement various functions. Various applications and various data may also be stored in the computer-readable storage medium, such as instruction processing code and various data used and / or generated by the application.

[0135] For example, when some computer instructions stored in the storage unit 410 are executed by the processing unit 420 , one or more steps in the instruction scheduling method described above may be performed.

[0136] For example, for a detailed description of the processing procedure of the instruction scheduling method in the instruction scheduling device 400, reference may be made to the relevant description in the above-mentioned embodiment of the instruction scheduling method, which will not be repeated here.

[0137] It should be noted that the instruction scheduling device provided in the embodiments of the present disclosure is exemplary and not restrictive. According to actual application needs, the instruction scheduling device may also include other conventional components or structures. For example, in order to realize the necessary functions of the instruction scheduling device, those skilled in the art may set other conventional components or structures according to the specific application scenarios, and the embodiments of the present disclosure do not limit this.

[0138] At least some embodiments of the present disclosure further provide a simultaneous multi-threading (SMT) processor, which includes the instruction scheduling device 400 provided by any of the aforementioned embodiments.

[0139] At least some embodiments of the present disclosure also provide another simultaneous multi-threaded processor, which is a pipeline of the simultaneous multi-threaded processor, wherein the pipeline includes a current pipeline stage, the current pipeline stage has multiple instructions belonging to multiple threads, the pipeline is configured to enable a priority thread scheduling policy, obtain a priority thread among the multiple threads, and is configured to select a target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage according to the priority thread.

[0140] For example, a simultaneous multi-threaded processor employs a pipeline design, enabling parallel processing of instructions from multiple threads within a single pipeline stage. This pipeline design can support a prioritized thread scheduling strategy, whereby a priority thread is identified based on predefined or dynamically adjusted priority rules when processing multiple concurrent threads. For details on the prioritized thread scheduling strategy, see the description of the aforementioned embodiments and will not be repeated here.

[0141] An exemplary description of the pipeline in the processor can be seen in Figure 1, which is not repeated here. For example, the current pipeline stage includes a branch prediction stage, an instruction fetch stage, an instruction decode stage, an instruction dispatch and rename stage, an instruction execute stage, or an instruction end stage.

[0142] In some embodiments, the simultaneous multi-threading processor further includes a priority thread register, wherein the priority thread register is configured to mark a priority thread among the plurality of threads when the priority thread register has a first value.

[0143] For example, when the priority thread register is a first value, the priority thread register can mark the priority thread among multiple threads and determine to enable the priority thread scheduling policy and the marked priority thread; when the priority thread register is a second value different from the first value, the multiple threads are not marked, and the priority thread scheduling policy is stopped.

[0144] At least some embodiments of the present disclosure further provide an electronic device, which may be implemented as a chip, for example, and which may include the simultaneous multi-threaded processor provided by any of the aforementioned embodiments. For example, the chip may be a separately packaged CPU chip, or a system-on-chip (SOC) in which the simultaneous multi-threaded processor is a module coupled to other modules (e.g., a GPU, a DSP, etc.).

[0145] At least some embodiments of the present disclosure further provide a non-transitory storage medium. Figure 6 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure.

[0146] For example, as shown in FIG6 , the storage medium 500 non-temporarily stores computer executable instructions 510 . When the non-temporary computer executable instructions 510 are executed by a computer (including a processing unit), the instruction scheduling method provided by any embodiment of the present disclosure may be executed.

[0147] For example, one or more computer instructions may be stored in the storage medium 500. Some of the computer instructions stored in the storage medium 500 may be, for example, instructions for implementing one or more steps in the above-mentioned instruction scheduling method.

[0148] For example, the storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a flash memory, or any combination thereof, or other suitable storage medium. For example, the storage medium 500 may include the storage unit 410 in the aforementioned instruction scheduling device 400.

[0149] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding description of the instruction scheduling method in the above embodiments, which will not be repeated here.

[0150] The electronic device provided by at least some embodiments of the present disclosure may also be implemented as a device comprising a processor according to any of the above embodiments. Figure 7 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0151] The electronic device in at least one embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs, desktop computers, etc. The electronic device 600 shown in FIG7 is merely an example and should not limit the functionality and scope of use of the embodiments of the present disclosure.

[0152] For example, as shown in FIG7 , in some examples, an electronic device 600 includes a processing device (e.g., a central processing unit, etc.) 601, which may include an SMT processor of any of the above-described embodiments, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the computer system are also stored in the RAM 603. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0153] For example, the following components may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 608 including, for example, a magnetic tape, hard disk, etc.; and a communication device 609, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. Removable media 611, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 610 as needed, so that computer programs read therefrom can be installed into the storage device 608 as needed. Although FIG. 7 shows the electronic device 600 including various devices, it should be understood that implementation or inclusion of all of the devices shown is not required. More or fewer devices may alternatively be implemented or included.

[0154] For example, the electronic device 600 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 609 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0155] For example, the electronic device 600 can be any electronic device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0156] For example, the storage device 608 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. The embodiments of the present disclosure are not limited in this regard.

[0157] The SMT processor used in the electronic device 600 has improved processor multi-thread instruction scheduling and execution efficiency, as well as improved processor core performance.

[0158] It should be noted that the electronic device 600 shown in FIG. 7 is merely an example and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0159] The technical effects of the above-mentioned instruction scheduling device, chip, processor, electronic device and non-transitory storage medium are the same as the technical effects of the above-mentioned instruction scheduling method, and will not be repeated here.

[0160] There are a few points to note:

[0161] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0162] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0163] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for scheduling instructions for a simultaneous multi-threaded processor, comprising: In response to a current pipeline stage having a plurality of instructions belonging to a plurality of threads and enabling a priority thread scheduling policy, obtaining a priority thread among the plurality of threads; According to the priority thread, a target instruction is selected from multiple instructions of the multiple threads to enter the current pipeline stage.

2. The method according to claim 1, further comprising: In response to the priority thread register being at a first value, it is determined to enable the priority thread scheduling policy and the priority thread.

3. The method according to claim 2, further comprising: In response to the priority thread register being a second value different from the first value, it is determined to stop the priority thread scheduling policy.

4. The method according to any one of claims 1 to 3, wherein: The step of selecting a target instruction from multiple instructions of the multiple threads according to the priority thread to enter the current pipeline stage includes: In the case where the priority thread meets the preset conditions, an instruction belonging to the priority thread is selected from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage, or, In the case that the priority thread does not meet the preset conditions, a non-priority thread scheduling strategy is adopted to select the target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage.

5. The method according to claim 4, further comprising: In response to the priority thread being inactive in the current pipeline stage, When the priority thread does not meet the preset condition, the non-priority thread scheduling strategy is adopted to select a target instruction from multiple instructions of the multiple threads to enter the current pipeline stage, including: The non-priority thread scheduling strategy is adopted to select an instruction that does not belong to the priority thread from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage.

6. The method according to claim 5, wherein: The non-priority thread scheduling strategy includes a round-robin scheduling strategy.

7. The method according to any one of claims 4 to 6, wherein: The preset conditions include: a quantitative relationship between the number of instructions belonging to the priority thread and a preset threshold, and the priority thread being active in the current pipeline stage.

8. The method according to any one of claims 1 to 7, wherein The current pipeline stage includes a branch prediction stage, an instruction fetch stage, an instruction decoding stage, an instruction dispatch and renaming stage, an instruction execution stage or an instruction end stage.

9. The method according to any one of claims 1 to 8, wherein In the case that there are multiple priority threads among the multiple threads, one priority thread among the multiple priority threads is selected as the target priority thread, wherein the target instruction belongs to the target priority thread.

10. An instruction scheduling device for a simultaneous multi-threaded processor, comprising: an acquisition module configured to, in response to a current pipeline stage having a plurality of instructions belonging to a plurality of threads and enabling a priority thread scheduling policy, acquire a priority thread among the plurality of threads; as well as The processing module is configured to select a target instruction from multiple instructions of the multiple threads according to the priority thread to enter the current pipeline stage.

11. The apparatus according to claim 10, further comprising a priority thread register, wherein The processing module is further configured to: In response to the priority thread register being at a first value, determining to enable the priority thread scheduling policy and the priority thread, or In response to the priority thread register being a second value different from the first value, it is determined to stop the priority thread scheduling policy.

12. The device according to claim 10 or 11, wherein The processing module is further configured to: In the case where the priority thread meets the preset conditions, an instruction belonging to the priority thread is selected from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage, or, In the case that the priority thread does not meet the preset conditions, a non-priority thread scheduling strategy is adopted to select the target instruction from the multiple instructions of the multiple threads to enter the current pipeline stage.

13. The device according to claim 12, wherein The processing module is further configured to: In response to the priority thread being inactive in the current pipeline stage, when the priority thread does not meet the preset conditions, the non-priority thread scheduling strategy is adopted to select an instruction that does not belong to the priority thread from multiple instructions of the multiple threads as the target instruction to enter the current pipeline stage.

14. The device according to any one of claims 10 to 13, wherein: The processing device is further configured to: if there are multiple priority threads among the multiple threads, select one of the multiple priority threads as a target priority thread, wherein the target instruction belongs to the target priority thread.

15. An instruction scheduling device, comprising: processing unit; as well as a storage unit storing computer-executable instructions; Wherein, when the computer executable instruction is executed by the processing unit, the instruction scheduling method described in any one of claims 1 to 9 is executed.

16. A simultaneous multi-threaded processor, comprising the instruction scheduling device according to any one of claims 10 to 14.

17. A simultaneous multithreaded processor comprising a pipeline, wherein: The pipeline includes a current pipeline stage, wherein the current pipeline stage has a plurality of instructions belonging to a plurality of threads, The pipeline is configured to enable a priority thread scheduling policy, obtain a priority thread from the multiple threads, and select a target instruction from multiple instructions of the multiple threads to enter the current pipeline stage according to the priority thread.

18. The simultaneous multi-threaded processor of claim 17, further comprising: The priority thread register is configured to mark a priority thread among the multiple threads when the priority thread register is at a first value.

19. An electronic device comprising the simultaneous multi-threading processor according to any one of claims 16 to 18.

20. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein: When the computer-executable instructions are executed by a computer, the instruction scheduling method according to any one of claims 1 to 9 is executed.

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