Wafer-level packaging structure and manufacturing method therefor, radio frequency assembly, and electronic device

Abstract

The present application provides a wafer-level packaging structure and a manufacturing method therefor, a radio frequency assembly, and an electronic device. The wafer-level packaging structure comprises: a filter chip, retaining walls, a protective layer, and conductive connectors. The filter chip comprises: a substrate, an electrode structure, and first pads. The substrate comprises: a support layer and a piezoelectric layer that are stacked. The electrode structure and the first pads are located on the side of the piezoelectric layer away from the support layer, and the conductive connectors are located on the side of the support layer away from the piezoelectric layer. Through holes are formed in the substrate, and each through hole comprises: a first through hole and a second through hole, wherein the first through hole passes through the support layer, the second support layer passes through the piezoelectric layer, and the minimum hole diameter of the first through hole is greater than the maximum hole diameter of the second through hole. Conductive structures are provided in the through holes of the substrate, and each conductive structure has one end electrically connected to a corresponding first pad and the other end electrically connected to a corresponding conductive connector. The present application improves the heat dissipation capability of a wafer-level packaging structure, thereby improving the power withstanding capability of the wafer-level packaging structure.

Description

Wafer-level packaging structure, manufacturing method thereof, radio frequency component and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the Intellectual Property Office of the People's Republic of China on March 27, 2024, with application number 202410372123.1 and application name "A wafer-level packaging structure, its manufacturing method, radio frequency component and electronic device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of wafer-level packaging technology, and in particular to a wafer-level packaging structure, a manufacturing method thereof, a radio frequency component, and an electronic device. Background Art

[0004] With the development of the communications industry, mobile phones, tablets, laptops and other terminal devices are covering more and more RF frequency bands, and the number of RF devices required by these devices is also increasing. However, with the trend of miniaturization of terminal devices, the size of RF components in terminal devices is getting smaller and smaller, which requires the size of RF devices to be reduced accordingly.

[0005] Surface acoustic wave (SAW) filters are one of the most important RF components in RF assemblies, with dozens of them found in terminal equipment. The industry primarily aims to reduce the size of SAW filters by optimizing their packaging. SAW filter packaging has evolved from ceramic seals to chip-size packages (CSPs) and then to wafer-level packaging (WLPs), significantly reducing their size. However, as the size of SAW filters decreases, their heat dissipation capacity also decreases, reducing their power handling capabilities. Summary of the Invention

[0006] Embodiments of the present application provide a wafer-level packaging structure, a manufacturing method thereof, a radio frequency component, and an electronic device for improving the power tolerance of a surface acoustic wave filter.

[0007] In a first aspect, embodiments of the present application provide a wafer-level packaging structure. The wafer-level packaging structure provided by embodiments of the present application may include: a filter chip, a retaining wall, a protective layer, and a conductive connector. The filter chip may include: a substrate, an electrode structure, and a first pad. The substrate may include: a stacked support layer and a piezoelectric layer, wherein the support layer and the piezoelectric layer comprise different materials. The electrode structure and the first pad are located on the side of the piezoelectric layer facing away from the support layer, the retaining wall is located on the side of the electrode structure and the first pad facing away from the support layer, and the protective layer is located on the side of the retaining wall facing away from the support layer. The protective layer, retaining wall, and substrate form a cavity, and at least a portion of the electrode structure is located within the cavity. In some embodiments of the present application, the cavity is not filled with a dielectric material; instead, the cavity may be filled with a gas such as air to facilitate the transmission of sound waves. In one possible implementation, the electrode structure and the first pad may comprise a metal material such as gold, silver, or copper. The electrode structure and the first pad may comprise the same metal material, or they may comprise different metal materials.

[0008] The filter chip in the embodiment of the present application can be a surface acoustic wave filter chip, and the substrate can include a supporting layer and a piezoelectric layer arranged in a stacked manner, and the surface of the substrate having one side of the piezoelectric layer is provided with an electrode structure. During the operation of the filter chip, sound waves can be generated in the piezoelectric layer by applying voltage to the electrode structure. After the sound waves generated in the piezoelectric layer are transmitted to the surface of the substrate, they can be transmitted in the cavity surrounded by the protective layer, the retaining wall and the substrate. The cavity is conducive to the transmission of sound waves and can improve the filtering effect of the filter chip. Of course, in some cases, the filter chip can also be a bulk acoustic wave filter chip or other types of chips. In the embodiments of the present application, the filter chip is taken as a surface acoustic wave filter chip as an example for explanation. Other types of chips can be implemented with reference to this, and the repeated parts will not be repeated.

[0009] The filter chip in the embodiment of the present application is packaged in a wafer-level packaging manner. Specifically, a retaining wall and a protective layer are provided on the side of the substrate having the piezoelectric layer. The retaining wall has a pattern portion and a hollow portion. The pattern portion of the retaining wall can cover the first pad, the hollow portion of the retaining wall can expose the electrode structure, and the protective layer covers the pattern portion and the hollow portion of the retaining wall. Therefore, the retaining wall and the protective layer can provide better protection for the electrode structure and the first pad. In addition, by providing a hollow portion in the retaining wall, the protective layer, the retaining wall and the substrate can form a cavity, and at least part of the electrode structure can be located in the cavity, so that the sound waves generated by the electrode structure can be transmitted in the cavity. In one possible implementation, the retaining wall can be made of a photosensitive material. During the manufacturing process, the structure of the retaining wall can be obtained by a photolithography process. The manufacturing process is relatively simple and the manufacturing cost is low. For example, a polyimide (PI) material can be used to make the retaining wall. Of course, other insulating materials can also be used to make the retaining wall, which is not limited here. In one possible implementation, the sum of the thicknesses of the retaining wall and the protective layer is less than 100 μm. For example, the sum of the thicknesses of the retaining wall and the protective layer can be around 50 μm, and the outer edge of the retaining wall can be basically flush with the outer edge of the protective layer. In this way, the total volume of the wafer-level packaging structure can be smaller, which is conducive to the miniaturized design of the wafer-level packaging structure.

[0010] In the embodiments of the present application, the conductive connector is located on the side of the support layer facing away from the piezoelectric layer. The conductive connector can electrically connect the filter chip to other components. For example, when the wafer-level packaging structure in the embodiments of the present application is applied to a radio frequency assembly, the filter chip can be electrically connected to a circuit board via the conductive connector. In one possible implementation, the conductive connector can be a conductive component such as a solder ball, and the filter chip can be electrically connected to the circuit board by welding or other methods.

[0011] In an embodiment of the present application, a through hole is provided in the substrate. The through hole may include: a first through hole and a second through hole. The first through hole passes through the support layer, and the second through hole passes through the piezoelectric layer. The minimum aperture of the first through hole is larger than the maximum aperture of the second through hole. The substrate is provided with a conductive structure within the through hole. The conductive structure passes through the first through hole and the second through hole in a direction perpendicular to the substrate surface. One end of the conductive structure is electrically connected to the first pad, and the other end is electrically connected to the conductive connector. In an embodiment of the present application, by providing a through hole in the substrate and providing a conductive structure within the through hole, the first pad on the front side of the filter chip (i.e., the surface of the piezoelectric layer facing away from the support layer) and the conductive connector on the back side of the filter chip (i.e., the surface of the support layer facing away from the piezoelectric layer) can be electrically connected. The conductive structure is generally made of a metal material with good electrical conductivity, and therefore, the conductive structure also has good thermal conductivity. In this way, heat generated on the front side of the filter chip can be transferred to the location of the through hole through the substrate, and the heat can be quickly dissipated through the conductive structure within the through hole. As a result, the heat dissipation capacity of the wafer-level packaging structure is improved, and the power tolerance of the wafer-level packaging structure is further improved.

[0012] Furthermore, the support layer in the substrate can include silicon (Si) material. Due to its excellent thermal conductivity (approximately 130 W / m / K), the substrate also offers excellent thermal conductivity. This allows heat generated on the front of the filter chip to be quickly transferred through the substrate to the vias, further enhancing the heat dissipation capabilities of the wafer-level packaging structure.

[0013] Furthermore, in an embodiment of the present application, the support layer and the piezoelectric layer comprise different materials. For example, the support layer may comprise silicon, and the piezoelectric layer may comprise at least one of lithium niobate, lithium tantalate, zinc oxide, and aluminum nitride. Of course, the support layer may also comprise other materials capable of providing support, and the piezoelectric layer may also comprise other piezoelectric materials, which are not limited herein. The thickness of the support layer may be in the range of 100 μm to 500 μm, and the thickness of the piezoelectric layer may be in the range of 100 nm to 1 μm. During the fabrication process, the piezoelectric layer is more difficult to etch than the support layer, and the etching rate of the piezoelectric layer is slower. Consequently, the diameter of the second through-hole in the etched piezoelectric layer is smaller. During the fabrication process, different etching processes may be used to etch the piezoelectric layer and the support layer, thereby reducing the etching difficulty of a single etching process. Furthermore, setting the diameter of the first through-hole in the support layer larger can increase the cross-sectional area of ​​the conductive structure, reduce the on-resistance of the conductive structure, and thereby improve the electrical performance of the wafer-level packaging structure.

[0014] In some embodiments of the present application, the substrate may further include: an acoustic reflection layer located between the support layer and the piezoelectric layer. The acoustic reflection layer may reflect the sound waves transmitted toward the support layer back to the front of the filter chip, so that the sound waves are concentrated on the surface (front) of the filter chip, reducing the loss of the sound waves. The above-mentioned through hole may further include: a third through hole, the third through hole passes through the acoustic reflection layer, and the maximum aperture of the second through hole is smaller than the minimum aperture of the third through hole. The conductive structure also passes through the third through hole in a direction perpendicular to the surface of the substrate, that is, in some embodiments, the conductive structure passes through the first through hole, the third through hole and the second through hole in a direction perpendicular to the surface of the substrate. Since the piezoelectric layer is more difficult to etch than the acoustic reflection layer, the etching rate of the piezoelectric layer is slower, and therefore, the maximum aperture of the second through hole obtained by etching is smaller than the minimum aperture of the third through hole.

[0015] Since the acoustic reflection layer has a wide range of material options and the etching rates of different materials vary greatly, the etching rate of the acoustic reflection layer may be lower than the etching rate of the supporting layer, and the maximum aperture of the third through hole in the acoustic reflection layer may be lower than the minimum aperture of the first through hole in the supporting layer. Alternatively, the etching rate of the acoustic reflection layer may be higher than the etching rate of the supporting layer, and the maximum aperture of the third through hole in the acoustic reflection layer may be higher than the minimum aperture of the first through hole in the supporting layer. Due to the large thickness of the supporting layer, the aperture of the first through hole in certain locations may be higher than the maximum aperture of the third through hole. Of course, in some cases, the minimum aperture of the third through hole in the acoustic reflection layer may also be higher than the maximum aperture of the first through hole in the supporting layer, which can be set according to actual conditions.

[0016] During the manufacturing process, a deep silicon etching process can be used to etch the support layer to form a first through hole penetrating the support layer. An inductively coupled plasma-reactive ion etching (ICP-RIE) process can be used to etch the acoustic reflective layer and the piezoelectric layer to form a third through hole penetrating the acoustic reflective layer, and a second through hole penetrating the piezoelectric layer. Due to the different etching processes or etching rates of different film layers, steps are formed at the interfaces between the different film layers during the process of drilling the substrate, causing the through hole to have a stepped shape at the interface between the different film layers. Specifically, the position where the first through hole connects to the second through hole is stepped, and the position where the second through hole connects to the third through hole is stepped.

[0017] During the manufacturing process, to avoid damaging the electrode structure and first pad on the front of the filter chip, the substrate is typically drilled with the backside of the filter chip facing upward, and etching is performed from the substrate surface with the support layer inward. As a result, in the direction from the support layer toward the piezoelectric layer, the aperture of the first through-hole decreases, the aperture of the second through-hole decreases, and the aperture of the third through-hole decreases.

[0018] In one possible implementation, the acoustic reflection layer may include: at least one low-acoustic-resistance layer and at least one high-acoustic-resistance layer, alternately stacked, wherein the acoustic resistance of the high-acoustic-resistance layer is greater than or equal to three times the acoustic resistance of the low-acoustic-resistance layer. Exemplarily, the low-acoustic-resistance layer may include: at least one of silicon dioxide (SiO2), silicon oxynitride (SiNO), and tantalum pentoxide (Ta2O5); and the high-acoustic-resistance layer may include: at least one of sapphire, aluminum oxide (Al2O3), silicon nitride (SiN), and aluminum nitride (AlN). The specific number of low-acoustic-resistance and high-acoustic-resistance layers may be set according to actual needs and is not limited here. In another possible implementation, the acoustic reflection layer may include only the low-acoustic-resistance layer. Exemplarily, the low-acoustic-resistance layer may include: at least one of silicon dioxide (SiO2), silicon oxynitride (SiNO), and tantalum pentoxide (Ta2O5). The thickness of the low-acoustic-resistance layer may be in the range of 100 nm to 1 μm.

[0019] In some embodiments of the present application, the conductive structure can fill the through hole. In the direction perpendicular to the surface of the substrate, the first pad and the through hole have an overlapping area, the conductive connector and the through hole have an overlapping area, one end of the conductive structure is in contact with the first pad, and the other end is in contact with the conductive connector. This arrangement can make the first pad on the front of the filter chip and the conductive connector on the back electrically conductive through the conductive structure, and the contact area between the conductive structure and the first pad and the conductive connector is large, so that the electrical connection effect between the conductive structure and the first pad and the conductive connector is better, thereby improving the electrical performance of the wafer-level packaging structure. In an embodiment of the present application, the conductive structure and the conductive connector can be in contact with each other. In some cases, the conductive structure can also be indirectly connected to the conductive connector through components such as a redistribution layer and a transfer plate, which can be arranged according to actual conditions.

[0020] In other embodiments of the present application, in a direction perpendicular to the surface of the substrate, the first pad and the through-hole have an overlapping area, the conductive connector and the through-hole do not overlap each other, and the filter chip may further include: a second pad located on the side of the substrate away from the electrode structure. The conductive structure covers the inner wall of the through-hole, one end of the conductive structure is in contact with the first pad, the other end is electrically connected to the second pad, and the conductive connector is in contact with the second pad. The conductive structure can be electrically connected to the conductive connector through the second pad, so that the first pad on the front of the filter chip and the conductive connector on the back are electrically conductive through the conductive structure and the second pad. In addition, the conductive structure does not fill the through-hole, and the heat generated on the front of the filter chip is transferred to the position of the through-hole through the substrate, and can be directly dissipated into the air through the conductive structure, thereby improving the heat dissipation efficiency of the filter chip.

[0021] In a specific setting, the conductive structure can be connected to the second pad as a whole. During the manufacturing process, after forming a through hole in the substrate, the same metal deposition process can be used to form a metal layer covering the inner wall of the through hole and extending to the surface of the substrate away from the electrode structure, thereby obtaining a conductive structure and a second pad that are electrically connected to each other. In an embodiment of the present application, the second pad and the conductive connector can be in contact and connected. In some cases, the second pad can also be indirectly connected to the conductive connector through components such as a redistribution layer and an adapter plate, which can be set according to actual conditions.

[0022] In an embodiment of the present application, by providing a through hole and a conductive structure in the substrate, the first pad on the front of the filter chip can be connected to the back through the conductive structure, without the need to lead out the electrical signal of the first pad through the retaining wall and the protective layer, that is, there is no need to pattern the protective layer, which can reduce the steps of the manufacturing process. Therefore, the protective layer can be set as a full-surface film layer without a pattern. In this way, the material selection range of the protective layer is relatively large. For example, the protective layer can include a non-photosensitive material. Of course, the protective layer can also be made of other materials that can play a protective function, which is not limited here.

[0023] In a second aspect, an embodiment of the present application further provides a method for manufacturing a wafer-level packaging structure. The method for manufacturing a wafer-level packaging structure provided by an embodiment of the present application may include:

[0024] Step 1: Provide a substrate, wherein the substrate may include a support layer and a piezoelectric layer stacked together, wherein the support layer and the piezoelectric layer are made of different materials.

[0025] For example, the support layer may include silicon, and the piezoelectric layer may include at least one of lithium niobate, lithium tantalate, zinc oxide, and aluminum nitride. Of course, the support layer may also include other materials capable of providing support, and the piezoelectric layer may also include other piezoelectric materials, which are not limited herein. The thickness of the support layer may be in the range of 100 μm to 500 μm, and the thickness of the piezoelectric layer may be in the range of 100 nm to 1 μm.

[0026] In some embodiments of the present application, the substrate may further include: an acoustic reflection layer located between the support layer and the piezoelectric layer. The acoustic reflection layer may include: at least one low acoustic resistance layer and at least one high acoustic resistance layer alternately stacked, and the acoustic resistance of the high acoustic resistance layer is greater than or equal to three times the acoustic resistance of the low acoustic resistance layer. For example, the low acoustic resistance layer may include: at least one of silicon dioxide (SiO2) material, silicon oxynitride (SiNO) material, and tantalum pentoxide (Ta2O5) material, and the high acoustic resistance layer may include at least one of sapphire material, aluminum oxide (Al2O3) material, silicon nitride (SiN) material, and aluminum nitride (AlN) material. Alternatively, the acoustic reflection layer may also include only the low acoustic resistance layer. During specific implementation, the specific structure of the acoustic reflection layer may be set according to actual needs.

[0027] Step 2: Make the substrate with the piezoelectric layer facing upward, and form an electrode structure and a first pad on the piezoelectric layer.

[0028] In a specific configuration, the electrode structure and the first pad may include metal materials such as gold, silver, and copper. In one possible implementation, the electrode structure and the first pad may include the same metal material. During the manufacturing process, a metal film layer may be formed on the surface of the substrate having the piezoelectric layer. The metal film layer may be patterned to obtain the structure of the electrode structure and the first pad. That is, the electrode structure and the first pad may be manufactured using the same patterning process. Of course, in some cases, the electrode structure and the first pad may also include different metal materials, and different patterning processes may be used to manufacture the electrode structure and the first pad.

[0029] Step 3: forming a retaining wall and a protective layer in sequence on the electrode structure and the first pad, so that the protective layer, the retaining wall and the substrate form a cavity, and at least a portion of the electrode structure is located in the cavity.

[0030] During the manufacturing process, an entire insulating film can be formed on the electrode structure and the first pad, and the insulating film can be patterned to obtain a retaining wall structure. Optionally, an insulating film can be formed on the electrode structure and the first pad by coating or deposition, or a prefabricated insulating film can be directly attached to the electrode structure and the first pad. In one possible implementation, a photosensitive material can be used to make the insulating film, so that the retaining wall structure can be formed by a photolithography process, the manufacturing process is relatively simple, and the manufacturing cost is low. For example, a photosensitive material such as polyimide (PI) material can be used to make the insulating film. Of course, other insulating materials can also be used to make the retaining wall, which is not limited here.

[0031] Afterwards, the prefabricated protective layer can be directly attached to the retaining wall, ensuring that the protective layer conforms to the patterned portion of the retaining wall and is suspended in the hollowed-out portion of the retaining wall, thereby forming a cavity between the protective layer, the retaining wall, and the substrate. In the embodiments of the present application, the protective layer is a solid film layer without a pattern. The material selection range for the protective layer is relatively wide; for example, the protective layer can include a non-photosensitive material. Of course, the protective layer can also be made of other materials that can provide a protective function, and this is not limited here.

[0032] Step 4: With the support layer facing upward, the substrate is patterned to form a through hole in the substrate. The through hole may include a first through hole and a second through hole, wherein the first through hole extends through the support layer, and the second through hole extends through the piezoelectric layer. The minimum aperture of the first through hole is larger than the maximum aperture of the second through hole. In practice, to facilitate contact and connection between the conductive structure subsequently formed within the through hole and the first pad, the substrate is punched at a position corresponding to the position of the first pad, so that the through hole exposes at least a portion of the first pad.

[0033] In an embodiment of the present application, the support layer and the piezoelectric layer include different materials. For example, the support layer may include a silicon material, and the piezoelectric layer may include at least one of a lithium niobate material, a lithium tantalate material, a zinc oxide material, and an aluminum nitride material. The thickness of the support layer may be in the range of 100um to 500um, and the thickness of the piezoelectric layer may be in the range of 100nm to 1um. Since the materials of the support layer and the piezoelectric layer are different, the piezoelectric layer is more difficult to etch than the support layer, and therefore, it is difficult to form a through hole through the substrate using the same etching process. In an embodiment of the present application, different etching processes may be used to etch the piezoelectric layer and the support layer. Specifically, the above step four may specifically include:

[0034] The substrate is placed with the support layer facing upward, and a deep silicon etching process is used to etch from the surface of the support layer toward the interior of the support layer to form a first through hole penetrating the support layer;

[0035] Afterwards, an inductively coupled plasma-reactive ion etching (ICP-RIE) process is used to etch from the surface of the piezoelectric layer close to the support layer toward the interior of the piezoelectric layer to form a second through hole penetrating the piezoelectric layer.

[0036] In the embodiment of the present application, different etching processes are used to etch the piezoelectric layer and the support layer. The support layer is first etched using a deep silicon etching process, and then the piezoelectric layer is etched using an inductively coupled plasma-reactive ion etching process. Compared with the deep silicon etching process, the inductively coupled plasma-reactive ion etching process has a higher plasma concentration and can etch materials that are more difficult to etch. Therefore, in the embodiment of the present application, different etching processes can be reasonably selected according to the materials of the support layer and the piezoelectric layer to etch the support layer and the piezoelectric layer respectively, which can reduce the etching difficulty of the single etching process and improve the feasibility and reliability of the substrate drilling process.

[0037] Because the piezoelectric layer is more difficult to etch than the supporting layer, the etching rate of the piezoelectric layer is slower, resulting in a smaller aperture of the second through-hole in the piezoelectric layer. Furthermore, during the etching of the piezoelectric layer, a portion of the inner wall of the first through-hole in the supporting layer is inevitably etched away, potentially increasing the aperture of the first through-hole in the supporting layer. Therefore, after etching the supporting and piezoelectric layers, the minimum aperture of the first through-hole in the supporting layer is larger than the maximum aperture of the second through-hole in the piezoelectric layer.

[0038] In some embodiments of the present application, the substrate may further include an acoustic reflective layer located between the support layer and the piezoelectric layer. Because the acoustic reflective layer is more difficult to etch than the support layer, and the piezoelectric layer is more difficult to etch than the acoustic reflective layer, it is difficult to etch the support layer, the acoustic reflective layer, and the piezoelectric layer using the same etching process. When the substrate includes a support layer, an acoustic reflective layer, and a piezoelectric layer, step S304 may specifically include:

[0039] The substrate is placed with the support layer facing upward, and a deep silicon etching process is used to etch from the surface of the support layer toward the interior of the support layer to form a first through hole penetrating the support layer;

[0040] Then, an inductively coupled plasma-reactive ion etching process is used to etch from the surface of the acoustic reflective layer close to the support layer toward the interior of the acoustic reflective layer to form a third through hole penetrating the acoustic reflective layer;

[0041] Afterwards, an inductively coupled plasma-reactive ion etching process is used to etch from the surface of the piezoelectric layer close to the support layer toward the interior of the piezoelectric layer to form a second through hole penetrating the piezoelectric layer.

[0042] Because both the acoustic reflector and piezoelectric layers are difficult to etch, inductively coupled plasma-reactive ion etching (ICP-RIE) is used for both layers. This makes it easier to form through-holes that penetrate the acoustic reflector and piezoelectric layers, reducing the difficulty of a single etching process. Furthermore, using the same etching process for both layers reduces the need to replace etching equipment and improves process efficiency.

[0043] Because the piezoelectric layer is more difficult to etch than the acoustic reflector layer and has a slower etching rate, the diameter of the second through-hole in the piezoelectric layer obtained by etching is smaller. Specifically, the maximum diameter of the second through-hole in the piezoelectric layer is smaller than the minimum diameter of the first through-hole in the supporting layer, and the maximum diameter of the second through-hole in the piezoelectric layer is smaller than the minimum diameter of the third through-hole in the acoustic reflector layer. Furthermore, due to the wide range of materials available for the acoustic reflector layer, the etching rates of different materials vary significantly. Therefore, the etching rate of the acoustic reflector layer may be smaller than that of the supporting layer, or it may be greater than that of the supporting layer. Therefore, the maximum diameter of the third through-hole in the acoustic reflector layer can be smaller than the minimum diameter of the first through-hole in the supporting layer; alternatively, the maximum diameter of the third through-hole in the acoustic reflector layer can be greater than the minimum diameter of the first through-hole in the supporting layer. Due to the thickness of the supporting layer, the diameter of the first through-hole may be larger than the maximum diameter of the third through-hole at certain locations. Of course, in some cases, the minimum aperture of the third through hole in the acoustic reflection layer may also be larger than the maximum aperture of the first through hole in the supporting layer.

[0044] Due to the different etching processes or etching rates of different film layers, steps will be formed at the interfaces between different film layers during the process of drilling the substrate, making the through holes in the interface between different film layers step-shaped. Specifically, the position where the first through hole connects to the second through hole is step-shaped, and the position where the second through hole connects to the third through hole is step-shaped.

[0045] Step 5: Forming a conductive structure electrically connected to the first pad within the through-hole, and forming a conductive connector electrically connected to the conductive structure; wherein the conductive structure extends through the first through-hole and the second through-hole in a direction perpendicular to the substrate surface. In one embodiment, when the substrate includes an acoustic reflective layer, the conductive structure also extends through the third through-hole in a direction perpendicular to the substrate surface.

[0046] In one possible implementation, a conductive material can be filled in the through hole to form a conductive structure that fills the through hole. The bottom of the through hole exposes at least a portion of the first pad, so that the conductive structure can be in contact and connected with the first pad. Afterwards, a conductive connector can be formed at the position of the conductive structure, so that the conductive connector is in contact and connected with the conductive structure. Exemplarily, the conductive connector can be a solder ball, and a ball planting process can be used to form the conductive connector at the position of the conductive structure. In an embodiment of the present application, the conductive structure and the conductive connector can be in contact and connected. In some cases, the conductive structure can also be indirectly connected to the conductive connector through components such as a redistribution layer and a transfer board, which can be set according to actual conditions.

[0047] In another possible implementation, a metal deposition process can be used to form a conductive structure covering the inner wall of the through hole, and the conductive structure is contacted and connected with the first pad exposed at the bottom of the through hole. In addition, in order to facilitate the electrical connection between the conductive structure and the subsequently formed conductive connector, a second pad can be formed on the surface of the substrate facing away from the electrode structure, and the second pad is electrically connected to the conductive structure. Afterwards, a conductive connector can be formed at the position of the second pad, and the conductive connector is contacted and connected with the second pad, so that the conductive connector is electrically connected to the conductive structure through the second pad. During the manufacturing process, the same metal deposition process can be used to form a metal layer covering the inner wall of the through hole and extending to the surface of the substrate facing away from the electrode structure, thereby obtaining a conductive structure and a second pad that are electrically connected to each other. In an embodiment of the present application, the second pad and the conductive connector can be contacted and connected. In some cases, the second pad can also be indirectly connected to the conductive connector through components such as a redistribution layer and a transfer plate, which can be set according to actual conditions.

[0048] In an embodiment of the present application, by forming a through hole in the substrate and forming a conductive structure in the through hole, the first pad on the front side of the filter chip (i.e., the surface of the piezoelectric layer facing away from the support layer) and the conductive connector on the back side of the filter chip (i.e., the surface of the support layer facing away from the piezoelectric layer) can be electrically connected. In addition, the conductive structure is generally made of a metal material with good electrical conductivity, and thus the thermal conductivity of the conductive structure is also good. In this way, the heat generated on the front side of the filter chip can be transferred to the position of the through hole through the substrate, and the heat can be quickly discharged through the conductive structure in the through hole. Thereby, the heat dissipation capacity of the wafer-level packaging structure is improved, and then the power tolerance of the wafer-level packaging structure is improved.

[0049] On the third aspect, the embodiment of the present application further provides a radio frequency component. The radio frequency component provided by the embodiment of the present application may include any wafer-level packaging structure in the first aspect above, or the radio frequency component provided by the embodiment of the present application may include a wafer-level packaging structure manufactured by any manufacturing method in the second aspect above. In addition, the radio frequency component in the embodiment of the present application may also include a circuit board, and the circuit board is electrically connected to the conductive connector in the wafer-level packaging structure. Exemplarily, the conductive connector may be a conductive component such as a solder ball, and the wafer-level packaging structure may be electrically connected to the circuit board by welding or the like. Since the heat dissipation capacity of the wafer-level packaging structure in the embodiment of the present application is relatively high, and thus the power tolerance of the wafer-level packaging structure is relatively high, the power tolerance of the radio frequency component including the wafer-level packaging structure is also relatively high.

[0050] In a fourth aspect, embodiments of the present application further provide an electronic device. The electronic device in the embodiments of the present application may include: any of the radio frequency components described in the third aspect above, and a housing, wherein the radio frequency component is located within the housing. Because the radio frequency component has a high power tolerance, the electronic device including the radio frequency component also has a high power tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1 is a schematic structural diagram of a wafer-level packaging structure provided in an embodiment of the present application;

[0052] FIG2 is a schematic diagram of the three-dimensional structure of a wafer-level packaging structure provided in an embodiment of the present application;

[0053] FIG3 is another structural schematic diagram of the wafer-level packaging structure provided in an embodiment of the present application;

[0054] FIG4 is another schematic structural diagram of a wafer-level packaging structure provided in an embodiment of the present application;

[0055] FIG5 is another schematic structural diagram of a wafer-level packaging structure provided in an embodiment of the present application;

[0056] FIG6 is another structural schematic diagram of the wafer-level packaging structure provided in an embodiment of the present application;

[0057] FIG7 is a schematic diagram of the topological structure of the filter chip in an embodiment of the present application;

[0058] FIG8 is a flow chart of a method for manufacturing a wafer-level packaging structure provided by an embodiment of the present application;

[0059] Figures 9 to 14 are schematic structural diagrams corresponding to the steps of the manufacturing method provided in the embodiment of the present application;

[0060] FIG15 is a schematic diagram of grayscale simulation of the embodiment of the present application and the comparative example;

[0061] FIG16 is a schematic structural diagram of an electronic device in an embodiment of the present application.

[0062] Figure markings: 11-filter chip; 111-substrate; 112-electrode structure; 113-first solder pad; 114-second solder pad; 12-retaining wall; 121-pattern part; 122-hollow part; 13-protective layer; 14-conductive connector; 201-support layer; 202-piezoelectric layer; 203-acoustic reflection layer; 203a-low acoustic resistance layer; 203b-high acoustic resistance layer; 204-conductive structure; 100-resonator; 400-electronic device; 41-cover plate; 42-display screen; 43-middle frame; 431-carrying plate; 432-frame; 44-back shell; Q-cavity; T-through hole; t1-first through hole; t2-second through hole; t3-third through hole; Vi-input end; Vo-output end; GND-ground end. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0064] It should be noted that the drawings in this application are only used to illustrate relative positional relationships and do not represent true proportions. The same reference numerals in the drawings in this application represent the same or similar structures, and thus their repeated descriptions will be omitted.

[0065] Words expressing position and direction described in this application, such as the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., are all explained based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application. Changes can also be made as needed, and all changes are included in the scope of protection of this application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0066] In order to improve the heat dissipation capability of the surface acoustic wave filter, and further improve the power tolerance capability of the surface acoustic wave filter, the embodiment of the present application provides a wafer-level packaging structure, a manufacturing method thereof, a radio frequency component and an electronic device. The wafer-level packaging structure provided in the embodiment of the present application can be a surface acoustic wave filter. Of course, in some cases, the wafer-level packaging structure in the embodiment of the present application can also be other radio frequency devices. For example, the wafer-level packaging structure can also be a bulk acoustic wave filter, which is not limited here. The wafer-level packaging structure in the embodiment of the present application can be used as a component alone; or, the wafer-level packaging structure in the embodiment of the present application can also be integrated into a radio frequency component. The radio frequency component in the embodiment of the present application can be applied to various types of electronic devices, for example, it can be applied to terminal devices such as mobile phones, tablet computers, laptop computers, smart wearable devices, or it can also be applied to other electronic devices such as smart TVs, smart door locks, smart home appliances, etc.

[0067] FIG1 is a schematic structural diagram of a wafer-level packaging structure provided in an embodiment of the present application. As shown in FIG1 , the wafer-level packaging structure provided in an embodiment of the present application may include: a filter chip 11, a retaining wall 12, a protective layer 13, and a conductive connector 14. Specifically, the filter chip 11 may include: a substrate 111, an electrode structure 112, and a first pad 113. The substrate 111 may include: a stacked support layer 201 and a piezoelectric layer 202, wherein the support layer 201 and the piezoelectric layer 202 are formed of different materials. The electrode structure 112 and the first pad 113 are located on the side of the piezoelectric layer 202 facing away from the support layer 201. The retaining wall 12 is located on the side of the electrode structure 112 and the first pad 113 facing away from the support layer 201. The protective layer 13 is located on the side of the retaining wall 12 facing away from the support layer 201. The protective layer 13, retaining wall 12, and substrate 111 enclose a cavity Q, and at least a portion of the electrode structure 112 is located within the cavity Q. In some embodiments of the present application, the cavity Q is not filled with a dielectric material, and the cavity Q may be filled with a gas such as air to facilitate the transmission of sound waves. In one possible implementation, the electrode structure 112 and the first pad 113 may include a metal material such as gold, silver, or copper. The electrode structure 112 and the first pad 113 may include the same metal material, or the electrode structure 112 and the first pad 113 may include different metal materials.

[0068] The filter chip 11 in the embodiment of the present application may be a surface acoustic wave filter chip, and the substrate 111 may include a support layer 201 and a piezoelectric layer 202 arranged in a stacked manner, and the surface of the substrate 111 having the piezoelectric layer 202 is provided with an electrode structure 112. During the operation of the filter chip 11, sound waves can be generated in the piezoelectric layer 202 by applying a voltage to the electrode structure 112. After the sound waves generated in the piezoelectric layer 202 are transmitted to the surface of the substrate 111, they can be transmitted in the cavity Q surrounded by the protective layer 13, the retaining wall 12 and the substrate 111. The cavity Q is conducive to the transmission of sound waves and can improve the filtering effect of the filter chip 11. Of course, in some cases, the filter chip 11 may also be a bulk acoustic wave filter chip or other types of chips. In the embodiment of the present application, the filter chip 11 is taken as a surface acoustic wave filter chip as an example for explanation. Other types of chips can be implemented with reference to the example, and the repeated parts will not be repeated.

[0069] FIG2 is a schematic diagram of the three-dimensional structure of the wafer-level packaging structure provided in an embodiment of the present application. In conjunction with FIG1 and FIG2, the filter chip 11 in the embodiment of the present application is packaged in a wafer-level packaging manner. Specifically, a retaining wall 12 and a protective layer 13 are provided on the side of the substrate 111 having the piezoelectric layer 202. The retaining wall 12 has a pattern portion 121 and a hollow portion 122. The pattern portion 121 of the retaining wall 12 can cover the first pad 113, and the hollow portion 122 of the retaining wall 12 can expose the electrode structure 112. The protective layer 13 covers the pattern portion 121 and the hollow portion 122 of the retaining wall 12. Therefore, the retaining wall 12 and the protective layer 13 can provide good protection for the electrode structure 112 and the first pad 113. In addition, by providing a hollow portion 122 in the retaining wall 12, the protective layer 13, the retaining wall 12, and the substrate 111 can enclose a cavity Q, and at least a portion of the electrode structure 112 is located within the cavity Q, so that the acoustic waves generated by the electrode structure 112 can be transmitted within the cavity Q. In one possible implementation, the retaining wall 12 can be made of a photosensitive material. During the manufacturing process, the structure of the retaining wall 12 can be obtained through a photolithography process, which is relatively simple and has low manufacturing costs. For example, the retaining wall 12 can be made of a polyimide (PI) material. Of course, other insulating materials can also be used to make the retaining wall 12, which is not limited here. In one possible implementation, the sum of the thicknesses of the retaining wall 12 and the protective layer 13 is less than 100 μm. For example, the sum of the thicknesses of the retaining wall 12 and the protective layer 13 may be around 50 μm, and the outer edge of the retaining wall 12 may be substantially flush with the outer edge of the protective layer 13. In this way, the total volume of the wafer-level packaging structure may be smaller, which is conducive to the miniaturized design of the wafer-level packaging structure.

[0070] As shown in FIG1 , in the embodiment of the present application, the conductive connector 14 is located on the side of the support layer 201 facing away from the piezoelectric layer 202. The conductive connector 14 can electrically connect the filter chip 11 to other components. For example, when the wafer-level packaging structure in the embodiment of the present application is applied to a radio frequency component, the filter chip 11 can be electrically connected to a circuit board via the conductive connector 14. In one possible implementation, the conductive connector 14 can be a conductive component such as a solder ball, and the filter chip 11 can be electrically connected to the circuit board by welding or other methods.

[0071] Continuing with FIG1 , a through hole T is provided in the substrate 111. The through hole T may include: a first through hole t1 and a second through hole t2. The first through hole t1 passes through the support layer 201, and the second through hole t2 passes through the piezoelectric layer 202. The minimum aperture of the first through hole t1 is greater than the maximum aperture of the second through hole t2. The substrate 111 is provided with a conductive structure 204 in the through hole T. The conductive structure 204 passes through the first through hole t1 and the second through hole t2 in a direction perpendicular to the surface of the substrate 111. One end of the conductive structure 204 is electrically connected to the first pad 113, and the other end is electrically connected to the conductive connector 14. In the embodiment of the present application, by providing the through hole T in the substrate 111 and providing the conductive structure 204 in the through hole T, the first pad 113 on the front side of the filter chip 11 (i.e., the surface of the piezoelectric layer 202 facing away from the support layer 201) can be electrically connected to the conductive connector 14 on the back side of the filter chip 11 (i.e., the surface of the support layer 201 facing away from the piezoelectric layer 202). The heat dissipation path of the filter chip 11 is indicated by the white arrows in FIG1 . The conductive structure 204 is generally made of a metal material with good electrical conductivity, and therefore, the conductive structure 204 also has good thermal conductivity. Thus, heat generated on the front surface of the filter chip 11 can be transferred through the substrate 111 to the location of the through-hole T, and then quickly dissipated through the conductive structure 204 within the through-hole T. This improves the heat dissipation capability of the wafer-level packaging structure, thereby increasing its power handling capability.

[0072] Furthermore, the support layer 201 in the substrate 111 may comprise silicon (Si). Since silicon has excellent thermal conductivity (approximately 130 W / m / K), the substrate 111 also has excellent thermal conductivity. This allows heat generated on the front surface of the filter chip 11 to be rapidly transferred to the location of the through-hole T through the substrate 111, further enhancing the heat dissipation capability of the wafer-level packaging structure.

[0073] In addition, in an embodiment of the present application, the support layer 201 and the piezoelectric layer 202 include different materials. For example, the support layer 201 may include a silicon material, and the piezoelectric layer 202 may include at least one of a lithium niobate material, a lithium tantalate material, a zinc oxide material, and an aluminum nitride material. Of course, the support layer 201 may also include other materials that can play a supporting role, and the piezoelectric layer 202 may also include other piezoelectric materials, which are not limited here. The thickness of the support layer 201 can be in the range of 100um to 500um, and the thickness of the piezoelectric layer 202 can be in the range of 100nm to 1um. During the manufacturing process, the piezoelectric layer 202 is more difficult to etch than the support layer 201, and the etching rate of the piezoelectric layer 202 is slower. Therefore, the aperture of the second through hole t2 in the etched piezoelectric layer 202 is smaller. During the manufacturing process, different etching processes can be used to etch the piezoelectric layer 202 and the support layer 201, thereby reducing the etching difficulty of a single etching process. Furthermore, by setting the aperture of the first through hole t1 in the support layer 201 to be larger, the cross-sectional area of ​​the conductive structure 204 can be increased, and the on-resistance of the conductive structure 204 can be reduced, thereby improving the electrical performance of the wafer-level packaging structure.

[0074] In some embodiments of the present application, as shown in FIG1 , the substrate 111 may further include: an acoustic reflection layer 203 located between the support layer 201 and the piezoelectric layer 202. The acoustic reflection layer 203 may reflect the sound waves transmitted toward the support layer 201 back to the front of the filter chip 11, so that the sound waves are concentrated on the surface (front) of the filter chip 11, thereby reducing the loss of the sound waves. The above-mentioned through hole T may further include: a third through hole t3, the third through hole t3 passes through the acoustic reflection layer 203, and the maximum aperture of the second through hole t2 is smaller than the minimum aperture of the third through hole t3. The conductive structure 204 also passes through the third through hole t3 in a direction perpendicular to the surface of the substrate 111. That is, in some embodiments, the conductive structure 204 passes through the first through hole t1, the third through hole t3, and the second through hole t2 in a direction perpendicular to the surface of the substrate 111. Since the piezoelectric layer 202 is more difficult to etch than the acoustic reflection layer 203 , the etching rate of the piezoelectric layer 202 is slower. Therefore, the maximum aperture of the etched second through hole t2 is smaller than the minimum aperture of the third through hole t3 .

[0075] Since the acoustic reflective layer 203 has a wide range of material options and the etching rates of different materials vary greatly, the etching rate of the acoustic reflective layer 203 may be lower than the etching rate of the support layer 201, or the etching rate of the acoustic reflective layer 203 may be higher than the etching rate of the support layer 201. In one possible implementation, as shown in FIG1 , when the etching rate of the acoustic reflective layer 203 is lower than the etching rate of the support layer 201, the maximum aperture of the third through hole t3 in the acoustic reflective layer 203 may be lower than the minimum aperture of the first through hole t1 in the support layer 201. In another possible implementation, as shown in FIG3 , which is another schematic structural diagram of a wafer-level packaging structure provided in an embodiment of the present application, when the etching rate of the acoustic reflective layer 203 is higher than the etching rate of the support layer 201, the maximum aperture of the third through hole t3 in the acoustic reflective layer 203 may be higher than the minimum aperture of the first through hole t1 in the support layer 201. Due to the relatively large thickness of the support layer 201, the diameter of the first through hole t1 at certain locations may be larger than the maximum diameter of the third through hole t3. Of course, in some cases, the minimum diameter of the third through hole t3 in the acoustic reflection layer 203 may also be larger than the maximum diameter of the first through hole t1 in the support layer 201, and this can be set according to actual conditions.

[0076] 1 and 3 , during the fabrication process, the support layer 201 may be etched using a deep silicon etching process to form a first through hole t1 penetrating the support layer 201. The acoustic reflective layer 203 and the piezoelectric layer 202 may be etched using an inductively coupled plasma-reactive ion etching (ICP-RIE) process to form a third through hole t3 penetrating the acoustic reflective layer 203 and a second through hole t2 penetrating the piezoelectric layer 202. Due to the different etching processes or etching rates of different film layers, steps may be formed at the interfaces between the different film layers during the drilling process of the substrate 111, resulting in the through hole T having a stepped shape at the interface between the different film layers. Specifically, the location where the first through hole t1 connects to the second through hole t2 is stepped, and the location where the second through hole t2 connects to the third through hole t3 is also stepped.

[0077] Continuing with Figures 1 and 3 , during the manufacturing process, to avoid damaging the electrode structure 112, first pad 113, and other structures on the front surface of the filter chip 11, the filter chip 11 is typically placed with its backside facing upward during the drilling process of the substrate 111, and etching is performed inward from the surface of the substrate 111 with the support layer 201. Consequently, in the direction from the support layer 201 toward the piezoelectric layer 202 (from bottom to top in Figures 1 and 3 ), the aperture of the first through hole t1 decreases, the aperture of the second through hole t2 decreases, and the aperture of the third through hole t3 decreases.

[0078] FIG4 is another schematic diagram of the structure of a wafer-level package structure provided in an embodiment of the present application. As shown in FIG4 , in one possible implementation, the acoustic reflective layer 203 may include: at least one low-acoustic-resistance layer 203a and at least one high-acoustic-resistance layer 203b alternately stacked, wherein the acoustic resistance of the high-acoustic-resistance layer 203b is greater than or equal to three times the acoustic resistance of the low-acoustic-resistance layer 203a. For example, the low-acoustic-resistance layer 203a may include: at least one of silicon dioxide (SiO2), silicon oxynitride (SiNO), and tantalum pentoxide (Ta2O5), and the high-acoustic-resistance layer 203b may include: at least one of sapphire, aluminum oxide (Al2O3), silicon nitride (SiN), and aluminum nitride (AlN). FIG4 illustrates an example in which the acoustic reflective layer 203 includes three low-resistance layers 203a and three high-resistance layers 203b. The number of low-resistance layers 203a and high-resistance layers 203b can be adjusted based on actual needs, without limitation. FIG5 illustrates another schematic diagram of a wafer-level package structure according to an embodiment of the present application. As shown in FIG5 , in another possible implementation, the acoustic reflective layer 203 may include only the low-resistance layer 203a. For example, the low-resistance layer 203a may include at least one of silicon dioxide (SiO2), silicon oxynitride (SiNO), and tantalum pentoxide (Ta2O5). The thickness of the low-resistance layer 203a may be in the range of 100 nm to 1 μm. It should be noted that to more clearly illustrate the specific structure of the acoustic reflective layer 203, structures such as through-holes, conductive structures, retaining walls, and protective layers are not shown in FIG4 and FIG5 .

[0079] As shown in FIG1 , in some embodiments of the present application, the conductive structure 204 can fill the through hole T. In a direction perpendicular to the surface of the substrate 111, the first pad 113 and the through hole T have an overlapping area, and the conductive connector 14 and the through hole T have an overlapping area. One end of the conductive structure 204 is in contact with the first pad 113, and the other end is in contact with the conductive connector 14. This arrangement allows the first pad 113 on the front of the filter chip 11 to be electrically connected to the conductive connector 14 on the back side through the conductive structure 204. In addition, the contact area between the conductive structure 204 and the first pad 113 and the conductive connector 14 is large, which improves the electrical connection effect between the conductive structure 204 and the first pad 113 and the conductive connector 14, thereby improving the electrical performance of the wafer-level packaging structure. In the structure shown in FIG1 , the conductive structure 204 is in contact with the conductive connector 14. In some cases, the conductive structure 204 can also be indirectly connected to the conductive connector 14 through components such as a redistribution layer and an adapter plate, which can be arranged according to actual conditions.

[0080] FIG6 is another schematic diagram of the structure of a wafer-level package provided in an embodiment of the present application. As shown in FIG6 , in other embodiments of the present application, in a direction perpendicular to the surface of the substrate 111, the first pad 113 and the through-hole T have an overlapping area, and the conductive connector 14 and the through-hole T do not overlap. The filter chip 11 may also include: a second pad 114 located on the side of the substrate 111 facing away from the electrode structure 112. A conductive structure 204 covers the inner wall of the through-hole T. One end of the conductive structure 204 is in contact with the first pad 113 and the other end is electrically connected to the second pad 114. The conductive connector 14 is also in contact with the second pad 114. The conductive structure 204 can be electrically connected to the conductive connector 14 via the second pad 114, thereby achieving electrical continuity between the first pad 113 on the front surface of the filter chip 11 and the conductive connector 14 on the back surface via the conductive structure 204 and the second pad 114. Furthermore, the conductive structure 204 does not fill the through hole T. The heat generated on the front side of the filter chip 11 is transferred to the position of the through hole T through the substrate 111 and can be directly dissipated into the air through the conductive structure 204, thereby improving the heat dissipation efficiency of the filter chip 11.

[0081] In a specific configuration, the conductive structure 204 can be connected to the second pad 114 as a whole. During the manufacturing process, after forming the through hole T in the substrate 111, the same metal deposition process can be used to form a metal layer covering the inner wall of the through hole T and extending to the surface of the substrate 111 on the side away from the electrode structure 112, thereby obtaining the conductive structure 204 and the second pad 114 electrically connected to each other. In the structure shown in FIG6 , the second pad 114 is in contact with the conductive connector 14. In some cases, the second pad 114 can also be indirectly connected to the conductive connector 14 through components such as a redistribution layer and an adapter plate, which can be configured according to actual conditions.

[0082] As shown in Figures 1 and 2, in an embodiment of the present application, by providing a through hole T and a conductive structure 204 in the substrate 111, the first pad 113 on the front of the filter chip 11 can be connected to the back through the conductive structure 204, without the need to lead out the electrical signal of the first pad 113 through the retaining wall 12 and the protective layer 13, that is, there is no need to pattern the protective layer 13, which can reduce the steps of the manufacturing process. Therefore, the protective layer 13 can be set as a full-surface film layer without a pattern. In this way, the material selection range of the protective layer 13 is relatively large. For example, the protective layer 13 can include a non-photosensitive material. Of course, the protective layer 13 can also be made of other materials that can play a protective function, which is not limited here.

[0083] FIG7 is a schematic diagram of the topological structure of the filter chip in the embodiment of the present application. As shown in FIG7 , the filter chip 11 in the embodiment of the present application may include a plurality of cascaded resonators 100, each of which may be cascaded in series and parallel, and each of which may have a different resonant frequency. In addition, the filter chip 11 may further include an input terminal Vi, an output terminal Vo, and a ground terminal GND, and the plurality of cascaded resonators 100 may be electrically connected to the input terminal Vi, the output terminal Vo, and the ground terminal GND. The electrode structure in the embodiment of the present application may include a plurality of interdigitated electrodes, and each resonator 100 may correspond to at least one interdigitated electrode.

[0084] The filter chip in the embodiment of the present application can be a low-pass filter chip, a high-pass filter chip, a band-pass filter chip, a band-stop filter chip or an active filter chip, etc.

[0085] Based on the same technical concept, the embodiment of the present application also provides a method for manufacturing a wafer-level packaging structure. Figure 8 is a flow chart of the method for manufacturing a wafer-level packaging structure provided by the embodiment of the present application, and Figures 9 to 14 are schematic diagrams of the structures corresponding to the steps in the manufacturing method provided by the embodiment of the present application. As shown in Figure 8, the method for manufacturing a wafer-level packaging structure provided by the embodiment of the present application may include:

[0086] S301, referring to Figure 9, provides a substrate 111. The substrate 111 may include a support layer 201 and a piezoelectric layer 202 that are stacked, and the support layer 201 and the piezoelectric layer 202 are made of different materials.

[0087] For example, the support layer 201 may include a silicon material, and the piezoelectric layer 202 may include at least one of a lithium niobate material, a lithium tantalate material, a zinc oxide material, and an aluminum nitride material. Of course, the support layer 201 may also include other materials capable of providing support, and the piezoelectric layer 202 may also include other piezoelectric materials, which are not limited herein. The thickness of the support layer 201 may be in the range of 100 μm to 500 μm, and the thickness of the piezoelectric layer 202 may be in the range of 100 nm to 1 μm.

[0088] In some embodiments of the present application, the substrate 111 may further include an acoustic reflection layer 203 located between the support layer 201 and the piezoelectric layer 202. The acoustic reflection layer 203 may include at least one low-acoustic-resistance layer and at least one high-acoustic-resistance layer alternately stacked, with the acoustic resistance of the high-acoustic-resistance layer being greater than or equal to three times the acoustic resistance of the low-acoustic-resistance layer. For example, the low-acoustic-resistance layer may include at least one of silicon dioxide (SiO2), silicon oxynitride (SiNO), and tantalum pentoxide (Ta2O5), and the high-acoustic-resistance layer may include at least one of sapphire, aluminum oxide (Al2O3), silicon nitride (SiN), and aluminum nitride (AlN). Alternatively, the acoustic reflection layer 203 may include only the low-acoustic-resistance layer. During implementation, the specific structure of the acoustic reflection layer 203 may be configured according to actual needs.

[0089] S302 , referring to FIG. 10 , the substrate 111 is positioned so that the side having the piezoelectric layer 202 faces upward, and an electrode structure 112 and a first pad 113 are formed on the piezoelectric layer 202 .

[0090] In a specific configuration, the electrode structure 112 and the first pad 113 may include metal materials such as gold, silver, and copper. In one possible implementation, the electrode structure 112 and the first pad 113 may include the same metal material. During the manufacturing process, a metal film layer may be formed on the surface of the substrate 111 on the side having the piezoelectric layer 202. By patterning the metal film layer, the structure of the electrode structure 112 and the first pad 113 is obtained, that is, the electrode structure 112 and the first pad 113 may be manufactured using the same patterning process. Of course, in some cases, the electrode structure 112 and the first pad 113 may also include different metal materials, and different patterning processes may be used to manufacture the electrode structure 112 and the first pad 113.

[0091] S303 , referring to FIG. 11 , sequentially forming a retaining wall 12 and a protective layer 13 on the electrode structure 112 and the first pad 113 , so that the protective layer 13 , the retaining wall 12 and the substrate 111 form a cavity Q, and at least a portion of the electrode structure 112 is located within the cavity Q.

[0092] During the manufacturing process, an entire insulating film can be formed on the electrode structure 112 and the first pad 113, and the structure of the retaining wall 12 can be obtained by patterning the insulating film. Optionally, an insulating film can be formed on the electrode structure 112 and the first pad 113 by coating or deposition, or a pre-made insulating film can be directly attached to the electrode structure 112 and the first pad 113. In one possible implementation, a photosensitive material can be used to make the insulating film, so that the structure of the retaining wall 12 can be formed by a photolithography process, the manufacturing process is relatively simple, and the manufacturing cost is low. For example, a photosensitive material such as polyimide (PI) material can be used to make the insulating film. Of course, other insulating materials can also be used to make the retaining wall 12, which is not limited here.

[0093] Afterwards, the prefabricated protective layer 13 can be directly attached to the retaining wall 12, such that the protective layer 13 is aligned with the patterned portion of the retaining wall 12 and is suspended in the hollowed portion of the retaining wall 12, thereby forming a cavity Q between the protective layer 13, the retaining wall 12, and the substrate 111. In the embodiment of the present application, the protective layer 13 is a solid film layer without a pattern. The material selection range for the protective layer 13 is relatively wide; for example, the protective layer 13 may include a non-photosensitive material. Of course, the protective layer 13 may also be made of other materials that can provide a protective function, and this is not limited here.

[0094] S304, referring to FIG. 12 , with the side of the substrate 111 having the support layer 201 facing upward, the substrate 111 is patterned to form a through hole T in the substrate 111. The through hole T may include a first through hole t1 and a second through hole t2. The first through hole t1 penetrates the support layer 201, and the second through hole t2 penetrates the piezoelectric layer 202. The minimum aperture of the first through hole t1 is greater than the maximum aperture of the second through hole t2. In a specific implementation, to facilitate contact and connection between the conductive structure subsequently formed in the through hole T and the first pad 113, the drilling position of the substrate 111 corresponds to the position of the first pad 113, so that the through hole T can expose at least a portion of the first pad 113.

[0095] In an embodiment of the present application, the support layer 201 and the piezoelectric layer 202 include different materials. For example, the support layer 201 may include a silicon material, and the piezoelectric layer 202 may include at least one of a lithium niobate material, a lithium tantalate material, a zinc oxide material, and an aluminum nitride material. The thickness of the support layer 201 may be in the range of 100um to 500um, and the thickness of the piezoelectric layer 202 may be in the range of 100nm to 1um. Since the materials of the support layer 201 and the piezoelectric layer 202 are different, the piezoelectric layer 202 is more difficult to etch than the support layer 201, and therefore, it is difficult to form a through hole T through the substrate 111 using the same etching process. In an embodiment of the present application, different etching processes may be used to etch the piezoelectric layer 202 and the support layer 201. Specifically, the above-mentioned step S304 may specifically include:

[0096] With the side of the substrate 111 having the support layer 201 facing upward, a deep silicon etching process is used to etch from the surface of the support layer 201 toward the interior of the support layer 201 to form a first through hole t1 penetrating the support layer 201;

[0097] Afterwards, an inductively coupled plasma-reactive ion etching (ICP-RIE) process is used to etch from the surface of the piezoelectric layer 202 close to the support layer 201 toward the inside of the piezoelectric layer 202 to form a second through hole t2 penetrating the piezoelectric layer 202 .

[0098] In the embodiment of the present application, different etching processes are used to etch the piezoelectric layer 202 and the support layer 201. The support layer 201 is first etched using a deep silicon etching process, and then the piezoelectric layer 202 is etched using an inductively coupled plasma-reactive ion etching process. Compared with the deep silicon etching process, the inductively coupled plasma-reactive ion etching process has a higher plasma concentration and can etch materials that are more difficult to etch. Therefore, in the embodiment of the present application, different etching processes can be reasonably selected according to the materials of the support layer 201 and the piezoelectric layer 202 to etch the support layer 201 and the piezoelectric layer 202 respectively, which can reduce the etching difficulty of a single etching process and improve the feasibility and reliability of the substrate 111 drilling process.

[0099] Because the piezoelectric layer 202 is more difficult to etch than the support layer 201, the etching rate of the piezoelectric layer 202 is slower. Consequently, the diameter of the second through hole t2 in the piezoelectric layer 202 obtained by etching is smaller. Furthermore, during the etching process of the piezoelectric layer 202, a portion of the inner wall of the first through hole t1 in the support layer 201 is inevitably etched away, which may also increase the diameter of the first through hole t1 in the support layer 201. Therefore, after etching the support layer 201 and the piezoelectric layer 202, the minimum diameter of the first through hole t1 in the support layer 201 is larger than the maximum diameter of the second through hole t2 in the piezoelectric layer 202.

[0100] Continuing with FIG. 12 , in some embodiments of the present application, the substrate 111 may further include an acoustic reflection layer 203 located between the support layer 201 and the piezoelectric layer 202. Since the acoustic reflection layer 203 is more difficult to etch than the support layer 201, and the piezoelectric layer 202 is more difficult to etch than the acoustic reflection layer 203, it is difficult to etch the support layer 201, the acoustic reflection layer 203, and the piezoelectric layer 202 using the same etching process. When the substrate 111 includes the support layer 201, the acoustic reflection layer 203, and the piezoelectric layer 202, the above step S304 may specifically include:

[0101] With the side of the substrate 111 having the support layer 201 facing upward, a deep silicon etching process is used to etch from the surface of the support layer 201 toward the interior of the support layer 201 to form a first through hole t1 penetrating the support layer 201;

[0102] Then, an inductively coupled plasma-reactive ion etching process is used to etch from the surface of the acoustic reflective layer 203 close to the support layer 201 toward the interior of the acoustic reflective layer 203 to form a third through hole t3 penetrating the acoustic reflective layer 203;

[0103] Afterwards, an inductively coupled plasma-reactive ion etching process is used to etch from the surface of the piezoelectric layer 202 close to the support layer 201 toward the interior of the piezoelectric layer 202 to form a second through hole t2 penetrating the piezoelectric layer 202 .

[0104] Because both the acoustic reflector layer 203 and the piezoelectric layer 202 are relatively difficult to etch, the inductively coupled plasma-reactive ion etching process is used for both the acoustic reflector layer 203 and the piezoelectric layer 202. This makes it easier to form a through hole that penetrates the acoustic reflector layer 203 and the piezoelectric layer 202, reducing the difficulty of a single etching process. Furthermore, using the same etching process for both the acoustic reflector layer 203 and the piezoelectric layer 202 reduces the frequency of etching equipment replacement and improves the efficiency of the etching process.

[0105] Because the piezoelectric layer 202 is more difficult to etch than the acoustic reflector layer 203, the etching rate of the piezoelectric layer 202 is slower. Therefore, the diameter of the second through hole t2 in the piezoelectric layer 202 obtained by etching is smaller. That is, the maximum diameter of the second through hole t2 in the piezoelectric layer 202 is smaller than the minimum diameter of the first through hole t1 in the support layer 201, and the maximum diameter of the second through hole t2 in the piezoelectric layer 202 is smaller than the minimum diameter of the third through hole t3 in the acoustic reflector layer 203. Furthermore, because the acoustic reflector layer 203 can be made from a wide range of materials, the etching rates of different materials vary significantly. Therefore, the etching rate of the acoustic reflector layer 203 may be lower than that of the support layer 201, or the etching rate of the acoustic reflector layer 203 may be higher than that of the support layer 201. Therefore, the maximum aperture of the third through hole t3 in the acoustic reflection layer 203 can be smaller than the minimum aperture of the first through hole t1 in the supporting layer 201; alternatively, the maximum aperture of the third through hole t3 in the acoustic reflection layer 203 can be larger than the minimum aperture of the first through hole t1 in the supporting layer 201. Due to the relatively large thickness of the supporting layer 201, the aperture of the first through hole t1 at certain locations may be larger than the maximum aperture of the third through hole t3. Of course, in some cases, the minimum aperture of the third through hole t3 in the acoustic reflection layer 203 may also be larger than the maximum aperture of the first through hole t1 in the supporting layer 201.

[0106] Due to the different etching processes or etching rates of different film layers, steps will be formed at the interfaces between different film layers during the process of drilling the substrate 111, so that the through hole T is stepped at the interfaces between different film layers. Specifically, the position where the first through hole t1 connects with the second through hole t2 is stepped, and the position where the second through hole t2 connects with the third through hole t3 is stepped.

[0107] S305. Forming a conductive structure electrically connected to the first pad within the through hole, and forming a conductive connector electrically connected to the conductive structure; wherein the conductive structure extends through the first through hole and the second through hole in a direction perpendicular to the substrate surface. In one embodiment, when the substrate includes an acoustic reflective layer, the conductive structure further extends through the third through hole in a direction perpendicular to the substrate surface.

[0108] 13 , in one possible implementation, a conductive material may be filled in the through hole T to form a conductive structure 204 that fills the through hole T. The bottom of the through hole T exposes at least a portion of the first pad 113, so that the conductive structure 204 can be in contact and connected with the first pad 113. Afterwards, a conductive connector 14 may be formed at the location of the conductive structure 204, so that the conductive connector 14 is in contact and connected with the conductive structure 204. Exemplarily, the conductive connector 14 may be a solder ball, and the conductive connector 14 may be formed at the location of the conductive structure 204 using a ball implantation process. In the structure shown in FIG13 , the conductive structure 204 is in contact and connected with the conductive connector 14. In some cases, the conductive structure 204 may also be indirectly connected to the conductive connector 14 through components such as a redistribution layer and an adapter plate, which may be configured according to actual conditions.

[0109] 14 , in another possible implementation, a metal deposition process can be used to form a conductive structure 204 covering the inner wall of the through hole T, and the conductive structure 204 is in contact with and connected to the first pad 113 exposed at the bottom of the through hole T. In addition, to facilitate electrical connection between the conductive structure 204 and the subsequently formed conductive connector 14, a second pad 114 can be formed on the surface of the substrate 111 facing away from the electrode structure 112, and the second pad 114 is electrically connected to the conductive structure 204. Subsequently, a conductive connector 14 can be formed at the location of the second pad 114, and the conductive connector 14 is in contact with and connected to the second pad 114, thereby electrically connecting the conductive connector 14 to the conductive structure 204 through the second pad 114. During the manufacturing process, the same metal deposition process can be used to form a metal layer covering the inner wall of the through hole T and extending to the surface of the substrate 111 facing away from the electrode structure 112, thereby obtaining the electrically connected conductive structure 204 and the second pad 114. In the structure shown in FIG14 , the second pad 114 is in contact with the conductive connector 14 . In some cases, the second pad 114 may also be indirectly connected to the conductive connector 14 through a redistribution layer, an adapter board, or other components, and may be configured according to actual conditions.

[0110] In the embodiment of the present application, by forming a through hole T in the substrate 111 and forming a conductive structure 204 in the through hole T, the first pad 113 on the front side of the filter chip (i.e., the surface of the piezoelectric layer 202 facing away from the support layer 201) can be electrically connected to the conductive connector 14 on the back side of the filter chip (i.e., the surface of the support layer 201 facing away from the piezoelectric layer 202). In addition, the conductive structure 204 is generally made of a metal material with good conductive properties, and therefore, the thermal conductivity of the conductive structure 204 is also good. In this way, the heat generated on the front side of the filter chip can be transferred to the position of the through hole T through the substrate 111, and the heat can be quickly discharged through the conductive structure 204 in the through hole T. Thereby, the heat dissipation capacity of the wafer-level packaging structure is improved, and then the power tolerance of the wafer-level packaging structure is improved.

[0111] The above describes the specific structure of the wafer-level packaging structure provided by the embodiment of the present application, and introduces the method for manufacturing the wafer-level packaging structure provided by the embodiment of the present application. The following compares the embodiment of the present application with the comparative example to introduce the effect of improving the heat dissipation capacity of the wafer-level packaging structure provided by the embodiment of the present application.

[0112] Figure 15 is a grayscale simulation diagram of the embodiment of the present application and the comparative example. (1) in Figure 15 is a simulation diagram of the heat dissipation effect of the wafer-level packaging structure in the comparative example. After the heat generated on the front of the filter chip in the comparative example is transferred to the position of the first pad, the heat is dissipated through the retaining wall and the protective layer. (2) in Figure 15 is a simulation diagram of the heat dissipation effect of the wafer-level packaging structure in the embodiment of the present application. In Figure 15, the input power of the wafer-level packaging structure of the embodiment of the present application and the comparative example is the same. The darker the color, the higher the temperature, and the lighter the color, the lower the temperature. It can also be clearly seen from the comparison of (1) and (2) in Figure 15 that the color of the wafer-level packaging structure in the embodiment of the present application shown in (2) in Figure 15 is lighter, indicating that the surface temperature of the wafer-level packaging structure in the embodiment of the present application is lower, indicating that the wafer-level packaging structure in the embodiment of the present application can quickly export heat and has a better heat dissipation effect.

[0113] Taking the wafer-level packaging structure in the embodiment of the present application and the comparative example, which includes 5 rows and 5 columns of resonators, as an example, and when the input power of the wafer-level packaging structure in the embodiment of the present application and the comparative example is the same, the thermal resistance matrix of the wafer-level packaging structure in the embodiment of the present application and the comparative example is compared and analyzed. Table 1 is the thermal resistance matrix of the wafer-level packaging structure in the comparative example, and Table 2 is the thermal resistance matrix of the wafer-level packaging structure in the embodiment of the present application. By comparing Table 1 and Table 2, it can be seen that the thermal resistance matrix parameters in Table 2 are significantly lower than the thermal resistance matrix parameters at the corresponding positions in Table 1, indicating that under the same input power, the heat dissipation capacity of the wafer-level packaging structure in the embodiment of the present application is better, so that the temperature of the wafer-level packaging structure in the steady state is lower.

[0114] Table 1 Thermal resistance matrix of wafer-level packaging structure in comparative example

[0115] Table 2 Thermal resistance matrix of wafer-level packaging structure in the embodiment of the present application

[0116] Table 3 Temperature of each resonator in the embodiment of the present application and the comparative example at the same input power

[0117] Table 3 shows the temperature of each resonator in the embodiment of the present application and the comparative example under the same input power. It can be seen more intuitively from Table 3 that under the same input power, the temperature of each resonator in the embodiment of the present application is much lower than the temperature of the resonator at the corresponding position in the comparative example. The temperature rise of each resonator in the embodiment of the present application is approximately 1 / 3 to 1 / 4 of the temperature rise of the resonator at the corresponding position in the comparative example. This shows that the wafer-level packaging structure in the embodiment of the present application has better heat dissipation capability.

[0118] Based on the same technical concept, an embodiment of the present application also provides a radio frequency component. The radio frequency component provided by the embodiment of the present application may include any of the above-mentioned wafer-level packaging structures, or the radio frequency component provided by the embodiment of the present application may include a wafer-level packaging structure manufactured by any of the above-mentioned manufacturing methods. In addition, the radio frequency component in the embodiment of the present application may also include a circuit board, and the circuit board is electrically connected to the conductive connector in the wafer-level packaging structure. Exemplarily, the conductive connector may be a conductive component such as a solder ball, and the wafer-level packaging structure may be electrically connected to the circuit board by welding or the like. Since the heat dissipation capacity of the wafer-level packaging structure in the embodiment of the present application is relatively high, and thus the power tolerance of the wafer-level packaging structure is relatively high, the power tolerance of the radio frequency component including the wafer-level packaging structure is also relatively high.

[0119] Based on the same technical concept, embodiments of the present application further provide an electronic device. The electronic device in the embodiments of the present application may include: any of the above-mentioned RF components and a housing, wherein the RF component is located within the housing. Because the above-mentioned RF components have a high power tolerance, the electronic device including the RF components also has a high power tolerance.

[0120] The electronic devices in the embodiments of the present application may be consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products, and communication electronic products. Among them, consumer electronic products may be mobile phones, tablet computers (pads), laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (such as smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may be smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (such as soybean milk machines, sweeping robots, etc.), etc. Vehicle-mounted electronic products may be car navigation systems, car high-density digital video discs (DVDs), etc. Financial terminal products may be automated teller machines (ATMs), self-service terminals, etc. Communication electronic products may be communication equipment such as servers, storage devices, radars, and base stations.

[0121] The following describes the structure of the electronic device in the embodiment of the present application, taking consumer electronic products such as mobile phones, tablet computers, and laptop computers as examples. Figure 16 is a schematic structural diagram of an electronic device in the embodiment of the present application. As shown in Figure 16, the electronic device 400 mainly includes a cover plate 41, a display screen 42, a middle frame 43, and a rear shell 44. Among them, the rear shell 44 can be a part of the above-mentioned shell, and the rear shell 44 and the display screen 42 are respectively located on both sides of the middle frame 43, and the middle frame 43 and the display screen 42 are arranged in the rear shell 44. The cover plate 41 is arranged on the side of the display screen 42 away from the middle frame 43, and the display surface of the display screen 42 faces the cover plate 41.

[0122] The display screen 42 can be a liquid crystal display (LCD), which can include a liquid crystal display panel and a backlight module. The LCD panel can be disposed between the cover plate 41 and the backlight module, which provides light for the LCD panel. The display screen 42 can also be an organic light emitting diode (OLED) display. Since OLED displays are self-luminous, a backlight module is not required.

[0123] The middle frame 43 may include a carrier plate 431 and a frame 432 surrounding the carrier plate 431. The electronic device 400 may also include electronic components such as printed circuit boards (PCBs), batteries, and cameras. The printed circuit boards, batteries, and cameras may be mounted on the carrier plate 431.

[0124] The electronic device 400 may further include a system-on-chip (SOC), a radio frequency component, etc., which are arranged on a printed circuit board PCB. The radio frequency component may be the radio frequency component described above in the embodiment of the present application. The printed circuit board PCB is used to carry the system-on-chip, the radio frequency component, etc., and is electrically connected to the system-on-chip, the radio frequency component, etc. Among them, the radio frequency component may include a filter chip, a processor, and other parts. The processor is used to process various signals, and the filter chip is an important part of radio frequency signal processing, which is used to pass signals of a specific frequency and block signals of other frequencies.

[0125] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0126] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A wafer-level packaging structure, characterized in that: include: filter chips, retaining walls, protective layers and conductive connectors; The filter chip comprises: a substrate, an electrode structure and a first pad; The substrate comprises: a supporting layer and a piezoelectric layer which are stacked, wherein the supporting layer and the piezoelectric layer are made of different materials; The electrode structure and the first pad are located on a side of the piezoelectric layer facing away from the support layer, the retaining wall is located on a side of the electrode structure and the first pad facing away from the support layer, and the protective layer is located on a side of the retaining wall facing away from the support layer; the protective layer, the retaining wall, and the substrate form a cavity, and at least a portion of the electrode structure is located within the cavity; The conductive connecting member is located on a side of the supporting layer away from the piezoelectric layer; The substrate is provided with a through hole, and the through hole includes: a first through hole and a second through hole, the first through hole passes through the support layer, the second through hole passes through the piezoelectric layer, and the minimum aperture of the first through hole is larger than the maximum aperture of the second through hole; the substrate is provided with a conductive structure in the through hole, the conductive structure passes through the first through hole and the second through hole in a direction perpendicular to the surface of the substrate, and one end of the conductive structure is electrically connected to the first pad, and the other end is electrically connected to the conductive connector.

2. The wafer-level packaging structure according to claim 1, wherein: The substrate further comprises: an acoustic reflection layer located between the support layer and the piezoelectric layer; The through hole further includes: a third through hole, the third through hole passing through the acoustic reflection layer, and the maximum aperture of the second through hole is smaller than the minimum aperture of the third through hole; The conductive structure further passes through the third through hole in a direction perpendicular to the substrate surface.

3. The wafer-level packaging structure according to claim 2, wherein: The position where the first through hole and the second through hole are connected is stepped, and the position where the second through hole and the third through hole are connected is stepped.

4. The wafer-level packaging structure according to claim 2, wherein: In the direction from the support layer to the piezoelectric layer, the aperture of the first through hole tends to decrease, the aperture of the second through hole tends to decrease, and the aperture of the third through hole tends to decrease.

5. The wafer-level packaging structure according to any one of claims 1 to 4, wherein: The conductive structure fills the through hole; In a direction perpendicular to the surface of the substrate, the first pad and the through hole have an overlapping area, and the conductive connection member and the through hole have an overlapping area; One end of the conductive structure is in contact with and connected to the first pad, and the other end is in contact with and connected to the conductive connector.

6. The wafer-level packaging structure according to any one of claims 1 to 4, wherein: In a direction perpendicular to the surface of the substrate, the first pad and the through hole have an overlapping area, and the conductive connecting member and the through hole do not overlap each other; The filter chip further includes: a second pad located on a side of the substrate away from the electrode structure; The conductive structure covers the inner wall of the through hole, one end of the conductive structure is in contact with and connected to the first pad, and the other end is electrically connected to the second pad, and the conductive connector is in contact with and connected to the second pad.

7. The wafer-level packaging structure according to any one of claims 2 to 6, wherein: The acoustic reflection layer comprises: at least one low acoustic resistance layer and at least one high acoustic resistance layer alternately stacked; the acoustic resistance of the high acoustic resistance layer is greater than or equal to three times the acoustic resistance of the low acoustic resistance layer; Alternatively, the acoustic reflection layer only includes a low acoustic resistance layer.

8. The wafer-level packaging structure according to any one of claims 1 to 7, wherein: The support layer includes silicon material, and the piezoelectric layer includes at least one of lithium niobate material, lithium tantalate material, zinc oxide material, and aluminum nitride material.

9. The wafer-level packaging structure according to any one of claims 1 to 8, wherein: The protective layer is a whole-surface film layer without any pattern, and the protective layer comprises a non-photosensitive material.

10. A method for manufacturing a wafer-level packaging structure, characterized in that: include: Providing a substrate; the substrate comprises a support layer and a piezoelectric layer stacked together, wherein the support layer and the piezoelectric layer comprise different materials; The substrate is placed with the piezoelectric layer facing upward, and an electrode structure and a first pad are formed on the piezoelectric layer; forming a retaining wall and a protective layer in sequence on the electrode structure and the first pad, so that the protective layer, the retaining wall and the substrate form a cavity, and at least a portion of the electrode structure is located in the cavity; The substrate is placed with the support layer facing upward, and patterned to form through holes in the substrate; wherein the through holes include: a first through hole and a second through hole, the first through hole penetrates the support layer, the second through hole penetrates the piezoelectric layer, and the minimum aperture of the first through hole is larger than the maximum aperture of the second through hole; A conductive structure electrically connected to the first pad is formed in the through hole, and a conductive connector electrically connected to the conductive structure is formed; wherein the conductive structure passes through the first through hole and the second through hole in a direction perpendicular to the surface of the substrate.

11. The production method according to claim 10, characterized in that: The support layer comprises silicon material, and the piezoelectric layer comprises at least one of lithium niobate material, lithium tantalate material, zinc oxide material, and aluminum nitride material; The patterning of the substrate to form a through hole in the substrate specifically includes: With the side of the substrate having the support layer facing upward, a deep silicon etching process is used to etch from the surface of the support layer toward the interior of the support layer to form a first through hole penetrating the support layer; An inductively coupled plasma-reactive ion etching process is adopted to etch from a surface of the piezoelectric layer close to the support layer toward an interior of the piezoelectric layer to form a second through hole penetrating the piezoelectric layer.

12. The production method according to claim 11, wherein: The substrate further comprises: an acoustic reflection layer located between the support layer and the piezoelectric layer; After forming the first through hole and before forming the second through hole, the method further includes: An inductively coupled plasma-reactive ion etching process is adopted to etch from the surface of the acoustic reflection layer close to the support layer toward the interior of the acoustic reflection layer to form a third through hole penetrating the acoustic reflection layer.

13. A radio frequency component, characterized in that: include: The wafer-level packaging structure according to any one of claims 1 to 9; Or, a wafer-level packaging structure manufactured by the manufacturing method according to any one of claims 10 to 12; The radio frequency component further includes a circuit board, which is electrically connected to the conductive connector in the wafer-level packaging structure.

14. An electronic device, characterized in that: include: The RF component and housing according to claim 13, wherein the RF component is located inside the housing.

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