Semiconductor device and imaging device

Abstract

The present invention improves the radiation resistance of a solid-state imaging element.　A semiconductor device (100) is characterized by comprising a semiconductor substrate (1) and a pixel circuit (10) formed on the semiconductor substrate, wherein: the pixel circuit includes a first semiconductor region (1) of a first conductivity type in the semiconductor substrate, a second semiconductor region (2) of a second conductivity type formed above the first semiconductor region and which, together with the first semiconductor region, forms a photodiode, insulating layers (5, 5a, 5b) formed around the photodiode in the semiconductor substrate in a planar view observed from a direction perpendicular to the plane of the semiconductor substrate, and electrode layers (6, 6a, 6b) formed on the insulating layer; and when the depth of the insulating layer in the direction perpendicular to the plane of the semiconductor substrate is denoted as D1 and the distance between the edge of the insulating layer on the photodiode side in the plane direction of the semiconductor substrate and the edge of the electrode layer on the photodiode side in the plane direction is denoted as D2, D2 < D1 is satisfied.

Description

Semiconductor device and imaging device

[0001] The present invention relates to a semiconductor device and an imaging device, and for example, to a semiconductor device having a solid-state imaging element formed on a semiconductor substrate.

[0002] In decommissioning work at nuclear facilities, imaging devices are attached to the tip of robot arms, etc., in order to perform work while understanding the situation inside the facility in a high-radiation environment. In recent years, as imaging devices to be used in high-radiation environments, there has been a demand for radiation-resistant cameras that are small, lightweight, and have high image quality, rather than the large, low-image-quality image pickup tubes used in conventional radiation-resistant cameras.

[0003] However, it is known that the characteristics of solid-state imaging devices formed on semiconductor substrates are degraded by the total dose effect of radiation such as gamma rays. For example, in the case of solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors, the dark current of the photodiodes serving as optical sensors increases due to the ionization caused by the total dose effect of gamma rays, resulting in operational malfunction due to whiteout.

[0004] Specifically, when radiation hits an element isolation oxide film layer (hereinafter also referred to as "STI") around a photodiode that constitutes a pixel, fixed positive charges (radiation induced positive charges) are generated due to the total dose effect, and the influence of these fixed positive charges inverts the P-well region near the STI to N-type, forming an N-type inversion region (induced N-region). Dark current flows from this N-type inversion region into the N-type diffusion region of the photodiode, which may cause a whiteout in the image.

[0005] Whiteout caused by the total dose effect can shorten the lifespan of solid-state imaging devices and ultimately cameras. For example, the cumulative radiation dose, which is an indicator of the radiation resistance of an image pickup tube, is several megaGy, while the cumulative radiation dose of a solid-state imaging device is several kiloGy to 100 kiloGy. As such, conventional solid-state imaging devices cannot be said to have high radiation resistance.

[0006] Meanwhile, a technology for improving the radiation resistance of solid-state imaging devices is disclosed in Patent Document 1. Specifically, Patent Document 1 describes that an electrode is disposed in an STI around a photodiode constituting a pixel, and a negative voltage is applied to the electrode, thereby offsetting the effect of an electric field from fixed positive charges generated by radiation and reducing dark current flowing into an N-type diffusion region of the photodiode.

[0007] Japanese Patent Application Laid-Open No. 2019-201164

[0008] Prior to filing this application, the inventors of the present application have studied a solid-state imaging device having a new structure based on the technology disclosed in the above-mentioned Patent Document 1. This study has revealed the following problems.

[0009] Generally, the STI in a solid-state imaging device is formed of an oxide film having a thickness (depth) that is at least one order of magnitude greater than that of the gate oxide film of a MOS transistor. Therefore, in order to sufficiently reduce dark current using the technology disclosed in Patent Document 1, it is necessary to generate a very large potential difference between the STI and the semiconductor substrate. That is, it is necessary to apply a negative voltage (e.g., −20 V to −30 V) having an absolute value greater than the power supply voltage (e.g., 3.3 V) applied to a typical CMOS sensor to the STI around the photodiode. When a semiconductor device is used under such a high bias condition, corrosion of the wiring within the semiconductor device may be accelerated depending on the operating environment, which may result in wiring breakage and other problems, potentially reducing the reliability of the semiconductor device.

[0010] The present invention has been made in view of the above-mentioned problems, and has an object to improve the radiation resistance of a solid-state imaging device.

[0011] A semiconductor device according to a representative embodiment of the present invention comprises a semiconductor substrate and a pixel circuit formed on the semiconductor substrate, the pixel circuit having a first semiconductor region of a first conductivity type in the semiconductor substrate, a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region, an insulating layer formed around the photodiode in the semiconductor substrate in a planar view seen in a direction perpendicular to the plane of the semiconductor substrate, and an electrode layer formed on the insulating layer, wherein when a depth of the insulating layer in a direction perpendicular to the plane of the semiconductor substrate is D1 and a distance between an end of the insulating layer on the photodiode side in the planar direction of the semiconductor substrate and an end of the electrode layer on the photodiode side in the planar direction is D2, D2<D1.

[0012] According to the semiconductor device of the present invention, it is possible to improve the radiation resistance of the solid-state imaging device.

[0013] 2A . FIG. 2B is a diagram showing the configuration of one pixel circuit constituting a solid-state imaging element as a semiconductor device according to an embodiment. FIG. 2C is a plan view showing the layout configuration of a pixel circuit of a semiconductor device according to an embodiment. FIG. 2D is a diagram schematically showing a cross-sectional structure of a portion AA′ of the pixel circuit shown in FIG. 2A. FIG. 2E is an enlarged view of a pixel circuit in a range indicated by reference sign S in FIG. 2A. FIG. 2F is a plan view showing the layout configuration of a semiconductor device in which a plurality of pixel circuits according to an embodiment are arranged. FIG. 2G is a diagram schematically showing the dark current suppression effect in a pixel circuit according to an embodiment. FIG. 2H is a diagram schematically showing the dark current suppression effect in a pixel circuit studied by the present inventor prior to filing the present application as a comparative example of the pixel circuit according to the embodiment. FIG. 2I is a diagram for explaining the dark current suppression effect of a pixel circuit according to an embodiment. FIG. 2J is a diagram showing an example of the configuration of an imaging device including a pixel circuit according to an embodiment. FIG. 2J is a diagram showing another example of the configuration of an imaging device including a pixel circuit according to an embodiment. FIG. 2I is a plan view showing the layout configuration of a pixel circuit according to another embodiment. 10B is a diagram schematically showing a cross-sectional structure of the pixel circuit shown in FIG. 10A taken along the line BB'. FIG.

[0014] 1. Overview of the Embodiments First, an overview of representative embodiments of the invention disclosed in this application will be described. Note that in the following description, as an example, reference numerals in the drawings corresponding to components of the invention are written in parentheses.

[0015] [1] A semiconductor device (100, 100A) according to a representative embodiment of the present invention comprises a semiconductor substrate (1) and a pixel circuit (10, 10A) formed on the semiconductor substrate, wherein the pixel circuit has a first semiconductor region (1) of a first conductivity type in the semiconductor substrate, a second semiconductor region (2) of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region, an insulating layer (5, 5a, 5b) formed around the photodiode in the semiconductor substrate in a planar view seen from a direction perpendicular to the plane of the semiconductor substrate (Z-axis direction), and an electrode layer (6, 6a, 6b) formed on the insulating layer, wherein D2 is a distance between an end of the insulating layer on the photodiode side in the planar direction of the semiconductor substrate and an end of the electrode layer on the photodiode side in the planar direction, and D2 satisfies the relationship D2<D1.

[0016] [2] In the semiconductor device described in [1] above, when the width of the electrode layer in the planar direction is defined as D3, D1≦D3 may be satisfied.

[0017] [3] In the semiconductor device described in [2] above, the insulating layer may include a first insulating layer (5a) and a second insulating layer (5b) formed at a distance from the first insulating layer in the planar direction, and may further include a third semiconductor region (3, 3A, 3a, 3b) of the first conductivity type formed between the first insulating layer and the second insulating layer on the first semiconductor region of the semiconductor substrate, and the electrode layer may include a first electrode layer (6a) formed on the first insulating layer and a second electrode layer (6b) formed on the second insulating layer.

[0018] [4] In the semiconductor device described in [3] above, the third semiconductor region (3) may be formed in a form that continuously surrounds at least a part of the periphery of the photodiode in a plan view.

[0019] [5] In the semiconductor device (100A) described above in [3], the third semiconductor region (3A) may be formed in a form that discontinuously surrounds at least a portion of the periphery of the photodiode in a plan view.

[0020] [6] In the semiconductor device (100A) described in [5] above, in a planar view, the length (L2) in the extension direction of the third semiconductor region extending along one side of the photodiode may be equal to or greater than half the length (L1) of that side of the photodiode PPD.

[0021] [7] In the semiconductor device (100A) described in [5] above, in a plan view, the plurality of third semiconductor regions (3A_1, 3A_2) may be formed spaced apart from each other along one side of the photodiode.

[0022] [8] In the semiconductor device described in [3] or [4] above, when the distance between the end of the first insulating layer on the side of the third semiconductor region in the planar direction and the end of the first electrode layer on the side of the third semiconductor region in the planar direction is D4, D4 may be less than D1.

[0023] [9] In the semiconductor device described in [3], [4] or [8] above, when the distance between the end of the second insulating layer on the side of the third semiconductor region in the planar direction and the end of the second electrode layer on the side of the third semiconductor region in the planar direction is D5, D5 may be less than D1.

[0024]

[10] In the semiconductor device according to [3], [4], [8], or [9] above, when the width of the second electrode layer in the planar direction is defined as D6, D1 may be less than or equal to D6.

[0025]

[11] An imaging device (200, 200A) according to a representative embodiment of the present invention includes the semiconductor device (100) described in any one of [1] to

[10] above, and a voltage supply circuit (30, 30A) that supplies a voltage (Vneg(-)) lower than a ground potential (GND) to the electrode layer, wherein the first semiconductor region is connected to the ground potential, and the voltage supply circuit may be capable of changing the magnitude of the voltage supplied to the electrode layer.

[0026] 2. Specific Examples of Embodiments Specific examples of embodiments of the present invention will be described below with reference to the drawings. In the following description, components common to each embodiment will be designated by the same reference numerals, and repeated description will be omitted. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from reality. The drawings may also include portions with different dimensional relationships and ratios. In this specification, the first conductivity type will be described as P-type and the second conductivity type as N-type, as an example, but the present invention is not limited to this.

[0027] FIG. 1 is a diagram showing the configuration of one pixel circuit that constitutes a solid-state imaging device as a semiconductor device according to an embodiment.

[0028] The semiconductor device 100 according to the first embodiment is, for example, a CMOS image sensor serving as a solid-state imaging device. The semiconductor device 100 is formed on a single semiconductor substrate such as silicon using, for example, a known CMOS LSI (Large Scale Integration) manufacturing process technology.

[0029] The semiconductor device 100 has a plurality of pixel circuits 10 formed on a semiconductor substrate 1. The pixel circuits 10 are, for example, four-transistor pixel circuits having four transistors, also known as APS (Active Pixel Sensor). Specifically, the pixel circuits 10 have a photodiode PPD, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplification transistor Mdrv, and a selection transistor Msel.

[0030] The photodiode PPD is, for example, a pinned photodiode, as will be described later. In the photodiode PPD, the anode electrode is connected to the ground potential GND, and the cathode electrode is connected to the source of the transfer transistor Mtg.

[0031] The transfer transistor Mtg is an element for transferring the charge of the photodiode PPD, and is, for example, a MOS transistor of the second conductivity type (N-type).

[0032] The transfer transistor Mtg has a source electrode connected to the cathode electrode of the photodiode PPD and a drain electrode connected to the gate electrode of the amplifier transistor Mdrv and the source electrode of the reset transistor Mfdr. A binary signal φTG is input to the gate electrode of the transfer transistor Mtg. The transfer transistor Mtg is switched on and off by the signal φTG.

[0033] The charge storage unit (floating diffusion) FD stores the charge transferred by the transfer transistor Mtg. The charge storage unit FD is formed at a node where the drain electrode of the transfer transistor Mtg, the gate electrode of the amplification transistor Mdrv, and the source electrode of the reset transistor Mfdr are commonly connected. The charge storage unit FD is realized by, for example, floating capacitance such as parasitic capacitance present at the node.

[0034] The reset transistor Mfdr is a charge discharging element that resets the voltage of the charge storage unit FD. The reset transistor (charge discharging transistor) Mfdr is, for example, a second conductivity type (N-channel) MOS transistor. The source electrode of the reset transistor Mfdr is connected to the charge storage unit FD, and the drain electrode of the reset transistor Mfdr is connected to a power supply voltage VRR. A binary signal φFDR is input to the gate electrode of the reset transistor Mfdr. The reset transistor Mfdr is switched on and off by the signal φFDR.

[0035] The amplifier transistor Mdrv is an element that amplifies a signal corresponding to the charge stored in the charge storage unit FD. The amplifier transistor Mdrv is, for example, a MOS transistor of a second conductivity type (N-channel type) and forms a source follower circuit.

[0036] The drain electrode of the amplifier transistor Mdrv is connected to the power supply voltage VDD, the gate electrode of the amplifier transistor Mdrv is connected to the charge storage unit FD, and the source electrode of the amplifier transistor Mdrv is connected to the output signal line OUT via the selection transistor Msel.

[0037] The selection transistor Msel is an element that switches whether or not the signal amplified by the amplifier transistor Mdrv is output to the output signal line OUT. The selection transistor Msel is, for example, a MOS transistor of the second conductivity type (N-channel type).

[0038] The drain electrode of the selection transistor Msel is connected to the source electrode of the amplification transistor Mdrv, and the source electrode of the selection transistor Msel is connected to the output signal line OUT. A signal φSEL is input to the gate electrode of the selection transistor Msel. The selection transistor Msel is switched on and off by the signal φSEL.

[0039] Here, the power supply voltage VDD is the power supply for the source follower circuit (amplification transistor Mdrv), and the power supply voltage VRR is the power supply for resetting the charge storage unit FD and the photodiode PPD. By separating the power supply voltages VDD and VRR, it becomes possible to optimize the operating conditions of the pixels. Furthermore, although the present embodiment illustrates a case where the power supply voltages VDD and VRR are separated, this is not limiting, and the power supply voltages VDD and VRR may be a common voltage.

[0040] The photodiode PPD accumulates charge in response to a received optical signal. The transfer transistor Mtg turns on when the signal φTG is enabled and transfers the charge accumulated by the photodiode PPD to the charge accumulation unit FD. The amplification transistor Mdrv amplifies a signal corresponding to the charge accumulated in the charge accumulation unit FD and outputs it to node N1. The selection transistor Msel turns on when the signal φSEL is enabled and outputs the signal from node N1 to the output signal line OUT. The reset transistor Mfdr turns on when the signal φFDR is enabled and connects the power supply voltage VRR to the charge accumulation unit FD. This causes the electrons accumulated in the charge accumulation unit FD to be discharged to the power supply voltage VRR, resetting the charge accumulation unit FD.

[0041] Next, a layout configuration of the pixel circuit 10 formed on the semiconductor substrate will be described. Fig. 2A is a plan view showing the layout configuration of the pixel circuit 10 of the semiconductor device 100 according to the embodiment.

[0042] FIG. 2B is a diagram schematically showing the cross-sectional structure of the pixel circuit 10 taken along line AA' in FIG. 2A.

[0043] FIG. 2C is an enlarged view of the pixel circuit 10 in the area indicated by reference character S in FIG. 2A.

[0044] In the following description, in the plan views and cross-sectional views of Figures 2A, 2B, and 2C, it is assumed that the semiconductor substrate 1 is disposed in a three-dimensional space defined by the X-, Y-, and Z-axes, and that the plane (main surface) of the semiconductor substrate 1 is parallel to the X-Y plane. It is also assumed that the line segment connecting points A and A' is parallel to the X-axis. For ease of explanation, the positive side in the Z-axis direction may be referred to as "up" and the negative side in the Z-axis direction as "down."

[0045] 2A and 2C show the layout configuration of the pixel circuit 10 in a plan view seen from a direction perpendicular to the plane (XY plane) of the semiconductor substrate 1 that constitutes the semiconductor device 100. Note that in FIGS. 2A to 2C, some of the wiring layers that connect circuit elements to each other are not shown.

[0046] The semiconductor substrate 1 is, for example, a P-type semiconductor substrate. The semiconductor substrate 1 is formed by doping silicon with a P-type impurity such as boron (B) (for example, by ion implantation), and functions as a first semiconductor region (P--) of a first conductivity type.

[0047] An N-well (N-) 2 is formed as a second semiconductor region of a second conductivity type on a first semiconductor region (P--) of a first conductivity type. The N-well 2 is formed, for example, by doping a semiconductor substrate 1 with an N-type impurity such as P (phosphorus).

[0048] In this embodiment, the first semiconductor region is, for example, the semiconductor substrate 1 (P--) itself. As shown in Figures 2A and 2B, the first semiconductor region (semiconductor substrate 1) and the N-well 2 form a PN junction photodiode.

[0049] In the semiconductor device 100, a pinning layer 4 is formed on the N well 2 as a P-type semiconductor layer (P+) having a higher P-type impurity concentration than the semiconductor substrate 1. The pinning layer 4 is formed, for example, by doping (e.g., ion implantation) the surface of the semiconductor substrate 1 with P-type impurities (e.g., boron (B) or the like). By forming the pinning layer 4, the photodiode becomes a buried photodiode PPD. In this embodiment, the buried photodiode PPD is also simply referred to as a "photodiode PPD."

[0050] More specifically, the photodiode PPD is formed, for example, in a polygonal shape in a planar view. Here, a polygonal shape refers to a shape having three or more corners, and examples thereof include a triangular shape, a rectangular shape (quadrilateral shape), a pentagonal shape, and a hexagonal shape. In this embodiment, as an example, the photodiode PPD is described as being formed in a rectangular shape, but this is not limited thereto. For example, the photodiode PPD may be circular in a planar view, or a portion of the photodiode PPD may be arc-shaped in a planar view.

[0051] 2A, in a plan view seen from a direction perpendicular to the plane of the semiconductor substrate 1 (Z-axis direction), an insulating layer 5 is formed around the photodiode PPD in the semiconductor substrate 1. The insulating layer 5 is an element isolation layer (element isolation oxide layer: STI) for isolating adjacent elements (pixel circuits 10) in the semiconductor device 100. The insulating layer 5 is made of, for example, a silicon oxide film (SiO ２ ) is formed.

[0052] In the semiconductor device 100 according to this embodiment, it is possible to apply a voltage to the insulating layer 5. That is, an electrode layer 6 is formed on the insulating layer 5, and a negative voltage can be applied to the insulating layer 5 via the electrode layer 6. The electrode layer 6 is made of, for example, polysilicon (poly-Si).

[0053] For example, the electrode layer 6 is preferably connected to a potential lower than the ground potential via a wiring layer made of a metal material (not shown). That is, it is preferable to apply a negative voltage Vneg(−) to the electrode layer 6.

[0054] 2A and 2B, the insulating layer 5 formed around the photodiode PPD is roughly divided into two regions. For example, the insulating layer 5 includes an insulating layer (STI) 5a adjacent to the photodiode PPD and an insulating layer (STI) 5b formed at a distance from the insulating layer 5a in the planar direction (XY planar direction) of the semiconductor substrate 1. Of the electrode layers 6 formed on the insulating layer 5, the electrode layer 6 formed on the insulating layer 5a is referred to as "electrode layer 6a," and the electrode layer 6 formed on the insulating layer 5b is referred to as "electrode layer 6b."

[0055] 2A , insulating layer 5a and insulating layer 5b may be formed so as to be partially connected to each other on semiconductor substrate 1. Similarly, electrode layer 6a and electrode layer 6b may be formed so as to be partially connected to each other on insulating layer 5a and insulating layer 5b. In this way, when a voltage is applied to one of electrode layer 6a and electrode layer 6b, the same voltage is also applied to the other.

[0056] 2A and 2B, a third semiconductor region 3 serving as a P-type semiconductor layer is formed between insulating layers 5a and 5b on the semiconductor substrate 1. The third semiconductor region 3 is formed by doping silicon with P-type impurities such as boron (B). The third semiconductor region 3 includes, for example, a P-well 3a (P-) having a higher P-type impurity concentration than the semiconductor substrate 1. The P-well 3a is electrically connected to, for example, the semiconductor substrate 1 and the pinning layer 4.

[0057] The third semiconductor region 3 further includes a P diffusion region 3b (P++) having a higher impurity concentration than the P well 3a. The P diffusion region 3b is formed on the P well 3a. The P diffusion region 3b is a region for connecting to an electrode layer for applying a voltage to the P well 3a, and as shown in FIG. 2B , is electrically connected to a wiring layer 8 (Metal) made of metal via a contact layer 7. Here, the wiring layer 8 is connected to, for example, ground potential. This connects the third semiconductor region 3 to ground potential.

[0058] 2A , the third semiconductor region 3 is formed in a shape that surrounds at least a portion of the periphery of the photodiode PPD in a planar view. More specifically, the third semiconductor region 3 is formed in a shape that surrounds at least one side of the polygonal photodiode PPD in a planar view. For example, in the case where the photodiode PPD is rectangular as in the present embodiment, the third semiconductor region 3 is formed in a shape that continuously surrounds at least three of the four sides of the photodiode PPD. As will be described later, the third semiconductor region 3 functions as a guard band that suppresses the generation of dark current due to the total dose effect.

[0059] Here, the dimensions around the insulating layer 5 are as follows: D1 is the length (depth) of the insulating layer 5 in the direction perpendicular to the plane of the semiconductor substrate (Z-axis direction), and D2 is the distance between the end of the insulating layer 5a on the photodiode PPD side in the planar direction of the semiconductor substrate 1 (XY planar direction) and the end of the electrode layer 6a on the photodiode PPD side in the planar direction, so that D2<D1.

[0060] 2B and 2C , for example, the distance (D2) between one side of the insulating layer 5a adjacent to one side parallel to the X-axis of the rectangular photodiode PPD and one side of the electrode layer 6a parallel to the X-axis on the photodiode PPD side is shorter than the depth (D1) in the Z-axis direction of the insulating layer 5. Similarly, the distance (D2) between one side of the insulating layer 5a adjacent to one side parallel to the Y-axis of the photodiode PPD and one side of the electrode layer 6a parallel to the Y-axis on the photodiode PPD side is shorter than the depth (D1) in the Z-axis direction of the insulating layer 5.

[0061] When the width of the electrode layer 6a in the planar direction of the semiconductor substrate 1 is D3, it is preferable that D1≦D3. For example, in Figures 2B and 2C, the width (D3) in the X-axis direction of the electrode layer 6a extending parallel to the Y-axis direction on the insulating layer 5a is longer than the depth (D1) of the insulating layer 5a in the Z-axis direction. Similarly, the width (D3) in the Y-axis direction of the electrode layer 6a extending parallel to the X-axis direction on the insulating layer 5a is longer than the depth (D1) of the insulating layer 5a in the Z-axis direction.

[0062] When the distance between the end of the insulating layer 5a on the third semiconductor region 3 side (opposite the photodiode PPD) in the planar direction and the end of the electrode layer 6a on the third semiconductor region 3 side (opposite the photodiode PPD) in the planar direction is D4, D4<D1 may be satisfied, or D4=D2 may be satisfied.

[0063] 2B and 2C , the distance (D4) between one side of the insulating layer 5a adjacent to one side of the third semiconductor region 3 parallel to the X-axis direction and one side of the electrode layer 6a parallel to the X-axis direction on the third semiconductor region 3 side is shorter than the depth (D1) in the Z-axis direction of the insulating layer 5. Similarly, the distance (D4) between one side of the insulating layer 5a adjacent to one side of the third semiconductor region 3 parallel to the Y-axis direction and one side of the electrode layer 6a parallel to the Y-axis direction on the third semiconductor region 3 side is shorter than the depth (D1) in the Z-axis direction of the insulating layer 5.

[0064] If the distance between the end of the insulating layer 5b on the third semiconductor region 3 side (photodiode PPD side) in the planar direction and the end of the electrode layer 6b on the third semiconductor region 3 side (photodiode PPD side) in the planar direction is D5, D5 may be less than D1.

[0065] 2B and 2C , the distance (D5) between one side of the insulating layer 5b adjacent to one side of the third semiconductor region 3 parallel to the X-axis direction and one side of the electrode layer 6b parallel to the X-axis direction on the third semiconductor region 3 side is shorter than the depth (D1) of the insulating layer 5b in the Z-axis direction. Similarly, the distance (D5) between one side of the insulating layer 5b adjacent to one side of the third semiconductor region 3 parallel to the Y-axis direction and one side of the electrode layer 6b parallel to the Y-axis direction on the third semiconductor region 3 side is shorter than the depth (D1) of the insulating layer 5b in the Z-axis direction.

[0066] When the width of electrode layer 6b in the planar direction of semiconductor substrate 1 is defined as D6, it is preferable that D1≦D6. For example, in Figures 2B and 2C, the width (D6) in the X-axis direction of electrode layer 6b extending parallel to the Y-axis direction on insulating layer 5b is longer than the depth (D1) of insulating layer 5a in the Z-axis direction. Similarly, the width (D6) in the Y-axis direction of electrode layer 6b extending parallel to the X-axis direction on insulating layer 5b is longer than the depth (D1) of insulating layer 5b in the Z-axis direction.

[0067] Furthermore, when the width of the third semiconductor region 3 in the planar direction of the semiconductor substrate 1 is defined as D7, it is preferable that D7≧D1.

[0068] 2A , in a plan view, in a region on the one side (a side other than the three sides) of the rectangular photodiode PPD, circuit elements other than the photodiode PPD that constitute the pixel circuit 10 are formed. For example, as shown in FIG. 2A , in a region on the one side on the negative side of the Y axis of the photodiode PPD, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplifier transistor Mdrv, and a selection transistor Msel are formed.

[0069] As shown in FIG. 2B, a SiO.sub.2 film is deposited on the surface of the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method. ２ A PMD (Pre Metal Dielectric) 9, which is a transparent insulating film such as a PMD film, is formed on the substrate.

[0070] Next, an example of arrangement in which a plurality of pixel circuits 10 shown in FIG. 2A are arranged on the semiconductor substrate 1 will be described.

[0071] FIG. 3 is a plan view showing the layout configuration of a semiconductor device 100 in which a plurality of pixel circuits 10 according to the embodiment are arranged.

[0072] 2A, 2B, and 2C, the semiconductor substrate 1 is arranged in a three-dimensional space defined by the X-axis, Y-axis, and Z-axis, and the plane of the semiconductor substrate 1 is parallel to the X-Y plane. Note that in FIG. 3, wiring layers connecting circuit elements, except for the bottommost layer, are not shown. In the plane of the semiconductor substrate 1 shown in FIG. 3, the Y-axis direction, which is a predetermined direction, is the column direction, and the X-axis direction is the row direction.

[0073] 3, in the semiconductor device 100, a plurality of pixel circuits 10 are formed on a semiconductor substrate, aligned in the row and column directions in the plane of the semiconductor substrate 1. In each pixel circuit 10, for example, a transfer transistor Mtg, a reset transistor Mfdr, an amplifier transistor Mdrv, and a selection transistor Msel are formed (arranged) on one side in the column direction (negative side in the Y-axis direction), and a photodiode PPD is formed on the other side in the column direction (positive side in the Y-axis direction).

[0074] As shown in FIG. 3, pixel circuits 10 adjacent to each other in the row direction (X-axis direction) have an insulating layer (STI) 5b and an electrode layer 6b that are common to each other in the row direction.

[0075] Here, it is preferable to adjust the range of STI in the row direction so that the distance between adjacent photodiodes PPD in the row direction (X-axis direction) (e.g., the distance between the centers of each photodiode PPD) is equal. This makes it possible to uniformize the resolution of pixels in the horizontal direction. Similarly, it is preferable to adjust the range of STI in the column direction so that the distance between adjacent photodiodes PPD in the column direction (Y-axis direction) (e.g., the distance between the centers of each photodiode PPD) is equal. This makes it possible to uniformize the resolution of pixels in the column direction.

[0076] Next, the effects of the semiconductor device 100 according to the embodiment having the above-described structure will be described.

[0077] First, the effect of suppressing dark current when no voltage (bias) is applied to the insulating layer 5 (electrode layer 6) in the pixel circuit 10 will be described.

[0078] Fig. 4 is a diagram schematically illustrating the dark current suppression effect in pixel circuit 10 according to the embodiment. Fig. 5 is a diagram schematically illustrating the dark current suppression effect in pixel circuit 90, which the present inventors investigated prior to filing the present application, as a comparative example of pixel circuit 10 according to the embodiment.

[0079] Fig. 4 schematically shows dark current electrons when radiation (ionizing radiation) such as gamma rays is irradiated to the pixel circuit 10 in a state where no bias (voltage) is applied to the electrode layer 6 of the insulating layer 5 of the pixel circuit 10. Fig. 5 schematically shows the flow of dark current when radiation (ionizing radiation) such as gamma rays is irradiated to the pixel circuit 90 in a state where no bias (voltage) is applied to the electrode layer 96 of the STI 95 of the pixel circuit 90, which the inventor of the present application studied prior to filing the present application.

[0080] 5, when the pixel circuit 90 according to the prior study example is irradiated with radiation, a fixed positive charge (+) is generated near the boundary between the STI 95 and the P-well 93 due to the total dose effect. Then, due to the influence of the electric field caused by the fixed positive charge (+), dark current electrons (-) that are naturally generated by thermal excitation or the like are accumulated near the boundary. Some of these dark current electrons (-) flow into the photodiode PPD through the depletion layer, generating dark current and causing whiteout in the image.

[0081] On the other hand, in the pixel circuit 10 according to the embodiment, as shown in FIG. 4 , the third semiconductor region 3 is formed between the insulating layer 5 a and the insulating layer 5 b, and the third semiconductor region 3 is connected to ground potential, so that holes (+) are supplied from the third semiconductor region 3 to the vicinity of the boundary between the STI 5 and the P-well 3. As a result, these holes (+) recombine with some of the dark current electrons (-) generated near the boundary, thereby reducing the dark current electrons (-). In other words, the dark current electrons (-) are swept from the third semiconductor region 3 to the ground potential. This makes it possible to reduce the dark current flowing into the photodiode PPD.

[0082] 2A , the third semiconductor region 3 is formed in a form that continuously surrounds at least a part of the periphery of the photodiode PPD in plan view, so that holes (+) are supplied over a wide range at the boundary between the STI 5 and the P-well 3, thereby further reducing the dark current that flows into the photodiode PPD. However, it is considered that the effect of reducing the dark current is limited only to the vicinity of the third semiconductor region 3 (guard band).

[0083] Next, the effect of suppressing dark current when a negative voltage is applied to the insulating layer 5 (electrode layer 6) in the pixel circuit 10 will be described.

[0084] Fig. 6 is a diagram schematically illustrating the dark current suppression effect in pixel circuit 10 according to the embodiment. Fig. 7 is a diagram schematically illustrating the dark current suppression effect in pixel circuit 90, which the inventors of the present application investigated prior to filing the present application, as a comparative example of pixel circuit 10 according to the embodiment.

[0085] 6 schematically shows dark current electrons when radiation (ionizing radiation) such as gamma rays is applied to pixel circuit 10 in a state where a negative voltage Vneg(-) is applied to electrode layer 6 of insulating layer 5 in pixel circuit 10 according to the embodiment. Fig. 7 schematically shows the flow of dark current when radiation (ionizing radiation) such as gamma rays is applied to pixel circuit 90 in a state where a negative voltage Vneg(-) is applied to electrode layer 96 of STI 95 in pixel circuit 90 that the inventor of the present application studied prior to filing the present application.

[0086] As shown in FIG. 7 , when the pixel circuit 90 according to the prior study is irradiated with radiation, the electric field within the STI 95 contributes to weakening the electric field of the inversion layer resulting from the fixed positive charge (+) generated by the total dose effect, thereby reducing the dark current electrons (−) flowing into the photodiode PPD. However, in reality, the film thickness (depth) of the STI 95 is at least one order of magnitude greater than that of the gate oxide film of the MOS transistor, and the distance between the electrode layer 96 formed on the STI 95 and the end of the STI 95 (the boundary between the STI 95 and the P-well 3a) is long, making it impossible to generate a sufficient electric field within the STI 95. As a result, the electric field of the inversion layer resulting from the fixed positive charge (+) generated by the total dose effect cannot be sufficiently weakened, and the dark current electrons (−) flowing into the photodiode PPD cannot be sufficiently suppressed. To achieve the effect of sufficiently suppressing dark current electrons (−) in the pixel circuit 90, as described above, it is believed that a very high negative voltage several times greater than the gate breakdown voltage of the MOS transistor must be applied. To generate such a very high negative voltage, a voltage generation circuit separate from the voltage generation circuit used in a normal CMOS sensor is required, resulting in disadvantages such as increased costs.

[0087] In contrast to this, the pixel circuit 10 according to the embodiment makes it possible to suppress the generation of dark current electrons due to the total dose effect without increasing the negative voltage Vneg(−) applied to the electrode layer 6 .

[0088] Specifically, in pixel circuit 10, a distance D2 between the end of insulating layer 5a on the photodiode PPD side in the planar direction (XY planar direction) and the end of electrode layer 6a on the photodiode PPD side in the planar direction (XY planar direction) is shorter than a depth D1 of insulating layer 5 (D2<D1), and therefore, compared to pixel circuit 90 according to the previously discussed prior example, the spread of electric field lines between electrode layer 6 and the side surface of insulating layer 5 on the photodiode PPD side is smaller, and a substantially stronger electric field can be exerted within insulating layer 5. This makes it possible to more effectively suppress the generation of dark current electrons at the boundary between the side surface of insulating layer 5 on the photodiode PPD side and P-well 3a.

[0089] Furthermore, in pixel circuit 10, by forming electrode layer 6a over a wide area on insulating layer 5a so that width D3 of electrode layer 6a in the planar direction is equal to or greater than depth D1 of insulating layer 5a (D1≦D3), the spread of electric field lines within insulating layer 5 is reduced, making it possible to generate a strong electric field overall within insulating layer 5. This makes it possible to strengthen the electric field overall from electrode layer 6a to the vicinity of the boundary between insulating layer 5a and P-well 3a compared to pixel circuit 90 according to the previously discussed prior example, thereby making it possible to more effectively suppress the generation of dark current electrons due to the total dose effect.

[0090] Furthermore, in the pixel circuit 10, the distance D4 between the end of the insulating layer 5a on the third semiconductor region 3 side in the planar direction and the end of the electrode layer 6a on the third semiconductor region 3 side in the planar direction is shorter than the depth D1 of the insulating layer 5 (D4<D1), so that the spread of the electric field lines between the electrode layer 6a and the side surface of the insulating layer 5a on the third semiconductor region 3 side is reduced, and a substantially strong electric field can be exerted on the insulating layer 5a on the third semiconductor region 3 side. This makes it possible to suppress reversion of the third semiconductor region 3 to N type near the boundary between the side surface of the insulating layer 5a on the third semiconductor region 3 side and the P-type third semiconductor region 3.

[0091] Similarly, the distance D5 between the end of the insulating layer 5b on the third semiconductor region 3 side in the planar direction and the end of the electrode layer 6b on the third semiconductor region 3 side in the planar direction is shorter than the depth D1 of the insulating layer 5 (D5<D1), so that a substantially strong electric field can be applied to the insulating layer 5b on the third semiconductor region 3 side. This makes it possible to suppress inversion of the third semiconductor region 3 to N type near the boundary between the side surface of the insulating layer 5b on the third semiconductor region 3 side and the P-type third semiconductor region 3.

[0092] Furthermore, in the pixel circuit 10, by forming the electrode layer 6b over a wide area on the insulating layer 5b so that the width D6 of the electrode layer 6b in the planar direction is equal to or greater than the depth D1 of the insulating layer 5b (D1≦D6), the spread of the electric field lines in the insulating layer 5b is reduced, and a strong electric field can be generated overall within the insulating layer 5b. This makes it possible to more effectively suppress the generation of dark current electrons due to the total dose effect.

[0093] Furthermore, it is preferable to form the third semiconductor region 3 so that the width D7 of the third semiconductor region 3 in the planar direction of the semiconductor substrate 1 is equal to or greater than the depth D1 of the insulating layer 5b (D1≦D7). This reliably prevents, for example, the N-type inversion regions formed on the side surfaces of the insulating layers 5a and 5b adjacent to the third semiconductor region 3 as a guard band in the X-axis direction from approaching each other, which would separate the P well 3a and the P diffusion region 3b, and cause the third semiconductor region 3 to fail to function as a guard band.

[0094] Even when D7<D1, by making D4<D1 and D5<D1, a strong electric field can be generated on the third semiconductor region 3 side of the insulating layers 5a and 5b, thereby making it possible to suppress the formation of an N-type inversion region on the third semiconductor region 3 side of the insulating layers 5a and 5b.

[0095] FIG. 8 is a diagram for explaining the effect of suppressing dark current electrons in the pixel circuit 10 according to the embodiment.

[0096] 8, the horizontal axis represents the cumulative radiation dose (+) and the vertical axis represents the negative voltage Vneg (-) that must be applied to the electrode layer 6 in order to sufficiently suppress dark current electrons. Reference numeral 801 denotes a graph of the experimental results for the pixel circuit 10 according to the embodiment, and reference numeral 802 denotes a graph of the experimental results for the pixel circuit 90 according to the previously discussed example.

[0097] 8 show that the negative voltage required to suppress dark current electrons increases as the cumulative dose of radiation increases. As can be seen from graphs 801 and 802, pixel circuit 10 according to the embodiment can reduce the negative voltage required to suppress dark current electrons compared to pixel circuit 90 according to the previously studied example.

[0098] As described above, the pixel circuit 10 according to the embodiment can improve the radiation resistance of the solid-state imaging device while suppressing the magnitude of the negative voltage required to suppress dark current electrons.

[0099] Next, an example of the configuration of an imaging device including the pixel circuit 10 will be shown.

[0100] Fig. 9A is a diagram showing an example of the configuration of an imaging device including pixel circuit 10 according to an embodiment. Fig. 9B is a diagram showing another example of the configuration of an imaging device including pixel circuit 10 according to an embodiment.

[0101] It is desirable to control the negative voltage (absolute value) required to suppress dark current electrons in the pixel circuit 10 so that it increases in accordance with the cumulative dose of radiation. For example, as shown in FIG. 9A , it is desirable for the imaging device 200 to include a voltage supply circuit 30 in addition to the pixel circuit 10.

[0102] The voltage supply circuit 30 is a circuit that supplies a negative voltage Vneg, which is a voltage lower than the ground potential, to the electrode layers 6 (6a, 6b). The voltage supply circuit 30 is configured to be able to change the magnitude of the voltage supplied to the electrode layers 6. For example, as shown in FIG. 9A , the voltage supply circuit 30 includes a plurality of resistors R connected in series between a power supply line to which a negative voltage Vneg(−) is applied from the outside and the ground potential GND, and a plurality of switches SW1 to SW5 connected between both ends of each resistor R and the electrode layer 6.

[0103] In the voltage supply circuit 30, the magnitude of the negative voltage applied to the electrode layer 6 can be changed by selectively turning on switches SW1 to SW5. Specifically, the voltage supply circuit 30 can switch the voltage applied to the electrode layer 6 between five levels: 0 [V], ¼×Vneg [V], ½×Vneg [V], ¾×Vneg [V], and Vneg [V]. FIG. 9A shows, as an example, a case in which ¼ Vneg [V] is applied to the electrode layer 6 by closing switch SW4. Note that the number of resistors R and the number of switches SW in the voltage supply circuit 30 can be changed depending on the range and magnitude of the negative voltage to be applied to the electrode layer 6. The magnitude of each resistor R can also be changed. For example, it is preferable to switch switches SW1 to SW5 so as to increase the negative voltage by one level when a whiteout (a state in which the image becomes white) is detected in the image captured by the imaging device 200.

[0104] The imaging device 200 equipped with the voltage supply circuit 30 can change the negative voltage according to the accumulated radiation dose, thereby reducing the risk of wiring corrosion caused by applying an excessive negative voltage for a long period of time, thereby improving the reliability of the imaging device 200 and extending the life of the imaging device 200.

[0105] 9B , the imaging device 200A may include a voltage supply circuit 30A having multiple variable resistors RV1 and RV2 connected in series between the power supply line Vneg(−) and the ground potential GND, instead of the above-described voltage supply circuit 30. With the voltage supply circuit 30A, it is possible to change the negative voltage applied to the electrode layer 6 by adjusting the resistance values ​​of the variable resistors RV1 and RV2.

[0106] <<Extending the Embodiments>> The invention made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the spirit of the invention.

[0107] For example, in the above embodiment, as shown in FIG. 2A, an example was given in which the third semiconductor region 3 as a guard band is formed in a form that continuously surrounds at least a portion of the periphery of the photodiode PPD in a planar view. However, if it is difficult to form the third semiconductor region 3 continuously due to constraints on the wiring layout on the semiconductor substrate 1, the third semiconductor region 3 may be formed discontinuously, as shown in FIGS. 10A and 10B.

[0108] FIG. 10A is a plan view showing the layout configuration of a pixel circuit 10A according to another embodiment.

[0109] FIG. 10B is a diagram schematically showing a cross-sectional structure of the pixel circuit 10A shown in FIG. 10A taken along line BB'.

[0110] 10A and 10B , in a pixel circuit 10A of a semiconductor device 100A according to another embodiment, the third semiconductor region 3A may be formed so as to discontinuously surround at least a portion of the periphery of the photodiode PPD in a plan view. That is, the third semiconductor region 3A may be formed as a guard band scattered within a region of the insulating layer 5 that is arranged so as to surround the periphery of the photodiode PPD.

[0111] In this case, in plan view, the length of the third semiconductor region 3A in the extension direction extending along one side of the photodiode PPD is preferably at least half the length of the side of the photodiode PPD. For example, as shown in Fig. 10A , when the length of one side of the photodiode PPD extending in the Y-axis direction on the positive side of the X-axis direction is L1 and the length of the third semiconductor region 3A extending in the Y-axis direction along that side is L2, it is preferable that L2 ≥ L1 / 2.

[0112] In addition, when the length L2 of the third semiconductor region 3A cannot be sufficiently ensured, the multiple third semiconductor regions 3A may be arranged spaced apart from each other along one side of the photodiode PPD in a plan view. For example, Fig. 10A shows a case where two third semiconductor regions 3A_1, 3A_2 are arranged spaced apart from each other along one side of the photodiode PPD extending in the Y-axis direction on the negative side of the X-axis direction.

[0113] Furthermore, when the photodiode PPD has an arc-shaped side in plan view, the third semiconductor region 3A may be formed continuously or discontinuously along the arc-shaped side of the photodiode PPD. Even in this case, the length of the guard band 3A is preferably at least half the length of the arc of the photodiode PPD.

[0114] In the above embodiment, the electrode layer 6b is formed on the insulating layer 5b formed on the outer side of the photodiode PPD, but this is not limiting. For example, if the electrode layer 6a is formed on the insulating layer 5a, the electrode layer 6b does not need to be formed on the insulating layer 5b.

[0115] Furthermore, in the above embodiment, the case where the semiconductor substrate 1 is P-type has been exemplified, but this is not limiting, and the semiconductor substrate 1 may be N-type. In this case, for example, a P-well may be formed by doping a low concentration of P-type impurities into an N-type semiconductor substrate, and the circuit elements that make up the pixel circuit 10 described above may be formed on the P-well.

[0116] 1...semiconductor substrate (first semiconductor region), 2...N well, 3...third semiconductor region (guard band), 3a...P well, 3b...P diffusion region, 4...pinning layer, 5, 5a, 5b...insulating layer (STI), 6, 6a, 6b...electrode layer, 7...contact layer, 8...wiring layer, 9...PMD, 10, 10A...pixel circuit, 30, 30A...voltage supply circuit, 100...semiconductor device, 200, 200A...imaging device, FD...charge storage section, GND...ground potential, Mdrv...amplifying transistor, Mfdr...reset transistor, Msel...selection transistor, Mtg...transfer transistor, N1...node, OUT...output signal line, P...pixel boundary line, PPD...embedded photodiode (photodiode), VDD, VRR...power supply voltage, φFDR...signal, φPDR...signal, φSEL...signal, φTG...signal.

Claims

1. A semiconductor device comprising: a semiconductor substrate; and a pixel circuit formed on the semiconductor substrate, wherein the pixel circuit has: a first semiconductor region of a first conductivity type in the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region; an insulating layer formed around the photodiode in the semiconductor substrate in a planar view seen in a direction perpendicular to the plane of the semiconductor substrate; and an electrode layer formed on the insulating layer, wherein, when D1 is the depth of the insulating layer in the direction perpendicular to the plane of the semiconductor substrate and D2 is the distance between the end of the insulating layer on the photodiode side in the planar direction of the semiconductor substrate and the end of the electrode layer on the photodiode side in the planar direction, D2 satisfies the relationship D2<D1.

2. A semiconductor device according to claim 1, wherein, when the width of said electrode layer in said planar direction is D3, D1≦D3.

3. A semiconductor device according to claim 2, wherein the insulating layer includes a first insulating layer and a second insulating layer formed at a distance from the first insulating layer in the planar direction, and further includes a third semiconductor region of the first conductivity type formed between the first insulating layer and the second insulating layer on the first semiconductor region of the semiconductor substrate, and the electrode layer includes a first electrode layer formed on the first insulating layer and a second electrode layer formed on the second insulating layer.

4. A semiconductor device according to claim 3, wherein the third semiconductor region is formed in a form that continuously surrounds at least a part of the periphery of the photodiode in a plan view.

5. A semiconductor device according to claim 3, wherein the third semiconductor region is formed in a form that discontinuously surrounds at least a part of the periphery of the photodiode in a plan view.

6. A semiconductor device according to claim 5, wherein, in a plan view, the length in the extension direction of the third semiconductor region extending along one side of the photodiode PPD is at least half the length of the side of the photodiode PPD.

7. A semiconductor device according to claim 5, wherein, in plan view, a plurality of said third semiconductor regions are formed spaced apart from one another along one side of said photodiode.

8. A semiconductor device according to claim 3, wherein, when the distance between the end of the first insulating layer on the side of the third semiconductor region in the planar direction and the end of the first electrode layer on the side of the third semiconductor region in the planar direction is D4, D4 < D1.

9. A semiconductor device according to claim 3, wherein, when the distance between the end of the second insulating layer on the side of the third semiconductor region in the planar direction and the end of the second electrode layer on the side of the third semiconductor region in the planar direction is D5, D5 < D1.

10. A semiconductor device according to claim 3, wherein, when the width of said second electrode layer in said planar direction is D6, D1≦D6.

11. An imaging device comprising: a semiconductor device according to any one of claims 1 to 10; and a voltage supply circuit that supplies a voltage lower than ground potential to the electrode layer, wherein the first semiconductor region is connected to the ground potential, and the voltage supply circuit is capable of changing the magnitude of the voltage supplied to the electrode layer.

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