Network interface card

Abstract

A network interface card (1) comprises: an MCU (11) having a processor (111); a serial memory (12); a serial memory controller (113); and a read buffer (114) for storing prefetched data from the serial memory (12). If data of a read address is not in the read buffer (114), the serial memory controller (113) reads the data from the serial memory (12), passes the data to the processor (111), and fills all regions of the read buffer (114) by prefetching data from the serial memory (12). If the data is in the read buffer (114), the serial memory controller (113) reads the data from the read buffer (114), passes the data to the processor (111), and fills the regions of the read buffer (114) in which the data of addresses lower than or equal to the serial memory (12) address corresponding to the data is stored, by prefetching data from the serial memory (12).

Description

Network Interface Card

[0001] The present disclosure relates to network interface cards.

[0002] In manufacturing plants and production lines, multiple control devices are often connected to a communication network, where various industrial communication protocols are used to transmit and receive data between the control devices.

[0003] As shown in Figure 7, many industrial communication protocols define control devices connected to a communication network as being classified into two types according to their roles: one is a main device (primary device) that controls other control devices, and the other is a slave device (secondary device) that is controlled by the primary device.

[0004] Each control device is equipped with a network interface card for communication, and whether the control device will be the primary device or the secondary device is determined depending on the configuration of the network interface card. Hereinafter, the network interface card for the primary device will be referred to as the primary card, and the network interface card for the secondary device will be referred to as the secondary card.

[0005] Conventionally, the following two designs have been used for primary and secondary cards: One, as shown in Figures 8A and 8B, is to share external interfaces such as bus bridges and communication LSIs between the primary and secondary cards, and to individually optimize the hardware around the CPU (Central Processing Unit) for each card (Prior Art 1).

[0006] Specifically, the primary card that controls the entire network including multiple secondary devices requires relatively high processing power and memory resources. Therefore, as shown in Fig. 8A, a high-speed, large-capacity memory is connected to the CPU via a parallel bus, and the primary communication protocol stack and primary data are stored in this memory.

[0007] On the other hand, the secondary card requires limited processing power and memory resources. Therefore, as shown in Figure 8B, it is equipped with a one-chip microcomputer, and the secondary communication protocol stack and secondary data are stored in the built-in memory incorporated in the one-chip microcomputer. In general, the capacity of the primary communication protocol stack and primary data is larger than the capacity of the secondary communication protocol stack and secondary data.

[0008] The other is to use common hardware for the primary and secondary cards (Prior Art 2). Specifically, the hardware for both the primary and secondary cards is configured as shown in Figure 8A. The communication protocol stack and data stored in memory are swapped depending on whether it is for the primary card or the secondary card.

[0009] However, while the circuit scale of the secondary card in the above-mentioned prior art 1 is small and can be manufactured inexpensively, the hardware configurations of the primary card and the secondary card are significantly different, which requires the development, manufacturing, and maintenance man-hours of two cards' worth of hardware.

[0010] On the other hand, in the above-mentioned prior art 2, the development man-hours, manufacturing man-hours, and maintenance man-hours required for the hardware are the same as for one card, but the hardware of the primary card is reused for the secondary card, which means that the circuit scale of the secondary card is larger than that of the secondary card in prior art 1, making the secondary card more expensive.

[0011] Instead of using the primary card's hardware for the secondary card as in Prior Art 2, it is also possible to use the secondary card's hardware for the primary card. However, in this case, the built-in memory alone would not provide the memory resources necessary to function as the primary card. Therefore, in addition to the built-in memory, it is necessary to connect a serial memory via the serial port of the one-chip microcomputer to ensure the memory resources necessary for the primary card.

[0012] However, to access the serial memory, the CPU of the one-chip microcomputer must access the serial port register to control commands, which places a heavy load on the CPU. Also, single reads from serial memory are generally relatively slow, making it difficult to meet the performance requirements for a primary card.

[0013] One aspect of the present disclosure is a network interface card comprising: a microcontroller unit having a processor, an internal memory, and a serial communication interface; a serial memory connected via the serial communication interface; a serial memory controller controlling communication between the serial memory and the processor; and a read buffer connected to the serial memory controller and storing consecutive data pre-fetched from the serial memory, wherein the serial memory controller, in response to a read command to the serial memory from the processor, searches for whether data at an address specified in the read command is present in the read buffer; if the data at the address specified in the read command is not present in the read buffer, reads the data from the serial memory and passes it to the processor, and fills the entire area of ​​the read buffer with data following the specified address by pre-fetching data from the serial memory; and if the data at the address specified in the read command is present in the read buffer, reads the data from the read buffer and passes it to the processor, and fills the area of ​​the read buffer where data at addresses below the serial memory address corresponding to the data is stored by pre-fetching data from the serial memory following the data already pre-fetched and stored in the read buffer.

[0014] 1 is a block diagram showing a schematic configuration of a network interface card (primary card) according to an embodiment of the present disclosure. FIG. 2 is a diagram showing an example of a bus space of a CPU provided in the network interface card of FIG. 1. FIG. 3 is a diagram illustrating an example of reading data from a serial memory in the network interface card of FIG. 1. FIG. 4 is a diagram illustrating another example of reading data from a serial memory in the network interface card of FIG. 1. FIG. 5 is a block diagram showing an example of a schematic configuration of a network interface card (secondary card) according to an embodiment of the present disclosure. FIG. 6 is a block diagram showing another example of a schematic configuration of a network interface card (secondary card) according to an embodiment of the present disclosure. FIG. 7 is a block diagram showing another example of a schematic configuration of a network interface card (secondary card) according to an embodiment of the present disclosure. FIG. 8 is a diagram showing a plurality of control devices connected to a communication network. FIG. 9 is a block diagram showing a schematic configuration of a network interface card (primary card) according to the prior art. FIG. 10 is a block diagram showing a schematic configuration of a network interface card (secondary card) according to the prior art.

[0015] A network interface card according to an embodiment of the present disclosure will be described below with reference to the drawings. The primary card 1 shown in Fig. 1 includes an MCU (microcontroller unit) 11, a serial memory 12 connected to the MCU 11, a bus bridge 13 connected to the MCU 11 via a bus 15, and a communication LSI (large-scale integrated circuit) 14.

[0016] The MCU 11 includes a CPU (processor) 111, an internal memory 112, a serial memory controller 113, a read buffer 114, and a serial port (serial communication interface) 115. The internal memory 112, the serial memory controller 113, and the serial port 115 are each connected to the CPU 111 via an internal bus (not shown) of the MCU 11.

[0017] The internal memory 112 stores a primary communication protocol stack and part of primary data, that is, a primary communication protocol stack #1 and primary data #1.

[0018] The serial memory controller 113 is serially connected to the serial memory 12 via a serial port 115, and is configured to manage data transfer and control between the CPU 111 and the serial memory 12. The serial memory controller 113 is also connected to a read buffer 114. The read buffer 114 is preferably configured as a ring buffer.

[0019] The serial memory 12 may be, for example, a serial flash memory. The serial memory 12 stores the primary communication protocol stack and primary data that do not fit into the built-in memory 112, i.e., primary communication protocol stack #2 and primary data #2.

[0020] Preferably, serial memory 12 stores programs and data used by programs that are accessed less frequently than programs and data used by programs stored in built-in memory 112. By arranging programs and data that are accessed more frequently in built-in memory 112, which has a faster access speed than serial memory 12, it is possible to improve the weighted average access speed to serial memory 12 and built-in memory 112. This makes it possible to optimize the performance of primary card 1 as a whole.

[0021] Preferably, programs and data used by the programs that can be read from consecutive addresses are allocated in the serial memory 12. By arranging them in this manner, as will be described later, consecutive writing to the read buffer 114 by burst read and consecutive reading from the read buffer 114 by the CPU can be performed. Therefore, the programs and data in the serial memory 12 can be read at high speed.

[0022] Here, the program is software that uses the primary communication protocol stack to realize network communication processes such as data transmission and reception. The data used by the program also includes network configuration data.

[0023] The bus bridge 13 is configured to be connectable to the internal bus of the control device in which the primary card 1 is provided via an interface such as PCI (Peripheral Component Interconnect) or PCI Express.

[0024] The communication LSI 14 is a large scale integrated circuit (LSI) configured to realize communication-related functions such as sending and receiving data to and from a network interface card provided in another control device connected via a communication network.

[0025] The following describes in detail the process in which the serial memory controller 113 reads data from the serial memory 12. The MCU 11 according to this embodiment is designed so that the address range of the serial memory 12 is mapped onto the bus space of the CPU 111, as shown in FIG.

[0026] In this way, the CPU 111 can access the serial memory 12 in the same way as it accesses a dynamic random access memory (DRAM) or a static random access memory (SRAM), thereby reducing the load on the CPU 111 and enabling high-speed access to the serial memory 12.

[0027] As an example, FIG. 2 shows that in addition to a 2 MB internal memory, a 16 MB serial memory is placed in the CPU bus space, and address m of the CPU bus space corresponds to address n of the serial memory space.

[0028] FIG. 3 shows the processing procedure when CPU 111 issues a data read command for logical address m when no data is stored in read buffer 114 or when no data is stored at the target address to be read.

[0029] First, the serial memory controller 113 receives a "read address m" command from the CPU 111, which is a read command for the serial memory 12. In response to this command, the serial memory controller 113 converts the logical address m into the physical address n of the serial memory 12.

[0030] Next, the serial memory controller 113 accesses the read buffer 114 and searches whether or not the data at the specified address n exists in the read buffer 114 .

[0031] When the serial memory controller 113 confirms that the data at the specified address n is not present in the read buffer 114, it accesses the serial memory 12. Specifically, the serial memory controller 113 performs a single read of the address n from the serial memory 12 and passes the read data at the address n to the CPU 111.

[0032] Furthermore, the serial memory controller 113 burst-reads 32B of data from the serial memory 12 starting from address n so as to fill the entire area of ​​the read buffer 114. As a result, data D at consecutive addresses from address n+1 to address n+32 is read. ｎ＋１ ~D ｎ＋３２ is stored in the read buffer.

[0033] In single read, a command and read address are sent for each access, followed by the transfer of one data word, whereas burst read does not require the sending of a command or address if it is transferring data from consecutive addresses after the final read address, resulting in a faster data transfer rate than single read.

[0034] Next, a processing procedure when a data read command for logical address m+1 is issued from the CPU 111 will be described with reference to Fig. 4. The read buffer 114 stores data D at consecutive addresses from n+1 to n+32 by the processing shown in Fig. 3. ｎ＋１ ~D ｎ＋３２ is already stored.

[0035] First, the serial memory controller 113 receives a "read address m+1" command from the CPU 111, which is a read command for the serial memory 12. In response to this command, the serial memory controller 113 converts the specified logical address, address m+1, into the physical address of the serial memory 12, address n+1.

[0036] Next, the serial memory controller 113 accesses the read buffer 114 and searches whether or not the data at address n+1 exists in the read buffer 114 .

[0037] The serial memory controller 113 reads the data D at the address n+1 specified on the read buffer 114. ｎ＋１ When it is confirmed that the data D exists, the data D is read from the read buffer 114. ｎ＋１ and passes it to the CPU 111. Furthermore, the serial memory controller 113 accesses the serial memory 12 to perform a burst read. As a result, the data following the data that has already been pre-read and stored in the read buffer 114, i.e., the data from physical address n+33 onwards, is read from the serial memory 12 and written to the read buffer 114.

[0038] Specifically, the already extracted data D ｎ＋１ The data D at physical address n+33 is stored in the area of ​​the read buffer 114. ｎ＋３３ As a result, data D at consecutive addresses from address n+2 to address n+33 is written. ｎ＋２ ~D ｎ＋３３ is stored in the read buffer.

[0039] The address location of the serial memory 12 at which data is stored in the read buffer can be determined, for example, by allocating an address pointer to the read location of the serial memory 12. Specifically, when the processing in Figure 3 described above is completed, the address pointer points to address n+32. Therefore, when the processing in Figure 4 is completed, the address pointer is incremented by one to address n+33.

[0040] Next, a processing procedure when a data read command for logical address m+4 is issued from the CPU 111 will be described with reference to Fig. 5. The read buffer 114 stores data D at consecutive addresses from n+2 to n+33 by the processing shown in Fig. 4. ｎ＋２ ~D ｎ＋３３ is stored.

[0041] First, the serial memory controller 113 receives a "read address m+4" command from the CPU 111, which is a read command for the serial memory 12. In response to this command, the serial memory controller 113 converts the specified logical address, address m+4, into the physical address of the serial memory 12, address n+4.

[0042] Next, the serial memory controller 113 accesses the read buffer 114 and searches whether or not the data at address n+4 exists in the read buffer 114 .

[0043] The serial memory controller 113 reads the data D at the address n+4 specified on the read buffer 114. ｎ＋４ When it is confirmed that the data D exists, the data D is read from the read buffer 114. ｎ＋４ and passes it to the CPU 111. Furthermore, the serial memory controller 113 accesses the serial memory 12 to perform a burst read. As a result, the data following the data that has already been pre-read and stored in the read buffer 114, i.e., the data from physical address n+34 onwards, is read from the serial memory 12 and written to the read buffer 114.

[0044] Specifically, the already extracted data D ｎ＋４Data D at addresses below address n+4 of the serial memory 12 corresponding to ｎ＋２ ~D ｎ＋４ The data D from the physical address n+34 onwards of the serial memory 12 is stored in the area of ​​the read buffer 114 where the data D ｎ＋３４ ~D ｎ＋３６ As a result, data D at consecutive addresses from address n+5 to address n+36 is written. ｎ＋５ ~D ｎ＋３６ is stored in the read buffer.

[0045] At the end of the processing in FIG. 4, the address pointer points to address n+33, and at the end of the processing in FIG. 5, the address pointer is incremented by three to address n+36.

[0046] As described above, the MCU 11 of this embodiment includes the serial memory controller 113, which controls and manages data transfer between the CPU 111 and the serial memory 12. This reduces the load on the CPU 111 and enables high-speed access to the serial memory 12.

[0047] Furthermore, the MCU 11 of this embodiment is designed so that the address range of the serial memory 12 is mapped to the bus space of the CPU 111. This allows the CPU 111 to access the serial memory 12 in the same way as it accesses DRAM or SRAM. This reduces the load on the CPU 111, and ultimately enables high-speed access to the serial memory 12.

[0048] Furthermore, in this embodiment, the serial memory controller 113 uses burst read to pre-read consecutive data in the serial memory 12 and stores the data in the read buffer 114. Therefore, high-speed access to data in the serial memory 12 can be achieved.

[0049] The read buffer 114 stores consecutive data following the address specified in a read command from the CPU 111 up to the capacity of the read buffer 114. This is particularly advantageous for programs and data that are read from consecutive addresses, as the data stored in the read buffer 114 continues to be hit. For example, network configuration data is often read from consecutive addresses, so by arranging it in the serial memory 12, it can be read at high speed.

[0050] By configuring the primary card 1 as described above, it is possible to increase the speed at which data is read from the serial memory 12, and it is possible to achieve the performance required for the functions of the primary card 1.

[0051] Next, the configuration of the secondary card 2 will be described with reference to Figures 6A to 6C. As shown in Figure 6A, the secondary card 2 can use the hardware of the primary card 1 as is. However, the built-in memory 112 must store a secondary communication protocol stack and secondary data instead of the primary communication protocol stack and primary data.

[0052] Alternatively, since the secondary card 2 does not require an additional memory such as the serial memory 12, the serial memory 12 may be removed as shown in Fig. 6B. If open terminal processing is required, pull-up or pull-down resistors for open terminal processing may be implemented according to footprints previously arranged on the printed circuit board of the secondary card 2 as shown in Fig. 6C.

[0053] In this way, the secondary card 2 in this embodiment can be used without making any major changes to the hardware of the primary card 1. In other words, the primary card 1 in this embodiment can increase memory resources by the capacity of the serial memory 12 with a circuit scale similar to that of the secondary card 2 while still maintaining the performance required of the primary card 1.

[0054] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the individual embodiments described above. Various additions, substitutions, modifications, partial deletions, etc. are possible to these embodiments without departing from the gist of the invention or the idea and intent of the present invention derived from the content described in the claims and their equivalents. For example, in the above embodiments, the order of each operation and the order of each process are shown as examples and are not limited to these.

[0055] In the above embodiment, the serial memory controller 113 and the read buffer 114 are incorporated into the MCU 11 , but they do not have to be incorporated into the MCU 11 .

[0056] The read buffer 114 may also be provided in the serial memory controller 113. A part of the built-in memory 112 may be used as the read buffer 114.

[0057] In the above embodiment, the capacity of the read buffer 114 is 32 B, but this is not limiting and the capacity may be larger or smaller than this.

[0058] In the above description, the physical address of the serial memory 12 is used as the address when referencing the read buffer 114, but this is not limiting. Data in the read buffer 114 may be referenced using a logical address in the CPU bus space.

[0059] The following additional notes are provided regarding the above-described embodiment and modifications. (Supplementary Note 1) A network interface card comprising: a microcontroller unit having a processor, an internal memory, and a serial communication interface; a serial memory connected via the serial communication interface; a serial memory controller controlling communication between the serial memory and the processor; and a read buffer connected to the serial memory controller and storing consecutive data pre-fetched from the serial memory, wherein the serial memory controller, in response to a read command from the processor to the serial memory, searches for whether or not data at an address specified in the read command is present in the read buffer; if the data at the address specified in the read command is not present in the read buffer, reads the data from the serial memory and passes it to the processor, and fills all areas of the read buffer with data following the specified address by pre-fetching data from the serial memory; and if the data at the address specified in the read command is present in the read buffer, reads the data from the read buffer and passes it to the processor, and fills the area of ​​the read buffer where data at addresses below the serial memory address corresponding to the data is stored, by pre-fetching data from the serial memory following the data already pre-fetched and stored in the read buffer. (Supplementary Note 2) The network interface card according to Supplementary Note 1, wherein the serial memory controller and the read buffer are incorporated into the microcontroller unit. (Supplementary Note 3) The network interface card according to Supplementary Note 1, wherein a program and / or data used by the program is stored separately in the built-in memory and the serial memory. (Supplementary Note 4) The network interface card according to Supplementary Note 3, wherein the program and the data stored in the serial memory are accessed less frequently by the processor than the program and the data stored in the built-in memory.(Supplementary Note 5) The network interface card according to Supplementary Note 3, wherein the serial memory stores the program and / or the data that can be read from consecutive addresses.

[0060] 1 Network Interface Card 11 MCU (Microcontroller Unit) 12 Serial Memory 111 CPU (Processor) 112 Built-in Memory 113 Serial Memory Controller 114 Read Buffer 115 Serial Port (Serial Communication Interface)

Claims

1. A network interface card comprising: a microcontroller unit having a processor, built-in memory, and a serial communications interface; a serial memory connected via the serial communications interface; a serial memory controller that controls communications between the serial memory and the processor; and a read buffer connected to the serial memory controller and storing consecutive data pre-fetched from the serial memory, wherein the serial memory controller, in response to a read command from the processor to the serial memory, searches for whether or not data at the address specified in the read command is present in the read buffer; if the data at the address specified in the read command is not present in the read buffer, reads the data from the serial memory and passes it to the processor, and fills the entire area of ​​the read buffer with data following the specified address by pre-fetching data from the serial memory; and if the data at the address specified in the read command is present in the read buffer, reads the data from the read buffer and passes it to the processor, and fills the area of ​​the read buffer where data at addresses below the serial memory address corresponding to the data is stored, by pre-fetching data from the serial memory following the data that has already been pre-fetched and stored in the read buffer.

2. The network interface card of claim 1, wherein said serial memory controller and said read buffer are incorporated into said microcontroller unit.

3. The network interface card according to claim 1, wherein the program and / or data used by the program are stored separately in the built-in memory and the serial memory.

4. A network interface card according to claim 3, wherein the frequency of access to the programs and data stored in the serial memory is lower than the frequency of access by the processor to the programs and data stored in the internal memory.

5. The network interface card according to claim 3, wherein the serial memory stores the program and / or the data that can be read from consecutive addresses.

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