Multilayer ceramic capacitor

Abstract

According to the present invention, each of a plurality of internal electrode layers (120, 130) is provided with a plurality of hole parts (120H, 130H) and a plurality of incision parts (120N, 130N) for insertion of a via conductor that is not electrically connected among a plurality of via conductors (140, 150). The plurality of hole parts (120H, 130H) each have a generally circular shape. The plurality of incision parts (120N, 130N) are each cut in an arc shape along virtual circles (VC) which are respectively continuous with generally rectangular edges (121, 131) of the plurality of internal electrode layers (120, 130), and which each have a center (C) positioned inside the edges (121, 131). The ratio of the radius of the generally circular shape of the hole parts (120H, 130H) to the radius of the virtual circles (VC) is 0.95 to 1.05 inclusive. The dimensions of the respective radii of the generally circular shape of the hole parts (120H, 130H) and the virtual circles (VC) are 25 μm to 50 μm inclusive. When a is the shortest distance between the edges (121, 131) and the center (C) of the virtual circles (VC), r is the radius of the virtual circles (VC), and d is the diameter of each of the plurality of via conductors (140, 150), the relational expression (r - d) < a < r is satisfied.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Japanese Patent Laid-Open Publication No. 2021-48261 (Patent Document 1) is a prior art document disclosing a multilayer capacitor. The multilayer capacitor described in Patent Document 1 includes a laminate, a plurality of first external electrodes, a plurality of second external electrodes, a plurality of first via conductors, and a plurality of second via conductors. In the laminate, a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked. The plurality of first external electrodes and the plurality of second external electrodes are formed on the outer surface of the laminate. The plurality of first via conductors electrically connect the first external electrode and the plurality of first internal electrodes. The plurality of second via conductors electrically connect the second external electrode and the plurality of second internal electrodes. A through hole is formed in the second internal electrode, and the first via conductor passes through the through hole while being insulated from the second internal electrode. A through hole is formed in the first internal electrode, and the second via conductor passes through the through hole while being insulated from the first internal electrode.

[0003] Japanese Patent Application Laid-Open No. 2021-48261

[0004] As multilayer ceramic capacitors become smaller, if only through holes are formed in the internal electrode layers to insert the via conductors, it may not be possible to ensure the required number of via conductors.

[0005] The present invention has been made in view of the above problems, and has an object to provide a multilayer ceramic capacitor that is miniaturized while ensuring the necessary number of via conductors.

[0006] A multilayer ceramic capacitor according to the present invention includes a laminate and a plurality of via conductors. The laminate includes a plurality of internal electrode layers alternately stacked in a stacking direction with dielectric layers sandwiched therebetween. The plurality of via conductors are provided inside the laminate and electrically connected to corresponding ones of the plurality of internal electrode layers. Each of the plurality of internal electrode layers has a plurality of holes and a plurality of cutouts for inserting via conductors that are not electrically connected among the plurality of via conductors. Each of the plurality of holes is approximately circular. Each of the plurality of cutouts is cut out in an arc shape along an imaginary circle that is continuous with the approximately rectangular edge of each of the plurality of internal electrode layers and has a center located inside the edge. The ratio of the radius of the approximately circular shape to the radius of the imaginary circle is 0.95 to 1.05. The radius of each of the approximately circular shape and the imaginary circle is 25 μm to 50 μm. If the shortest distance between the edge and the center of the imaginary circle is a, the radius of the imaginary circle is r, and the diameter of each of the plurality of via conductors is d, then the relationship (r−d)<a<r is satisfied.

[0007] According to the present invention, it is possible to reduce the size of a multilayer ceramic capacitor while ensuring the required number of via conductors.

[0008] 1 is a plan view of a multilayer ceramic capacitor according to a first embodiment of the present invention, as viewed from the first main surface side. It is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, as viewed from the direction of the arrows along line II-II. It is a cross-sectional view of the multilayer ceramic capacitor of FIG. 2, as viewed from the direction of the arrows along line III-III. It is a cross-sectional view of the multilayer ceramic capacitor of FIG. 2, as viewed from the direction of the arrows along line IV-IV. It is a diagram for explaining the dimensional relationship between a first hole, a second hole, a first cutout, and a second cutout in a first internal electrode layer and a second internal electrode layer in a laminate. It is a diagram for explaining the dimensional relationship between an imaginary circle along which cutouts located on each side of the edge of an internal electrode layer are aligned, and a via conductor. It is a diagram for explaining the dimensional relationship between an imaginary circle along which cutouts located at the four corners of the edge of an internal electrode layer are aligned, and a via conductor. It is a plan view of a multilayer ceramic capacitor according to a second embodiment of the present invention, as viewed from the first main surface side. It is a cross-sectional view of the multilayer ceramic capacitor of FIG. 8, as viewed from the direction of the arrows along line IX-IX. It is a cross-sectional view of the multilayer ceramic capacitor of FIG. 9, as viewed from the direction of the arrows along line X-X. 10 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 9 as viewed from the direction of the arrows along line XI-XI.

[0009] Hereinafter, multilayer ceramic capacitors according to embodiments of the present invention will be described with reference to the drawings. In the following description of the embodiments, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and description thereof will not be repeated.

[0010] (Embodiment 1) Fig. 1 is a plan view of a multilayer ceramic capacitor according to embodiment 1 of the present invention, viewed from the first main surface side. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, viewed from the direction of the arrows along line II-II. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 2, viewed from the direction of the arrows along line III-III. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 2, viewed from the direction of the arrows along line IV-IV.

[0011] As shown in FIGS. 1 to 4, the multilayer ceramic capacitor 1 according to the first embodiment of the present invention includes a laminate 100, a plurality of first via conductors 140, and a plurality of second via conductors 150.

[0012] As shown in Figure 2, the laminate 100 includes a plurality of first internal electrode layers 120 and a plurality of second internal electrode layers 130 stacked alternately in the stacking direction with dielectric layers 110 sandwiched between them, and has a first main surface 101 and a second main surface 102 located on the opposite side of the first main surface 101 in the stacking direction.

[0013] The dielectric layer 110 may be made of any material, such as a ceramic material containing BaTiO, CaTiO, SrTiO, SrZrO, or CaZrO as a main component. A minor component selected from the group consisting of a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to the main component in a smaller amount than the main component.

[0014] The laminate 100 may have any shape. In this embodiment, the laminate 100 has a rectangular parallelepiped shape as a whole. A rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of a rectangular parallelepiped are rounded, but has six surfaces and can be perceived as a rectangular parallelepiped as a whole. Therefore, the laminate 100 has a first main surface 101, a second main surface 102, a first side surface 103, a second side surface 104, a third side surface 105, and a fourth side surface 106.

[0015] The first side surface 103 to the fourth side surface 106 of the laminate 100 constitute four side surfaces of the surface of the laminate 100 other than the first main surface 101 and the second main surface 102. That is, the laminate 100 further has the first side surface 103 to the fourth side surface 106, which are four side surfaces connecting the first main surface 101 and the second main surface 102. The first side surface 103 faces the second side surface 104, and the third side surface 105 faces the fourth side surface 106. In this embodiment, the first side surface 103 to the fourth side surface 106 of the laminate 100 are orthogonal to the first main surface 101 and the second main surface 102, respectively, but they do not have to be orthogonal.

[0016] The dimensions of the laminate 100 are arbitrary, but for example, when viewed from the first main surface 101 side, the vertical dimension of the rectangle can be 300 μm to 1000 μm, the horizontal dimension can be 300 μm to 1000 μm, and the dimensions in the stacking direction of the dielectric layers 110, the first internal electrode layers 120 and the second internal electrode layers 130 can be 50 μm to 200 μm. The dimension of the laminate 100 in the stacking direction refers to the thickness of the laminate 100.

[0017] As shown in Fig. 3, each of the plurality of first internal electrode layers 120 has a substantially rectangular outer shape. As shown in Fig. 4, the second internal electrode layer 130 has a substantially rectangular outer shape that is substantially the same as the first internal electrode layer 120.

[0018] Each of the plurality of internal electrode layers has a plurality of holes and a plurality of cutouts for inserting via conductors that are not electrically connected among the plurality of via conductors. Specifically, as shown in Figures 2 and 3, each of the plurality of first internal electrode layers 120 has a plurality of first holes 120H and a plurality of first cutouts 120N for inserting a plurality of second via conductors 150. As shown in Figures 2 and 4, each of the plurality of second internal electrode layers 130 has a plurality of second holes 130H and a plurality of second cutouts 130N for inserting a plurality of first via conductors 140.

[0019] The material of the first internal electrode layer 120 and the second internal electrode layer 130 is arbitrary, and for example, contains a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals, as a main component. The first internal electrode layer 120 and the second internal electrode layer 130 may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 110. In that case, the ratio of the common material contained in the first internal electrode layer 120 and the second internal electrode layer 130 is, for example, 20 vol % or less.

[0020] The thickness of each of the first internal electrode layers 120 and the second internal electrode layers 130 is arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode layers 120 and the second internal electrode layers 130 is arbitrary, but can be, for example, about 10 layers or more and 70 layers or less in total.

[0021] In the multilayer ceramic capacitor 1, the first internal electrode layer 120 and the second internal electrode layer 130 face each other with the dielectric layer 110 interposed therebetween, thereby forming a capacitance.

[0022] 2 to 4, the plurality of first via conductors 140 are provided inside the laminate 100 and are electrically connected to the plurality of first internal electrode layers 120. The plurality of first via conductors 140 are inserted through second hole portions 130H formed in each of the plurality of second internal electrode layers 130, and are insulated from the plurality of second internal electrode layers 130. In this embodiment, the plurality of first via conductors 140 are arranged in a zigzag pattern along the sides of the first main surface 101 when viewed from the stacking direction.

[0023] The plurality of second via conductors 150 are provided inside the laminate 100 and are electrically connected to the plurality of second internal electrode layers 130. The plurality of second via conductors 150 are inserted through first holes 120H formed in each of the plurality of first internal electrode layers 120, and are insulated from the plurality of first internal electrode layers 120. In this embodiment, the plurality of second via conductors 150 are arranged in a zigzag pattern along the sides of the first main surface 101 when viewed from the stacking direction. The first via conductors 140 and the second via conductors 150 are arranged side by side in a matrix.

[0024] Each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is provided inside the laminate 100 in a manner extending in the stacking direction from the first main surface 101 to the second main surface 102 of the laminate 100. That is, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed on the first main surface 101 of the laminate 100, but is not exposed on the second main surface 102. However, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 may be exposed on the second main surface 102.

[0025] By arranging the plurality of first via conductors 140 and the plurality of second via conductors 150 alternately in a zigzag pattern as described above, magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1. Note that the arrangement of the first via conductors 140 and the second via conductors 150 is not limited to the arrangement described above.

[0026] The first via conductor 140 and the second via conductor 150 are substantially cylindrical in shape. The diameter of the first via conductor 140 and the second via conductor 150 is d, and the dimension of the diameter d is, for example, 15 μm or more and 40 μm or less. The dimension of the diameter d is the maximum diameter of the first via conductor 140 and the second via conductor 150. Furthermore, the pitch between adjacent first via conductors 140 and second via conductors 150, more specifically, the distance between the center of the first via conductor 140 and the center of the second via conductor 150, is, for example, 50 μm or more and 200 μm or less.

[0027] The material of the first via conductor 140 and the second via conductor 150 is arbitrary, and for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals, can be used.

[0028] A plurality of external electrodes connected to the first via conductors 140 and the second via conductors 150 may be formed on the first main surface 101. The material of the external electrodes is arbitrary. For example, the external electrodes are plated electrodes formed by a plating process using a rotary plating method. Examples of materials that constitute the plated electrodes include Cu, Ni, and Sn. The plated electrodes may be composed of a single layer or multiple layers. The external electrodes may be formed by firing a metal paste applied to the first main surface 101. The metal paste may contain a glassy inorganic material as a co-material.

[0029] Here, the first hole portion 120H, the second hole portion 130H, the first cutout portion 120N, and the second cutout portion 130N will be described in detail.

[0030] 5 is a diagram for explaining the dimensional relationship between the first hole, the second hole, the first cutout, and the second cutout in the first internal electrode layer and the second internal electrode layer in the laminate. As shown in FIG. 5, the length L1 of the laminate 100 is, for example, 300 μm or more and 1000 μm or less, and the width W1 is, for example, 300 μm or more and 1000 μm or less. In this embodiment, the edge of the laminate 100 is approximately square when viewed from the stacking direction.

[0031] When viewed from the stacking direction, the edges 121, 131 of each of the first internal electrode layers 120 and the second internal electrode layers 130 are substantially rectangular. A substantially rectangular shape is not limited to a perfect rectangle, but also includes a rectangle with cutouts formed on the sides and at the four corners, as described below. In this embodiment, when viewed from the stacking direction, the edges 121, 131 of each of the first internal electrode layers 120 and the second internal electrode layers 130 are substantially square. The length L2 of each of the first internal electrode layers 120 and the second internal electrode layers 130 is, for example, 280 μm or more and 980 μm or less, and the width W2 is, for example, 280 μm or more and 980 μm or less.

[0032] Each of the plurality of first hole portions 120H and the plurality of second hole portions 130H is substantially circular. The term "substantially circular" does not necessarily mean a perfect circle, but also includes an ellipse with a major axis / minor axis ratio of 1.2 or less. If the pitch interval between the first hole portions 120H and the second hole portions 130H is p, the dimension of the pitch interval p is, for example, 50 μm or more and 200 μm or less.

[0033] Each of the plurality of first cutout portions 120N and the plurality of second cutout portions 130N is cut out in an arc shape along an imaginary circle VC that is continuous with the substantially rectangular edges 121, 131 of the first internal electrode layer 120 and the second internal electrode layer 130, respectively, and whose center is located inside the edges 121, 131. The imaginary circle VC is not limited to a perfect circle, and may be an ellipse with a major axis / minor axis ratio of 1.2 or less. In this embodiment, each of the plurality of first cutout portions 120N and the plurality of second cutout portions 130N is formed on each side and at each corner of the substantially rectangular edges 121, 131.

[0034] The ratio of the radius of the approximately circular shape of the first hole portion 120H and the second hole portion 130H to the imaginary circle VC of the first cutout portion 120N and the second cutout portion 130N is 0.95 or more and 1.05 or less. In this embodiment, the ratio of the radius of the approximately circular shape of the first hole portion 120H and the second hole portion 130H to the imaginary circle VC of the first cutout portion 120N and the second cutout portion 130N is 1. When the first hole portion 120H and the second hole portion 130H are elliptical, the radius of the approximately circular shape is the minor axis of the ellipse. When the imaginary circle VC is elliptical, the radius of the imaginary circle VC is the minor axis of the ellipse.

[0035] The radius of the substantially circular shapes of the first hole portion 120H and the second hole portion 130H and the imaginary circle VC of the first cutout portion 120N and the second cutout portion 130N is not less than 25 μm and not more than 50 μm.

[0036] The first via conductor 140 only needs to be in contact with the first internal electrode layer 120, and may partially protrude outside the approximately rectangular edge 121 of the first internal electrode layer 120. The second via conductor 150 only needs to be in contact with the second internal electrode layer 130, and may partially protrude outside the approximately rectangular edge 131 of the second internal electrode layer 130.

[0037] Fig. 6 is a diagram for explaining the dimensional relationship between the via conductor and an imaginary circle along which the cutouts located on each side of the edge of the internal electrode layer are aligned. Fig. 7 is a diagram for explaining the dimensional relationship between the via conductor and an imaginary circle along which the cutouts located at the four corners of the edge of the internal electrode layer are aligned.

[0038] As shown in Figures 6 and 7, the shortest distance between the edges 121, 131 of the first internal electrode layer 120 and the second internal electrode layer 130 and the center C of the virtual circle VC of the first cutout portion 120N and the second cutout portion 130N is a, the radius of the virtual circle VC is r, and the diameter of the first via conductor 140 and the second via conductor 150 is d.

[0039] The relationship a<r is satisfied because the first notch portion 120N and the second notch portion 130N are continuous with the edges 121 and 131, respectively. The dimension (r−a) is, for example, 12 μm or more and 30 μm or less.

[0040] If the first via conductor 140 or the second via conductor 150 is shifted inward of the edges 121, 131 by (r-d / 2), the first via conductor 140 and the second internal electrode layer 130, or the second via conductor 150 and the first internal electrode layer 120, will be electrically connected, causing a short circuit defect.

[0041] If the first via conductor 140 or the second via conductor 150 is shifted outside the edges 121, 131 by (a + d / 2), the first via conductor 140 and the first internal electrode layer 120, or the second via conductor 150 and the second internal electrode layer 130, will not be electrically connected, resulting in an open defect.

[0042] Since a short circuit does not occur even when the first via conductor 140 or the second via conductor 150 is shifted by (a+d / 2) to the outside of the edges 121 and 131, it is preferable that (a+d / 2)>(r-d / 2). In other words, it is preferable that the relationship (r-d)<a is satisfied.

[0043] Therefore, in this embodiment, the first internal electrode layer 120, the second internal electrode layer 130, the first via conductor 140 and the second via conductor 150 are formed so as to satisfy the relationship (rd)<a<r.

[0044] Here, a method for manufacturing the multilayer ceramic capacitor 1 according to the first embodiment of the present invention will be described.

[0045] First, a ceramic green sheet and a conductive paste for the internal electrode layers are prepared. Known ceramic green sheets can be used, and for example, they can be produced by applying a ceramic slurry containing ceramic powder, a resin component, and a solvent onto a substrate and drying it.

[0046] The conductive paste for the internal electrode layers is a conductive paste for forming the first internal electrode layer 120 and the second internal electrode layer 130, and a known conductive paste can be used. The conductive paste for the internal electrode layers contains particles made of a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or a precursor thereof, and a solvent. The conductive paste for the internal electrode layers may further contain a resin component that serves as a dispersant and a binder.

[0047] Next, the internal electrode pattern is formed by applying the conductive paste for the internal electrode layers to the ceramic green sheets by a method such as screen printing. The internal electrode pattern that becomes the first internal electrode layer 120 has first holes 120H and first cutouts 120N. The internal electrode pattern that becomes the second internal electrode layer 130 has second holes 130H and second cutouts 130N.

[0048] Next, a mother laminate is produced by stacking a plurality of ceramic green sheets on which the internal electrode patterns have been formed. When producing the mother laminate, ceramic green sheets on which no internal electrode patterns have been formed may be arranged on the outer sides in the stacking direction. The produced mother laminate is preferably pressed by a method such as a rigid press or a hydrostatic press.

[0049] Next, through holes for forming first via conductors 140 and through holes for forming second via conductors 150 are formed in the mother laminate. The through holes are formed, for example, by irradiating with laser light.

[0050] Next, the formed through holes are filled with a conductive paste for forming first via conductors 140 and second via conductors 150. The conductive paste for via conductors contains particles made of a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or a precursor thereof, and a solvent. The conductive paste for via conductors may further contain a resin component that serves as a dispersant and a binder.

[0051] A ceramic green sheet without an internal electrode pattern may be laminated on one end face in the lamination direction of the mother laminate filled with the conductive paste for via conductors. In this case, it is preferable to press the mother laminate after lamination using a method such as a rigid press or a hydrostatic press.

[0052] Next, the mother laminate is cut by a cutting method such as press cutting, dicing, or laser cutting to produce laminated chips, which are then fired to produce the multilayer ceramic capacitor 1.

[0053] The multilayer ceramic capacitor 1 according to this embodiment includes a laminate 100 and a plurality of via conductors 140, 150. The laminate 100 includes a plurality of internal electrode layers 120, 130 alternately stacked in the stacking direction with a dielectric layer 110 sandwiched therebetween. The plurality of via conductors 140, 150 are provided inside the laminate 100 and are electrically connected to corresponding internal electrode layers of the plurality of internal electrode layers 120, 130, respectively. Each of the plurality of internal electrode layers 120, 130 has a plurality of holes 120H, 130H and a plurality of cutouts 120N, 130N formed therein for inserting via conductors of the plurality of via conductors 140, 150 that are not electrically connected. Each of the plurality of holes 120H, 130H is substantially circular. Each of the plurality of cutout portions 120N, 130N is cut out in an arc shape along an imaginary circle VC that is continuous with the substantially rectangular edges 121, 131 of each of the plurality of internal electrode layers 120, 130 and has a center C located inside the edges 121, 131. The ratio of the radius of the substantially circular shape of the hole portions 120H, 130H to the radius of the imaginary circle VC is 0.95 or more and 1.05 or less. The radius of each of the substantially circular shape of the hole portions 120H, 130H and the imaginary circle VC is 25 μm or more and 50 μm or less. When the shortest distance between the edge 121, 131 and the center C of the imaginary circle VC is a, the radius of the imaginary circle VC is r, and the diameter of each of the plurality of via conductors 140, 150 is d, the relationship (r - d) < a < r is satisfied.

[0054] This makes it possible to reduce the size of the multilayer ceramic capacitor 1 while suppressing open defects and ensuring the required number of via conductors 140, 150. Furthermore, compared to a case where the cutout portions 120N, 130N are not formed and all are formed as holes 120H, 130H, it is possible to increase the opposing area between the first internal electrode layer 120 and the second internal electrode layer 130 while reducing the size of the multilayer ceramic capacitor 1, thereby increasing the capacitance.

[0055] In this embodiment, the diameter d of each of the plurality of via conductors 140, 150 is 15 μm or more and 40 μm or less, which allows the multilayer ceramic capacitor 1 to be effectively miniaturized.

[0056] In the multilayer ceramic capacitor according to Example 1, L1 = W1 = 530 μm, L2 = W2 = 470 μm, a = 25 μm, r = 37 μm, d = 15 μm, and p = 140 μm. In the multilayer ceramic capacitor according to Example 2, L1 = W1 = 530 μm, L2 = W2 = 470 μm, a = 10 μm, r = 37 μm, d = 40 μm, and p = 150 μm. In the multilayer ceramic capacitor according to Example 3, L1 = W1 = 530 μm, L2 = W2 = 470 μm, a = 10 μm, r = 29 μm, d = 20 μm, and p = 150 μm.

[0057] In the multilayer ceramic capacitors according to Examples 1 to 3, it was possible to reduce the size of the multilayer ceramic capacitor 1 while suppressing open defects and ensuring the required number of via conductors 140, 150.

[0058] (Embodiment 2) A multilayer ceramic capacitor according to embodiment 2 of the present invention will be described below with reference to the drawings. The multilayer ceramic capacitor according to embodiment 2 of the present invention differs from the multilayer ceramic capacitor according to embodiment 1 of the present invention mainly in that notches are not formed at the four corners of the edges of the internal electrode layers. Therefore, the same reference numerals are used to designate components that are the same as those in the multilayer ceramic capacitor according to embodiment 1 of the present invention, and the description thereof will not be repeated.

[0059] Fig. 8 is a plan view of the multilayer ceramic capacitor according to embodiment 2 of the present invention, viewed from the first main surface side. Fig. 9 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 8, viewed from the direction of the arrows IX-IX. Fig. 10 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 9, viewed from the direction of the arrows X-X. Fig. 11 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 9, viewed from the direction of the arrows XI-XI.

[0060] As shown in FIGS. 8 to 11, the multilayer ceramic capacitor 2 according to the second embodiment of the present invention includes a laminate 200, a plurality of first via conductors 140, and a plurality of second via conductors 150.

[0061] In this embodiment, the plurality of second via conductors 150 are arranged in three rows vertically along the sides of the first main surface 101, as viewed from the stacking direction. The plurality of first via conductors 140 are arranged in two rows vertically so as to be located between the rows of second via conductors 150, as viewed from the stacking direction. The first via conductors 140 and the second via conductors 150 are arranged in a matrix.

[0062] By arranging the second via conductors 150 around the first via conductors 140 and the first via conductors 140 around the second via conductors 150, the magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 2. Note that the arrangement of the first via conductors 140 and the second via conductors 150 is not limited to the above arrangement.

[0063] As shown in Figures 10 and 11, each of the multiple first cutout portions 120N and the multiple second cutout portions 130N is formed on each side of the approximately rectangular shape of the edges 121, 131, and is not formed on the four corners of the approximately rectangular shape of the edges 121, 131.

[0064] This improves the coplanarity of the first main surface 101 of the laminate 200. Specifically, if the first cutouts 120N and the second cutouts 130N are formed at the four corners of the approximately rectangular shape of the edges 121, 131, the thickness of the mother laminate at the four corners is reduced by the thickness of the first cutouts 120N and the second cutouts 130N. Therefore, when the mother laminate is pressed, the portions of the first main surface 101 located on the four corners are recessed, and the coplanarity of the first main surface 101 is reduced.

[0065] In this embodiment, since the first cutout portion 120N and the second cutout portion 130N are not formed at the four corners of the approximately rectangular shape of the edges 121, 131, it is possible to prevent the portions of the first main surface 101 located on the four corners from becoming recessed, thereby improving coplanarity.

[0066] By improving the coplanarity on the first main surface 101 of the laminate 200, the end faces of the first via conductor 140 and the second via conductor 150 exposed on the first main surface 101 can be stably installed on the mounting board, thereby improving the mountability of the laminated ceramic capacitor 2.

[0067] In the multilayer ceramic capacitor according to Example 4, L1 = W1 = 530 μm, L2 = W2 = 470 μm, a = 22.87 μm, r = 37 μm, d = 15 μm, and p = 150 μm. In the multilayer ceramic capacitor according to Example 5, L1 = W1 = 530 μm, L2 = W2 = 470 μm, a = 8.73 μm, r = 37 μm, d = 40 μm, and p = 160 μm. In the multilayer ceramic capacitor according to Example 6, L1 = W1 = 530 μm, L2 = W2 = 470 μm, a = 8.73 μm, r = 29 μm, d = 21 μm, and p = 160 μm.

[0068] In the multilayer ceramic capacitors according to Examples 4 to 6, it was possible to reduce the size of the multilayer ceramic capacitor 2 while suppressing open defects and ensuring the required number of via conductors 140, 150.

[0069] In the above-described embodiments, configurations that can be combined may be combined with each other.

[0070] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0071] 1, 2 Multilayer ceramic capacitor, 100, 200 Laminate, 101 First main surface, 102 Second main surface, 103 First side surface, 104 Second side surface, 105 Third side surface, 106 Fourth side surface, 110 Dielectric layer, 120 First internal electrode layer, 120H First hole portion, 120N First cutout portion, 130N Second cutout portion, 121, 131 Edge, 130 Second internal electrode layer, 130H Second hole portion, 140 First via conductor, 150 Second via conductor, C Center, VC Virtual circle.

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of internal electrode layers alternately stacked in a stacking direction with dielectric layers sandwiched therebetween; and a plurality of via conductors provided inside the laminate and electrically connected to corresponding internal electrode layers of the plurality of internal electrode layers, wherein each of the plurality of internal electrode layers has a plurality of holes and a plurality of cutouts for inserting via conductors of the plurality of via conductors that are not electrically connected, each of the plurality of holes being approximately circular, and each of the plurality of cutouts being cut out in an arc shape along an imaginary circle that is continuous with the approximately rectangular edge of each of the plurality of internal electrode layers and has its center located inside the edge, wherein the ratio of the radius of the approximately circular shape to the radius of the imaginary circle is 0.95 or more and 1.05 or less, and the radius of each of the approximately circular shape and the imaginary circle is 25 μm or more and 50 μm or less, and wherein the relationship (r - d) < a < r is satisfied, where a is the shortest distance between the edge and the center of the imaginary circle, r is the radius of the imaginary circle, and d is the diameter of each of the plurality of via conductors.

2. The multilayer ceramic capacitor according to claim 1, wherein the diameter d is 15 μm or more and 40 μm or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the plurality of cutouts are not formed at the four corners of the substantially rectangular shape.

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