Light detection device and electronic apparatus

Abstract

Provided is a light detection device with which it is possible to reduce dark current. This light detection device comprises a semiconductor substrate, a plurality of photoelectric conversion units, separation parts, impurity diffusion regions, and a sealing region. The semiconductor substrate has a first surface serving as a light-receiving surface, and a second surface on the side opposite from the first surface. The plurality of photoelectric conversion units are formed in a two-dimensional array on the semiconductor substrate, said photoelectric conversion units generating electric signals in response to light that is incident from the first surface. The separation parts have an insulating film formed in a thickness direction from the first surface of the semiconductor substrate to the second surface thereof, said separation parts separating adjacent photoelectric conversion units. The impurity diffusion regions are formed between the photoelectric conversion units and the insulating films and include impurities for suppressing dark current. The sealing region seals the impurities that are diffused in directions other than the direction from the impurity diffusion regions to the photoelectric conversion units.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to a light detection device and an electronic device including the light detection device.

[0002] Conventionally, electronic devices with an imaging function, such as digital still cameras and digital video cameras, use solid-state imaging elements, such as charge-coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors, as photodetectors. The photodetector has unit pixels, each of which combines a photodiode (photoelectric conversion element) that performs photoelectric conversion with a transistor, and an image is constructed based on pixel signals output from a plurality of unit pixels arranged in a plane.

[0003] In a photodetector, a plurality of unit pixels are arranged in an array on a semiconductor substrate primarily made of silicon (Si), and isolation regions are formed between the unit pixels to electrically isolate the unit pixels. The isolation regions are formed by junction isolation or by an insulating film. However, when the isolation regions are formed by an insulating film, dark current generated at the interface between the semiconductor substrate and the insulating film becomes an issue.

[0004] Patent Document 1 listed below discloses a method of suppressing dark current by forming an array of optical sensors on a silicon semiconductor substrate, forming a region rich in halogen (fluorine (F) or the like) between an isolation region and the optical sensor (near the interface), and inactivating traps at the silicon interface. Furthermore, methods of implanting halogen, particularly fluorine (F), such as ion implantation or diffusion from SiOF, are disclosed.

[0005] Special Publication No. 2007-504666

[0006] However, fluorine (F) that binds to the interface traps between the isolation region formed by the insulating film and silicon and electrically inactivates the traps is likely to be released from the traps due to out-diffusion or the like during a thermal process or the like in the semiconductor device formation process. As a result, the inactivated traps may become activated again and become a source of dark current.

[0007] The present disclosure has been made in view of the above circumstances, and has an object to provide a photodetector and electronic equipment capable of reducing dark current.

[0008] One aspect of the present disclosure is a photodetector device comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate and capable of generating an electrical signal in response to light incident from the first surface; a separation unit having an insulating film formed in a thickness direction from the first surface toward the second surface of the semiconductor substrate and separating adjacent photoelectric conversion units; an impurity diffusion region formed between the photoelectric conversion units and the insulating film and containing impurities for suppressing dark current; and a sealing region that seals off impurities diffusing from the impurity diffusion region in at least a direction other than toward the photoelectric conversion units.

[0009] Another aspect of the present disclosure is a photodetector including: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a first photoelectric conversion unit disposed on the first surface side of the semiconductor substrate and capable of generating an electrical signal in response to first light incident from the first surface; a second photoelectric conversion unit disposed on the second surface side of the semiconductor substrate and capable of generating an electrical signal in response to second light having a wavelength range different from that of the first light; a through via that penetrates the semiconductor substrate from the second surface of the semiconductor substrate to the first photoelectric conversion unit, has a sidewall covered with an insulating film, and transmits the electrical signal generated in the first photoelectric conversion unit to the second surface side; an impurity diffusion region formed between the second photoelectric conversion unit and the insulating film and containing impurities for suppressing dark current; and a sealing region that seals off impurities diffusing from the impurity diffusion region in at least directions other than toward the first photoelectric conversion unit or the second photoelectric conversion unit.

[0010] Another aspect of the present disclosure is an electronic device including a photodetector device comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate and capable of generating an electrical signal in response to light incident from the first surface; a separation unit having an insulating film formed in a thickness direction from the first surface toward the second surface of the semiconductor substrate and separating adjacent photoelectric conversion units; an impurity diffusion region formed between the photoelectric conversion units and the insulating film and containing impurities for suppressing dark current; and a sealing region that seals off impurities diffusing from the impurity diffusion region in at least a direction other than toward the photoelectric conversion units.

[0011] 1 is a block diagram showing an example of a schematic configuration of a photodetector according to a first embodiment of the present disclosure; FIG. 2 is a circuit configuration diagram of a pixel shown in FIG. 1; FIG. 3 is an example of a partial cross-sectional view enlarging a region of a dotted line B of a pixel separating portion shown in FIG. 3; FIG. 4 is a cross-sectional view (part 5) showing a process procedure of a method for forming a photodetector according to a first embodiment of the present disclosure; FIG. 5 is a cross-sectional view (part 6) showing a process procedure of a method for forming a photodetector according to a first embodiment of the present disclosure; FIG. 6 is a cross-sectional view (part 7) showing a process procedure of a method for forming a photodetector according to a first embodiment of the present disclosure; FIG. 7 is a cross-sectional view (part 8) showing a process procedure of a method for forming a photodetector according to a first embodiment of the present disclosure; FIG. 9 is a cross-sectional view (part 9) showing a process procedure of a method for forming a photodetector according to a first embodiment of the present disclosure. FIG. 10 is a cross-sectional view (part 10) showing a process procedure of a method for forming a photodetector according to a first embodiment of the present disclosure. FIG. 11 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector according to a first modified example of the first embodiment of the present disclosure. FIG. 12 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector according to a second modified example of the first embodiment of the present disclosure. FIG. 13 is a partial cross-sectional view showing an enlarged region of a dotted line B1 of a pixel separator shown in FIG. 7 above. FIG. 14 is a cross-sectional view (part 1) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 15 is a cross-sectional view (part 2) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 16 is a cross-sectional view (part 3) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 17 is a cross-sectional view (part 4) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 18 is a cross-sectional view (part 5) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure.FIG. 10 is a cross-sectional view (part 6) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 11 is a cross-sectional view (part 7) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 12 is a cross-sectional view (part 8) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 13 is a cross-sectional view (part 9) showing a process procedure of a method for forming a photodetector according to a second embodiment of the present disclosure. FIG. 14 is an example of a partial cross-sectional view of a pixel separator according to a first modified example of the second embodiment of the present disclosure. FIG. 15 is an example of a partial cross-sectional view of a pixel separator according to a second modified example of the second embodiment of the present disclosure. FIG. 16 is an example of a partial cross-sectional view of a pixel separator according to a third modified example of the second embodiment of the present disclosure. FIG. 17 is an example of a partial cross-sectional view of a pixel separator according to a fourth modified example of the second embodiment of the present disclosure. FIG. 18 is an example of a partial cross-sectional view of a pixel separator according to a fifth modified example of the second embodiment of the present disclosure. FIG. 19 is an example of a partial cross-sectional view of a pixel separator according to a sixth modified example of the second embodiment of the present disclosure. FIG. 19 is a cross-sectional view (part 1) showing a process procedure of a method for forming a photodetector according to a seventh modified example of the second embodiment of the present disclosure. FIG. 10 is a cross-sectional view (part 2) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 11 is a cross-sectional view (part 3) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 12 is a cross-sectional view (part 4) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 13 is a cross-sectional view (part 5) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 14 is a cross-sectional view (part 6) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 15 is a cross-sectional view (part 7) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 16 is a cross-sectional view (part 8) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 17 is a cross-sectional view (part 9) showing a process procedure of a method for forming a photodetector according to a seventh modification of the second embodiment of the present disclosure. FIG. 18 is a partial vertical cross-sectional view of a pixel separator according to a third embodiment of the present disclosure. FIG. 19 is a partial vertical cross-sectional view of a pixel separator according to a fourth embodiment of the present disclosure. FIG. 10 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector according to a fifth embodiment of the present disclosure.26 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector according to a sixth embodiment of the present disclosure. FIG. 27 is an example of a partial cross-sectional view in which the region of dotted line B2 of the pixel separating portion shown in FIG. 20 is enlarged. FIG. 28 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector according to a seventh embodiment of the present disclosure. FIG. 29 is an example of a partial cross-sectional view in which the region of dotted line D of the through via shown in FIG. 22 is enlarged. FIG. 29 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector according to an eighth embodiment of the present disclosure. FIG. 29 is a block diagram showing an example of the configuration of an electronic device. FIG. 29 is a block diagram showing an example of a schematic configuration of a vehicle control system to which the present technology is applied. FIG. 29 is an explanatory diagram showing an example of installation positions of the outside vehicle information detection unit and the imaging unit shown in FIG.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts will be designated by identical or similar reference numerals, and redundant description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0013] In this specification, the "first conductivity type" refers to either p-type or n-type, and the "second conductivity type" refers to either p-type or n-type, which is different from the "first conductivity type." Furthermore, the "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the semiconductor regions have the same "n" and "n" attached, this does not mean that the impurity densities of the respective semiconductor regions are strictly the same.

[0014] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Note that the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0015] <First Embodiment> (Overall Configuration of Photodetection Device) Fig. 1 is a block diagram showing an example of a schematic configuration of a photodetection device according to a first embodiment of the present disclosure. The photodetection device 1A is a semiconductor device configured as, for example, a CMOS image sensor, which uses photoelectric conversion elements such as photodiodes constituting each pixel to convert an amount of charge corresponding to the intensity of light imaged on the pixel into an electrical signal and outputs this as image data. The photodetection device 1A can be configured as an integrated system-on-chip (SoC) such as a CMOS LSI, for example. However, for example, some of the components shown below may be configured as separate LSIs.

[0016] As shown in the figure, the photodetection device 1A is configured to include components such as a pixel array section 11, a vertical drive section 12, a column processing section 13, a horizontal drive section 14, a system control section 15, a signal processing section 16, and a data storage section 17.

[0017] The pixel array unit 11 includes a group of photoelectric conversion elements such as photodiodes that constitute pixels 110 arranged in an array in the horizontal direction (row direction) and the vertical direction (column direction). The pixel array unit 11 converts the amount of charge corresponding to the intensity of incident light focused on each pixel 110 into an electrical signal and outputs it as a pixel signal. The pixel array unit 11 may include, for example, effective pixels arranged in an area capable of receiving actual light and dummy pixels arranged outside the area and shielded by metal or the like. Note that optical elements such as micro-on-chip lenses and color filters that focus incident light are formed on each pixel 110 of the pixel array unit 11 (not shown). The area formed by the arrayed pixels 110 constitutes a so-called "image height" that corresponds to the target space to be imaged.

[0018] The vertical drive unit 12 is configured to include a shift register, an address decoder, etc. The vertical drive unit 12 supplies drive signals, etc. to each pixel 110 via a plurality of pixel drive lines 18, thereby driving each pixel 110 of the pixel array unit 11, for example, simultaneously or row by row.

[0019] The column processing unit 13 reads out pixel signals from each pixel for each pixel column of the pixel array unit 11 via vertical signal lines (VSL) 19, and performs noise removal processing, correlated double sampling (CDS) processing, A / D (Analog-to-Digital) conversion processing, etc. The pixel signals processed by the column processing unit 13 are output to the signal processing unit 16.

[0020] The horizontal driving unit 14 is configured to include a shift register, an address decoder, etc. The horizontal driving unit 14 sequentially selects the pixels 110 corresponding to the pixel columns of the column processing unit 13. By the selective scanning by the horizontal driving unit 14, pixel signals processed for each pixel 110 in the column processing unit 13 are output sequentially to the signal processing unit 16.

[0021] The system control unit 15 includes a timing generator that generates various timing signals, etc. The system control unit 15 controls the driving of the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on timing signals generated by, for example, a timing generator (not shown).

[0022] The signal processing unit 16 performs signal processing such as arithmetic processing on the pixel signals supplied from the column processing unit 13, while temporarily storing data in the data storage unit 17 as necessary, and outputs an image signal based on each pixel signal. The signal processing unit 16 also performs signal processing in accordance with the flags output from the column processing unit 13.

[0023] It should be noted that the photodetector 1A to which the present technology is applied is not limited to the configuration described above. For example, the photodetector 1 may be configured such that the data storage unit 17 is disposed after the column processing unit 13, and pixel signals output from the column processing unit 13 are supplied to the signal processing unit 16 via the data storage unit 17. Alternatively, the photodetector 1 may be configured such that the column processing unit 13, the data storage unit 17, and the signal processing unit 16 are cascade-connected to process the pixel signals in parallel.

[0024] (Pixel Circuit Configuration) FIG. 2 is a circuit configuration diagram of a pixel 110. As shown in FIG. 2, each of the multiple pixels 110 includes a photoelectric conversion region 21 and a pixel circuit (readout circuit) 22. The photoelectric conversion region 21 includes a photoelectric conversion unit 23, a transfer transistor TR, and a charge retention region (floating diffusion) FD. The pixel circuit 22 is electrically connected to the charge retention region FD of the photoelectric conversion region 21. In the first embodiment, as an example, a circuit configuration is used in which one pixel circuit 22 is assigned to one pixel 110. However, this is not limited thereto, and one pixel circuit 22 may be shared by multiple pixels 110. For example, a circuit configuration may be used in which one pixel circuit 22 is shared by four pixels 110 (one pixel block) arranged in a 2×2 array, two pixels in each of the horizontal and vertical directions.

[0025] The photoelectric conversion unit 23 is formed of, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The cathode side of the photoelectric conversion unit 23 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

[0026] The transfer transistor TR transfers the signal charge photoelectrically converted by the photoelectric conversion unit 23 to the charge holding region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 23, and the drain region of the transfer transistor TR is electrically connected to the charge holding region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 18 (see FIG. 1).

[0027] The charge holding region FD temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 23 via the transfer transistor TR.

[0028] The pixel circuit 22 reads out the signal charges held in the charge holding region FD, converts the read-out signal charges into a pixel signal, and outputs the pixel signal. In other words, the pixel circuit 22 converts the signal charges photoelectrically converted by the photoelectric conversion element PD into a pixel signal based on the signal charges and outputs the pixel signal. The pixel circuit 22 includes, but is not limited to, pixel transistors, such as an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG. Each of these pixel transistors (AMP, SEL, RST, FDG) and the transfer transistor TR described above is configured as a field-effect transistor, such as a MOSFET. Alternatively, these transistors may be MISFETs.

[0029] Among the pixel transistors included in the pixel circuit 22, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG each function as a switching element, and the amplification transistor AMP functions as an amplification element. Note that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0030] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge retention region FD and the source region of the switching transistor FDG.

[0031] The select transistor SEL has a source region electrically connected to the vertical signal line 19 (VSL), a drain region electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a select transistor drive line among the pixel drive lines 18 (see FIG. 1).

[0032] The reset transistor RST has a source region electrically connected to the drain region of the switching transistor FDG, a drain region electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP, and a gate electrode electrically connected to a reset transistor drive line among the pixel drive lines 18 (see FIG. 1).

[0033] The switching transistor FDG has a source region electrically connected to the charge retention region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 18 (see FIG. 1).

[0034] When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 19 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and the charge retention region FD of the amplification transistor AMP.

[0035] When the transfer transistor TR is turned on, the transfer transistor TR transfers the signal charge generated in the photoelectric conversion portion 23 to the charge holding region FD.

[0036] When the reset transistor RST is turned on, it resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 22.

[0037] The amplification transistor AMP generates, as a pixel signal, a signal whose voltage corresponds to the level of the signal charge held in the charge holding region FD. The amplification transistor AMP constitutes a source follower amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 23. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the charge holding region FD and outputs a voltage corresponding to the potential to the column processing unit 13 via the vertical signal line 19 (VSL).

[0038] The switching transistor FDG controls charge retention by the charge retention region FD and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0039] 3 is a partial vertical cross-sectional view showing an example of a semiconductor structure of the photodetector 1A according to the first embodiment of the present disclosure. As shown in the figure, the semiconductor structure 30A generally includes, for example, a semiconductor layer 31 (an example of a semiconductor substrate), a wiring layer 32, a fixed charge film 33, an anti-reflection film 34, an insulating film 35, a color filter 36, and an on-chip lens 37. Such a semiconductor structure 30A can be formed by integrally bonding, for example, a first silicon substrate including the wiring layer 32 and various logic circuits (not shown) with a second silicon substrate including the semiconductor layer 31.

[0040] A fixed charge film 33, an anti-reflection film 34, an insulating film 35, a color filter 36, and an on-chip lens 37 are laminated in this order on a first surface S1, which is a light incident surface of the semiconductor layer 31. A wiring layer 32 is laminated on a second surface S2 of the semiconductor layer 31.

[0041] The on-chip lens 37 is an optical lens for efficiently collecting light incident on the photodetector 1A from the outside and forming an image on each pixel 110 of the semiconductor layer 31. Typically, the on-chip lens 37 is disposed for each pixel 110.

[0042] The color filters 36 are optical filters that selectively transmit light of a predetermined wavelength from the light collected by the on-chip lens 37. In this example, four color filters 36 are used that selectively transmit red light, green light, blue light, and near-infrared light, respectively, but this is not limiting. A color filter 36 corresponding to one of the colors (wavelengths) is arranged in each pixel 110.

[0043] The semiconductor layer 31 is provided with an n-type layer 311 constituting a photodiode PD, which is the photoelectric conversion unit 23, and a p-type layer 312, which is a well layer (hereinafter referred to as a p-well 312). Each n-type layer 311 of the semiconductor layer 31 generates an amount of charge according to the intensity of light incident through the on-chip lens 37 and the color filter 36, converts this into an electrical signal, and outputs it as a pixel signal. Furthermore, the p-well 312 of the semiconductor layer 31 is provided with, for example, a gate electrode 322 of the transfer transistor TR and a charge retention region FD.

[0044] The semiconductor layer 31 is provided with a pixel separator 40A (an example of a separator) that electrically separates adjacent pixels 110. The pixel separator 40A has a trench structure formed by, for example, an etching process, and extends in the thickness direction of the semiconductor layer 31, that is, in the direction indicated by the arrow Z in FIG. 3 . The pixel separator 40A prevents light incident on a pixel 110 from entering an adjacent pixel 110. In the first embodiment of the present disclosure, the pixel separator 40A is configured with an insulating film 41 provided on the second surface S2 side of the semiconductor layer 31, and a polysilicon film 42 extending from the insulating film 41 to the first surface S1 of the semiconductor layer 31.

[0045] The p-well 312, the transfer transistor TR, and the charge retention region FD are electrically connected to metal wiring 321 in the wiring layer 32. The gate electrode 322 of the transfer transistor TR is connected to the pixel drive line 18 via the metal wiring 321, and a drive signal for controlling the transfer transistor TR is supplied from the vertical drive unit 12. When a drive signal is supplied to the gate electrode 322, the transfer transistor TR transfers the signal charge accumulated in the n-type layer 311 to the charge retention region FD. In this example, the wiring layer 32 is formed on a semiconductor support substrate (not shown). The wiring layer 32 is typically formed by stacking multiple layers of metal wiring 321 with an interlayer insulating film sandwiched between them. The stacked metal wiring 321 are electrically connected, for example, by vias. The wiring layer 32 is formed of a metal such as aluminum (Al) or copper (Cu). On the other hand, the interlayer insulating film is formed of, for example, silicon oxide or the like.

[0046] The fixed charge film 33 generates negative fixed charges. It is preferable to use a material for the fixed charge film 33 that can generate fixed charges and strengthen pinning by being deposited on a substrate such as silicon, and a high refractive index material film or a high dielectric film having negative charges can be used. This suppresses the generation of dark current.

[0047] Ta2O3 or silicon oxide (SiO2) is used for the anti-reflection film 34 and the insulating film 35. Low bending strength material spacers 38, which serve as a light-shielding film, are provided on the back side (light incident surface side) of the insulating film 35. The low bending strength material spacers 38 are formed in a lattice shape so as to open the photoelectric conversion units 23. In other words, the low bending strength material spacers 38 are formed in positions corresponding to the pixel separation units 40A.

[0048] Fig. 4 is an example of a partial cross-sectional view enlarging the region indicated by the dotted line B in the pixel separating portion 40A shown in Fig. 3. In Fig. 4, the sidewall (DTI interface) of the polysilicon film 42 is covered with an insulating film 43 made of SiOF. The insulating film 43 may be made of silicon oxide (SiO2) + SiOF.

[0049] In the first embodiment of the present disclosure, an F-diffused Si layer 44 (an example of an impurity diffusion region) is provided between the insulating film 43 and the p-well 312, i.e., between the silicon (Si) and the polysilicon film 42 and the insulating film 43, to supply fluorine (F), which serves as a halogen for suppressing dark current. Furthermore, in the first embodiment of the present disclosure, a sealing film 45 (an example of a sealing region) made of silicon nitride (SiN) is provided between the polysilicon film 42 and the insulating film 43 to seal fluorine (F) that penetrates the insulating film 43 from the F-diffused Si layer 44. In other words, fluorine (F) that diffuses from the F-diffused Si layer 44 in directions other than the p-well 312 is sealed. The sealing film 45 made of silicon nitride (SiN) is provided only on a surface parallel to the sidewall of the polysilicon film 42. This can suppress variations in optical isolation characteristics between adjacent pixels 110. This is due to variations in the trench opening and sealing film formation processes during the manufacturing process, which cause variations in the improvement of the angles between parallel and non-parallel surfaces, resulting in fluctuations in the reflection and transmission characteristics of light incident on the isolation region.By using only parallel surfaces, this variation can be suppressed.

[0050] According to the structure of the first embodiment of the present disclosure, traps at the interface with the pixel separating section 40A can be inactivated by fluorine (F), and the generation of dark current caused by interfacial recombination can be suppressed.

[0051] 5A to 5J are cross-sectional views showing the process steps of a method for forming the photodetector 1A according to the first embodiment of the present disclosure. The photodetector 1A is manufactured using various types of equipment, such as a film formation apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0052] The manufacturing equipment deposits a SiO2 film 52 to a thickness of about 200 to 500 nm on a silicon semiconductor substrate 51 into which impurity ions for forming a photodiode have been implanted, and processes the silicon semiconductor substrate 51 and the SiO2 film 52 by 100 to 400 nm by RIE according to a device isolation region formation pattern (FIG. 5A).

[0053] Next, the manufacturing equipment deposits an insulating film 53 made of silicon nitride (SiN) to a thickness of about 30 to 70 nm on the surfaces of the silicon semiconductor substrate 51 and the SiO2 film 52 by a method such as CVD, and then etches the silicon semiconductor substrate 51 to a depth of 5 to 10 μm along the SiO2 film 52 of the hard mask by anisotropic RIE (FIG. 5B), and, if necessary, injects P-type impurities such as boron from the inner wall 51 a of the etched silicon semiconductor substrate 51. The impurity injection method may be plasma doping, solid-phase diffusion from boron-containing glass (BSG), or vapor-phase diffusion, and the impurities are not injected into the region covered with the insulating film 53.

[0054] Next, the manufacturing equipment removes the insulating film 53 and the SiO2 film 52 of the hard mask, and deposits an insulating film 43 made of SiOF as a fluorine (F) diffusion source and a sealing film 45 made of silicon nitride (SiN) on the silicon semiconductor substrate 51. At this time, silicon oxide (SiO2) may be sandwiched at the interface between the silicon (Si) and SiOF (FIG. 5C).

[0055] Next, the manufacturing equipment deposits a polysilicon film 42 by CVD or the like. At this time, p-type impurities such as boron (B) are doped by ion implantation or the like. Alternatively, amorphous silicon containing B (B-DAS) may be deposited (FIG. 5D).

[0056] Next, the manufacturing equipment etches the polysilicon film 42, insulating film 43, sealing film 45, and upper portions of the trenches on the surface of the silicon semiconductor substrate 51, and deposits an insulating film 41 such as silicon oxide (SiO2) on the upper portions of the trenches and on the surface of the silicon semiconductor substrate 51. At this time, planarization processing is performed as necessary (FIG. 5E).

[0057] Thereafter, in order to form pixel transistors such as the photodiode PD, the charge retention region FD, and the gate electrode 322 of the transfer transistor TR, the manufacturing equipment (not shown) performs ion implantation of impurities, CVD processes for gate polysilicon and insulating film, and a heat treatment process for activation, thereby forming interlayer insulation and forming an electrode / metal wiring pattern 321 ( FIG. 5F ). ​​After the deposition of the insulating film 43 made of SiOF in FIG. 5C , fluorine (F) diffuses from the insulating film 43 into the silicon semiconductor substrate 51 in the heat treatment process up to this point, and the fluorine (F) binds to the interface traps of the silicon semiconductor substrate 51, thereby inactivating the traps.

[0058] Thereafter, in the back surface processing step, the manufacturing equipment thins and flattens the silicon semiconductor substrate 51 to generate the semiconductor layer 31 (FIG. 5G), deposits the fixed charge film 33 (FIG. 5H), deposits the anti-reflection film 34 and the insulating film 35 (FIG. 5I), and forms the low refractive index spacer 38, the color filter 36, and the on-chip lens 37, thereby forming the photodetector 1A (FIG. 5J).

[0059] <Effects of First Embodiment> As described above, according to the first embodiment, the F-diffused Si layer 44 that supplies fluorine (F), which serves as a halogen for suppressing dark current, is provided on the trench sidewall of the insulating film 43, i.e., between the photoelectric conversion unit 23 and the insulating film 43, thereby inactivating the interface traps. In addition, the sealing film 45 that does not allow fluorine (F) to pass through is provided between the insulating film 43 and the polysilicon film 42 to seal in the fluorine (F), preventing the fluorine (F) from being released from the traps by out-diffusion, thereby reducing the interface trap density and the dark current. Note that the first embodiment can also be implemented using a conductor other than the polysilicon film 42.

[0060] 6A is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector 1A1 according to a first modification of the first embodiment of the present disclosure. In Fig. 6A, the same parts as those in Fig. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0061] In the pixel separating portion 40A1 according to the first modification, the polysilicon film 42 is made conductive by being doped with a p-type impurity such as boron (B). Furthermore, the polysilicon film 42 is connected to a metal electrode 323 provided in the wiring layer 32.

[0062] The metal electrode 323 is electrically connected to the polysilicon film 42 via the insulating film 41 in the pixel separating section 40A1. The metal electrode 323 is also connected to an external mechanism (not shown) that applies voltage. The metal electrode 323 applies a negative voltage (for example, -3 V) to the polysilicon film 42 during operation. This induces holes near the pixel separating section 40A1, and electrons generated by surface recombination annihilate with the holes, thereby suppressing the generation of dark current. The voltage applied to the polysilicon film 42 may be 0 V.

[0063] 6B is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector 1A2 according to a second modification of the first embodiment of the present disclosure. In Fig. 6B, the same parts as those in Fig. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0064] The pixel separating portion 40A2 according to the second modification does not penetrate the semiconductor layer 31, but is formed partway from the second surface S2 to the first surface S1 of the semiconductor layer 31. In the pixel separating portion 40A2 according to the second modification, as in the first embodiment, an F-diffused Si layer 44 that supplies fluorine (F), which serves as halogen for suppressing dark current, is provided on the trench sidewall of the insulating film 43, i.e., between the photoelectric conversion unit 23 and the insulating film 43, to inactivate interface traps. In addition, a sealing film 45 that does not allow fluorine (F) to pass through is provided between the insulating film 43 and the polysilicon film 42 to seal in the fluorine (F), thereby reducing the area of ​​the interface between the semiconductor layer 31 and the insulating film 43, which is advantageous for suppressing dark current.

[0065] 7 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector 1B according to a second embodiment of the present disclosure. In Fig. 7, the same parts as those in Fig. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0066] In the semiconductor structure 30B of the second embodiment, a buried film 61 made of silicon oxide (SiO2) that fills the trench of the pixel separating portion 40B is provided between the insulating film 35 and the color filter 36. The pixel separating portion 40B according to the second embodiment is formed in the thickness direction (the direction indicated by the arrow Z in FIG. 7 ) so as not to penetrate the semiconductor layer 31 but to reach partway from the first surface S1 to the second surface S2 of the semiconductor layer 31.

[0067] Fig. 8 is an example of a partial cross-sectional view enlarging the region indicated by the dotted line B1 in the pixel separating portion 40B shown in Fig. 7. In Fig. 8, the sidewall of the buried film 61 is covered with an insulating film 62 made of SiOF. The insulating film 62 may be made of silicon oxide (SiO2) or a laminated film of silicon oxide (SiO2) and SiOF.

[0068] In the second embodiment of the present disclosure, an F-diffused Si layer 63 is provided between the insulating film 62 and the p-well 312, i.e., in silicon (Si), to supply fluorine (F), which serves as a halogen for suppressing dark current. Furthermore, in the second embodiment of the present disclosure, a sealing film 64 made of titanium nitride (TiN) is provided between the buried film 61 and the insulating film 62 to seal fluorine (F) that permeates from the F-diffused Si layer 63 through the insulating film 62. In other words, fluorine (F) that diffuses from the F-diffused Si layer 63 in directions other than the p-well 312 is sealed. The sealing film 64 is connected to the fixed charge film 33.

[0069] According to the structure of the second embodiment of the present disclosure, traps at the interface with the pixel separating section 40B are inactivated by fluorine (F), thereby suppressing the generation of dark current caused by interface recombination. Furthermore, since the sealing film 64 is conductive, a negative voltage (e.g., −3 V) is applied during operation by connecting it to a mechanism capable of applying voltage, for example, via the fixed charge film 33. This induces holes near the pixel separating section 40B, and electrons generated by surface recombination annihilate with the holes, thereby suppressing the generation of dark current. Note that the voltage applied to the sealing film 64 may be 0 V.

[0070] 9A to 9I are cross-sectional views showing the process steps of a method for forming a photodetector 1B according to the second embodiment of the present disclosure. The photodetector 1B is manufactured using various types of equipment, such as a film formation apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0071] The manufacturing equipment creates a semiconductor layer 31 in which the photoelectric conversion portion 23, the charge retention region FD, the gate electrode 322 of the transfer transistor TR, and the like are formed, and stacks a wiring layer 32 on the semiconductor layer 31 (FIG. 9A).

[0072] Then, the manufacturing equipment thins and flattens the semiconductor layer 31 in a back surface forming process (FIG. 9B). Next, the manufacturing equipment forms trenches TH1 in accordance with the isolation regions of the pixel array section 11 by photolithography and RIE processes (FIG. 9C).

[0073] Next, the manufacturing equipment deposits an insulating film 62 as a fluorine (F) diffusion source in trench TH1 and Al2O3 as a sealing film 64 to prevent outward diffusion of fluorine (F) by ALD. At this time, silicon oxide (SiO2) may be sandwiched at the interface between silicon (Si) and SiOF. Furthermore, the Al2O3 of the sealing film 64 has a fixed charge and also functions to induce holes on the silicon surface (FIG. 9D).

[0074] Next, the manufacturing equipment deposits a tantalum oxide film (Ta2O5) or the like as an anti-reflection film 34 mainly on the flat surface portion by PVD or CVD (FIG. 9E), and then deposits insulating films 35, 61-1 such as silicon oxide (SiO2) or HfO2 by ALD (FIG. 9F).

[0075] Furthermore, the manufacturing equipment deposits a thin film metal 61-2 such as titanium nitride (TiN) to a thickness of 20 to 100 nm by a CVD method, an ALD method, or the like, and then fills the trench TH1 with an insulating film 61-3 such as silicon oxide (SiO2) (FIG. 9G). Note that after the SiOF deposition (FIG. 9D), a thermal process at about 400°C, such as a CVD process or an ALD process, causes fluorine (F) to diffuse from the SiOF into the silicon (Si), and the fluorine (F) binds to the interface traps of the silicon (Si), thereby deactivating the traps.

[0076] Next, the manufacturing equipment removes the thin film metal 61-2 and insulating film 61-3 from the flat portion on the back surface (FIG. 9H).Furthermore, the manufacturing equipment deposits an insulating film 65 such as silicon oxide (SiO2) (FIG. 9I), and forms the low-refractive index spacer 38, the color filter 36, and the on-chip lens 37, thereby completing the photodetector 1B.

[0077] <Effects of Second Embodiment> As described above, according to the second embodiment, the sealing film 64 is conductive, and therefore a negative voltage (for example, −3 V) is applied during operation by connecting it to a mechanism that can apply a voltage, for example, via the fixed charge film 33. This induces holes in the vicinity of the pixel separating portion 40B, and electrons generated by surface recombination annihilate with the holes, thereby suppressing the generation of dark current.

[0078] 10 is an example of a partial cross-sectional view of a pixel separator 40B1 according to a first modification of the second embodiment of the present disclosure. In Fig. 10, the same parts as those in Fig. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0079] In a first modification of the second embodiment, in the pixel separation section 40B1, an aluminum oxide (Al2O3) film 66 is disposed between an insulating film 62 covering the F-diffused Si layer 63 and a sealing film 64 made of titanium nitride (TiN). Furthermore, an insulating film 67 made of silicon oxide (SiO2) is disposed between the sealing film 64 and the aluminum oxide film 66. Instead of the aluminum oxide (Al2O3) film 66, a silicon nitride (SiN) film may be used, or a composite film of aluminum oxide (Al2O3) and silicon nitride (SiN) films may also be used. Furthermore, when the aluminum oxide film 66 is used, holes are induced at the silicon (Si) interface by fixed charges, enhancing the pinning effect.

[0080] 11 is an example of a partial cross-sectional view of a pixel separator 40B2 according to a second modification of the second embodiment of the present disclosure. In Fig. 11, the same parts as those in Fig. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0081] In the second modification of the second embodiment, a high-dielectric film 68 such as HfO2 is added to the pixel separating portion 40B2 between the sealing film 64 and the aluminum oxide film 66. Compared to the first modification, holes can be induced more effectively when a negative charge is applied using the sealing film 64 as an electrode.

[0082] 12 is an example of a partial cross-sectional view of a pixel separator 40B3 according to a third modification of the second embodiment of the present disclosure. In Fig. 12, the same parts as those in Fig. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0083] The third modified example of the second embodiment is an application example in which a p-type diffusion layer 69 is formed on the silicon (Si) side of the pixel isolation portion 40B3. The p-type diffusion layer 69 is formed by plasma doping during trench formation, solid-phase diffusion from BSG, p-type silicon epitaxial growth, or the like. The p-type diffusion layer 69 is formed in the entire trench region. The structure of the third modified example makes it easy to form an electrode structure that fixes the p-type diffusion layer 69 to the ground potential.

[0084] 13 is an example of a partial cross-sectional view of a pixel separator 40B4 according to a fourth modification of the second embodiment of the present disclosure. In Fig. 13, the same parts as those in Fig. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0085] The fourth modified example of the second embodiment is an example in which the p-type diffusion layer 69 is not formed on the substrate surface side where the pixel transistors are arranged. By adopting the structure of the fourth modified example, it becomes possible to arrange the pixel transistors having the n-type diffusion layer near the pixel isolation portion 40B4, which is advantageous for miniaturization and high integration.

[0086] 14 is an example of a partial cross-sectional view of a pixel separator 40B5 according to a fifth modification of the second embodiment of the present disclosure. In Fig. 14, the same parts as those in Fig. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0087] The fifth modification of the second embodiment is a modification in which the silicon (Si) interface in the pixel separating portion 40B5 does not include the insulating film 62 made of SiOF. In the structure of the fifth modification, the thickness of the insulating film between the titanium nitride (TiN) sealing film 64 and the F-diffused Si layer 63 can be made thinner, so that holes are more likely to be induced when a negative potential is applied to the titanium nitride (TiN) electrode.

[0088] 15 is an example of a partial cross-sectional view of a pixel separator 40B6 according to a sixth modification of the second embodiment of the present disclosure. In Fig. 15, the same parts as those in Fig. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0089] The sixth modification of the second embodiment is a modification in which a p-type diffusion layer 69 is formed in the silicon (Si) of the pixel isolation portion 40B6. The p-type diffusion layer 69 can be formed by plasma doping during trench formation, solid-phase diffusion from BSG, p-type silicon epitaxial growth, or the like. The p-type diffusion layer 69 is not formed on the surface side of the substrate where the pixel transistors are arranged. This structure allows pixel transistors having n-type diffusion layers to be arranged near the pixel isolation portion 40B6, which is advantageous for miniaturization and high integration. Although not described here, the formation of the p-type diffusion layer 69 in the pixel isolation portion 40B6 can be applied to each of the above embodiments.

[0090] 16A to 16I are cross-sectional views showing the steps of a method for forming a photodetector 1B according to a seventh modification of the second embodiment of the present disclosure. In Fig. 16A to Fig. 16I, the same parts as those in Fig. 5A to Fig. 5J are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0091] The manufacturing equipment deposits a SiO2 film 52 to a thickness of about 200 to 500 nm on a silicon semiconductor substrate 51 into which impurity ions for forming a photodiode have been implanted, and processes the silicon semiconductor substrate 51 and the SiO2 film 52 by 100 to 400 nm by RIE according to a device isolation region formation pattern (FIG. 16A).

[0092] Next, the manufacturing equipment deposits an insulating film 53 made of silicon nitride (SiN) to a thickness of about 30 to 70 nm on the surfaces of the silicon semiconductor substrate 51 and the SiO2 film 52 by a method such as CVD, etches the silicon semiconductor substrate 51 to a depth of 5 to 10 μm along the SiO2 film 52 of the hard mask by anisotropic RIE (FIG. 16B), and, if necessary, injects P-type impurities such as boron from the inner wall 51 a of the etched silicon semiconductor substrate 51.

[0093] Next, the manufacturing equipment removes the insulating film 53 and the SiO2 film 52 of the hard mask, and deposits an insulating film 43 made of SiOF as a fluorine (F) diffusion source on the silicon semiconductor substrate 51. Then, the manufacturing equipment deposits a polysilicon film 42 by CVD or the like (FIG. 16C).

[0094] Next, the manufacturing equipment etches the polysilicon film 42 on the surface of the silicon semiconductor substrate 51 and the upper part of the trench (FIG. 16D).Then, the manufacturing equipment deposits an insulating film 41 such as silicon oxide (SiO2) on the upper part of the trench (FIG. 16E).

[0095] Thereafter, although not shown, the manufacturing equipment performs ion implantation of impurities, CVD processes for gate polysilicon and insulating film, and a heat treatment process for activation to form pixel transistors such as the photodiode PD, charge retention region FD, and gate electrode 322 of the transfer transistor TR, thereby forming interlayer insulation and electrodes or metal wiring 321 ( FIG. 16F ). After the deposition of the insulating film 43 made of SiOF in FIG. 16C , fluorine (F) diffuses from the insulating film 43 to the silicon semiconductor substrate 51 in the heat treatment process up to this point, and the fluorine (F) binds to interface traps in the silicon semiconductor substrate 51, thereby inactivating the traps.

[0096] Thereafter, the manufacturing equipment thins and planarizes the silicon semiconductor substrate 51 in a backside surface treatment process to produce a semiconductor layer 31 (FIG. 16G). Next, the manufacturing equipment removes the polysilicon film 42 and the insulating film 43 by wet removal to form a trench TH2 (FIG. 16H). Next, the manufacturing equipment deposits a fixed charge film 33 in the trench TH2 by the ALD method (FIG. 16H). Thereafter, the manufacturing equipment executes the same process procedures as those shown in FIGS. 9D to 9I.

[0097] 17 is a partial vertical cross-sectional view of a pixel separator 40C according to a third embodiment of the present disclosure. In Fig. 17, the same parts as those in Fig. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted. A photo-detecting device 1C according to the third embodiment of the present disclosure includes a pixel separator 40C.

[0098] In the third embodiment, an insulating film made of aluminum oxide (Al2O3) or silicon nitride (SiN) is used for the sealing film 70 in the pixel separation section 40C. According to the structure of the third embodiment, by using aluminum oxide (Al2O3) or aluminum oxide (Al2O3) + silicon nitride (SiN) for the sealing film 70, fluorine (F) can be confined at the silicon (Si) interface, thereby inactivating interface traps. Furthermore, aluminum oxide (Al2O3) has a fixed charge, and holes are induced near the pixel separation section 40C, and electrons generated by surface recombination annihilate with the holes, thereby suppressing the generation of dark current.

[0099] <Fourth embodiment> Fig. 18 is a partial vertical cross-sectional view of a pixel separator 40D according to a fourth embodiment of the present disclosure. In Fig. 18, the same parts as those in Fig. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted. A photodetection device 1D according to the fourth embodiment of the present disclosure includes a pixel separator 40D.

[0100] In the fourth embodiment, in the pixel separation section 40D, an insulating film made of aluminum oxide (Al2O3) or silicon nitride (SiN) is used as the sealing film 70. Also in the fourth embodiment, a conductive metal oxide film, here a transparent electrode (LaO) 71 (an example of a conductive material), is deposited between the filling film 61 and the sealing film 70 in the pixel separation section 40D.

[0101] The transparent electrode 71 is connected to a metal electrode (not shown) provided on the first surface S1 (rear surface) of the semiconductor layer 31, and is connected to a mechanism capable of applying a voltage via the metal electrode, so that a negative voltage (for example, −3 V) is applied during operation. This induces holes at the silicon (Si) interface of the pixel separation section 40D, and electrons generated by surface recombination annihilate the holes, thereby suppressing the generation of dark current. Note that the voltage applied to the transparent electrode 71 may be 0 V.

[0102] Fifth Embodiment Fig. 19 is a partial longitudinal cross-sectional view showing an example of a semiconductor structure of a photodetector 1E according to a fifth embodiment of the present disclosure. In Fig. 19, the same components as those in Fig. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. Here, the pixel 110 refers to a semiconductor structure configured to function as a SPAD (Single Photon Avalanche Diode). The SPAD is a photoelectric conversion unit that detects incident light (photons), converts the carriers generated thereby into an electrical signal using avalanche multiplication, and outputs the electrical signal.

[0103] 19, the semiconductor structure 30E of the photodetector 1E is an LSI chip in which a first semiconductor substrate 30-1 and a second semiconductor substrate 30-2 including a logic substrate and the like are bonded together. The dotted line C in Fig. 19 indicates the bonding surface between the first semiconductor substrate 30-1 and the second semiconductor substrate 30-2. The first semiconductor substrate 30-1 and the second semiconductor substrate 30-2 are electrically connected via contacts made of, for example, copper (Cu).

[0104] The first semiconductor substrate 30-1 generally includes, for example, a silicon single crystal semiconductor layer 31-1 (an example of a semiconductor substrate), a wiring layer 32-1, a planar film 33-1, and an on-chip lens 37. The planar film 33-1 and the on-chip lens 37 are stacked in this order on a first surface S1, which is the light incident surface of the semiconductor layer 31-1. The wiring layer 32-1 is stacked on a second surface S2 of the semiconductor layer 31-1.

[0105] The semiconductor layer 31-1 includes a semiconductor region 1111 that constitutes each pixel 110, that is, a photoelectric conversion unit. The semiconductor region 1111 is a region where various electronic elements such as SPADs and transistors are formed, and is covered with, for example, a p-type hole accumulation layer 1112.

[0106] A p-type multiplication region 1113 with a controlled impurity concentration and an n-type cathode region 1114 joined thereto are formed in the semiconductor region 1111. In this example, the multiplication region 1113 is located on the first surface S1 side where external light is incident, and the cathode region 1114 is located on the wiring layer 32-1 side.

[0107] A p++ diffusion region 1115 is formed in the semiconductor layer 31-1 near the wiring layer 32-1 so as to surround the outer periphery of the semiconductor region 1111. The p++ diffusion region 1115 is electrically connected to a first wiring pattern 1116 formed in the wiring layer 32-1 via a contact electrode. Meanwhile, the cathode region 1114 is electrically connected to a second wiring pattern 1118 formed in the wiring layer 32-1 via a cathode electrode 1117. In this example, the first wiring pattern 1116 is an anode power supply wiring pattern, and the second wiring pattern 1118 is a cathode power supply wiring pattern.

[0108] Therefore, by applying a predetermined voltage between the multiplication region 1113 and the cathode region 1114 , an avalanche multiplication region is formed in the junction region between the multiplication region 1113 and the cathode region 1114 .

[0109] A pixel separating section 40E is formed in the semiconductor layer 31-1 to separate the pixels 110. The pixel separating section 40E has a trench structure formed by, for example, an etching process, and extends in the thickness direction of the semiconductor layer 31-1, that is, in the direction indicated by the arrow Z in Fig. 19. In the fifth embodiment of the present disclosure, the pixel separating section 40E is formed by an insulating film 81 that extends from the first surface S1 to the second surface S2 of the semiconductor layer 31.

[0110] In the fifth embodiment of the present disclosure, the pixel separation unit 40E is provided with an F-diffused Si layer 82 between the insulating film 81 and the hole accumulation layer 1112, i.e., between the silicon (Si) and the insulating film 81, which supplies fluorine (F) as a halogen for suppressing dark current. Furthermore, in the fifth embodiment of the present disclosure, a sealing film 83 made of silicon nitride (SiN) is provided between the insulating film 81 and the F-diffused Si layer 82 to seal in fluorine (F) diffusing from the F-diffused Si layer 82 in directions other than toward the silicon (Si).

[0111] <Operation and Effects of Fifth Embodiment> As described above, according to the fifth embodiment, it is possible to reduce the leakage current generated at the separation interface of the pixel separation section 40E, and to achieve a reduction in the dark current rate (DCR).

[0112] 20 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector 1F according to a sixth embodiment of the present disclosure. In Fig. 20, the same parts as those in Fig. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, the pixel 110 refers to a semiconductor structure configured to function as a gate iToF.

[0113] In a sixth embodiment of the present disclosure, a p-well 312 formed in a semiconductor layer 31 of a semiconductor structure 30F is provided with, for example, a gate electrode 322-1 of a first transfer transistor TR1, a gate electrode 322-2 of a second transfer transistor TR2, a first charge retention region FD1, and a second charge retention region FD2. The photodetector 1F includes a first transfer transistor TR1 and a second transfer transistor TR2 for a photoelectric conversion unit 23 provided in each pixel 110, and is configured to be able to distribute charges (electrons) generated by photoelectric conversion in the photoelectric conversion unit 23 to the first charge retention region FD1 and the second charge retention region FD2. The first transfer transistor TR1 is electrically connected to the first charge retention region FD1 via metal wiring 321 of a wiring layer 32. The second transfer transistor TR2 is electrically connected to the second charge retention region FD2 via metal wiring 321 of the wiring layer 32.

[0114] The photodetector 1F according to the sixth embodiment of the present disclosure alternately transfers electrons stored in the photodiode PD, i.e., the photoelectric conversion unit 23, to the first charge holding region FD1 and the second charge holding region FD2 by alternately applying pulses to the gate electrode 322-1 of the first transfer transistor TR1 and the gate electrode 322-2 of the second transfer transistor TR2.

[0115] Fig. 21 is an example of a partial cross-sectional view in which the region of the dotted line B2 of the pixel separating portion 40F shown in Fig. 20 is enlarged. In Fig. 21, the same parts as those in Fig. 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0116] In the pixel separation unit 40F according to the sixth embodiment of the present disclosure, an F-diffused Si layer 63 is provided between the insulating film 62 and the p-well 312, that is, in the silicon (Si), to supply fluorine (F), which serves as a halogen for suppressing dark current. Furthermore, in the sixth embodiment of the present disclosure, a sealing film 64 made of titanium nitride (TiN) is provided between the filling film 61 and the insulating film 62 to seal fluorine (F) that permeates from the F-diffused Si layer 63 through the insulating film 62. In other words, fluorine (F) that diffuses from the F-diffused Si layer 63 in directions other than the p-well 312 is sealed.

[0117] <Operation and Effects of Sixth Embodiment> As described above, according to the sixth embodiment, it is possible to reduce dark signals caused by leakage currents occurring at the interfaces of the pixel separating section 40F, thereby improving distance measurement accuracy.

[0118] 22 is a partial longitudinal cross-sectional view showing an example of a semiconductor structure of a photodetector 1G according to a seventh embodiment of the present disclosure. The photodetector 1G functions as an organic sensor. As shown in the figure, the semiconductor structure 30G is generally configured to include, for example, a silicon single crystal semiconductor layer 1310 (an example of a semiconductor substrate), a wiring layer 1320, an insulating film 1330, and an on-chip lens 1340.

[0119] An insulating film 1330 and an on-chip lens 1340 are laminated in this order on a first surface S1, which is a light incident surface of the semiconductor layer 1310. On a second surface S2 of the semiconductor layer 1310, a wiring layer 1320 is laminated.

[0120] The on-chip lens 1340 is an optical lens for efficiently collecting light incident on the photodetector 1G from the outside and forming an image on each pixel 110 of the semiconductor layer 1310. The on-chip lens 1340 also serves as a planarizing layer.

[0121] B (blue) filters 1331 and G (green) filters 1332 are alternately provided in the insulating film 1330. The B filters 1331 transmit blue light wavelengths out of the light collected by the on-chip lens 1340. The G filters 1332 transmit green light wavelengths out of the light collected by the on-chip lens 1340.

[0122] The semiconductor layer 1310 has an n-type layer 1311-1 and a p-well 1311-2 on the second surface S2 side, which is the front surface, that constitutes a photodiode PD, which is an inorganic photoelectric conversion unit 1311 (an example of a second photoelectric conversion unit). Furthermore, the p-well 1311-2 of the semiconductor layer 1310 is provided with, for example, a gate electrode 322-1 of a first transfer transistor TR1, a gate electrode 322-2 of a second transfer transistor TR2, a first charge retention region FD1, and a second charge retention region FD2. The photodetector 1G includes, for example, a first transfer transistor TR1-1 and a second transfer transistor TR2-1 for the inorganic photoelectric conversion unit 1311 provided in each pixel 110, and is configured to be able to distribute charge (electrons) generated by photoelectric conversion in the inorganic photoelectric conversion unit 1311 to the first charge retention region FD1-1 and the second charge retention region FD2-1. The first transfer transistor TR1-1 is electrically connected to the first charge retention region FD1-1 via a metal wiring 1321 of the wiring layer 1320. The second transfer transistor TR2-1 is electrically connected to the second charge retention region FD2-1 via a metal wiring 1321 of the wiring layer 1320.

[0123] An organic photoelectric conversion unit 1312 (an example of a first photoelectric conversion unit) is provided on the first surface S1 side, which is the back surface, of the semiconductor layer 1310. Furthermore, an IR pass filter 1313 is provided on the semiconductor layer 1310 between the inorganic photoelectric conversion unit 1311 and the organic photoelectric conversion unit 1312 in the vertical direction (the direction indicated by arrow Z in FIG. 22 ).

[0124] The organic photoelectric conversion unit 1312 generates an amount of charge according to the intensity of blue light incident through the on-chip lens 37 and the B filter 1331, converts this into an electrical signal, and outputs it as a pixel signal. The organic photoelectric conversion unit 1312 also generates an amount of charge according to the intensity of green light incident through the on-chip lens 37 and the G filter 1332, converts this into an electrical signal, and outputs it as a pixel signal.

[0125] The IR pass filter 1313 transmits red light or IR light wavelengths from the light collected by the on-chip lens 1340. The n-type layer 1311-1 of the inorganic photoelectric conversion unit 1311 generates an amount of charge according to the intensity of the red light or IR (infrared) light incident via the on-chip lens 1340 and the IR pass filter 1313, converts this into an electrical signal, and outputs it as a pixel signal.

[0126] The semiconductor layer 31 is provided with a through via 1350 that electrically separates adjacent pixels 110. The through via 1350 is configured with a conductor 1351 made of, for example, metal, and extends in the thickness direction of the semiconductor layer 1310, that is, in the direction indicated by the arrow Z in FIG. 22 , with one end connected to the organic photoelectric conversion unit 1312. The other end of the through via 1350 is connected to a metal wiring 1321 of the wiring layer 1320. This allows the photodetector 1G to efficiently transfer charges generated in the organic photoelectric conversion unit 1312 on the first surface S1 side of the semiconductor layer 1310 to the second surface S2 side of the semiconductor layer 1310 via the through via 1350, thereby improving the characteristics.

[0127] Fig. 23 is an example of an enlarged partial cross-sectional view of the region indicated by the dotted line D in the through via 1350 shown in Fig. 22. In Fig. 23, the sidewall of the conductor 1351 is covered with an insulating film 1352 made of SiOF. Note that the insulating film 1352 may be made of silicon oxide (SiO2) or a laminated film of silicon oxide (SiO2) and SiOF.

[0128] In the seventh embodiment of the present disclosure, an F-diffused Si layer 1353 is provided between the insulating film 1352 and the p-well 1311-2, that is, in silicon (Si), to supply fluorine (F), which serves as a halogen for suppressing dark current. Furthermore, in the seventh embodiment of the present disclosure, a sealing film 1354 (an example of a sealing region) is provided between the conductor 1351 and the insulating film 1352 to seal fluorine (F) that permeates from the F-diffused Si layer 1353 through the insulating film 1352. In other words, fluorine (F) that diffuses from the F-diffused Si layer 1353 in directions other than those toward the p-well 1311-2 is sealed.

[0129] The sealing film 1354 is composed of a titanium nitride (TiN) film 1355 arranged on the conductor 1351 side, an insulating film 1356 made of silicon oxide (SiO2) covering the titanium nitride film 1355, and an aluminum oxide (Al2O3) film 1357 arranged between the insulating film 1356 and the insulating film 1352.

[0130] According to the structure of the seventh embodiment of the present disclosure, traps at the interface with the through via 1350 can be inactivated by fluorine (F), thereby suppressing the generation of dark current caused by interfacial recombination.

[0131] <Effects of Seventh Embodiment> Previously, dark current generated by traps at the silicon (Si) interface of the through via 1350 was erroneously detected as a dark signal in the photodiode PD in the semiconductor layer 1310. Therefore, in the seventh embodiment, by providing the through via 1350 with an F-diffused Si layer 1353 and a sealing film 1354, it is possible to suppress the dark current and reduce erroneous detection.

[0132] Eighth Embodiment Figure 24 is a partial vertical cross-sectional view showing an example of a semiconductor structure of a photodetector 1H according to an eighth embodiment of the present disclosure. The photodetector 1H according to the eighth embodiment of the present disclosure is configured as a back-illuminated CMOS image sensor configured by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. That is, the photodetector 1H shown in Figure 24 has a three-layer stacked structure.

[0133] The photodetector 1H is made up of, for example, a first semiconductor substrate on which a sensor circuit is formed, a second semiconductor substrate on which a logic circuit is formed, and a third semiconductor substrate on which a memory circuit is formed. The logic circuit and the memory circuit are each configured to operate in response to input and output of signals from and to the outside.

[0134] As shown in FIG. 24, a photodiode (PD) 234-3 serving as a photoelectric conversion unit of a pixel is formed on a semiconductor substrate (for example, a silicon substrate) 211-3, and the source / drain regions of each pixel transistor are formed in the semiconductor well region.

[0135] A gate electrode is formed on the surface of the substrate constituting the pixel via a gate insulating film, and the gate electrode and a pair of source / drain regions form pixel transistors Tr1-3 and Tr2-3.

[0136] The pixel transistor Tr1-3 adjacent to the photodiode (PD) 234-3 corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD).

[0137] An interlayer insulating film is formed on the first semiconductor substrate 211-3, and connection holes are formed in the interlayer insulating film, and connection conductors 244-3 are formed to connect to the pixel transistors Tr1-3 and Tr2-3.

[0138] Furthermore, a multilayer wiring layer 245-3 is formed by forming multiple layers of metal wiring 240-3 so as to connect to each connecting conductor 244-3. The copper wiring 240-3 (metal wiring) is formed of copper (Cu) wiring. Normally, each copper wiring is covered with a barrier metal film that prevents Cu diffusion. For this reason, a protective film, which is a cap film for the copper wiring, is formed on the multilayer wiring layer 245-3.

[0139] Furthermore, an aluminum pad 280-3 serving as an electrode for external connection is formed on the lowest layer of the multilayer wiring layer 245-3 of the first semiconductor substrate 211-3. That is, the aluminum pad 280-3 is formed at a position closer to the bonding surface 291-3 with the second semiconductor substrate 212-3 than the copper wiring 240-3. This electrode for external connection is used as one end of wiring related to the input and output of signals to and from the outside. Note that, although the electrode is described here as being made of aluminum, the electrode may also be made of other metals.

[0140] Furthermore, a contact 265-3 is formed on the first semiconductor substrate 211-3 to be used for electrical connection with the second semiconductor substrate 212-3. The contact 265-3 is connected to a contact 311-3 of the second semiconductor substrate 212-3 (described later) and is also connected to an aluminum pad 280a-3 of the first semiconductor substrate 211-3.

[0141] A pad hole 351-3 is formed in the first semiconductor substrate 211-3 so as to reach the aluminum pad 280a-3 from the rear surface side (light-receiving surface side) of the first semiconductor substrate 211-3.

[0142] An insulating protective film is formed on the entire back surface of the first semiconductor substrate 211-3, and a light-shielding film is formed on the area to be shielded from light. Also, on-chip color filters 274-3 are formed on the planarization film in correspondence with each pixel, and on-chip microlenses 275-3 are formed on the color filters.

[0143] On the other hand, a logic circuit is formed on the second semiconductor substrate 212-3. That is, a plurality of transistors constituting the logic circuit, namely, MOS transistor Tr6-3, MOS transistor Tr7-3, and MOS transistor Tr8-33, are formed in a p-type semiconductor well region of the semiconductor substrate (e.g., silicon substrate) 212-3.

[0144] In addition, a connecting conductor 254-3 is formed on the second semiconductor substrate 212-3, and is connected to the MOS transistor Tr6-3, the MOS transistor Tr7-3, and the MOS transistor Tr8-3.

[0145] Furthermore, a multilayer wiring layer 255-3 is formed by forming a plurality of layers of metal wiring 250-3 so as to connect to each of the connection conductors 254-3.

[0146] The metal wiring is made of copper (Cu) wiring. A protective film, which is a cap film for the copper wiring (metal wiring) 250-3, is formed on the multi-wiring layer 255-3.

[0147] Furthermore, an aluminum pad 320-3 serving as an electrode is formed on the bottom layer of the multi-layer wiring layer 255-3 of the second semiconductor substrate 212-3.

[0148] Furthermore, the second semiconductor substrate 212-3 is formed with a contact 311-3 used for electrical connection with the first semiconductor substrate 211-3 and the third semiconductor substrate 213-3. The contact 311-3 is connected to the contact 265-3 of the first semiconductor substrate 211-3 and also to the aluminum pad 330a-3 of the third semiconductor substrate 213-3.

[0149] A memory circuit is formed on the third semiconductor substrate 213-3. That is, a plurality of transistors constituting the memory circuit, namely, MOS transistor Tr11-3, MOS transistor Tr12-3, and MOS transistor Tr13-3, are formed in a p-type semiconductor well region of the semiconductor substrate (e.g., silicon substrate) 213-3.

[0150] Furthermore, on the third semiconductor substrate 213-3, a connecting conductor 344-3 is formed which is connected to the MOS transistor Tr11-3, the MOS transistor Tr12-3, and the MOS transistor Tr13-3.

[0151] Furthermore, a multilayer wiring layer 345-3 is formed by forming a plurality of layers of metal wiring 340-3 so as to connect to each of the connection conductors 344-3.

[0152] The metal wiring is made of copper (Cu) wiring. A protective film, which is a cap film for the copper wiring (metal wiring 340-3), is formed on the multi-layer wiring layer 345-3.

[0153] Furthermore, an aluminum pad 330-3 serving as an electrode is formed on the top layer of the multi-wiring layer 345-3.

[0154] The contact 265-3 and the contact 311-3 are provided, so that signals can be input and output to and from each of the first semiconductor substrate 211-3 to the third semiconductor substrate 213-3 via the aluminum pad 280a-3.

[0155] As described above, the photodetector 1H is also configured by bonding the interlayer films of the second semiconductor substrate 212-3 and the third semiconductor substrate 213-3 together at the bonding surface 292-3, and by bonding the interlayer films of the second semiconductor substrate 212-3 and the first semiconductor substrate 211-3 together at the bonding surface 291-3.

[0156] That is, first, the two lower semiconductor substrates are bonded together with their circuit surfaces facing each other, and the second-layer semiconductor substrate (second semiconductor substrate 212-3) is thinned. Then, the topmost semiconductor substrate (first semiconductor substrate 211-3) is bonded as a backside type, stacked, and further thinned. At this time, after planarizing the upper layer of the contact 311-3, the first semiconductor substrate 211-3 is bonded as a backside type to the second semiconductor substrate 212-3.

[0157] By doing so, when stacking circuits, it is not necessary to use a support substrate to thin the silicon substrate.

[0158] In this technology, an aluminum pad 280-3 is also provided on the first semiconductor substrate 211-3. No electrode for external connection is provided on the second semiconductor substrate 212-3 having a logic circuit that requires input and output of signals from the outside, or on the third semiconductor substrate 213-3 having a memory circuit, but an electrode for external connection (aluminum pad 280a-3) is provided on the first semiconductor substrate 211-3 having a sensor circuit.

[0159] In this way, the pad hole 351-3 does not become deep, and the electrode for external connection can be exposed.

[0160] Furthermore, in this technology, an aluminum pad 280-3 is also provided on the first semiconductor substrate 211-3, and the aluminum pad 280-3 can also block light caused by hot carriers emitted from each transistor on the second semiconductor substrate 212-3.

[0161] In this way, with this technology, it is not necessary to provide a deep pad hole, and light caused by hot carriers can be easily blocked.

[0162] 24, the aluminum pad 320-3 is provided on the second semiconductor substrate, and the aluminum pad 330-3 is provided on the third semiconductor substrate 213-3, but the aluminum pad 320-3 and the aluminum pad 330-3 may not be provided. For example, if the contact 311-3 is directly connected to the copper wiring 340-3 of the third semiconductor substrate 213-3, there is no need to provide the aluminum pad 320-3 and the aluminum pad 330-3.

[0163] Furthermore, the shape of the contacts electrically connecting the semiconductor substrates is not limited to those shown as contact 265-3 and contact 311-3. Furthermore, the holes for forming the contacts can be deep holes because they can be opened before the on-chip microlenses are formed. For example, contacts may be provided that penetrate the second semiconductor substrate and connect the copper wiring of the first semiconductor substrate with the copper wiring of the third semiconductor substrate.

[0164] In the eighth embodiment of the present disclosure, an F-diffused Si layer 1410 is provided on at least a portion of the sidewall of the contact 265-3 of the first semiconductor substrate 211-3 on which an insulating film is provided, the F-diffused Si layer 1410 supplying fluorine (F), which serves as a halogen for suppressing dark current in silicon (Si). Furthermore, in the eighth embodiment of the present disclosure, a sealing film 1420 (an example of a sealing region) that is impermeable to fluorine (F), is provided between the contact 265-3 and the F-diffused Si layer 1410 to seal fluorine (F) diffusing from the F-diffused Si layer 1410 in directions other than the silicon (Si) region of the first semiconductor substrate 211-3.

[0165] In the eighth embodiment of the present disclosure, an F-diffused Si layer 1430 is provided on at least a portion of the sidewall of the contact 311-3 of the second semiconductor substrate 212-3 on which the insulating film is provided. Furthermore, in the eighth embodiment of the present disclosure, a sealing film 1440 (an example of a sealing region) that is impermeable to fluorine (F) is provided between the contact 311-3 and the F-diffused Si layer 1430 to seal in fluorine (F) diffusing from the F-diffused Si layer 1430 in directions other than the silicon (Si) region of the second semiconductor substrate 212-3.

[0166] <Effects of the Eighth Embodiment> As described above, according to the eighth embodiment, outward diffusion of fluorine (F) can be prevented at least in the region where the insulating film is provided of the contacts 265-3, 311-3, and effects similar to those of the first embodiment can be obtained.

[0167] <Other Embodiments> As described above, the present technology has been described using the first to eighth embodiments, the first and second modifications of the first embodiment, and the first to sixth modifications of the second embodiment. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Upon understanding the gist of the technical content disclosed in the first to eighth embodiments, it will be clear to those skilled in the art that various alternative embodiments, examples, and operational techniques can be included in the present technology. Furthermore, the configurations disclosed in the first to eighth embodiments, the first and second modifications of the first embodiment, and the first to sixth modifications of the second embodiment can be appropriately combined within a range that does not cause contradictions. For example, configurations disclosed in multiple different embodiments may be combined, or configurations disclosed in multiple different modifications of the same embodiment may be combined.

[0168] <Examples of application to electronic devices> Furthermore, the photodetector device as described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0169] Fig. 25 is a block diagram showing an example of the configuration of an electronic device. As shown in Fig. 25, an electronic device 2010 includes an optical system 2020, a photodetector 2030, and a DSP (Digital Signal Processor) 2040. The DSP 2040, a display device 2050, an operation system 2060, a memory 2080, a recording device 2090, and a power supply system 2100 are connected via a bus 2070, and the electronic device 2010 is capable of capturing still images and moving images.

[0170] The optical system 2020 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 2030 , forming an image on the light receiving surface (sensor section) of the photodetector 2030 .

[0171] Any of the photodetector devices having the above-described configuration examples is applied as the photodetector 2030. Electrons are accumulated in the photodetector 2030 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 2020. A signal corresponding to the electrons accumulated in the photodetector 2030 is then supplied to the DSP 2040.

[0172] The DSP 2040 performs various signal processing on the signal from the photodetector 2030 to acquire an image, and temporarily stores the image data in the memory 2080. The image data stored in the memory 2080 is recorded in the recording device 2090 or supplied to the display device 2050 to display the image. In addition, the operation system 2060 accepts various operations by the user and supplies operation signals to each block of the electronic device 2010, and the power supply system 2100 supplies power necessary to drive each block of the electronic device 2010.

[0173] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0174] Fig. 26 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 26, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0175] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0176] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0177] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0178] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0179] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0180] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0181] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0182] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0183] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 26, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0184] Fig. 27 is a diagram showing an example of the installation position of the image capturing unit 12031. In Fig. 27, a vehicle 12100 has image capturing units 12101, 12102, 12103, 12104, and 12105 as the image capturing unit 12031.

[0185] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0186] 27 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0187] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0188] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0189] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0190] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0191] The present disclosure may also be configured as follows: (1) A photodetector comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate and capable of generating an electrical signal in response to light incident from the first surface; a separation unit having an insulating film formed in a thickness direction from the first surface to the second surface of the semiconductor substrate and separating adjacent photoelectric conversion units; an impurity diffusion region formed between the photoelectric conversion units and the insulating film and containing an impurity for suppressing dark current; and a sealing region for sealing impurities diffusing from the impurity diffusion region in directions other than at least toward the photoelectric conversion units. (2) The photodetector according to (1), wherein the impurity is a halogen. (3) The photodetector according to (1), wherein the separation unit is formed from the first surface to the second surface. (4) The photodetector according to (1), wherein the separation unit is formed partway between the first surface and the second surface. (5) The photodetector according to (1), wherein the separation portion is formed partway from the second surface to the first surface. (6) The photodetector according to (2), wherein the material of the semiconductor substrate is silicon, and the halogen is fluorine (F). (7) The photodetector according to (6), wherein the insulating film has one of a silicon oxide (SiO2) film, a SiOF film, and a SiO2+SiOF stacked film. (8) The photodetector according to (6), wherein the sealing region is a silicon nitride (SiN) film. (9) The photodetector according to (8), wherein the silicon nitride (SiN) film is provided only on a surface parallel to a sidewall of the separation portion. (10) The photodetector according to (1), wherein the separation portion has a conductor. (11) The photodetector according to (10), wherein the conductor is a polysilicon film. (12) The photodetector according to (10), wherein the conductor is connected to a voltage applying mechanism, and 0 V or a negative voltage is applied from the mechanism during operation. (13) The photodetector according to (6), wherein the sealing region is a titanium nitride (TiN) film.(14) The photodetector according to (13), wherein the titanium nitride (TiN) film is connected to a voltage application mechanism and receives 0 V or a negative voltage from the mechanism during operation. (15) The photodetector according to (6), wherein the sealing region is an aluminum oxide (Al2O3) film or a silicon nitride (SiN) film. (16) The photodetector according to (15), wherein a conductive material made of a metal or a metal compound is provided between the isolation section and the aluminum oxide (Al2O3) film, and the conductive material is connected to a voltage application mechanism and receives 0 V or a negative voltage from the mechanism during operation. (17) The photodetector according to (1), wherein the photoelectric conversion section is a photodiode. (18) The photodetector according to (1), wherein the photoelectric conversion section is a SPAD. (19) The photodetector according to (1), wherein the photoelectric conversion section is a gate iToF. (20) A photodetector comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a first photoelectric conversion unit disposed on the first surface side of the semiconductor substrate and capable of generating an electrical signal in response to first light incident from the first surface; a second photoelectric conversion unit disposed on the second surface side of the semiconductor substrate and capable of generating an electrical signal in response to second light having a wavelength range different from that of the first light; a through via that penetrates the semiconductor substrate from the second surface of the semiconductor substrate to the first photoelectric conversion unit, has a sidewall covered with an insulating film, and transmits the electrical signal generated in the first photoelectric conversion unit to the second surface side; an impurity diffusion region that is formed between the first photoelectric conversion unit or the second photoelectric conversion unit and the insulating film and contains impurities for suppressing dark current; and a sealing region that seals off impurities that diffuse from the impurity diffusion region in at least directions other than those toward the first photoelectric conversion unit or the second photoelectric conversion unit. (21) The photodetector according to (20), wherein the semiconductor substrate is made of silicon, and the impurity is fluorine (F).(22) An electronic device comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate and capable of generating an electric signal in response to light incident from the first surface; a separation unit having an insulating film formed in a thickness direction from the first surface toward the second surface of the semiconductor substrate and separating adjacent photoelectric conversion units; an impurity diffusion region formed between the photoelectric conversion units and the insulating film and containing impurities for suppressing dark current; and a sealing region for sealing impurities diffusing from the impurity diffusion region in at least a direction other than toward the photoelectric conversion units.

[0192] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H Photodetector device 11 Pixel array section 12 Vertical drive section 13 Column processing section 14 Horizontal drive section 15 System control section 16 Signal processing section 17 Data storage section 18 Pixel drive line 19 Vertical signal line 21 Photoelectric conversion region 22 Pixel circuit (readout circuit) 22 Pixel circuit 23 Photoelectric conversion section 30-1 First semiconductor substrate 30-2 Second semiconductor substrate 30A, 30B, 30E, 30F, 30G Semiconductor structure 31, 31-1 Semiconductor layer 32, 32-1 Wiring layer 33 Fixed charge film 33-1 Planarization film 34 Anti-reflection film 35, 41, 43, 53, 61-1, 61-3, 62, 65, 67, 81 Insulating film 36 Color filter 37 On-chip lens 38 Low-flexural-index spacer 40A, 40A1, 40A2, 40B, 40B1, 40B2, 40B3, 40B4, 40B5, 40B6, 40C, 40D, 40E, 40F Pixel separation section 42 Polysilicon film 44, 63, 82 F-diffused Si layer 45, 64, 70, 83 Sealing film 51 Silicon semiconductor substrate 51a Inner wall 52 Silicon oxide (SiO2) film 61 Buried film 61-2 Thin film metal 66 Aluminum oxide (Al2O3) film 68 High-dielectric film 69 P-type diffusion layer 71 Transparent electrode 83 Sealing film 110 Pixel 211-3 First semiconductor substrate 212-3 Second semiconductor substrate 213-3 Third semiconductor substrate 234-3 Photodiode (PD) 240-3 Metal wiring 244-3 Connecting conductor 245-3 Multilayer wiring layer 250-3 Metal wiring 254-3 Connecting conductor 255-3 Multilayer wiring layer 265-3 Contact 274-3 On-chip color filter 275-3 On-chip microlens 280-3 Aluminum pad 280a Aluminum pad 280a-3 Aluminum pad 291-3 Bonding surface 311 N-type layer 311-3 Contact 312 P-well 320-3 Aluminum pad 321 Metal wiring 322, 322-1,322-2 Gate electrode 323 Metal electrode 330a-3 Aluminum pad 340-3 Metal wiring 344-3 Connecting conductor 345-3 Multilayer wiring layer 351-3 Pad hole 1111 Semiconductor region 1112 Hole accumulation layer 1113 Multiplication region 1114 Cathode region 1115 Diffusion region 1116 First wiring pattern 1117 Cathode electrode 1118 Second wiring pattern 1310 Semiconductor layer 1311 Inorganic photoelectric conversion section 1311-1 n-type layer 1311-2 p-well 1312 Organic photoelectric conversion section 1313 IR pass filter 1320 Wiring layer 1321 Metal wiring 1330 Insulating film 1331 B filter 1332 G filter 1340 On-chip lens 1350 Through via 1351 Conductor 1352 Insulating film 1353 F-diffused Si layer 1354 Sealing film 1355, 1357 Film 1355 Titanium nitride film 1356 Insulating film 2010 Electronic device 2020 Optical system 2030 Photodetector 2040 DSP 2050 Display device 2060 Operation system 2070 Bus 2080 Memory 2090 Recording device 2100 Power supply system 12000 Vehicle control system 12001 Communication network 12010 Drive system control unit 12020 Body system control unit 12030 Outside vehicle information detection unit 12040 Inside vehicle information detection unit 12041 Driver state detection unit 12050 Integrated control unit 12051 Microcomputer 12052 Audio / image output unit 12061 Audio speaker 12062 Display unit 12063 Instrument panel 12100 Vehicle 12101, 12102, 12103, 12104, 12105 Imaging unit 12111, 12112, 12113, 12114 Imaging range,

Claims

1. A photodetector comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate and capable of generating an electrical signal in response to light incident from the first surface; a separation unit having an insulating film formed in the thickness direction from the first surface toward the second surface of the semiconductor substrate and separating adjacent photoelectric conversion units; an impurity diffusion region formed between the photoelectric conversion units and the insulating film and containing impurities for suppressing dark current; and a sealing region for sealing off impurities diffusing from the impurity diffusion region in at least a direction other than toward the photoelectric conversion units.

2. The photodetector device of claim 1, wherein the impurity is a halogen.

3. The photodetector device according to claim 1, wherein the separation section is formed from the first surface to the second surface.

4. The photodetector according to claim 1, wherein the separation section is formed partway from the first surface to the second surface.

5. The photodetector according to claim 1, wherein the separation section is formed partway from the second surface to the first surface.

6. The photodetector device according to claim 2, wherein the material of the semiconductor substrate is silicon, and the halogen is fluorine (F).

7. The photodetector according to claim 6, wherein the insulating film comprises one of a silicon oxide (SiO2) film, a SiOF film, and a SiO2+SiOF laminated film.

8. The photodetector device according to claim 6, wherein the sealing region is a silicon nitride (SiN) film.

9. The photodetector according to claim 8, wherein the silicon nitride (SiN) film is provided only on a surface parallel to a sidewall of the isolation portion.

10. The photodetector device according to claim 1, wherein the separator comprises a conductor.

11. The photodetector device according to claim 10, wherein the conductor is a polysilicon film.

12. The photodetector device according to claim 10, wherein the conductor is connected to a mechanism for applying a voltage, and 0 V or a negative voltage is applied from the mechanism during operation.

13. The photodetector device according to claim 6, wherein the sealing region is a titanium nitride (TiN) film.

14. The photodetector device according to claim 13, wherein the titanium nitride (TiN) film is connected to a mechanism for applying a voltage, and 0 V or a negative voltage is applied to the titanium nitride (TiN) film from the mechanism during operation.

15. The photodetector device according to claim 6, wherein the sealing region is an aluminum oxide (Al2O3) film or a silicon nitride (SiN) film.

16. The photodetector device according to claim 15, further comprising a conductive material made of a metal or metal compound between the separation section and the aluminum oxide (Al2O3) film, the conductive material being connected to a mechanism for applying a voltage, and receiving 0 V or a negative voltage from the mechanism during operation.

17. The photodetector according to claim 1, wherein the photoelectric conversion section is a photodiode.

18. The photodetector according to claim 1, wherein the photoelectric conversion unit is a SPAD.

19. The photodetector according to claim 1, wherein the photoelectric conversion unit is a gate iToF.

20. A photodetector comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a first photoelectric conversion unit arranged on the first surface side of the semiconductor substrate and capable of generating an electrical signal in response to first light incident from the first surface; a second photoelectric conversion unit arranged on the second surface side of the semiconductor substrate and capable of generating an electrical signal in response to second light having a wavelength range different from that of the first light; a through via that penetrates the semiconductor substrate from the second surface to the first photoelectric conversion unit, has a sidewall covered with an insulating film, and transmits the electrical signal generated in the first photoelectric conversion unit to the second surface side; an impurity diffusion region formed between the first photoelectric conversion unit or the second photoelectric conversion unit and the insulating film, and containing impurities for suppressing dark current; and a sealing region that seals off impurities that diffuse from the impurity diffusion region in at least directions other than toward the first photoelectric conversion unit or the second photoelectric conversion unit.

21. The photodetector device according to claim 20, wherein the material of the semiconductor substrate is silicon, and the impurity is fluorine (F).

22. An electronic device comprising a photodetector including: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate and capable of generating an electrical signal in response to light incident from the first surface; a separation unit having an insulating film formed in the thickness direction from the first surface toward the second surface of the semiconductor substrate and separating adjacent photoelectric conversion units; an impurity diffusion region formed between the photoelectric conversion units and the insulating film and containing impurities for suppressing dark current; and a sealing region for sealing off impurities diffusing from the impurity diffusion region in at least a direction other than toward the photoelectric conversion units.

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