Light detection device

Abstract

The present invention reduces wiring volume. A light detection device according to the present technology comprises a pixel array unit in which a plurality of pixels are arranged in an array in plan view. The pixel array unit includes first and second pixels lined up adjacent to each other in one direction in plan view. The first pixels each include a first photoelectric conversion unit, a first charge-holding unit for holding a signal charge photoelectrically converted by the first photoelectric conversion unit, and a first pixel transistor including a gate electrode and a pair of main electrode regions. The second pixels each include a second photoelectric conversion unit, a second charge-holding unit for holding a signal charge photoelectrically converted by the second photoelectric conversion unit, and a second pixel transistor including a gate electrode and a pair of main electrode regions. The respective pairs of main electrode regions of the first and second pixel transistors are lined up in the one direction, and the first charge-holding unit, the first transistor, the second transistor, and the second charge-holding unit are lined up in the stated order in the one direction.

Description

Photodetector

[0001] The present technology (technology according to the present disclosure) relates to a photodetector, and in particular to a technology that is effective when applied to a photodetector having pixel transistors provided in a photoelectric conversion region.

[0002] Photodetection devices such as solid-state imaging devices and distance measuring devices include a charge holding section that holds signal charges photoelectrically converted by the photoelectric conversion section of a pixel, and a readout circuit that reads out the signal charges held in the charge holding section and outputs a pixel signal based on the readout signal charges.

[0003] Japanese Patent Application Laid-Open No. 2003-124222 discloses a shared circuit configuration in which a single readout circuit is shared by the charge holding sections of a plurality of pixels.

[0004] WO2022 / 209681

[0005] In recent years, the market has demanded high-resolution image sensors, and the development of image sensors with reduced pixel size is progressing. In image sensors with relatively small pixel sizes, the parasitic wiring capacitance of the wiring affects image quality performance. A shared circuit configuration in which one readout circuit is shared by each charge storage unit of multiple pixels can reduce wiring capacitance, but further reduction in wiring capacitance is desired.

[0006] Therefore, the present engineers focused on the arrangement of pixel transistors included in the readout circuit and developed the present technology.

[0007] An object of the present technology is to provide a technology that can reduce wiring capacitance.

[0008] (1) A photodetector according to one aspect of the present technology includes a pixel array unit in which a plurality of pixels are arranged in an array in a plan view. The pixel array unit includes first and second pixels arranged adjacent to each other in one direction in a plan view. The first pixel includes a first photoelectric conversion unit, a first charge retention unit configured to retain signal charges photoelectrically converted by the first photoelectric conversion unit, and a first pixel transistor including a gate electrode and a pair of main electrode regions. The second pixel includes a second photoelectric conversion unit, a second charge retention unit configured to retain signal charges photoelectrically converted by the second photoelectric conversion unit, and a second pixel transistor including a gate electrode and a pair of main electrode regions. The pair of main electrode regions of each of the first and second pixel transistors are arranged in the one direction, and the first charge retention unit, the first transistor, the second transistor, and the second charge retention unit are arranged in this order in the one direction.

[0009] (2) A photodetector according to another aspect of the present technology includes a first charge retention portion, a first pixel transistor, a second pixel transistor, and a second charge retention portion, which are arranged in this order in one direction on a semiconductor layer, each of the first and second pixel transistors including a gate electrode and a pair of main electrode regions, and the pair of main electrode regions of each of the first and second pixel transistors are aligned in one direction.

[0010] (3) A photodetector according to another aspect of the present technology includes a pixel array section in which a plurality of pixels are arranged in an array in a planar view, the pixel array section including first and second pixels arranged adjacent to each other in a first direction in a planar view, the first pixel having a first photoelectric conversion section, a second photoelectric conversion section, a first charge retention section, a second charge retention section, a first pixel transistor, and a second pixel transistor, the second pixel having a third photoelectric conversion section, a fourth photoelectric conversion section, the third charge retention section, a fourth charge retention section, a third pixel transistor, and a fourth pixel transistor, the first pixel and the second pixel belonging to different pixel sharing units, source / drain regions of the first and third pixel transistors being arranged in the first direction, and the first charge retention section, the first pixel transistor, the third pixel transistor, and the third charge retention section being arranged in this order in the first direction.

[0011] 5A is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 6 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present technology. FIG. 7 is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit of the solid-state imaging device according to the first embodiment of the present technology. FIG. 8 is a plan view schematically showing a configuration example of a pixel block included in the pixel array unit of FIG. 1. FIG. 9 is an enlarged plan view of a main part obtained by enlarging a part of FIG. 4. FIG. 10 is an enlarged plan view of a main part obtained by enlarging a part of FIG. 1. FIG. 11 is an enlarged plan view of a main part obtained by enlarging a part of FIG. 5A. FIG. 5B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a5-a5 cutting line of FIG. 5A. FIG. 5C is a longitudinal sectional view schematically showing a connection state by wiring of FIG. 4. FIG. 6D is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit of a solid-state imaging device according to a second embodiment of the present technology. FIG. 7E is a plan view schematically showing a configuration example of a pixel block and a readout circuit of a solid-state imaging device according to the second embodiment of the present technology. FIG. 8F is an equivalent circuit diagram showing a pixel block and a readout circuit, illustrating a modification 2-1 according to the second embodiment of the present technology. FIG. 8G is an equivalent circuit diagram showing a pixel block and a readout circuit, illustrating a modification 2-1 according to the second embodiment of the present technology. 10 is a diagram showing a modified example 2-2 according to the second embodiment of the present technology and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 10 is a diagram showing a modified example 2-2 according to the second embodiment of the present technology and is a plan view schematically showing the pixel block. FIG. 10 is a diagram showing a modified example 2-3 according to the second embodiment of the present technology and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 10 is a diagram showing a modified example 2-3 according to the second embodiment of the present technology and is a plan view schematically showing the pixel block. FIG. 10 is a diagram showing a modified example 2-4 according to the second embodiment of the present technology and is a plan view schematically showing the pixel block. FIG. 10 is a diagram showing a modified example 2-5 according to the second embodiment of the present technology and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 10 is a diagram showing a modified example 2-5 according to the second embodiment of the present technology and is a plan view schematically showing the pixel block. FIG. 10 is a diagram showing a modified example 2-6 according to the second embodiment of the present technology and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 10 is a diagram showing a modified example 2-6 according to the second embodiment of the present technology and is a plan view schematically showing the pixel block. FIG. 10 is a diagram showing a modified example 2-7 according to the second embodiment of the present technology and is a plan view schematically showing the pixel block.Fig. 2 is a diagram showing a modified example 2-8 according to a second embodiment of the present technology and is a plan view schematically showing a pixel block. Fig. 3 is a diagram showing a modified example 2-9 according to the second embodiment of the present technology and is a plan view schematically showing a pixel block. Fig. 4 is a diagram showing a modified example 2-10 according to the second embodiment of the present technology and is a plan view schematically showing a pixel block. Fig. 5 is a diagram showing a schematic configuration of an electronic device according to a third embodiment of the present technology.

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0013] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0014] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0016] In addition, in the following embodiments, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type as the conductivity type of the semiconductor, but the conductivity types may be selected in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type.

[0017] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is referred to as the Z direction. In the following embodiments, the direction indicating the thickness of a semiconductor layer 21 (described later) will be described as the Z direction. In the following embodiments, the Y direction will be described as "one direction" of the present technology.

[0018] In the following embodiments, a plan view refers to a case where the semiconductor layer 21 is viewed from the Z direction, and a cross-sectional view refers to a case where a cross section along the Z direction is viewed from a direction perpendicular to the cross section (Z direction).

[0019] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. Also, in this first embodiment, the solid-state imaging device will be described having a circuit configuration in which a readout circuit is assigned to each pixel block (pixel unit) with eight pixels as one unit.

[0020] FIG. 1 is a chip layout diagram showing an example of a configuration of a solid-state imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example of a configuration of a solid-state imaging device according to the first embodiment of the present technology. FIG. 3 is an equivalent circuit diagram showing an example of a configuration of a pixel block and a readout circuit according to the first embodiment of the present technology. FIG. 4 is a plan view schematically showing an example of a configuration of a pixel block included in the pixel array unit of FIG. 1. FIG. 5A is a plan view of a main part enlarged from a part of FIG. 1 (a first shared pixel block of a first pixel block). FIG. 5B is a plan view of a main part enlarged from a part of FIG. 1 (a second shared pixel block of a first pixel block). FIG. 5C is a plan view of a main part enlarged from a part of FIG. 1 (a part of a second shared pixel block of a second pixel block). FIG. 6 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a5-a5 cutting line of FIG. 5A. FIG. 7 is a longitudinal cross-sectional view schematically showing a connection state by the wiring of FIG. 4.

[0021] 4, in order to make the drawing easier to understand, a multilayer wiring layer 61, which will be described later, is not shown. Also, while Fig. 1 is a plan view of the semiconductor chip 2 as seen from its light incident surface side, Fig. 4 is a plan view of the semiconductor chip 2 as seen from the opposite side to the light incident surface side (the multilayer wiring layer side).

[0022] <<Overall Configuration of Solid-State Imaging Device>> First, the overall configuration of a solid-state imaging device 1A will be described with reference to FIGS. 1 to 4. FIG.

[0023] 1, a solid-state imaging device 1A according to a first embodiment of the present technology is mainly configured with a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in FIG. 25, this solid-state imaging device 1A (101) takes in image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0024] As shown in FIG. 1 , a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including mutually orthogonal X and Y directions, a rectangular pixel array section 2A provided in the center and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (see FIG. 5 ) described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0025] The solid-state imaging device 1A may be packaged in various types of packages and then mounted on an electronic device, or may be mounted directly on an electronic device in the form of a chip.

[0026] The pixel array unit 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 25. The pixel array unit 2A has a plurality of pixels (sensor pixels) 3 arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0027] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device. Although not shown, a connecting member such as a bonding wire or a bump electrode is connected to the bonding pad 14.

[0028] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0029] 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via vertical signal lines 11.

[0030] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0031] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0032] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0033] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0034] <Pixel Block> The semiconductor chip 2 includes a pixel block 15A and a readout circuit (pixel circuit) 17A shown in FIG.

[0035] 3 and 4, the pixel block 15A includes a plurality of pixels 3. Although not limited to this, the pixel block 15A of the first embodiment may include, for example, two shared pixel blocks 16A (first and second shared pixel blocks 16A) arranged adjacent to each other in the Y direction in a plan view, as shown in FIG. １ , 16A ２ ) and the first shared pixel block 16A１ The second shared pixel block 16A includes, as one unit, four pixels 3 (3a, 3b, 3c, 3d) arranged two by two in a 2×2 arrangement in the X direction and the Y direction in a plan view, and ２ Each pixel block 15A includes four pixels 3 (3e, 3f, 3g, 3h) arranged two by two in a 2×2 arrangement in the X and Y directions in plan view as one unit. That is, the pixel block 15A of the first embodiment includes eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h) arranged two by two in a 2×4 arrangement. In FIG. 4, two pixel blocks 15A (15A １ and 15A ２ 1 is illustrated, the pixel blocks 15A are repeatedly arranged in both the X direction and the Y direction to form the pixel array section 2A shown in Fig. 1. That is, in the pixel array section 2A, pixel blocks 15A each including eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h) arranged in a 2 x 4 pattern are repeatedly arranged in both the X direction and the Y direction.

[0036] 3 , each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in one pixel block 15A has common components. Specifically, each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in one pixel block 15A includes a photoelectric conversion unit 25 that photoelectrically converts light into signal charges, a floating diffusion region FD serving as a charge storage unit that stores (accumulates) the signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD.

[0037] Each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in one pixel block 15A further includes a photoelectric conversion region 22 of a semiconductor layer 21 shown in Fig. 6. Each of the photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR is provided in the photoelectric conversion region 22 of the semiconductor layer 21, as shown in Fig. 6. Fig. 6 illustrates two pixels 3a and 3b out of the eight pixels 3 included in one pixel block 15A.

[0038] 3 is configured, for example, by a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge. The cathode side of the photoelectric conversion unit 25 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

[0039] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0040] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0041] 3, the input stage side of the readout circuit (pixel circuit) 17A is electrically connected to the floating diffusion region FD of the pixel 3. The readout circuit 17A of the first embodiment is, for example, a shared pixel block 16 (16A １ and 16A ２ ) as one unit, and two shared pixel blocks 16A (16A １ , 16A ２) and the input stage of the readout circuit 17A of the first embodiment is shared by the pixel block 15A (the first and second shared pixel blocks 16A １ , 16A ２ 3, the readout circuit 17A is electrically connected to each of the eight floating diffusion regions FD included in the first pixel block 15A. That is, the readout circuit 17A is shared by the eight pixels 3 included in the first pixel block 15A. １ A read circuit 17A electrically connected to each floating diffusion region FD of １ and the input stage side is the second pixel block 15A. ２ A read circuit 17A electrically connected to each floating diffusion region FD of ２ The read circuit 17A is an example of the read circuit 17A. １ The input stage side of the first pixel block 15A １ The readout circuit 17A is electrically connected to the floating diffusion region FD of each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in the ２ The input stage side of the second pixel block 15A ２ In the first embodiment, the readout circuit 17A is electrically connected to the floating diffusion region FD of each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in the readout circuit 17A. １ corresponds to a specific example of a “first readout circuit” of the present technology, and the readout circuit 17A ２ corresponds to a specific example of a “second readout circuit” of the present technology.

[0042] The read circuit 17A (17A) shown in FIG. １ , 17A ２ ) reads out the signal charges held in the floating diffusion region FD of the pixel 3 and outputs a pixel signal based on the read-out signal charges. In other words, the read-out circuit 17A converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charges and outputs the pixel signal.

[0043] 3, the readout circuit 17A includes, but is not limited to, for example, two amplification transistors AMP, two selection transistors SEL, and one reset transistor RST as pixel transistors Q. These pixel transistors Q (AMP, SEL, RST) and the transfer transistor TR are insulated gate field effect transistors, and for example, the gate insulating film is made of silicon oxide (SiO ２ The pixel transistor Q and the transfer transistor TR are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0044] As shown in FIG. 3, the readout circuit 17A (17A １ , 17A ２ ), the two amplification transistors AMP are connected in parallel, and the two selection transistors SEL are also connected in parallel. The two amplification transistors AMP and the two selection transistors SEL are connected in series.

[0045] Read circuit 17A (17A １ , 17A ２ Of the pixel transistors Q (two AMPs, two SELs, and one RST) included in the pixel pixel MOS transistor Q, the two select transistors SEL and the one reset transistor RST mainly function as switching elements, and the remaining two amplifying transistors AMP mainly function as amplifying elements.

[0046] 3, the source region of each of the two amplification transistors AMP is electrically connected to the drain region of each of the two selection transistors SEL, and the drain region is electrically connected to the power supply line VDD and the drain region of the reset transistor RST. The gate electrodes of each of the two amplification transistors AMP are connected to one pixel block 15A (first and second shared pixel blocks 16A). １ , 16A ２ ) and is electrically connected to the floating diffusion region FD of each of the eight pixels 3 (3a, 3b, 3c, 3d, 3a, 3b, 3c, 3d) included in the pixel array 10, and is also electrically connected to the source region of the reset transistor RST.

[0047] 3, the source region of each of the two select transistors SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of each of the two amplifier transistors AMP, and the gate electrode of each of the two select transistors SEL is electrically connected to a select transistor drive line among the pixel drive lines 10 shown in FIG.

[0048] 3, the source region of the reset transistor RST is electrically connected to the gate electrode of each of the amplification transistors AMP and is also electrically connected to the floating diffusion region FD of each of the eight pixels 3 (3a, 3b, 3c, 3d, 3a, 3b, 3c, 3d) that share it. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 shown in FIG.

[0049] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0050] When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line VDD.

[0051] The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the readout circuit 17A.

[0052] 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifier transistor AMP constitutes a source-follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0053] During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of each pixel 3 (photoelectric conversion region 22) are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the readout circuit 17A and applied to the gate electrode of the amplifier transistor AMP of the readout circuit 17A. A horizontal line selection control signal is applied from the vertical shift register to the gate electrode of the select transistor SEL of the readout circuit 17A. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the readout circuit 17A to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0054] 3 are mounted on a semiconductor layer 21 (see FIG. 6) described later. The pixel transistors Q (AMP, SEL, RST) included in the readout circuit 17A of FIG. 3 are also mounted on the semiconductor layer 21 (see FIG. 6).

[0055] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the solid-state imaging device 1A (semiconductor chip 2) will be described.

[0056] As shown in Figure 6, the solid-state imaging device 1A of this first embodiment has a semiconductor layer 21 that has a thickness in the Z direction and has a first surface portion S1 and a second surface portion S2 that are located on opposite sides of each other in the thickness direction (Z direction).

[0057] In addition, the solid-state imaging device 1A according to the first embodiment further includes a shallow isolation region (field isolation region) 31 provided in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21, and element formation regions 21a and 21b partitioned by this shallow isolation region 31 and provided in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21.

[0058] In addition, the solid-state imaging device 1A according to the first embodiment further includes a deep isolation region 41 extending from the second surface portion S2 side of the semiconductor layer 21 toward the first surface portion S1 side, and a photoelectric conversion region 22 partitioned by this deep isolation region 41 and provided in the semiconductor layer 21.

[0059] The solid-state imaging device 1A according to the first embodiment further includes a multi-layer wiring layer 61 provided on the first surface S1 side of the semiconductor layer 21.

[0060] In addition, the solid-state imaging device 1A according to the first embodiment further includes a planarization film 71, an optical filter layer 73, and a lens layer 74 arranged in sequence from the second surface S2 side of the semiconductor layer 21.

[0061] Here, the first surface S1 of the semiconductor layer 21 is sometimes referred to as a main surface or element formation surface, and the second surface S2 is sometimes referred to as a back surface. The solid-state imaging device 1A according to the first embodiment is a back-illuminated image sensor that photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 using a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is sometimes referred to as a light incident surface.

[0062] In addition, the solid-state imaging device 1A of this first embodiment separates the pixels 3 using an isolation structure including a shallow isolation region 31 provided in the surface layer on the first surface S1 side of the semiconductor layer 21 and a deep isolation region 41 extending from the second surface S1 side of the semiconductor layer 21 toward the first surface S1 side.

[0063] In the first embodiment, the shallow isolation region 31 and the deep isolation region 41 are described separately, but the shallow isolation region 31 and the deep isolation region 41 may be collectively referred to as the isolation region.

[0064] 6 , the planarization film 71 is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21. As the planarization film 71, for example, a light-transmitting silicon oxide film can be used.

[0065] 6 , the optical filter layer 73 is provided on the side of the planarization film 71 opposite to the semiconductor layer 21 side. This optical filter layer 73 separates the color of incident light that is incident from the light incident surface side (second surface portion S2 side) of the solid-state imaging device 1A. This optical filter layer 73 includes an optical filter portion 73 a for each pixel 3 (for each photoelectric conversion region 22) that transmits light of a specific wavelength, such as, but not limited to, red (R), green (G), or blue (B).

[0066] 6 , the lens layer 74 is provided on the side of the optical filter layer 73 opposite to the planarization film 71. The lens layer 74 includes a microlens (on-chip lens) 74 a for each pixel 3 (for each photoelectric conversion region 22) that collects irradiated light and allows the collected light to efficiently enter the photoelectric conversion region 22.

[0067] That is, the pixel 3 of this first embodiment includes a photoelectric conversion region 22, a planarization film 71 provided on the second surface portion S2 side of this photoelectric conversion region 22, an optical filter portion 73a, and a microlens 74a.

[0068] Although omitted in this first embodiment, a lattice-shaped light-shielding film having a planar pattern in plan view that opens on the light-receiving surface side of each of the plurality of photoelectric conversion regions 22 may be provided between the planarization film 71 and the optical filter layer 73 so as to prevent light incident on a given photoelectric conversion region 22 from leaking into an adjacent photoelectric conversion region 22. This light-shielding film has the same lattice-shaped planar pattern as the deep isolation region 41 described below, and is disposed in a position that overlaps the deep isolation region 41 in plan view. For example, a tungsten (W) film having light-shielding properties can be used as this light-shielding film.

[0069] <Semiconductor Layer> As shown in Figure 6, the semiconductor layer 21 includes a deep isolation region 41 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 defined by the deep isolation region 41. The semiconductor layer 21 further includes a shallow isolation region 31 provided in a surface layer portion of the first surface portion S1 of the semiconductor layer 21 and element formation regions 21a and 21b defined by the shallow isolation region 31. As shown in Figures 4 to 6, the photoelectric conversion region 22 and the element formation regions 21a and 21b are each provided for each pixel 3. The semiconductor layer 21 may be formed of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In this first embodiment, although not limited thereto, a p-type semiconductor substrate made of single crystal silicon is used as the semiconductor layer 21.

[0070] <Shallow Isolation Region> As shown in FIGS. 4 to 6 , the shallow isolation region 31 is provided on the first surface S1 of the semiconductor layer 21 across multiple photoelectric conversion regions 22 (multiple pixels 3) in a plan view. Although not shown in detail, the shallow isolation region 31 includes a shallow recessed portion provided on the first surface S1 side of the semiconductor layer 21 and an isolation insulating film provided inside (inside) the shallow recessed portion so as to fill the shallow recessed portion. The shallow recessed portion can be formed, for example, by selectively etching the first surface S1 of the semiconductor layer 21 using photolithography and dry etching. The isolation insulating film can be formed by depositing, for example, a silicon oxide film as an insulating film on the first surface S1 side of the semiconductor layer 21 by CVD so as to fill the inside of the shallow recessed portion, and then selectively removing the silicon oxide film on the first surface S1 side of the semiconductor layer 21 by etch-back or CMP so that the silicon oxide film inside the shallow recessed portion remains.

[0071] The shallow isolation region 31 separates the element formation regions 21 a and 21 b and electrically isolates these element formation regions 21 a and 21 b. The shallow isolation region 31 is a trench type shallowly recessed region formed in the surface layer on the first surface S1 side of the semiconductor layer 21 to separate and isolate the element formation regions 21 a and 21 b.

[0072] Here, the inside of the shallow recess formed in the semiconductor layer 21 is filled with a film after the shallow recess is formed, and the shallow recess is still called the shallow recess even after the film is filled in. The shallow recess may also be called a recess or a groove.

[0073] <Element Formation Region> As shown in FIGS. 4 to 6, each of the element formation regions 21a and 21b is partitioned into an island shape by a shallow isolation region 31 and is surrounded by the shallow isolation region 31, so that the element formation regions 21a and 21b are insulated and isolated from each other.

[0074] Each of the element formation regions 21a and 21b overlaps the photoelectric conversion region 22 in a plan view and is provided for each pixel 3 on the surface layer portion of the first surface portion S1 of the semiconductor layer 21. The element formation region 21a is provided with the transfer transistor TR and floating diffusion region FD described above. On the other hand, the element formation region 21b is provided with the pixel transistor Q described above.

[0075] As shown in FIGS. 4 to 6, the shared pixel block 16A １ The element formation regions 21a of the four pixels 3 (3a, 3b, 3c, and 3d) included in the shared pixel block 16A are arranged in a plan view. １ The shared pixel block 16A surrounds the center of the １ The shared pixel block 16A is arranged adjacent to the shared pixel block 16A with the shallow isolation region 31 interposed therebetween. １ The element formation regions 21b of the four pixels 3 (3a, 3b, 3c, and 3d) included in the shared pixel block 16A １ The second insulating film 24 is disposed adjacent to the element forming region 21a on the outside of the element forming region 21a so as to surround the central portion of the element forming region 21a.

[0076] Similarly, the shared pixel block 16A ２ The element formation regions 21a of the four pixels 3 (3e, 3f, 3g, and 3h) included in the shared pixel block 16A are also located in the same area as the shared pixel block 16A in plan view. ２ The shared pixel block 16A surrounds the center of the ２ The shared pixel block 16A is arranged adjacent to the shared pixel block 16A with the shallow isolation region 31 interposed therebetween. ２ The element formation regions 21b of the four pixels 3 (3e, 3f, 3g, and 3h) included in the shared pixel block 16A are also ２ The second insulating film 24 is disposed adjacent to the element forming region 21a on the outside of the element forming region 21a so as to surround the central portion of the element forming region 21a.

[0077] <Deep Isolation Region> As shown in FIG. 6 , the deep isolation region 41 extends along the thickness direction (Z direction) of the semiconductor layer 21. The deep isolation region 41 of the first embodiment is not limited thereto, but may have, for example, a first surface S1 side of the semiconductor layer 21 connected to the bottom of the shallow isolation region 31, and a second surface S2 side of the semiconductor layer 21 reaching the second surface S2 of the semiconductor layer 21. Although not shown in detail, the deep isolation region 41 includes, for example, a deep recessed portion provided on the first surface S1 side of the semiconductor layer 21 and an isolation insulating film provided inside (inside) the deep recessed portion so as to fill the deep recessed portion. The deep recessed portion can be formed, for example, by selectively etching the semiconductor layer 21 using photolithography and dry etching techniques. The isolation insulating film can be formed by depositing, for example, a silicon oxide film as an insulating film on the first surface S1 side of the semiconductor layer 21 by the ALD method so as to fill the inside of the deep recess, and then selectively removing the silicon oxide film on the first surface S1 side of the semiconductor layer 21 by the etch-back method or the CMP method so that the silicon oxide film inside the deep recess remains.

[0078] 4, the deep isolation region 41 includes a stripe-shaped first planar extension portion extending in the X direction in a plan view and a stripe-shaped second planar extension portion Y extending in the Y direction. The deep isolation region 41 further includes an intersection portion (intersection portion) where the first planar extension portion and the second planar extension portion intersect with each other on the same plane. In this first embodiment, the first planar extension portion and the second planar extension portion are, for example, perpendicular to each other.

[0079] The first planar extensions are repeatedly arranged at predetermined intervals in the Y direction. The second planar extensions Y are repeatedly arranged at predetermined intervals in the X direction. That is, as shown in FIG. 4 , the deep isolation region 41 has a grid-like planar pattern in plan view.

[0080] 4, the deep isolation region 41 corresponding to one photoelectric conversion region 22 (one pixel 3) has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. On the other hand, referring to FIG. 4, the deep isolation region 41 corresponding to one shared pixel block 16A has a composite planar pattern having a cross-shaped planar pattern in which a first planar extension portion X and a second planar extension portion Y are arranged orthogonal to each other within the rectangular annular planar pattern.

[0081] 5A , the photoelectric conversion region 22 is surrounded by deep isolation regions 41 in a plan view, and has a rectangular shape including four sides. Specifically, the photoelectric conversion region 22 is surrounded by two deep isolation regions 41 (first planar extensions) located on the outside of each of two sides opposite each other in the Y direction, and two deep isolation regions 41 (second planar extensions) located on the outside of each of two sides opposite each other in the X direction. The photoelectric conversion region 22 is partitioned by the deep isolation regions 41 and is electrically and optically isolated from adjacent photoelectric conversion regions 22.

[0082] As shown in Figure 6, the photoelectric conversion region 22 has a p-type well region 23 provided in the semiconductor layer 21, an n-type semiconductor region 24 provided in this p-type well region 23, and a photoelectric conversion section 25 including the p-type well region 23 and the n-type semiconductor region 24.

[0083] 6, the p-type well region 23 is provided over a wide area across the first surface S1 side and the second surface S2 side of the semiconductor layer 21. The p-type well region 23 is provided in the photoelectric conversion region 22, and also in each of the element formation regions 21a and 21b. The p-type well region 23 is in contact with each of the shallow isolation region 31 and the deep isolation region 41. The p-type well region 23 is composed of a p-type semiconductor region doped (introduced) with impurities that exhibit p-type conductivity.

[0084] 6 , the n-type semiconductor region 24 is provided in the p-type well region 23, spaced apart from the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, and the shallow isolation region 31 and the deep isolation region 41, for each photoelectric conversion region 22. The n-type semiconductor region 24 has a three-dimensional structure, and six surfaces, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type well region 23. The n-type semiconductor region 24 forms a pn junction with the p-type well region 23 on these six surfaces.

[0085] 6 , the photoelectric conversion unit 25 is provided in the photoelectric conversion region 22. The photoelectric conversion unit 25 includes a p-type well region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type well region 23 and the n-type semiconductor region 24.

[0086] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side (light incident surface side) of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided in the semiconductor layer 21, spaced apart from the first surface S1 of the semiconductor layer 21. The photoelectric conversion unit 25 is provided for each photoelectric conversion region 22 (pixel 3).

[0087] In the photoelectric conversion section 25 of the first embodiment, the well region 23 is configured as a p-type and the semiconductor region 24 is configured as an n-type, so that the signal charges photoelectrically converted by the photoelectric conversion section 25 are electrons.

[0088] <Floating Diffusion Region> As shown in FIGS. 5A and 5B, one shared pixel block 16A (16A １ , 16A ２The floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c, and 3d) included in the shared pixel block 16A are provided adjacent to each other outside the central portion of the shared pixel block 16A with shallow isolation regions 31 interposed therebetween, so as to surround the central portion of the shared pixel block 16A in a plan view. As shown in FIG. 6 , each floating diffusion region FD is provided in a p-type well region 23 in the surface layer portion on the first surface S1 side of the semiconductor layer 21. Each floating diffusion region FD is made of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0089] <Transfer Transistor> As shown in FIGS. 5A and 5B, one shared pixel block 16A (16A １ , 16A ２ The transfer transistors TR of each of the four pixels 3 ((3a, 3b, 3c, 3d), (3e, 3f, 3g, 3h)) included in the shared pixel block 16A are arranged outside the floating diffusion region FD so as to surround the central part of the shared pixel block 16A in a plan view.

[0090] As shown in FIG. 6 , the transfer transistor TR is provided in the element formation region 21a on the first surface S1 side of the semiconductor layer 21. The transfer transistor TR has a gate electrode 53 provided on the first surface S1 side of the semiconductor layer 21 and a gate insulating film 52 provided between the gate electrode 53 and the semiconductor layer 21. The transfer transistor TR also has an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region, and a p-type well region 23 functioning as a channel formation region. The transfer transistor TR is, for example, a planar type in which the gate electrode 53 is provided outside the semiconductor layer 21 with the gate insulating film 52 interposed therebetween, but is not limited thereto. For example, a vertical type transistor in which the gate electrode 53 extends from inside to outside the semiconductor layer 21 can also be used as the transfer transistor TR.

[0091] The gate insulating film 52 is made of, for example, a silicon oxide film, and the gate electrode 53 is made of, for example, a polycrystalline silicon (doped polysilicon) film doped with impurities that reduce the resistance value.

[0092] When a gate voltage is applied to the gate electrode 53 and the transfer transistor TR is turned on, a charge transfer path (channel) electrically connecting the n-type semiconductor region 24 and the n-type floating diffusion region FD is formed in the p-type well region 23. Then, signal charges (electrons) photoelectrically converted by the photoelectric conversion unit 25 are transferred from the n-type semiconductor region 24 to the n-type floating diffusion region FD through the charge transfer path.

[0093] <Pixel Transistor> As shown in FIGS. 4 to 6, the shared pixel block 16A (16A １ , 16A ２ As described above, a pixel transistor Q is provided in the element formation region 21b of each of the four pixels 3 ((3a, 3b, 3c, 3d), (3e, 3f, 3g, 3h)) included in the pixel array 21.

[0094] In the first embodiment, for example, the first shared pixel block 16A shown in FIG. 5A is used, but is not limited to this. １ In the four pixels 3 (3a, 3b, 3c, and 3d), an amplifier transistor AMP is provided as a pixel transistor Q in the element formation region 21b of each of the pixels 3a and 3b. A reset transistor RTS is provided as a pixel transistor Q in the element formation region 21b of the pixel 3c. A dummy transistor DMY is provided as a pixel transistor Q in the element formation region 21b of the pixel 3d.

[0095] Also, the second shared pixel block 16A shown in FIG. ２ In the four pixels 3 (3e, 3f, 3g, 3h), a dummy transistor DMY is provided as a pixel transistor Q in the element formation region 21b of each of the pixels 3e and 3f. A selection transistor SEL is provided as a pixel transistor Q in the element formation region 21b of each of the pixels 3g and 3h.

[0096] Each of the pixel transistors Q (AMP, SEL, RST) is included in the readout circuit 17A, but the pixel transistor Q (DMY) is not included in the readout circuit 17A. This dummy transistor DMY may be used depending on the circuit configuration of the readout circuit 17A.

[0097] 5A and 6 , the amplification transistor AMP serving as the pixel transistor Q has a gate electrode 54 provided on the outside of the first surface portion S1 of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 54 and the first surface portion S1 of the semiconductor layer 21. The amplification transistor AMP also has a pair of main electrode regions 55 a and 55 b that are provided in the semiconductor layer 21 on both sides of the gate electrode 54 in the gate length direction (the direction of the gate length Lg) and function as a source region and a drain region, and a channel formation portion provided between the pair of main electrode regions 55 a and 55 b.

[0098] Each of the pair of main electrode regions 55a and 55b is made up of, for example, an n-type semiconductor region provided in the p-type well region 23. The channel formation portion is made up of, for example, the p-type well region 23. The gate insulating film 52 is made up of, for example, a silicon oxide film. The gate electrode 55 is made up of, for example, a polycrystalline silicon (doped polysilicon) film doped with impurities that reduce the resistance value.

[0099] As the pixel transistors Q, the selection transistor SEL, reset transistor RST, and dummy transistor DMY other than the amplification transistor AMP also have the same configuration as the amplification transistor AMP, so a description of these pixel transistors Q (SEL, RST, DMY) will be omitted.

[0100] <Plane Pattern of Pixels and Separation Between Pixels> As shown in FIGS. 4, 5A, and 5B, one shared pixel block 16A (16A １ , 16A ２) have different planar patterns including the arrangement of the element formation regions 21a and 21b. In this first embodiment, as shown in FIGS. 4, 5A, and 5B, the planar patterns of the pixels 3a (3e) and 3b (3f) arranged in the X direction are inverted patterns with the boundary between the pixels 3a (3e) and 3b (3f) as the inversion axis. Furthermore, the planar patterns of the pixels 3c (3g) and 3d (3h) arranged in the X direction are inverted patterns with the boundary between the pixels 3c (3g) and 3d (3h) as the inversion axis. Furthermore, the planar patterns of the pixels 3a (3e) and 3c (3g) arranged in the Y direction are inverted patterns with the boundary between the pixels 3a (3e) and 3c (3g) as the inversion axis. In addition, the planar patterns of pixels 3b (3f) and 3d (3h) arranged in the Y direction are inverted patterns with the boundary between pixels 3b (3f) and 3d (3h) as the inversion axis.

[0101] As shown in FIG. 5A, the first shared pixel block 16A １ The four pixels 3 (3a, 3b, 3c, d3) included in the second shared pixel block 16A are physically (structurally) separated by an isolation region including a shallow isolation region 31 and a deep isolation region 41. The floating diffusion regions FD and transfer transistors TR of the four pixels 3 (3a, 3b, 3c, d3) are also physically (structurally) separated by an isolation region including a shallow isolation region 31 and a deep isolation region 41. The floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c, d3) are individually isolated, and the transfer transistors TR of the four pixels 3 (3a, 3b, 3c, d3) are also individually isolated. Also, as shown in FIG. 5B , the second shared pixel block 16A includes four pixels 3 (3a, 3b, 3c, d3) and four floating diffusion regions FD and transfer transistors TR of the four pixels 3 (3a, 3b, 3c, d3) are individually isolated. ２The four pixels 3 (3e, 3f, 3g, 3h) included in the pixel array 10 are also physically (structurally) separated by an isolation region including a shallow isolation region 31 and a deep isolation region 41. The floating diffusion regions FD and transfer transistors TR of the four pixels 3 (3e, 3f, 3g, 3h) are also physically (structurally) separated by an isolation region including a shallow isolation region 31 and a deep isolation region 41. The floating diffusion regions FD of the four pixels 3 (3e, 3f, 3g, dh) are also individually isolated, and the transfer transistors TR of the four pixels 3 (3e, 3f, 3g, dh) are also individually isolated.

[0102] <First Pixel Block and Second Pixel Block> As shown in FIG. 4, two pixel blocks 15A (first and second pixel blocks 15A) are arranged adjacent to each other in the Y direction. １ , 15A ２ ) is the first pixel block 15A １ The first shared pixel block 16A included in １ and the second pixel block 15A ２ The second shared pixel block 16A included in ２ The first pixel block 15A and the second pixel block 15B are adjacent to each other in the Y direction. １ First shared pixel block 16A １ The two pixels 3a and 3b included in the second pixel block 15A ２ The second shared pixel block 16A ２ In other words, the pixel array unit 2A of the first embodiment includes a first pixel block 15A. １ and the pixels 3a and 3b included in the second pixel block 15A. ２ The pixels 3a and 3b included in the first pixel block 15A are arranged adjacent to each other in the Y direction. １ and a second pixel block 15A including pixels 3g and 3h as second pixels. ２Furthermore, pixels 3a and 3b as first pixels are arranged adjacent to each other in the X direction intersecting with the Y direction, and pixels 3 as first pixels are repeatedly arranged in the X direction. Furthermore, pixels 3g and 3h as second pixels are arranged adjacent to each other in the X direction intersecting with the Y direction, and pixels 3 as second pixels are repeatedly arranged in the X direction.

[0103] 3 is configured with pixel transistors Q included in a circuit block 18A shown in FIG. 4. The circuit block 18A is configured with two pixel blocks 15A (first and second pixel blocks 15A) arranged adjacent to each other in the Y direction in a plan view. １ , 15A ２ ) in the first pixel block 15A １ First shared pixel block 16A １ two amplification transistors AMP provided in each of the pixels 3a and 3b included in the first pixel block 15A; １ The second shared pixel block 16A ２ and a reset transistor RST provided in the pixel 3c included in the second pixel block 15A. ２ The second shared pixel block 16A ２ and two selection transistors SEL, one for each of the pixels 3g and 3h included in the first and second pixel blocks 15A, which are adjacent to each other in the Y direction. １ and 15A ２ The circuit block 18A is provided for each readout circuit 17A in correspondence with the readout circuit 17A. １ The readout circuit 17A (17A) is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, 3d) included in the １ ) is a pixel transistor Q of the first pixel block 15A １ the amplifier transistor AMP and the reset transistor RST of the second pixel block 15A, ２ and a select transistor SEL.

[0104] 4 to 5C , in each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in the pixel block 15A, a pair of main electrode regions 55a and 55b of the pixel transistor Q are aligned along the Y direction in a plan view. In addition, in each of the eight pixels 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h) included in the pixel block 15A, the floating diffusion regions FD and the pixel transistors Q are aligned along the Y direction in this order in a plan view.

[0105] 5A and 5C, the first pixel blocks 15A are arranged adjacent to each other in the Y direction. １ and the second pixel block 15A ２ In the first pixel block 15A, １ a pair of main electrode regions 55a and 55b of the pixel transistor Q (AMP) included in the pixel 3a of the second pixel block 15A; ２ 5A and 5C , a pair of main electrode regions 55 a and 55 b of the pixel transistor Q (SEL) included in the pixel 3 g are aligned along the Y direction, and the floating diffusion region FD and pixel transistor Q (AMP) included in the pixel 3 a and the pixel transistor Q (SEL) and floating diffusion region FD included in the pixel 3 g are aligned along the Y direction in this order (FD, AMP, SEL, FD). １ and the second pixel block 15A ２ In the first pixel block 15A, １ a pair of main electrode regions 55a and 55b of the pixel transistor Q (AMP) included in the pixel 3b of the second pixel block 15A; ２ A pair of main electrode regions 55a and 55b of the pixel transistor Q (SEL) included in pixel 3h are aligned along the Y direction, and the floating diffusion region FD and pixel transistor Q (AMP) included in pixel 3b and the pixel transistor Q (SEL) and floating diffusion region FD included in pixel 3h are aligned in this order (FD, AMP, SEL, FD) in the Y direction.

[0106] Here, the first pixel block 15A １a pair of main electrode regions 55a and 55b of the pixel transistor Q (AMP) included in the pixel 3a of the second pixel block 15A; ２ 5A and 5C, the pair of main electrode regions 55a and 55b of the pixel transistor Q (SEL) included in the pixel 3g in the first pixel block 15A function as a source region and a drain region, as described above. １ the pixel transistor Q (AMP) included in the pixel 3a of the second pixel block 15A; ２ The pixel transistor Q (SEL) included in the pixel 3g of the first pixel block 15A includes a source region and a drain region. １ the source region and the drain region of the pixel transistor Q (AMP) included in the pixel 3a of the second pixel block 15A; ２ The source and drain regions of the pixel transistors SEL included in the pixels 3g of the first pixel block 15A are aligned in the Y direction. １ the drain region and the source region of the pixel transistor Q (AMP) included in the pixel 3a of the second pixel block 15A ２ The drain regions and source regions of the pixel transistors Q (SEL) included in the pixels 3g of the first pixel block 15A are arranged in this order along the Y direction. １ a pair of main electrode regions 55a and 55b of the pixel transistor Q (AMP) included in the pixel 3b of the second pixel block 15A; ２ 5A and 5C, the pair of main electrode regions 55a and 55b of the pixel transistor Q (SEL) included in the pixel 3h of the first pixel block 15A function as a source region and a drain region, as described above. １ the pixel transistor Q (AMP) included in the pixel 3b of the second pixel block 15A;２ The pixel transistor Q (SEL) included in the pixel 3h of the first pixel block 15A includes a source region and a drain region. １ the source region and the drain region of the pixel transistor Q (AMP) included in the pixel 3b of the second pixel block 15A; ２ The source and drain regions of the pixel transistors SEL included in the pixels 3h of the first pixel block 15A are aligned in the Y direction. １ the drain region and the source region of the pixel transistor Q (AMP) included in the pixel 3b of the second pixel block 15A ２ The drain regions and source regions of the pixel transistors Q (SEL) included in the pixels 3h are arranged in this order along the Y direction.

[0107] In this first embodiment, the first pixel block 15A １ The pixels 3a and 3b included in the second pixel block 15A correspond to a specific example of a “first pixel” of the present technology. ２ The pixels 3g and 3h included in the first pixel block 15A correspond to a specific but not limitative example of a "second pixel" in the present technology. １ The amplification transistors AMP of the pixels 3a and 3b included in the second pixel block 15A correspond to a specific but not limitative example of “first pixel transistor” of the present technology. ２ The select transistor SEL of each of the pixels 3g and 3h included in the pixel 3a corresponds to a specific but not limitative example of a “second pixel transistor” of the present technology. The amplifier transistor AMP and the select transistor SEL are arranged adjacent to each other in the Y direction in plan view.

[0108] In the first embodiment, the first pixel block 15A １ The floating diffusion region FD and the pixel transistor Q (AMP) included in each of the pixels 3a and 3b (first pixels) in the second pixel block 15A correspond to a specific example of a “first charge holding unit” and a “first pixel transistor” in the present technology. ２ The floating diffusion region FD and the pixel transistor Q (SEL) included in each of the pixels 3g and 3h (second pixels) correspond to a specific but not limitative example of a "second charge holding unit" and a "second pixel transistor" in the present technology.

[0109] 6, the multilayer wiring layer 61 is provided on the first surface S1 side of the semiconductor layer 21. The multilayer wiring layer 61 includes an interlayer insulating film 62 provided on the first surface S1 side of the semiconductor layer 21 so as to cover the element formation regions 21a, 21b and the shallow isolation region 31, and a first-layer wiring layer provided on the opposite side of the interlayer insulating film 62 from the semiconductor layer 21. The first wiring layer includes wirings 64a, 64b, and 64c shown in FIGS.

[0110] As shown in Figures 4, 5A, and 5B, the wiring 64a extends along the Y direction between two pixels 3 aligned in the X direction of the pixel block 15A in a plan view, i.e., between the pixel row of pixels 3a, 3c, 3e, and 3g aligned in the Y direction and the pixel row of pixels 3b, 3d, 3f, and 3h aligned in the Y direction.

[0111] 4 and 5A, one end of the wiring 64a is connected to the first shared pixel block 16A. １ and the first shared pixel block 16A. １ 1. The gate electrode 54 is electrically connected to the gate electrode 54 of each pixel transistor Q (AMP) of the two pixels 3 (3a, 3b) included in the pixel array 1.

[0112] 4 and 5B, the other end of the wiring 64a opposite to the one end is connected to the second shared pixel block 16A. ２ The floating diffusion regions FD are electrically connected to the four pixels 3 (3e, 3f, 3g, 3h) included in the pixel array 1.

[0113] 7, the wiring 64a is electrically connected to the floating diffusion region FD and the gate electrode 54 of the pixel transistor Q (AMP) via each contact electrode 63a provided in the interlayer insulating film 62. In addition, the wiring 64a includes, but is not limited to, a main line portion (trunk line portion) that extends in the Y direction between two pixels 3 aligned in the X direction of the pixel block 15A in a plan view, and sub-line portions (branch line portions) that extend in the X direction from the main line portion.

[0114] As shown in FIGS. 4, 5A, and 5C, the wiring 64b is connected to two pixel blocks 15A (first pixel block 15A) arranged in the Y direction in a plan view. １ and the second pixel block 15A ２ ) in the first pixel block 15A １ Between two pixels 3a and 3b arranged in the X direction, and the second pixel block 15A ２ The first and second pixel blocks 15A are arranged between two pixels 3g and 3h aligned in the X direction. １ , 15A ２ It stretches over the entire area.

[0115] 4 and 5A, one end of the wiring 64b extends along the X direction and is connected to the first pixel block 15A. １ The main electrode region 55a is electrically connected to the main electrode region 55a of each pixel transistor Q (AMP) of two pixels 3a and 3b arranged in the X direction.

[0116] 4 and 5C, the other end of the wiring 64b, which is opposite to the one end, extends along the X direction and is connected to the second pixel block 15A. ２ The pixel 55 is electrically connected to the main electrode region 55b of the select transistor SEL of each of two pixels 3g and 3h arranged in the X direction.

[0117] 7, the wiring 64b is electrically connected to the main electrode region 55a of the amplifier transistor AMP and the main electrode region 55b of the select transistor SEL via a contact electrode 63b provided in the interlayer insulating film 62. The wiring 64b also includes, but is not limited to, a main line portion (trunk portion) that extends in the Y direction between two pixels 3 aligned in the X direction of the pixel block 15A in a plan view, and sub-line portions (branch portions) that extend in the X direction from the main line portion.

[0118] 4 and 5C , the wiring 64c extends in the X direction across two pixels 3g and 3h that are aligned in the X direction in the pixel block 15A in a plan view. One end of the wiring 64c is electrically connected to the main electrode region 55a of the select transistor SEL included in pixel 3g, and the other end opposite to the one end is electrically connected to the main electrode region 55a of the select transistor SEL included in pixel 3h.

[0119] Although not limited to this, the wiring 64c is electrically connected to the main electrode region 55b of the select transistor SEL via a contact electrode 63c provided in the interlayer insulating film 62, as shown in FIG.

[0120] That is, in the readout circuit 17A of the first embodiment, two amplification transistors (AMP, AMP) are connected in parallel via wiring 64b, and two selection transistors (SEL, SEL) are connected in parallel via wiring 64c. Furthermore, the two amplification transistors Q (AMP, AMP) and the two selection transistors (SEL, SEL) are connected in series via wiring 64b.

[0121] The first wiring layer including the wirings 64a, 64b, and 64c may be made of a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly containing Al or Cu. The interlayer insulating film 62 may be made of a silicon oxide film. The contact electrodes 63a, 63b, and 63c provided in the interlayer insulating film 62 may be made of a high-melting-point metal such as tungsten (W).

[0122] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described. As described above, the solid-state imaging device 1A according to the first embodiment has the first and second pixel blocks 15A arranged adjacent to each other in the Y direction in a plan view. １ and 15A ２ In the first pixel block 15A, １ and the pixels 3a and 3b included in the second pixel block 15A. ２ Pixels 3g and 3h included in the pixel 3a are arranged adjacent to each other in the Y direction in plan view.

[0123] A pair of main electrode regions 55a and 55b (the drain and source regions of the amplifier transistor AMP and the drain and source regions of the select transistor SEL) of the amplifier transistor AMP included in pixel 3a and the select transistor SEL included in pixel 3g are aligned in the Y direction, and the floating diffusion region FD and amplifier transistor AMP included in pixel 3a, and the select transistor SEL and floating diffusion region FD included in pixel 3g are aligned in this order in the Y direction. １ In the pixel 3a of the second pixel block 15A, the floating diffusion region FD, the drain region and the source region of the amplification transistor AMP are arranged in this order along the Y direction. ２ In the pixel 3g, the drain region and source region of the selection transistor SEL and the floating diffusion region FD are arranged in this order along the Y direction.

[0124] Furthermore, a pair of main electrode regions 55a and 55b (the drain region and source region of the amplifier transistor AMP and the drain region and source region of the select transistor SEL) of the amplifier transistor AMP included in pixel 3b and the select transistor SEL included in pixel 3h are aligned in the Y direction, and the floating diffusion region FD and amplifier transistor AMP included in pixel 3b, and the select transistor SEL and floating diffusion region FD included in pixel 3h are aligned in this order in the Y direction. １ In the pixel 3b of the second pixel block 15A, the floating diffusion region FD, the drain region and the source region of the amplification transistor AMP are arranged in this order along the Y direction. ２ In the pixel 3h, the drain region and source region of the selection transistor SEL and the floating diffusion region FD are arranged in this order along the Y direction.

[0125] With this configuration, as shown in FIG. 5A, the first pixel block 15A １In two pixels 3a and 3b arranged side by side in the X direction, the wiring length along the X direction of the wiring 64a that electrically connects the floating diffusion region FD included in one pixel 3a to the floating diffusion region FD included in the other pixel 3b can be made the shortest.

[0126] Also, as shown in FIG. 5A, the first pixel block 15A １ In two pixels 3 a and 3 b arranged side by side in the X direction, the wiring length along the X direction of the wiring 64 a that electrically connects the gate electrode 54 of the pixel transistor Q (AMP) included in one pixel 3 a to the gate electrode 54 of the pixel transistor Q (AMP) included in the other pixel 3 b can be made the shortest.

[0127] Also, as shown in FIG. 5A, the first pixel block 15A １ In two pixels 3a and 3b arranged in the X direction, the wiring length along the Y direction of the wiring 64a that electrically connects each floating diffusion region FD, FD and the gate electrode 54 of each amplification transistor AMP can be made the shortest.

[0128] Also, as shown in FIG. 5A, the first pixel block 15A １ In two pixels 3a and 3b aligned in the X direction, the length of the wiring 64b along the X direction that electrically connects the main electrode region 55a of the amplifier transistor AMP included in one pixel 3a to the main electrode region 55a of the amplifier transistor AMP included in the other pixel 3b can be made the shortest.

[0129] Also, as shown in FIG. 5C, the second pixel block 15A ２ In two pixels 3g and 3h aligned in the X direction, the wiring length along the X direction of the wiring 64b that electrically connects the main electrode region 55b of the select transistor SEL included in one pixel 3g to the main electrode region 55b of the select transistor SEL included in the other pixel 3h can be made the shortest.

[0130] Also, as shown in FIGS. 5A and 5C, the first pixel block 15A １ The two pixels 3a and 3b arranged in the X direction and the second pixel block 15A ２In the two pixels 3g and 3h arranged in the X direction, the wiring length along the Y direction of the wiring 64b that electrically connects the main electrode region 55a of each of the amplification transistors AMP included in the two pixels 3a and 3b to the main electrode region 55b of the selection transistor SEL included in each of the two pixels 3g and 3h can be made the shortest.

[0131] Also, as shown in FIG. 5C, the second pixel block 15A ２ In two pixels 3g and 3h aligned in the X direction, the wiring length along the X direction of the wiring 64c that electrically connects the main electrode region 55a of the select transistor SEL included in one pixel 3g to the main electrode region 55a of the select transistor SEL included in the other pixel 3h can be made the shortest.

[0132] Therefore, according to the solid-state imaging device 1A according to the first embodiment, it is possible to reduce the wiring capacitance in the readout circuit 17A including the amplifying transistor AMP and two selection transistors SEL that are used in parallel connection.

[0133] Furthermore, according to the solid-state imaging device 1A of the first embodiment, the wiring capacitance in the readout circuit 17A can be reduced, which allows the pixels 3 to be miniaturized and allows for higher image quality.

[0134] In the first embodiment described above, two pixel rows, each of which has four pixels 3 arranged in the Y direction, are arranged in the X direction. １ , second pixel block 15A ２ ), the present technology can also be applied to a pixel block including one pixel column in which a plurality of pixels 3 are arranged in the Y direction.

[0135] Furthermore, the select transistor SEL can be omitted as necessary. When the select transistor SEL is omitted, the source region of the amplifier transistor AMP is electrically connected to the vertical signal line 11 (VSL). Even when the select transistor SEL is omitted, the present technology can be applied.

[0136] In the first embodiment described above, as an example, a circuit configuration is used in which one readout circuit 17A is assigned to one pixel block 15A. However, the assignment of the readout circuits 17A is not limited to this first embodiment. For example, a circuit configuration may be used in which one readout circuit 17A is assigned to two or more pixel blocks 15A, or a circuit configuration may be used in which one readout circuit 17A is assigned to each shared pixel block 16A.

[0137] In the first embodiment described above, as an example, the number of pixels 3 included in the shared pixel block 16A is set to four. However, the number of pixels 3 included in the shared pixel block 16A is not limited to this in the first embodiment.

[0138] [Second Embodiment] In this second embodiment, an example in which the present technology is applied to a solid-state imaging device including phase pixels will be described. Fig. 8 is an equivalent circuit diagram showing an example configuration of a pixel block and a readout circuit of the solid-state imaging device according to the second embodiment of the present technology. Fig. 9 is a plan view schematically showing an example configuration of the pixel block of the solid-state imaging device according to the second embodiment of the present technology.

[0139] A solid-state imaging device 1B according to the second embodiment of the present technology includes a pixel block (pixel unit) 15B and a readout circuit 17B shown in FIG.

[0140] 8 and 9 , the pixel block 15B includes a plurality of pixels 3. In the second embodiment, the pixel block 15B includes, for example, but is not limited to, four pixels 3 (3 a, 3 b, 3 c, 3 d) arranged in a 2×2 pattern, two by two adjacent to each other in each of the X and Y directions in plan view.

[0141] 8 mainly illustrates one pixel block 15B, and FIG. 9 illustrates two pixel blocks 15B (first pixel block 15B １ , second pixel block 15B ２9, the pixel blocks 15B are repeatedly arranged in the X and Y directions to form the pixel array section 2A shown in FIG. 1 in the same manner as in the first embodiment. The pixel array section 2A of the first embodiment includes a first pixel block 15B including pixels 3a and 3b as first pixels, as shown in FIG. １ and a second pixel block 15B including pixels 3c and 3d as second pixels. ２ The pixels 3a and 3b as first pixels are arranged adjacent to each other in the X direction intersecting with the Y direction, and the pixels 3 as first pixels are repeatedly arranged in the X direction. The pixels 3c and 3d as second pixels are arranged adjacent to each other in the X direction intersecting with the Y direction, and the pixels 3 as second pixels are repeatedly arranged in the X direction.

[0142] 8 , the pixel 3 of the second embodiment is configured as a phase difference pixel that detects a phase difference between two photoelectric conversion units 25 provided in one photoelectric conversion region 22. The present technology can also be applied to a solid-state imaging device 1B that includes such a phase difference pixel.

[0143] As shown in Fig. 8, the photoelectric conversion region 22 of the second embodiment includes a first photoelectric conversion cell 22L and a second photoelectric conversion cell 22R. Each of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R has a photoelectric conversion unit 25, a transfer transistor TR, and a floating diffusion region FD similar to those of the first embodiment. As shown in Fig. 9, the photoelectric conversion region 22 of the second embodiment includes two element formation regions 21a (21a １ , 21a ２ ) and one element formation region 21b.

[0144] <Element Formation Region> As shown in FIG. 9, two element formation regions 21a (21a １ , 21a ２ As in the first embodiment, each of the two element forming regions 21a (21a) is partitioned into an island shape by the shallow isolation region 31 and is surrounded by the shallow isolation region 31, and is insulated and isolated from each other. １ , 21a ２The transfer transistor TR and the floating diffusion region FD are provided in each of the element formation regions 21b. On the other hand, the pixel transistor Q included in the readout circuit 17B is provided in the element formation region 21b.

[0145] As shown in FIG. 9, the pixel block 15B (first pixel block 15B １ , second pixel block 15B ２ The element formation regions 21a of the four pixels 3 (3a, 3b, 3c, 3d) included in １ are arranged adjacent to each other with a shallow isolation region 31 interposed therebetween, outside the center of a pixel group including four pixels 3 (3a, 3b, 3c, 3d).

[0146] The element forming regions 21a of the four pixels 3 (3a, 3b, 3c, 3d) included in the pixel block 15B are ２ The element forming region 21a surrounds the center of the pixel group including four pixels 3 (3a, 3b, 3c, 3d). １ The element forming region 21a is located outside the １ The two element forming regions 21a (21a １ , 21a ２ ) are aligned in the X direction.

[0147] The element formation regions 21b of the four pixels 3 (3e, 3f, 3g, 3h) included in the pixel block 15B are also formed in the element formation regions 21a so as to surround the center of the pixel group including these four pixels 3 (3a, 3b, 3c, 3d). １ The element forming region 21a is located outside the １ The element formation region 21b of the second embodiment differs from the element formation region 21b of the first embodiment in that the planar shape is an H-shape including a first portion extending in the X direction in plan view and second portions extending in the Y direction on both sides of the first portion in the X direction.

[0148] <Pixel Transistor> As shown in FIG. 9, the pixel block 15B (15B １ , 15B ２As described above, the pixel transistor Q is provided in the element formation region 21b of each of the four pixels 3 (3a, 3b, 3c, 3d) included in the pixel array 21.

[0149] In the second embodiment, for example, but not limited to, in two pixels 3 (3a, 3b) aligned in the X direction, two amplifier transistors AMP are aligned in the X direction as pixel transistors Q in the element formation region 21b of pixel 3a, and an amplifier transistor AMP and a dummy transistor DMY are aligned in the X direction as pixel transistors Q in pixel 3b. The amplifier transistor AMP of pixel 3b is disposed on the pixel 3a side. The two amplifier transistors AMP of pixel 3a and the amplifier transistor AMP of pixel 3b are aligned adjacent to each other in the X direction.

[0150] Furthermore, in this second embodiment, although not limited thereto, for example, in two pixels 3 (3c, 3d) aligned in the X direction, a selection transistor SEL and a reset transistor RST are aligned in the X direction as pixel transistors Q in the element formation region 21b of pixel 3c, and a selection transistor SEL and a dummy transistor DMY are aligned in the X direction as pixel transistors Q in the element formation region 21b of pixel 3d. The selection transistor SEL of pixel 3c is arranged on the pixel 3d side, and the selection transistor SEL of pixel 3d is arranged on the pixel 3c side. The selection transistors SEL of pixels 3c and 3d are aligned adjacent to each other in the X direction.

[0151] In the second embodiment, the pixel transistors Q (AMP, SEL, RST) provided in each of the four pixels 3 (3a, 3b, 3c, 3d) have a pair of main electrode regions that function as a source region and a drain region aligned in the Y direction. That is, in the second embodiment, the pixel transistors Q (AMP, SEL, RST) provided in each of the four pixels 3 (3a, 3b, 3c, 3d) include a drain region and a source region. １ The select transistors SEL of the pixels 3c and 3d included in the first pixel block 15B １The readout circuit 17B (see FIG. 8) is not included in the components of the readout circuit 17B electrically connected to the floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c, 3d) included in the second pixel block 15B. Instead, the readout circuit 17B is included in the second pixel block 15B. ２ The pixel 3c and the pixel 3d included in the circuit 10 include, as components thereof, the selection transistor SEL of each of the pixels 3c and 3d.

[0152] <Plane Pattern of Pixels> As shown in FIG. 9, one pixel block 15B (15B １ , 15B ２ Each of the four pixels 3 (3a, 3b, 3c, 3d) included in the pixel 3 has a different planar pattern including the arrangement of the element formation regions 21a and 21b.

[0153] In this second embodiment, the planar patterns of pixels 3a and 3b arranged in the X direction are inverted patterns with the boundary between pixels 3a and 3b as the inversion axis. Furthermore, the planar patterns of pixels 3c and 3d arranged in the X direction are inverted patterns with the boundary between pixels 3c and 3d as the inversion axis. Furthermore, the planar patterns of pixels 3a and 3c arranged in the Y direction are inverted patterns with the boundary between pixels 3a and 3c as the inversion axis. Furthermore, the planar patterns of pixels 3b and 3d arranged in the Y direction are inverted patterns with the boundary between pixels 3b and 3d as the inversion axis.

[0154] <First Pixel Block and Second Pixel Block> As shown in FIG. 9, two pixel blocks 15B (first pixel block 15B) are arranged adjacent to each other in the Y direction. １ , second pixel block 15B ２ ) is the first pixel block 15B １ Pixels 3a and 3b of the second pixel block 15B ２ Pixels 3c and 3d are arranged adjacent to each other in the Y direction.

[0155] 8, the readout circuit 17B has three amplification transistors AMP, AMP, AMP, two selection transistors SEL, SEL, and one reset transistor RST as pixel transistors Q. Of the three amplification transistors AMP, as shown in FIG. １ The remaining one amplifier transistor AMP is provided in the pixel 3a included in the first pixel block 15B １ The reset transistor RST is provided in the pixel 3b included in the first pixel block 15B. １ On the other hand, as shown in FIG. 9, the two selection transistors SEL are provided in the pixel 3c included in the second pixel block 15B1, which is different from the first pixel block 15B1. ２ That is, the readout circuit 17B of the second embodiment includes, as components, the first pixel block 15B. １ The second pixel block 15B includes three amplifier transistors AMP and one reset transistor RST provided in the pixel 3 of ２ The readout circuit 17B includes two selection transistors SEL provided in the pixels 3 of the first pixel block 15B. １ the selection transistor SEL provided in each of the pixels 3c and 3d in the second pixel block 15B; ２ The reset transistor provided in the pixel 3c of the first pixel block 15B is included in a readout circuit 17B different from the readout circuit 17B shown in FIG. １ The readout circuit 17B electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, 3d) included in the first pixel block 15B is １ the amplifier transistor AMP and the second pixel block 15B ２ The select transistor SEL and the reset transistor RST are also included.

[0156] 9 , in each of the four pixels 3 (3a, 3b, 3c, 3d) included in the pixel block 15B, a pair of main electrode regions 55a and 55b of the pixel transistor Q (AMP, SEL, RST) are aligned along the Y direction in a plan view. In addition, in each of the four pixels 3 (3a, 3b, 3c, 3d) included in the pixel block 15B, the floating diffusion regions FD and the pixel transistors Q are aligned along the Y direction in this order in a plan view.

[0157] As shown in FIG. 9, the first pixel blocks 15B are arranged adjacent to each other in the Y direction. １ and the second pixel block 15B ２ In the first pixel block 15B １ a pair of main electrode regions 55a and 55b of the amplifier transistor AMP included in the pixel 3a of the second pixel block 15B; ２ A pair of main electrode regions 55a and 55b of the select transistor SEL included in the pixel 3c are aligned along the Y direction, and the floating diffusion region FD and the amplification transistor AMP included in the pixel 3a and the select transistor Q (SEL) and the floating diffusion region FD included in the pixel 3c are aligned along the Y direction in this order (FD, AMP, SEL, FD). １ In the pixel 3a of the second pixel block 15B, the floating diffusion region FD, the drain region and the source region of the amplification transistor AMP are arranged in this order along the Y direction. ２ In the pixel 3c, the drain region and source region of the selection transistor SEL and the floating diffusion region FD are arranged in this order along the Y direction.

[0158] As shown in FIG. 9, the first pixel blocks 15B arranged adjacent to each other in the Y direction １ and the second pixel block 15B ２ In the first pixel block 15B １ a pair of main electrode regions 55a and 55b of the amplifier transistor AMP included in the pixel 3b of the second pixel block 15A; ２A pair of main electrode regions 55a and 55b of the select transistor SEL included in pixel 3d are aligned along the Y direction, and the floating diffusion region FD and the amplification transistor Q (AMP) included in pixel 3b and the select transistor SEL and the floating diffusion region FD included in pixel 3d are aligned along the Y direction in this order (FD, AMP, SEL, FD). １ In the pixel 3b of the second pixel block 15B, the floating diffusion region FD, the drain region and the source region of the amplification transistor AMP are arranged in this order along the Y direction. ２ In the pixel 3d, the drain region and source region of the selection transistor SEL and the floating diffusion region FD are arranged in this order along the Y direction.

[0159] In other words, the pixel array section of the second embodiment includes first pixel blocks 15B arranged adjacent to each other in the Y direction. １ pixel 3a as the first pixel of the second pixel block 15B; ２ 9, the first pixel block 15B includes a pixel 3c as a second pixel. １ The pixel 3a of the second pixel block 15B has two photoelectric conversion units 25 as first and second photoelectric conversion units, two floating diffusion regions FD as first and second charge holding units, and two pixel transistors Q (AMP, AMP) as first and second pixel transistors. ２Pixel 3c includes two photoelectric conversion units 25 as third and fourth photoelectric conversion units, two floating diffusion regions FD as third and fourth charge retention units, and two pixel transistors Q (SEL, RST) as third and fourth pixel transistors. Pixel 3a and pixel 3c belong to different pixel sharing units (pixel blocks 15B). As shown in FIG. 9 , the source / drain regions of pixel transistor Q (AMP) as the first pixel transistor and pixel transistor (SEL) as the third transistor are aligned in the Y direction, and the floating diffusion region FD as the first charge retention unit, pixel transistor Q (AMP) as the first pixel transistor, pixel transistor Q (SEL) as the third pixel transistor, and floating diffusion region FD as the third charge retention unit are aligned in this order in the Y direction.

[0160] The pixel array section of the second embodiment also includes first pixel blocks 15B arranged adjacent to each other in the Y direction. １ pixel 3b as the first pixel of the second pixel block 15B; ２ 9, the first pixel block 15B includes a pixel 3d as a second pixel. １ The pixel 3b of the second pixel block 15B has two photoelectric conversion units 25 as first and second photoelectric conversion units, two floating diffusion regions FD as first and second charge storage units, and two pixel transistors Q (AMP, DMY) as first and second pixel transistors. ２Pixel 3d includes two photoelectric conversion units 25 as third and fourth photoelectric conversion units, two floating diffusion regions FD as third and fourth charge retention units, and two pixel transistors Q (SEL, DMY) as third and fourth pixel transistors. Pixels 3b and 3d belong to different pixel sharing units (pixel block 15B). As shown in FIG. 9 , the source / drain regions of the pixel transistor Q (AMP) as the first pixel transistor and the pixel transistor (SEL) as the third transistor are aligned in the Y direction, and the floating diffusion region FD as the first charge retention unit, the pixel transistor Q (AMP) as the first pixel transistor, the pixel transistor Q (SEL) as the third pixel transistor, and the floating diffusion region FD as the third charge retention unit are aligned in this order in the Y direction.

[0161] In the second embodiment, the first pixel block 15B １ The pixels 3a and 3b included in the second pixel block 15B correspond to a specific example of a “first pixel” of the present technology. ２ In the second embodiment, the pixels 3c and 3d included in the first pixel block 15B correspond to a specific example of a "second pixel" of the present technology. １ The two photoelectric conversion units 25, the two floating diffusion regions FD, and the two pixel transistors Q included in each of the pixels 3 a and 3 b (first pixels) correspond to specific examples of “first photoelectric conversion unit,” “second photoelectric conversion unit,” “first charge holding unit,” “second charge holding unit,” “first pixel transistor,” and “second charge transistor” of the present technology. ２ The two photoelectric conversion units 25, the two floating diffusion regions FD, and the two pixel transistors Q included in each of the pixels 3b and 3d (second pixels) correspond to specific examples of "third photoelectric conversion unit," "fourth photoelectric conversion unit," "third charge holding unit," "fourth charge holding unit," "third pixel transistor," and "fourth charge transistor" of the present technology. In the second embodiment, the amplification transistor corresponds to a specific example of "first pixel transistor" of the present technology, and the selection transistor SEL corresponds to a specific example of "second pixel transistor" of the present technology.

[0162] <Multi-layer wiring layer> As shown in FIG. 9, two pixel blocks 15B (15B １ , 15B ２ ) have wirings 64a, 64b, 64c, and 64d extending therethrough. Each of these wirings 64a, 64b, 64c, and 64d is provided in the first wiring layer of the multi-layer wiring layer, as in the first embodiment described above.

[0163] The wiring 64a is connected to the first pixel block 15B. １ The wiring 64a is electrically connected to the gate electrodes of the two amplification transistors (AMP, AMP) provided in the pixel 3a of the first pixel block 15B. １ The wiring 64a is electrically connected to two floating diffusion regions provided in each of the four pixels 3 (3a, 3b, 3c, and 3d) in the first pixel block 15B. １ The pixel 3a is electrically connected to the main electrode region 55a of the reset transistor RST provided in the pixel 3a.

[0164] The wiring 64b is connected to the first pixel block 15B. １ The first pixel block 15B is electrically connected to the main electrode region 55b of each of the two pixel transistors Q (AMP, AMP) provided in the pixel 3a of the first pixel block 15B. １ The wiring 64b is electrically connected to the main electrode region 55b of the amplifier transistor AMP provided in the pixel 3b of the second pixel block 15B. ２ The pixel electrodes 55a and 55b are electrically connected to the main electrode regions 55a of the selection transistors (SEL, SEL) provided in the pixels 3c and 3d.

[0165] The wiring 64c is connected to the second pixel block 15B. ２ The wiring 64d is electrically connected to the main electrode region 55b of the selection transistor Q (SEL, SEL) provided in each of the pixels 3c and 3d of the first pixel block 15B. １ The first pixel block 15B is electrically connected to the main electrode region 55b of the amplifier transistor AMP provided on the pixel 3b side of the two pixel transistors Q (AMP, AMP) provided in the pixel 3a of the first pixel block 15B. １The pixel 3b is electrically connected to the main electrode region 55b of the amplifier transistor AMP provided in the pixel 3b.

[0166] That is, in the readout circuit 17B of the second embodiment, three amplification transistors (AMP, AMP, AMP) are connected in parallel via wiring 64b, and two selection transistors (SEL, SEL) are connected in parallel via wiring 64c. The three amplification transistors (AMP, AMP, AMP) and the two selection transistors (SEL, SEL) are connected in series via wiring 64b.

[0167] <Autofocus> In an electronic device equipped with the solid-state imaging device 1B of this second embodiment, the signal charges of the two photoelectric conversion units 25, 25 provided in one photoelectric conversion region 22 are read out for each pixel 3, and the phase difference therebetween is detected.

[0168] When the focus is correct, there is no difference in the amount of signal charge accumulated in the two photoelectric conversion units 25 included in one photoelectric conversion region 22. In contrast, when the focus is not correct, there is a difference between the amount of signal charge Q1 accumulated in one of the two photoelectric conversion units 25 and the amount of signal charge Q2 accumulated in the other photoelectric conversion unit 25. When the focus is not correct, the electronic device performs an operation such as moving the objective lens so that Q1 and Q2 coincide with each other. This is autofocus.

[0169] <<Major Effects of the Second Embodiment>> As described above, the solid-state imaging device 1B according to the first embodiment has the first and second pixel blocks 15B arranged adjacent to each other in the Y direction in a plan view. １ and 15B ２ In the first pixel block 15B １ and the pixels 3a and 3b included in the second pixel block 15B. ２ Pixels 3c and 3d included in the pixel 3c are arranged adjacent to each other in the Y direction in plan view.

[0170] Then, the first pixel block 15B １ the amplifier transistor AMP included in the pixel 3a and the second pixel block 15B ２A pair of main electrode regions 55a and 55b (the drain region and source region of the amplifier transistor AMP, and the drain region and source region of the select transistor SEL) of each of the select transistors SEL included in the pixel 3c of the first pixel block 15B are arranged in this order in the Y direction. １ The floating diffusion region FD and the amplification transistor AMP included in the pixel 3a, and the second pixel block 15B ２ The selection transistor SEL and the floating diffusion region FD included in the pixel 3c are arranged in this order in the Y direction.

[0171] In addition, the first pixel block 15B １ the amplifier transistor AMP included in the pixel 3b and the second pixel block 15B ２ A pair of main electrode regions 55a and 55b (the drain region and source region of the amplifier transistor AMP, and the drain region and source region of the select transistor SEL) of each of the select transistors SEL included in the pixel 3d of the first pixel block 15B are arranged in this order in the Y direction. １ The floating diffusion region FD and the amplification transistor AMP included in the pixel 3b of the second pixel block 15B ２ The selection transistor SEL and the floating diffusion region FD included in the pixel 3d are arranged in this order in the Y direction.

[0172] With this configuration, the length of the wiring 64a that electrically connects the floating diffusion region FD and the gate electrode 54 of the amplification transistor AMP can be minimized.

[0173] In addition, the first pixel block 15B １ the main electrode regions 55b of the amplifier transistors AMP and AMP arranged in the pixels 3a and 3b of the second pixel block 15B; ２ This allows the wiring length of the wiring 64b that electrically connects the selection transistors SEL arranged in the pixels 3c and 3d to the main electrode regions 55a of the SEL.

[0174] In addition, the second pixel block 15B ２ the main electrode region 55b of the selection transistor SEL arranged in the pixel 3c of the second pixel block 15B; ２This makes it possible to minimize the length of the wiring 64c that electrically connects the main electrode region 55b of the selection transistor SEL arranged in the pixel 3d.

[0175] In addition, the first pixel block 15B １ the main electrode region 55b of the amplifier transistor AMP arranged in the pixel 3a of the first pixel block 15B; １ This makes it possible to minimize the length of the wiring 64d that electrically connects the main electrode region 55b of the amplifier transistor AMP arranged in the pixel 3b.

[0176] Therefore, in the solid-state imaging device 1B according to the second embodiment, it is also possible to reduce the wiring capacitance in the readout circuit 17B including the two amplification transistors AMP and the two selection transistors SEL that are used in parallel connection.

[0177] Also in the solid-state imaging device 1B according to the second embodiment, the wiring capacitance in the readout circuit 17B can be reduced, so that the pixels 3 can be miniaturized and high image quality can be achieved.

[0178] In the second embodiment described above, the pixel block 15B (first pixel block 15B) is a pixel block in which two pixel rows, each having two pixels 3 arranged in the Y direction, are arranged in the X direction. １ , second pixel block 15B ２ ), the present technology can also be applied to a pixel block including one pixel column in which a plurality of pixels 3 are arranged in the Y direction.

[0179] Furthermore, the select transistor SEL can be omitted as necessary. When the select transistor SEL is omitted, the source region of the amplifier transistor AMP is electrically connected to the vertical signal line 11 (VSL). Even when the select transistor SEL is omitted, the present technology can be applied.

[0180] In the second embodiment described above, as an example, a circuit configuration is used in which one readout circuit 17B is assigned to one pixel block 15B. However, the assignment of the readout circuits 17B is not limited to this second embodiment. For example, a circuit configuration may be used in which one readout circuit 17B is assigned to every two or more pixel blocks 15B.

[0181] In the second embodiment described above, as an example, the number of pixels 3 included in the pixel block 15B is set to four. However, the number of pixels 3 included in the pixel block 15B is not limited to this second embodiment.

[0182] 10 is a diagram showing a modification 2-1 according to the second embodiment of the present technology, and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 11 is a diagram showing a modification 2-1 according to the second embodiment of the present technology, and is a plan view schematically showing a pixel block.

[0183] 10, this modification 2-1 differs from the second embodiment in the number of amplifier transistors AMP included in the readout circuit 17B. That is, as shown in FIG. 10, the readout circuit 17B of this modification 2-1 includes four amplifier transistors AMP connected in parallel. And, as shown in FIG. 11, the amplifier transistors AMP are connected in parallel to the first pixel block 15B. １ Two dummy transistors DMY are arranged in each of the pixels 3 a and 3 b in the pixel block 15B. Since the pixel block 15B includes a dummy transistor DMY, by changing the connection between the wiring 64 a and the wiring 64 b, the dummy transistor DMY can be changed to an amplification transistor AMP, and the number of amplification transistors AMP can be increased.

[0184] The present technology can also be applied to this modification 2-1, and the same effects as those of the second embodiment described above can be obtained.

[0185] 12 is a diagram showing Modification 2-2 according to the second embodiment of the present technology, and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 13 is a diagram showing Modification 2-2 according to the second embodiment of the present technology, and is a plan view schematically showing the pixel block.

[0186] 12, this modification 2-2 differs from the second embodiment in the number of amplifier transistors AMP included in the readout circuit 17B. That is, as shown in FIG. 12, the readout circuit 17B of this modification 2-2 includes two amplifier transistors AMP connected in parallel. And, as shown in FIG. 13, the amplifier transistors AMP are included in the second block 15B. １ In the pixel block 15B, the amplifier transistor AMP can be changed to a dummy transistor DMY by changing the connection between the wiring 64a and the wiring 64b, and the number of amplifier transistors AMP can be reduced compared to the second embodiment.

[0187] The present technology can also be applied to this modification 2-2, and the same effects as those of the second embodiment described above can be obtained.

[0188] 14 is a diagram showing Modification 2-3 according to the second embodiment of the present technology, and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 15 is a diagram showing Modification 2-3 according to the second embodiment of the present technology, and is a plan view schematically showing the pixel block.

[0189] As shown in FIG. 14 , this modification 2-3 differs from the second embodiment in the number of select transistors SEL included in the readout circuit 17B. That is, as shown in FIG. 14 , the readout circuit 17B of this modification 2-3 includes three select transistors SEL connected in parallel. As shown in FIG. 15 , one select transistor SEL is arranged in pixel 3c, and two select transistors SEL are arranged in pixel 3d. Because the pixel block 15B includes dummy transistors DMY, the dummy transistors DMY can be changed to select transistors SEL by changing the connections of the wiring 64a and wiring 64b, and the number of select transistors SEL can be increased compared to the first embodiment.

[0190] The present technology can also be applied to this modified example 2-3, and the same effects as those of the second embodiment described above can be obtained.

[0191] <Modification 2-4> FIG. 16 is a diagram showing Modification 2-4 according to the second embodiment of the present technology, and is a plan view schematically showing a pixel block.

[0192] 16, this modification 2-4 differs from the second embodiment in the arrangement of the reset transistor RST included in the readout circuit 17B. That is, as shown in FIG. 16, the reset transistor RST of this modification 2-4 is arranged in the element formation region 21b of the pixel 3b. Because the pixel block 15B includes a dummy transistor DMY, by changing the connection between the wiring 64a and the wiring 64b, the dummy transistor DMY can be changed to the reset transistor RST, and the arrangement of the reset transistor RST can be changed.

[0193] The present technology can also be applied to this modified example 2-4, and the same effects as those of the second embodiment described above can be obtained.

[0194] 17 is a diagram showing Modification 2-5 according to the second embodiment of the present technology, and is an equivalent circuit diagram showing a pixel block and a readout circuit. FIG. 18 is a diagram showing Modification 2-5 according to the second embodiment of the present technology, and is a plan view schematically showing the pixel block.

[0195] As shown in FIG. 17 , this modification 2-5 differs from the second embodiment in the number of reset transistors RST included in the readout circuit 17B. That is, as shown in FIG. 17 , the readout circuit 17B of this modification 2-5 includes two reset transistors RSTL connected in parallel. As shown in FIG. 18 , one reset transistor RST is provided for each of pixels 3c and 3d. Because the pixel block 15B includes a dummy transistor DMY, by changing the connection of the wiring 64a and the wiring 64b, the dummy transistor DMY can be changed to a reset transistor RST, thereby increasing the number of reset transistors RST compared to the first embodiment.

[0196] The present technology can also be applied to this modified example 2-5, and the same effects as those of the second embodiment described above can be obtained.

[0197] 19 is a diagram showing Modification 2-6 according to the second embodiment of the present technology, and is an equivalent circuit diagram showing a pixel block and a readout circuit. Fig. 20 is a diagram showing Modification 2-6 according to the second embodiment of the present technology, and is a plan view schematically showing the pixel block.

[0198] As shown in FIG. 19, this modification 2-6 differs from the second embodiment in the configuration of the readout circuit 17B.

[0199] 19, the readout circuit 17B of this modified example 2-6 further includes a switching transistor FDG as a pixel transistor, and the number of amplification transistors AMP is two.

[0200] The switching transistor FDG has a drain region electrically connected to the source region of the reset transistor RST, and a source region electrically connected to each of the gate electrodes of the two amplification transistors AMP and to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d). The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 10 shown in FIG. 2. The switching transistor FDG controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplification transistor AMP. The reset transistor RST of this modification 2-6 has a source region electrically connected to the drain region of the switching transistor FDG.

[0201] 20, the reset transistor RST and switching transistor FDG of this modification 2-6 are each provided in the element formation region 21b of pixel 3b. Because pixel block 15B includes a dummy transistor DMY, the dummy transistor DMY can be changed to the reset transistor RST by changing the connection between wiring 64a and wiring 64b. Furthermore, the amplification transistor AMP can be changed to the switching transistor FDG by changing the connection between wiring 64a and wiring 64b.

[0202] In this modification 2-6, the main electrode region 55a of the reset transistor RST and the main electrode region 55a of the switching transistor FDG are electrically connected via a wiring 64e.

[0203] The present technology can also be applied to this modified example 2-6, and the same effects as those of the second embodiment described above can be obtained.

[0204] <Modification 2-7> FIG. 21 is a diagram showing Modification 2-7 according to the second embodiment of the present technology, and is a plan view schematically showing a pixel block.

[0205] 21, in this modified example 2-7, two transfer transistors TR are provided in each of the two element formation regions 21a included in one pixel 3. That is, in each pixel 3 of this modified example 2-7, two transfer transistors TR are provided in each of the two photoelectric conversion cells (22L, 22R).

[0206] The present technology can also be applied to this modified example 2-7, and the same effects as those of the second embodiment described above can be obtained.

[0207] <Modification 2-8> FIG. 22 is a diagram showing Modification 2-8 according to the second embodiment of the present technology, and is a plan view schematically showing a pixel block.

[0208] As shown in FIG. 22, this modification 2-8 differs from the modification in that the planar shape of the element formation region 21b is different.

[0209] That is, the element formation region of the second embodiment described above has an H-shape in plan view, including a first portion extending in the X direction in plan view and second portions extending in the Y direction on both sides of the first portion in the X direction.

[0210] In contrast, as shown in FIG. 21, the element formation region 21b of this modified example 2-8 has a C-shaped planar shape including a first portion extending in the X direction in a planar view and a second portion extending in the Y direction on both sides of the first portion in the X direction.

[0211] The present technology can also be applied to this modified example 2-8, and the same effects as those of the second embodiment described above can be obtained.

[0212] <Modification 2-9> FIG. 23 is a diagram showing Modification 2-9 according to the second embodiment of the present technology, and is a plan view schematically showing a pixel block.

[0213] As shown in FIG. 23, in this modification 2-9, the floating diffusion region FD is arranged so as to contact the outer peripheral edge of the element formation region 21a in a plan view, and although not shown in detail, the floating diffusion region FD and the contact electrode are electrically and mechanically connected at the side portion of the element formation region 21a.

[0214] The present technology can also be applied to this modified example 2-9, and the same effects as those of the second embodiment described above can be obtained.

[0215] <Modification 2-10> FIG. 24 is a diagram showing Modification 2-9 according to the second embodiment of the present technology, and is a plan view schematically showing a pixel block.

[0216] 24, in this modification 2-10, the planar shape of the element formation region 21b is rectangular. １ one of the pair of main electrode regions 55a and 55b of the amplifier transistor AMP included in the pixel 3a of the second pixel block 15B ２ The pixel 3c includes a selection transistor SEL and a main electrode region 55a, which is also used as one of the pair of main electrode regions 55a and 55b.

[0217] In addition, in this modified example 2-10, the first pixel block 15B １ one of the pair of main electrode regions 55a and 55b of the amplifier transistor AMP included in the pixel 3b of the second pixel block 15B ２ The pixel 3d also serves as one of the pair of main electrode regions 55a and 55b of the selection transistor SEL included in the pixel 3d.

[0218] In addition, in this modified example 2-10, the first pixel block 15B １ one of the pair of main electrode regions 55a and 55b of the dummy transistor DMY included in the pixel 3b of the second pixel block 15B ２ The region 55a also serves as one of the pair of main electrode regions 55a and 55b of the reset transistor RST included in the pixel 3d.

[0219] The present technology can also be applied to this modified example 2-10, and the same effects as those of the above-described embodiment 2 can be obtained. Note that, although not shown in detail, in this modified example 2-10, as in the first embodiment, the pixels 3 are separated from each other by an isolation region including a shallow isolation region 31 and a deep isolation region 41, and therefore the planar shapes of the element formation regions 21 a and 21 b are rectangular, as shown in FIG.

[0220] Third Embodiment <Application Example to Electronic Devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0221] FIG. 25 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a third embodiment of the present technology.

[0222] 25, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging devices 1A and 1B according to the first and second embodiments of the present technology and the modified example of the second embodiment are used in an electronic device (for example, a camera) as the solid-state imaging device 101.

[0223] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause charge transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0224] With this configuration, the wiring capacitance can be reduced in the solid-state imaging device 101, and the image quality performance of the electronic device 100 of the fifth embodiment can be improved.

[0225] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0226] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0227] Note that the present technology may be configured as follows: (1) A photodetector device including a pixel array unit in which a plurality of pixels are arranged in an array in a planar view, the pixel array unit including first and second pixels lined up adjacent to each other in one direction in a planar view, the first pixels including a first photoelectric conversion unit, a first charge retention unit that retains signal charges photoelectrically converted by the first photoelectric conversion unit, and a first pixel transistor including a gate electrode and a pair of main electrode regions, the second pixels including a second photoelectric conversion unit, a second charge retention unit that retains signal charges photoelectrically converted by the second photoelectric conversion unit, and a second pixel transistor including a gate electrode and a pair of main electrode regions, the pair of main electrode regions of each of the first and second pixel transistors are lined up in the one direction, and the first charge retention unit, the pixel first transistor, the pixel second transistor, and the second charge retention unit are lined up in this order in the one direction. (2) The photodetector according to (1), further comprising: a first readout circuit that reads out the signal charge held in the first charge holding unit of the first pixel and outputs a pixel signal based on the readout signal charge; and a second readout circuit that reads out the signal charge held in the second charge holding unit of the second pixel and outputs a pixel signal based on the readout signal charge, wherein the first readout circuit includes each of the first and second pixel transistors. (3) The photodetector according to (2), wherein the first pixel transistor is an amplification transistor, and the second pixel transistor is a selection transistor. (4) The photodetector according to any of (1) to (3), wherein the pixel array unit further includes a first pixel block including the first pixel and a second pixel block including the second pixel. (5) The photodetector according to any of (1) to (4), wherein the one direction is a first direction, and the first and second pixels are repeatedly arranged in a second direction intersecting the first direction in a plan view.(6) The photodetector according to (5) above, wherein the pair of main electrode regions of the first pixel transistor include a first source region and a first drain region, the main electrode region of the second pixel transistor includes a second source region and a second drain region, and the first source region, first drain region, second source region, and second drain region are aligned in this order in the first direction. (7) The photodetector according to any of (1) to (6) above, wherein the first charge holding portion and the gate electrode of the first pixel transistor are electrically connected via a first wiring, and one of the pair of main electrode regions of the first pixel transistor and one of the pair of main electrode regions of the second pixel transistor are electrically connected via a second wiring. (8) The photodetector according to any one of claims 1 to 6, wherein the first charge holding portion and the gate electrode of the first pixel transistor are electrically connected via a wiring, and one of the pair of main electrode regions of the first pixel transistor and one of the pair of main electrode regions of the second pixel transistor are shared. (9) The photodetector according to any one of claims 1 to 8, wherein the first pixel further has a first transfer transistor that transfers signal charges photoelectrically converted in the first photoelectric conversion portion to the first charge holding portion, and the second pixel further has a second transfer transistor that transfers signal charges photoelectrically converted in the second photoelectric conversion portion to the second charge holding portion. (10) A photodetector device comprising a first charge retention portion, a first pixel transistor, a second pixel transistor, and a second charge retention portion, which are arranged in this order in one direction on a semiconductor layer, each of the first and second pixel transistors including a gate electrode and a pair of main electrode regions, and the pair of main electrode regions of each of the first and second pixel transistors being aligned in one direction.(11) A photodetector device comprising: a pixel array section in which a plurality of pixels are arranged in an array in a planar view; the pixel array section includes first and second pixels arranged adjacent to each other in a first direction in a planar view; the first pixel has a first photoelectric conversion section, a second photoelectric conversion section, a first charge retention section, a second charge retention section, a first pixel transistor, and a second pixel transistor; the second pixel has a third photoelectric conversion section, a fourth photoelectric conversion section, a third charge retention section, a fourth charge retention section, a third pixel transistor, and a fourth pixel transistor; the first pixel and the second pixel belong to different pixel sharing units; source / drain regions of the first and third pixel transistors are arranged side by side in the first direction; and the first charge retention section, the first pixel transistor, the third pixel transistor, and the third charge retention section are arranged side by side in this order in the first direction. (12) The photodetector according to (11), further comprising: a first readout circuit that reads out signal charges held in the first and second charge holding units of the first pixel and outputs a pixel signal based on the readout signal charges; and a second readout circuit that reads out signal charges held in the third and fourth charge holding units of the second pixel and outputs a pixel signal based on the readout signal charges, wherein the first readout circuit includes each of the first and third pixel transistors. (13) The photodetector according to (12), wherein the first pixel transistor is an amplification transistor, and the third pixel transistor is a selection transistor. (14) The photodetector according to any of (11) to (13), wherein the pixel array unit further includes a first pixel block including the first pixel and a second pixel block including the second pixel. (15) The photodetector according to any of (11) to (14), wherein each of the first and second pixels is repeatedly arranged in a second direction intersecting the first direction in a plan view. (16) The photodetector device according to any one of (11) to (15), wherein the first and second charge retention portions and the gate electrodes of the first and third pixel transistors are electrically connected via a first wiring, and the source region of the first pixel transistor and the drain region of the third pixel transistor are electrically connected via a second wiring.(17) The photodetector device according to any one of (1) to (16), wherein the first and second charge retention portions and the gate electrodes of the first and second pixel transistors are electrically connected via wiring, the source region of the first pixel transistor and the drain region of the second pixel transistor are shared, and the source region of the second pixel transistor and the drain region of the fourth pixel transistor are shared. (18) The photodetector device according to any one of (11) to (17), wherein the first pixel further comprises a first transfer transistor that transfers the signal charge photoelectrically converted in the first photoelectric conversion unit to the first charge holding unit, and a transfer transistor that transfers the signal charge photoelectrically converted in the second photoelectric conversion unit to the second charge holding unit, and the second pixel further comprises a third transfer transistor that transfers the signal charge photoelectrically converted in the third photoelectric conversion unit to the third charge holding unit, and a fourth transfer transistor that transfers the signal charge photoelectrically converted in the fourth photoelectric conversion unit to the fourth charge holding unit.

[0228] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0229] DESCRIPTION OF SYMBOLS 1A, 1B Solid-state imaging device 2... Semiconductor chip 2A... Pixel array section 2B... Peripheral section 3, 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h... Pixels (sensor pixels) 4... Vertical drive circuit 5... Column signal processing circuit 6... Horizontal drive circuit 7... Output circuit 8... Control circuit 10... Pixel drive line 11... Vertical signal line 12... Horizontal signal line 13... Logic circuit 14... Bonding pad 15A, 15A １ , 15A ２ , 15B, 15B １ , 15B ２ ...Pixel blocks 16A, 16A １ , 16A ２ ...Shared pixel blocks 17A, 17A１ , 17A ２ , 17B...readout circuit 18A...circuit block 21...semiconductor layers 21a, 21a １ , 21a ２ , 21b...element formation region 22...photoelectric conversion region 22L, 22R...photoelectric conversion cell 23...p-type well region 24...n-type semiconductor region 25...photoelectric conversion section 31...shallow isolation region 41...deep isolation region 52...gate insulating film 53...gate electrode 54...gate electrode 55a, 55b...main electrode region 61...multilayer wiring layer 62...interlayer insulating film 63a, 63b, 63c, 63d...contact electrode 64a, 64b, 64c, 64d...wiring 100...electronic device 101...solid-state imaging device 102...optical lens (optical system) 103...shutter device 104...drive circuit 105...signal processing circuit 106...incident light AMP...amplifying transistor FD...n-type floating diffusion region FDG...switching transistor Q...pixel transistor RST...reset transistor SEL...selection transistor S1 ...first surface portion S2...second surface portion TR...transfer transistor

Claims

1. A photodetector comprising a pixel array section in which a plurality of pixels are arranged in an array in a planar view, the pixel array section including first and second pixels lined up adjacent to each other in one direction in a planar view, the first pixels having a first photoelectric conversion section, a first charge retention section that retains signal charges photoelectrically converted by the first photoelectric conversion section, and a first pixel transistor including a gate electrode and a pair of main electrode regions, the second pixels having a second photoelectric conversion section, a second charge retention section that retains signal charges photoelectrically converted by the second photoelectric conversion section, and a second pixel transistor including a gate electrode and a pair of main electrode regions, the pair of main electrode regions of each of the first and second pixel transistors being lined up in the one direction, and the first charge retention section, the first pixel transistor, the second pixel transistor, and the second charge retention section being lined up in this order in the one direction.

2. The photodetection device described in claim 1, further comprising: a first readout circuit that reads out the signal charge held in the first charge holding section of the first pixel and outputs a pixel signal based on the readout signal charge; and a second readout circuit that reads out the signal charge held in the second charge holding section of the second pixel and outputs a pixel signal based on the readout signal charge, wherein the first readout circuit includes each of the first and second pixel transistors.

3. The photodetector device according to claim 2, wherein the first pixel transistor is an amplification transistor, and the second pixel transistor is a selection transistor.

4. The photodetector device according to claim 1, wherein the pixel array section further includes a first pixel block including the first pixel and a second pixel block including the second pixel.

5. The photodetector device according to claim 1, wherein the one direction is a first direction, and the first and second pixels are repeatedly arranged in a second direction that intersects with the first direction in a plan view.

6. The photodetector device according to claim 5, wherein the pair of main electrode regions of the first pixel transistor include a first source region and a first drain region, the main electrode region of the second pixel transistor includes a second source region and a second drain region, and the first source region, first drain region, second source region, and second drain region are arranged in this order in the first direction.

7. The photodetector device according to claim 1, wherein the first charge holding portion and the gate electrode of the first pixel transistor are electrically connected via a first wiring, and one of the pair of main electrode regions of the first pixel transistor and one of the pair of main electrode regions of the second pixel transistor are electrically connected via a second wiring.

8. The photodetector according to claim 1, wherein the first charge holding section and the gate electrode of the first pixel transistor are electrically connected via wiring, and one of the pair of main electrode regions of the first pixel transistor and one of the pair of main electrode regions of the second pixel transistor are shared.

9. The photodetector according to claim 1, wherein the first pixel further comprises a first transfer transistor that transfers the signal charge photoelectrically converted in the first photoelectric conversion unit to the first charge storage unit, and the second pixel further comprises a second transfer transistor that transfers the signal charge photoelectrically converted in the second photoelectric conversion unit to the second charge storage unit.

10. A photodetector device comprising a first charge retention portion, a first pixel transistor, a second pixel transistor, and a second charge retention portion arranged in this order in one direction on a semiconductor layer, wherein each of the first and second pixel transistors includes a gate electrode and a pair of main electrode regions, and the pair of main electrode regions of each of the first and second pixel transistors are aligned in one direction.

11. A photodetector comprising a pixel array section in which a plurality of pixels are arranged in an array in a planar view, the pixel array section including first and second pixels arranged adjacent to each other in a first direction in a planar view, the first pixel having a first photoelectric conversion section, a second photoelectric conversion section, a first charge retention section, a second charge retention section, a first pixel transistor, and a second pixel transistor, the second pixel having a third photoelectric conversion section, a fourth photoelectric conversion section, a third charge retention section, a fourth charge retention section, a third pixel transistor, and a fourth pixel transistor, the first pixel and the second pixel belonging to different pixel sharing units, the source / drain regions of the first and third pixel transistors being arranged in the first direction, and the first charge retention section, the first pixel transistor, the third pixel transistor, and the third charge retention section being arranged in this order in the first direction.

12. The photodetection device described in claim 11, further comprising: a first readout circuit that reads out the signal charges held in the first and second charge holding units of the first pixel and outputs a pixel signal based on the read-out signal charges; and a second readout circuit that reads out the signal charges held in the third and fourth charge holding units of the second pixel and outputs a pixel signal based on the read-out signal charges, wherein the first readout circuit includes each of the first and third pixel transistors.

13. The photodetector device according to claim 12, wherein the first pixel transistor is an amplification transistor, and the third pixel transistor is a selection transistor.

14. The photodetector device according to claim 11, wherein the pixel array section further includes a first pixel block including the first pixel and a second pixel block including the second pixel.

15. The photodetector device according to claim 11, wherein the first and second pixels are repeatedly arranged in a second direction intersecting the first direction in a plan view.

16. The photodetector device according to claim 11, wherein the first and second charge retention portions and the gate electrodes of the first and third pixel transistors are electrically connected via a first wiring, and the source region of the first pixel transistor and the drain region of the third pixel transistor are electrically connected via a second wiring.

17. The photodetector device according to claim 11, wherein the first and second charge retention portions and the gate electrodes of the first and second pixel transistors are electrically connected via wiring, the source region of the first pixel transistor and the drain region of the second pixel transistor are shared, and the source region of the second pixel transistor and the drain region of the fourth pixel transistor are shared.

18. The photodetector device of claim 11, wherein the first pixel further comprises a first transfer transistor that transfers the signal charge photoelectrically converted in the first photoelectric conversion unit to the first charge holding unit, and a transfer transistor that transfers the signal charge photoelectrically converted in the second photoelectric conversion unit to the second charge holding unit, and the second pixel further comprises a third transfer transistor that transfers the signal charge photoelectrically converted in the third photoelectric conversion unit to the third charge holding unit, and a fourth transfer transistor that transfers the signal charge photoelectrically converted in the fourth photoelectric conversion unit to the fourth charge holding unit.

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