Solid-state imaging element and electronic device

Abstract

The present disclosure is related to a solid-state imaging element and an electronic device configured to enable the further miniaturizing of pixel size. A first series active area is a single active area provided by forming an active area constituting a first gate and an active area constituting a second gate in a continuous linear shape and arranging the first gate and the second gate in series; and a second series active area is a single active area provided by forming an active area constituting a second amplification gate and an active area constituting a selection gate in a continuous linear shape and arranging the second amplification gate and the selection gate in series. The first and second series active areas are arranged parallel to each other. The present technology can be applied to, for example, a Voltage-Domain global shutter type CMOS image sensor.

Description

Solid-state imaging device and electronic device

[0001] The present disclosure relates to a solid-state imaging device and an electronic device, and more particularly to a solid-state imaging device and an electronic device that enable further miniaturization of pixel size.

[0002] In recent years, there has been a demand for miniaturization of pixel size in global shutter CMOS (Complementary Metal Oxide Semiconductor) image sensors, which do not cause focal plane distortion during imaging, as the number of pixels increases.In addition, the voltage-domain method has been proposed as one method for achieving simultaneous charge accumulation in global shutter CMOS image sensors.

[0003] For example, Patent Document 1 discloses a voltage-domain global shutter CMOS image sensor that uses a transistor in the first-stage source follower.

[0004] Japanese Patent Application Laid-Open No. 2022-45912

[0005] Incidentally, when considering a configuration using a capacitive element in the first-stage source follower in a voltage-domain global shutter CMOS image sensor, there is a demand for miniaturizing the pixel size by improving layout efficiency.

[0006] The present disclosure has been made in view of such circumstances, and aims to make it possible to further reduce pixel size.

[0007] a first capacitor having one end connected to the first node and holding a voltage of a pixel signal at a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal at a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, the third capacitor constituting a source follower circuit together with a first amplifier gate of the pixel circuit; a second amplifier gate that generates a pixel signal according to charges accumulated at a second node connected to a gate electrode of the second amplifier gate; a select gate that selects a pixel to output the pixel signal generated by the second amplifier gate; and a pixel having a sample-and-hold circuit having at least a first gate connecting two nodes, a fourth node serving as a connection point with the other end of the second capacitor, a second gate connecting the second node, and a third gate resetting charges accumulated in the second node, the third node, and the fourth node, wherein the active area constituting the first gate and the active area constituting the second gate are formed in a continuous straight line, and a first series active area which is a single active area provided by arranging the first gate and the second gate in series, and a second series active area which is a single active area provided by arranging the second amplifier gate and the active area constituting the select gate in series are arranged in parallel to each other.

[0008] An electronic device according to one aspect of the present disclosure includes a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding a voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal of a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and constituting a source follower circuit together with a first amplification gate of the pixel circuit; a second amplification gate that generates a pixel signal according to charges accumulated at a second node connected to a gate electrode; a selection gate that selects a pixel to output the pixel signal generated by the second amplification gate; a third node that is a connection point with the other end of the first capacitor; and the second gate and the active area constituting the second gate are formed in a continuous straight line, and a first series active area is a single active area provided by arranging the first gate and the second gate in series, and the active area constituting the second amplifying gate and the active area constituting the selection gate are formed in a continuous straight line, and a second series active area is a single active area provided by arranging the second amplifying gate and the selection gate in series, and the ...

[0009] In one aspect of the present disclosure, a solid-state imaging device includes a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding a voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and constituting a source follower circuit together with a first amplification gate of the pixel circuit. a second amplifier gate connected to a gate electrode of the first capacitor for generating a pixel signal corresponding to the charge accumulated at a second node; a selector gate for selecting a pixel to output the pixel signal generated by the second amplifier gate; a third node serving as a connection point with the other end of the first capacitor, a first gate connecting the second node, a fourth node serving as a connection point with the other end of the second capacitor, a second gate connecting the second node, and a third gate for resetting the charge accumulated at the second node, the third node, and the fourth node. The active area constituting the first gate and the active area constituting the second gate are formed in a continuous straight line, and a first series active area is a single active area formed by arranging the first gate and the second gate in series, and the active area constituting the second amplification gate and the active area constituting the selection gate are formed in a continuous straight line, and a second series active area is a single active area formed by arranging the second amplification gate and the selection gate in series, and are arranged in parallel to each other.

[0010] 1 is a block diagram showing a configuration example of an embodiment of an imaging device to which the present technology is applied. FIG. 1 is a circuit diagram showing a first configuration example of a pixel. FIG. 2 is a diagram showing a first cross-sectional configuration example of a solid-state imaging element. FIG. 3 is a diagram showing a second cross-sectional configuration example of a solid-state imaging element. FIG. 4 is a diagram showing an example of a first planar layout of a pixel. FIG. 5 is a diagram showing an example of a second planar layout of a pixel. FIG. 6 is a diagram showing an example of a first planar layout of pixels arranged in a 2×2 array. FIG. 7 is a diagram showing an example of a second planar layout of pixels arranged in a 2×2 array. FIG. 8 is a diagram showing an example of a planar layout of an MIM layer of pixels arranged in a 2×2 array. FIG. 9 is a diagram showing an example of a third planar layout of pixels arranged in a 2×2 array. FIG. 10 is a circuit diagram showing a configuration example of a four-pixel sharing structure of the pixel of FIG. 2. FIG. 11 is a diagram showing an example of a fifth planar layout of pixels arranged in a 2×2 array with a four-pixel sharing structure. FIG. 12 is a diagram showing an example of a sixth planar layout of pixels arranged in a 2×2 array with a four-pixel sharing structure. FIG. 13 is a diagram showing an example of a seventh planar layout of pixels arranged in a 2×2 array with a four-pixel sharing structure. FIG. 14 is a diagram showing an example of an eighth planar layout of pixels arranged in a 2×1 array with a two-pixel sharing structure. 19A and 19B are diagrams showing an example of a ninth planar layout of pixels arranged in a 2×1 arrangement with a two-pixel sharing structure; FIG. 19B are diagrams showing an example of a tenth planar layout of pixels arranged in a 2×1 arrangement with a two-pixel sharing structure; FIG. 19C are circuit diagrams showing a second configuration example of pixels; FIG. 19D are circuit diagrams showing an example of a four-pixel sharing structure of the pixel of FIG. 19A are diagrams showing an example of an eleventh planar layout of pixels arranged in a 2×2 arrangement with a four-pixel sharing structure; FIG. 19E are diagrams showing an example of a twelfth planar layout of pixels arranged in a 2×2 arrangement with a four-pixel sharing structure; FIG. 19F are diagrams showing an example of a thirteenth planar layout; FIG. 19G are diagrams showing an example of a third configuration example of pixels; FIG. 19H are diagrams showing an example of a fourteenth planar layout; FIG. 19H are diagrams showing an example of a fifteenth planar layout; FIG. 19I are diagrams showing an example of a sixteenth planar layout; FIG. 19I are diagrams showing an example of a seventeenth planar layout; FIG. 19I are diagrams showing an example of an eighteenth planar layout; FIG. 19I are diagrams showing an example of a nineteenth planar layout;16 is a circuit diagram showing a tenth configuration example of a pixel. FIG. 17 is a diagram showing a usage example using an image sensor.

[0011] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

[0012] <Configuration Example of Imaging Apparatus> FIG. 1 is a block diagram showing a configuration example of an embodiment of an imaging apparatus to which the present technology is applied.

[0013] 1, the imaging device 11 is configured to include an optical system 12, a solid-state imaging element 13, an imaging control circuit 14, a signal processing circuit 15, a monitor 16, and a memory 17. For example, the imaging device 11 can be applied to various electronic devices such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions, and is capable of capturing still images and moving images.

[0014] The optical system 12 is composed of one or more lenses, and collects incident light from the subject that enters the imaging device 11, directs it to the solid-state imaging element 13, and forms an image of the subject on the light-receiving surface (sensor section) of the solid-state imaging element 13.

[0015] The solid-state image sensor 13 captures an image of the subject formed on the light receiving surface via the optical system 12 under the control of the image capture control circuit 14 , and supplies an image signal obtained by the image capture to the signal processing circuit 15 .

[0016] The imaging control circuit 14 controls imaging by the solid-state imaging element 13. For example, the imaging control circuit 14 supplies the solid-state imaging element 13 with an imaging control signal including a vertical synchronization signal VSYNC, which is a periodic signal with a constant frequency (e.g., 60 Hz) indicating the timing of imaging.

[0017] The signal processing circuit 15 performs various signal processing on the image signal output from the solid-state image sensor 13 , and supplies the image data obtained as a result of the processing to a monitor 16 or a memory 17 .

[0018] The monitor 16 displays an image in accordance with the image data supplied from the signal processing circuit 15, and the memory 17 stores (records) the image data supplied from the signal processing circuit 15. If the solid-state imaging device 13 has a communication interface, the image data may be transmitted to an external device.

[0019] The solid-state imaging device 13 includes a pixel array section 21, a timing control circuit 22, a vertical scanning circuit 23, a digital-to-analog converter (DAC) 24, a load complementary metal oxide (MOS) circuit block 25, and a column signal processing circuit 26.

[0020] A plurality of pixels 31 are arranged in an array in the pixel array unit 21. Hereinafter, a group of pixels 31 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 31 arranged in a direction perpendicular to the rows will be referred to as a "column." In the pixel array unit 21, each pixel 31 photoelectrically converts incident light to generate an analog pixel signal, and the pixel signals are output in parallel in the column direction in order for each row selected by the vertical scanning circuit 23.

[0021] The timing control circuit 22 controls the operation timing of each of the vertical scanning circuit 23 , the DAC 24 , and the column signal processing circuit 26 in synchronization with the vertical synchronization signal VSYNC supplied from the imaging control circuit 14 .

[0022] The vertical scanning circuit 23 sequentially selects rows so as to scan in the vertical direction, and supplies various control signals to the pixels 31 provided in each selected row, causing the pixels 31 to output analog pixel signals.

[0023] The DAC 24 generates a sawtooth ramp signal by DA conversion and supplies it to the column signal processing circuit 26 .

[0024] In the load MOS circuit block 25, a MOS transistor (for example, the constant current source 44 in FIG. 2) that supplies a constant current is provided for each column.

[0025] The column signal processing circuit 26 refers to the ramp signal supplied from the DAC 24, performs AD (Analog to Digital) conversion on the analog pixel signals output from the pixels 31 via the load MOS circuit block 25, and removes noise by performing CDS (Correlated Double Sampling) processing on the digital pixel signals.

[0026] Then, image data obtained as a result of the column signal processing circuit 26 performing signal processing on the pixel signals is output from the solid-state imaging device 13 .

[0027] <First Configuration Example of Pixel> A first configuration example of the pixel 31 will be described with reference to FIGS.

[0028] FIG. 2 shows an example of a circuit diagram of a pixel 31 according to the first configuration example.

[0029] As shown in FIG. 2 , the pixel 31 is composed of a pixel circuit 41 that generates a pixel signal corresponding to the amount of incident light, and a sample-and-hold circuit 42 that samples the pixel signal generated in the pixel circuit 41 and holds it at a constant level of voltage, and is connected to a constant current source 44 via a vertical signal line 43.

[0030] The pixel circuit 41 includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplifier gate 56, and a switch gate 57. The sample-and-hold circuit 42 includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplifier gate 66, a selection gate 67, and a capacitor 68. When the pixel 31 is configured using a semiconductor substrate with a two-layer structure, the pixel circuit 41 is provided on the first semiconductor substrate layer, and the sample-and-hold circuit 42 is provided on the second semiconductor substrate layer. In FIG. 2 , a rectangle illustrated between the pixel circuit 41 and the sample-and-hold circuit 42 represents a connection point where the two semiconductor substrate layers are connected (e.g., a Cu-Cu connection).

[0031] The anode of the photoelectric conversion unit 51 is grounded, and the cathode of the photoelectric conversion unit 51 is connected to the source of the transfer gate 52. The drain of the transfer gate 52 is connected to the source of the FD gate 53 and the gate electrode of the amplifier gate 56, and this connection point is called an FD (Floating Diffusion) node. The drain of the FD gate 53 is connected to the source of the reset gate 54 and one end of the capacitor 55. The drain of the reset gate 54 is connected to a power supply VDD, and the other end of the capacitor 55 is grounded. The drain of the amplifier gate 56 is connected to a power supply AMD, and the source of the amplifier gate 56 is connected to the drain of the switch gate 57. The source of the switch gate 57 is connected to a capacitor 68 of the sample-and-hold circuit 42.

[0032] The connection point between one end of the capacitor 61 and one end of the capacitor 62 is called the V1 node, and the source of the switch gate 57 and one end of the capacitor 68 are connected to this V1 node. The other end of the capacitor 61 is connected to the source of the SR gate 63, and the other end of the capacitor 62 is connected to the source of the SD gate 64. The drains of the SR gate 63 and the SD gate 64 are connected to this connection point, which is called the V2 node. The gate electrode of the amplifier gate 66 and the source of the RB gate 65 are connected to this V2 node. The drain of the RB gate 65 is connected to the power supply VREG, and the drain of the amplifier gate 66 is connected to the power supply VDD. The source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43. The other end of the capacitor 68 is connected to a signal line that supplies a ramp signal RAMP.

[0033] The photoelectric conversion unit 51 is configured by a photodiode that photoelectrically converts incident light that is incident on the pixel 31, and accumulates the electric charge generated by the photoelectric conversion.

[0034] The transfer gate 52 is driven in accordance with a control signal TRG supplied from the vertical scanning circuit 23, and transfers the charge accumulated in the photoelectric conversion unit 51 to the FD node at the timing when the transfer gate 52 is turned on.

[0035] The FD gate 53 is driven in accordance with a control signal FDG supplied from the vertical scanning circuit 23, and connects a capacitor 55 to the FD node while the transfer gate 52 is on. For example, by connecting the capacitor 55 to the FD node via the FD gate 53, it is possible to increase the storage capacitance that holds the charge transferred from the photoelectric conversion unit 51, and to perform HDR (High Dynamic Range) imaging.

[0036] The reset gate 54 is driven in accordance with a control signal RST supplied from the vertical scanning circuit 23, and when the reset gate 54 is turned on, the charge stored in the capacitor 55 and the charge stored in the FD node via the FD gate 53 are discharged to the power supply VDD and reset.

[0037] The capacitor 55 holds the charge transferred from the photoelectric conversion unit 51 together with the FD node while it is connected to the FD node via the FD gate 53 .

[0038] The amplification gate 56 generates a pixel signal according to the charge stored in the FD node or the charge stored in the FD node and the capacitor 55. The amplification gate 56 forms a source follower circuit together with a capacitor 68 connected via a switch gate 57, and outputs the generated pixel signal to the V1 node.

[0039] The switch gate 57 is driven in accordance with a control signal SW supplied from the vertical scanning circuit 23, and connects the amplifier gate 56 to the V1 node while the switch gate 57 is on. Then, the pixel signal generated in the amplifier gate 56 is output to the V1 node via the switch gate 57.

[0040] The capacitor 61 holds the voltage of the pixel signal (hereinafter also referred to as a P-phase signal) at the reset level at which the FD node is reset, in a signal holding capacitance C. A signal holding node that holds a charge corresponding to the P-phase signal between the capacitor 61 and the SR gate 63 is called a VCR node.

[0041] The capacitor 62 holds, in a signal holding capacitance C, the voltage of a pixel signal (hereinafter also referred to as a D-phase signal) at a pixel signal level corresponding to the charge generated in the photoelectric conversion unit 51 and held in the FD node (or the FD node and capacitor 55). A signal holding node that holds the charge corresponding to the D-phase signal between the capacitor 62 and the SD gate 64 is referred to as a VCD node.

[0042] The SR gate 63 is driven in accordance with a control signal SR supplied from the vertical scanning circuit 23, and when the SR gate 63 is turned on, it connects the VCR node to the V2 node, causing the charge corresponding to the P-phase signal held in the VCR node to be held by the VCR node and the V2 node.

[0043] The SD gate 64 is driven in accordance with a control signal SD supplied from the vertical scanning circuit 23, and when the SD gate 64 is turned on, it connects the VCD node to the V2 node, causing the charge corresponding to the D-phase signal that was held in the VCD node to be held by the VCD node and the V2 node.

[0044] The RB gate 65 is driven in accordance with a control signal RB supplied from the vertical scanning circuit 23, and when the RB gate 65 is turned on, the charges held by the VCR node and the V2 node, as well as the charges held by the VCD node and the V2 node, are discharged to the power supply VREG and reset.

[0045] The amplifier gate 66 generates a P-phase signal, which is a pixel signal corresponding to the charges held by the VCR node and the V2 node, and a D-phase signal, which is a pixel signal corresponding to the charges held by the VCD node and the V2 node. The amplifier gate 66 forms a source follower circuit together with the constant current source 44 connected via a selection gate 67, and outputs the P-phase signal and the D-phase signal to the vertical signal line 43.

[0046] The selection gate 67 is driven in accordance with a control signal SEL supplied from the vertical scanning circuit 23, and while the row is selected as the row from which pixel signals are to be read out and the selection gate 67 is turned on, the amplification gate 66 is connected to the vertical signal line 43. Then, the pixel signals (P-phase signal and D-phase signal) generated in the amplification gate 66 are read out to the vertical signal line 43 via the selection gate 67.

[0047] Capacitor 68 is used as a constant current source that sinks a constant current into the V1 node as charge accumulates at a constant rate in accordance with ramp signal RAMP.

[0048] The solid-state imaging device 13 can employ an MIM (Metal Insulator Metal) structure in which an insulator is sandwiched between upper and lower electrodes as the capacitors 61, 62, and 68. The global shutter solid-state imaging device 13 can further improve image quality by employing a Capacitive-Current-Source method in which the MIM-structured capacitor 68 is used as a constant current source for the first-stage source follower in a Voltage-Domain system.

[0049] For example, in a conventional circuit structure that does not employ the Capacitive-Current-Source method, there is a concern that variations in transistors may be a factor when writing pixel signals to the MIM structure. In contrast, the solid-state imaging device 13 employing the Capacitive-Current-Source method can suppress variations in transistors by supplying a ramp signal RAMP to the capacitor 68.

[0050] FIG. 3 shows a first example of the cross-sectional configuration of the solid-state imaging device 13. As shown in FIG.

[0051] As shown in Figure 3, the solid-state imaging element 13 has a three-layer structure consisting of a first semiconductor substrate 101, a second semiconductor substrate 102, and a third semiconductor substrate 103 stacked one on top of the other, and a plurality of pixels 31 are arranged in a pixel array section 21.

[0052] The first semiconductor substrate 101 is constructed by stacking a wiring layer 112 on the surface of a semiconductor layer 111, and on the light-receiving surface side, which is the back surface of the semiconductor layer 111, an on-chip lens 113 is stacked to collect light for each pixel 31.

[0053] The semiconductor layer 111 is provided with a photoelectric conversion unit 51 for each pixel 31, as well as various elements (e.g., transfer gates 52, FD gates 53, etc.) that constitute the pixel circuit 41. The semiconductor layer 111 is also provided with an element isolation unit 121 that optically and electrically isolates adjacent pixels 31 from each other.

[0054] The wiring layer 112 is provided with a plurality of wires and a plurality of through electrodes for electrical connection with the second semiconductor substrate 102 for each pixel 31. Furthermore, in the peripheral region of the wiring layer 112 (the region outside the pixel array section 21), pads 122 used for connecting the solid-state imaging element 13 to the outside are arranged, and openings 123 are provided for wire bonding to the pads 122.

[0055] The second semiconductor substrate 102 is configured by laminating a wiring layer 132 on the front surface of a semiconductor layer 131 and laminating a bonding layer 133 on the rear surface of the semiconductor layer 131 .

[0056] In the semiconductor layer 131 , various elements (SR gate 63 , SD gate 64 , RB gate 65 , amplification gate 66 , and selection gate 67 ) that constitute the sample-and-hold circuit 42 are provided for each pixel 31 .

[0057] The wiring layer 132 is provided with a plurality of wires and a plurality of through electrodes for electrical connection with the first semiconductor substrate 101 for each pixel 31. In addition, the wiring layer 132 is provided with an MIM (Metal Insulator Metal) structure for forming the capacitors 61, 62, and 68 that constitute the sample-and-hold circuit 42 for each pixel 31.

[0058] The bonding layer 133 is provided to bond the second semiconductor substrate 102 to the third semiconductor substrate 103 .

[0059] In the following description, the layer in which the SR gate 63, SD gate 64, RB gate 65, amplifier gate 66, and select gate 67 are provided in the semiconductor layer 131 of the second semiconductor substrate 102 is referred to as the base layer 141. Also, the layer in which the MIM structures constituting the capacitors 61, 62, and 68 are provided in the wiring layer 132 of the second semiconductor substrate 102 is referred to as the MIM layer 142.

[0060] The third semiconductor substrate 103 is configured by laminating a wiring layer 152 on the surface of a semiconductor layer 151. The semiconductor layer 151 is provided with various elements that constitute a logic circuit that drives the solid-state imaging device 13, and the wiring layer 152 is provided with a plurality of wires and a plurality of through electrodes.

[0061] The solid-state imaging element 13 is configured with such a layered structure, and as shown in the configuration example shown in Figure 3, the first semiconductor substrate 101 and the second semiconductor substrate 102 are configured by bonding the front side of the semiconductor layer 111 to the front side of the semiconductor layer 131, and the second semiconductor substrate 102 and the third semiconductor substrate 103 are configured by bonding the back side of the semiconductor layer 131 to the front side of the semiconductor layer 151.

[0062] Fig. 4 shows a second example of the cross-sectional configuration of the solid-state imaging device 13. In the solid-state imaging device 13A shown in Fig. 4, components common to those of the solid-state imaging device 13 shown in Fig. 3 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0063] As shown in Figure 4, the solid-state imaging element 13A has a three-layer structure formed by stacking a first semiconductor substrate 101, a second semiconductor substrate 102A, and a third semiconductor substrate 103, and the first semiconductor substrate 101 and the third semiconductor substrate 103 are configured in the same manner as the solid-state imaging element 13 in Figure 3.

[0064] 3, the second semiconductor substrate 102A is configured by laminating a wiring layer 132 on the front surface of a semiconductor layer 131 and a bonding layer 133 on the back surface of the semiconductor layer 131, but the orientation is different from that of the second semiconductor substrate 102 in Fig. 3. That is, the side of the semiconductor layer 131 on which the wiring layer 132 is laminated faces the third semiconductor substrate 103, and the side of the back surface of the semiconductor layer 131 on which the bonding layer 133 is laminated faces the first semiconductor substrate 101.

[0065] Therefore, in the solid-state imaging element 13A, as shown in the configuration example in FIG. 4, the first semiconductor substrate 101 and the second semiconductor substrate 102A are configured by bonding the front side of the semiconductor layer 111 to the back side of the semiconductor layer 131, and the second semiconductor substrate 102A and the third semiconductor substrate 103 are configured by bonding the front side of the semiconductor layer 131 to the front side of the semiconductor layer 151.

[0066] A first planar layout of pixel 31 will be described with reference to FIG.

[0067] 5A shows an example of a first planar layout of the base layer 141 of the pixel 31, and FIG. 5B shows an example of a planar layout of the MIM layer 142 of the pixel 31. In the planar layout of the base layer 141 of the pixel 31 described below, the area hatched with dots is referred to as the active area, and the active area is provided with a semiconductor layer that forms the source and drain of the transistor. Furthermore, the rectangles shown with dashed lines represent contacts connected to the source, drain, and gate electrode of the transistor.

[0068] 5A, an SR gate 63, an SD gate 64, an RB gate 65, an amplifier gate 66, and a selection gate 67 that constitute the sample-and-hold circuit 42 are arranged on the base layer 141 of one pixel region of the pixel 31. In addition to these elements, a well contact WC for fixing the potential of the semiconductor layer is also provided.

[0069] The pixel 31 is configured by connecting the drain of the SR gate 63 and the drain of the SD gate 64, and uses a layout in which the SR gate 63 and the SD gate 64 are arranged in series. Therefore, the active area that constitutes the SR gate 63 and the active area that constitutes the SD gate 64 are formed in a continuous straight line, and the single active area provided by arranging the SR gate 63 and the SD gate 64 in series is called a first series active area 201.

[0070] In pixel 31, the source of amplifying gate 66 and the drain of selecting gate 67 are connected, and a layout is used in which amplifying gate 66 and selecting gate 67 are arranged in series. Therefore, the active area constituting amplifying gate 66 and the active area constituting selecting gate 67 are formed in a continuous straight line, and a single active area provided by arranging amplifying gate 66 and selecting gate 67 in series is referred to as second series active area 202.

[0071] As shown in FIG. 5B, a capacitor 61, a capacitor 62, and a capacitor 68 are arranged in the MIM layer 142 of one pixel region of the pixel 31.

[0072] Capacitors 61, 62, and 68 can share an upper electrode 81 formed to cover the entire area in which they are provided. Capacitors 61, 62, and 68 are configured by sandwiching an insulator between their respective lower electrodes and upper electrodes 81, and are provided with a plurality of MIM holes 82 as shown by the dashed rectangles.

[0073] In the first planar layout of the pixels 31, the pixels 31 are arranged in an array in the pixel array section 21, with one pixel region of the base layer 141 shown in A of Fig. 5 being a repeating unit and one pixel region of the MIM layer 142 shown in B of Fig. 5 being a repeating unit. At this time, the first planar layout of the pixels 31 is configured so that the repeating unit in the base layer 141 and the repeating unit in the MIM layer 142 approximately coincide with each other in a planar view.

[0074] 5A, in the first planar layout of the pixel 31, the first series active area 201 in which the SR gate 63 and the SD gate 64 are provided and the second series active area 202 in which the amplification gate 66 and the selection gate 67 are provided are arranged parallel to each other. This allows the pixel 31 to have an efficient layout.

[0075] A second planar layout of the pixel 31 will be described with reference to FIG.

[0076] Fig. 6A shows an example of a second planar layout in the base layer 141 of the pixel 31, and Fig. 6B shows an example of a planar layout in the MIM layer 142 of the pixel 31. In the second planar layout shown in Fig. 6, the same components as those in the first planar layout in Fig. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0077] As shown in A of Fig. 6, the second planar layout of pixel 31 has the same arrangement of the SR gate 63, SD gate 64, RB gate 65, and well contact WC as the first planar layout of Fig. 5. The second planar layout of pixel 31 is also the same as the first planar layout of Fig. 5 in that the first series active area 201 in which the SR gate 63 and the SD gate 64 are provided and the second series active area 202 in which the amplification gate 66 and the selection gate 67 are provided are arranged parallel to each other.

[0078] In the second planar layout of the pixel 31, the arrangement of the second series active area 202 in which the amplification gate 66 and the selection gate 67 are provided is different from that in the first planar layout of Fig. 5. That is, in the first planar layout of Fig. 5, the first series active area 201 and the second series active area 202 are arranged so that both ends in the horizontal direction are aligned.

[0079] In contrast, in the second planar layout of pixel 31, the second series active area 202 is arranged at a position shifted in the horizontal direction so that the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. Therefore, as shown in Fig. 6, the left end of the second series active area 202 makes the left side surface of one pixel region of pixel 31 convex toward the left, and the right end of the second series active area 202 makes the right side surface of one pixel region of pixel 31 concave toward the left.

[0080] 6, the source of the RB gate 65 may be arranged on a straight line that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series.

[0081] In the second planar layout of the pixel 31, one pixel region of the base layer 141 shown in Fig. 6A is a repeating unit, and one pixel region of the MIM layer 142 shown in Fig. 6B is a repeating unit, and the plurality of pixels 31 are arranged in an array in the pixel array section 21. In this case, the repeating unit in the base layer 141 and the repeating unit in the MIM layer 142 do not match in plan view, and the second planar layout of the pixel 31 is configured so that the left side surface is convex and the right side surface is concave.

[0082] 6A, in the second planar layout of the pixel 31, the first series active area 201 in which the SR gate 63 and the SD gate 64 are provided and the second series active area 202 in which the amplifier gate 66 and the select gate 67 are provided are arranged parallel to each other. Furthermore, in the second planar layout of the pixel 31, the sources of the amplifier gate 66 and the RB gate 65 are arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series, thereby making it possible to connect the V2 node in the shortest possible way. This allows the pixel 31 to achieve a more efficient layout.

[0083] 7 shows an example of a first planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array (i.e., the planar layout of each pixel 31 is the same as that shown in A of FIG. 5 above). Hereinafter, i is used to identify a specific pixel 31 among the multiple pixels 31, and the respective pixels 31 are distinguished by i=1, 2, 3, 4.

[0084] FIG. 8 shows an example of a second planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array (i.e., the planar layout of each pixel 31 is the same as A in FIG. 6 described above).

[0085] Figure 9 shows an example of the planar layout of the MIM layer 142 of four pixels 31[0] to 31[3] arranged in a 2x2 array (i.e., the planar layout of each pixel 31 is the same as B of Figure 5 and B of Figure 6 described above).

[0086] As shown in FIGS. 7 and 9, the first planar layout of the pixel 31 is configured so that the repeating unit in the base layer 141 and the repeating unit in the MIM layer 142 substantially coincide with each other in plan view.

[0087] As shown in Figures 8 and 9, the second planar layout of pixel 31 is configured so that the repeating unit in the base layer 141 and the repeating unit in the MIM layer 142 do not match in a planar view, and the left side is convex and the right side is concave.

[0088] FIG. 10 shows an example of a third planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array.

[0089] 10, in the third planar layout, the well contact WC can be shared by horizontally adjacent pixels 31. In the example shown in Fig. 10, the well contact WC is shared by horizontally adjacent pixels 31 [0] and 31 [1], and the well contact WC is shared by horizontally adjacent pixels [2] and 31 [1].

[0090] In this way, in the third planar layout, by sharing the well contact WC between the pixels 31, it is possible to further improve the efficiency of the layout.

[0091] FIG. 11 shows an example of a fourth planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array.

[0092] As shown in FIG. 11 , in the fourth planar layout, horizontally adjacent pixels 31 can share the drains of their RB gates 65 (both drains connected to the power supply VREG) and the drains of their amplifier gates 66 (both drains connected to the power supply VDD). In the example shown in FIG. 11 , the drains of the RB gates 65[0] of horizontally adjacent pixels 31[0] and RB gates 65[1] of pixels 31[1] are shared, and the drains of the amplifier gates 66[0] of horizontally adjacent pixels 31[0] and RB gates 66[1] of pixels 31[1] are shared. Similarly, the drains of the RB gates 65[2] of horizontally adjacent pixels 31[2] and RB gates 65[3] of pixels 31[3] are shared, and the drains of the amplifier gates 66[2] of horizontally adjacent pixels 31[2] and RB gates 66[3] of pixels 31[3] are shared.

[0093] In this way, in the fourth planar layout, it is possible to further improve the efficiency of the layout by sharing the drains of the RB gates 65 between the pixels 31 and sharing the drains of the amplifier gates 66 between the pixels 31. It is to be noted that even if only one of the sharing of the drains of the RB gates 65 and the sharing of the drains of the amplifier gates 66 is performed, it is possible to improve the efficiency of the layout.

[0094] 12, the solid-state imaging device 13 can employ a four-pixel sharing structure in which four pixels 31[0] to 31[3] in a 2x2 array share a V2 node. In the four-pixel sharing structure, an RB gate 65, an amplification gate 66, and a selection gate 67 are shared. Note that in the drawings of the four-pixel sharing structure described below, the pixel circuit 41 is not shown.

[0095] FIG. 13 is a diagram showing an example of a fifth planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array in a four-pixel sharing structure.

[0096] 13 , in the fifth planar layout, the first series active areas 201[0] to 201[3] and the second series active area 202 are arranged parallel to each other. Also, in the fifth planar layout, the pair of the first series active area 201[0] and the first series active area 201[1] is arranged in series on a straight line, and the pair of the first series active area 201[2] and the first series active area 201[3] is arranged in series on a straight line. This allows the pixel 31 to have an efficient layout.

[0097] 13, all of the first series active areas 201[0] to 201[3] are arranged parallel to the second series active area 202, but by arranging at least one of the first series active areas 201[0] to 201[3] parallel to the second series active area 202, the layout efficiency of the pixel 31 can be improved. Furthermore, by arranging at least one pair of the first series active areas 201[0] to 201[3] in series on a straight line, the layout efficiency of the pixel 31 can be improved.

[0098] FIG. 14 is a diagram showing an example of a sixth planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array in a four-pixel sharing structure.

[0099] 14 , in the sixth planar layout, the first series active areas 201[0] to 201[3] and the second series active area 202 are arranged parallel to each other. Also, in the sixth planar layout, the pair of the first series active area 201[0] and the first series active area 201[1] are arranged parallel to each other, and the pair of the first series active area 201[2] and the first series active area 201[3] are arranged parallel to each other. This allows the pixel 31 to have an efficient layout.

[0100] In addition, by arranging at least one pair of the first series active areas 201[0] to 201[3] in parallel to each other, the pixel 31 can achieve an efficient layout.

[0101] FIG. 15 is a diagram showing an example of a seventh planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array in a four-pixel sharing structure.

[0102] 15, in the seventh planar layout, the first series active areas 201[0] to 201[3] and the second series active area 202 are arranged parallel to one another. In the seventh planar layout, the midpoints between all of the SR gates 63 and SD gates 64, the amplifier gates 66, and the sources of the RB gates 65 are arranged in a straight line as indicated by the dashed dotted line. This allows the pixel 31 to have an efficient layout.

[0103] 16 is a diagram showing an example of an eighth planar layout of two pixels 31[0] and 31[1] arranged in a 2 × 1 matrix in a two-pixel sharing structure. Note that in the two-pixel sharing structure, as in the four-pixel sharing structure shown in FIG. 12 above, the RB gate 65, the amplification gate 66, and the selection gate 67 are shared by the pixels 31[0] and 31[1] that share the V2 node.

[0104] 16 , in the eighth planar layout, the first series active area 201[0] and the first series active area 201[1] are arranged parallel to the second series active area 202. This allows the pixel 31 to have an efficient layout.

[0105] In the eighth planar layout shown in FIG. 16, the first series active area 201[0], the first series active area 201[1], and the second series active area 202 are arranged in the center, the RB gate 65 is arranged below them, and the well contact WC is arranged above them.

[0106] FIG. 17 is a diagram showing an example of a ninth planar layout of two pixels 31[0] and 31[1] arranged in a 2×1 matrix with a two-pixel sharing structure.

[0107] 17 , in the ninth planar layout, the first series active area 201[0] and the first series active area 201[1] are arranged parallel to the second series active area 202. This allows the pixel 31 to have an efficient layout.

[0108] In the ninth planar layout shown in FIG. 17, the first series active area 201[0], the first series active area 201[1], and the second series active area 202 are arranged on the upper side, and the RB gate 65 and the well contact WC are arranged vertically below them.

[0109] FIG. 18 is a diagram showing an example of a tenth planar layout of two pixels 31[0] and 31[1] arranged in a 2×1 matrix with a two-pixel sharing structure.

[0110] 18 , in the tenth planar layout, the first series active area 201[0] and the first series active area 201[1] are arranged parallel to the second series active area 202. Furthermore, the midpoints of all the SR gates 63 and SD gates 64, the sources of the amplification gates 66, and the RB gates 65 are arranged in a straight line as shown by the dashed dotted line. This allows the pixel 31 to have an efficient layout.

[0111] <Second Configuration Example of Pixel> A second configuration example of the pixel 31 will be described with reference to FIGS.

[0112] Fig. 19 shows an example of a circuit diagram of a pixel 31a which is the second configuration example. In the pixel 31a shown in Fig. 19, the same components as those in the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0113] As shown in FIG. 19, the pixel 31 a has a common configuration with the pixel 31 in FIG. 2 in that it is configured with a pixel circuit 41 and a sample-and-hold circuit 42 a and is connected to a constant current source 44 via a vertical signal line 43 .

[0114] 2 in that it includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplification gate 66, a selection gate 67, and a capacitor 68. The sample and hold circuit 42a further includes a DIFF gate 69.

[0115] 19, the drain of the DIFF gate 69 is connected to a V1 node which is a connection point between the source of the switch gate 57 and one end of the capacitor 61. The source of the DIFF gate 69 is connected to a connection point between one end of the capacitor 62 and one end of the capacitor 68, and this connection point is referred to as a V3 node.

[0116] By providing the DIFF gate 69, the pixel 31a can reduce leakage during a period in which pixel signals are held in the capacitors 61 and 62. For example, the DIFF gate 69 is driven in accordance with the control signal DIFF, and the DIFF gate 69 is turned off during a readout standby period after a global operation period, thereby separating the capacitors 61 and 62. On the other hand, during a readout period, a complete global operation period, and / or a complete row readout period, the DIFF gate 69 is turned on, thereby connecting the capacitors 61 and 62.

[0117] Furthermore, as shown in FIG. 20, the solid-state imaging device 13 can employ a four-pixel sharing structure in which four pixels 31a[0] to 31a[3] in a 2×2 array are shared at the V2 node.

[0118] FIG. 21 is a diagram showing an example of an eleventh planar layout of four pixels 31a[0] to 31a[3] arranged in a 2×2 array in a four-pixel sharing structure.

[0119] 21 , in the eleventh planar layout, the first series active areas 201[0] to 201[3] and the second series active area 202 are arranged parallel to each other. Also, in the eleventh planar layout, the pair of the first series active area 201[0] and the first series active area 201[1] is arranged in series on a straight line, and the pair of the first series active area 201[2] and the first series active area 201[3] is arranged in series on a straight line. This allows the pixel 31a to have an efficient layout.

[0120] Furthermore, in the eleventh planar layout, the DIFF gate 69 is arranged so that its positional relationship with the SR gate 63 and the SD gate 64 is line-symmetric. That is, the center of the DIFF gate 69 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows the pixel 31a to have a more efficient layout.

[0121] <Configuration Example Using MOS Capacitors> FIG. 22 is a diagram showing an example of a twelfth planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 array in a four-pixel sharing structure.

[0122] The twelfth planar layout shown in FIG. 22 has a four-pixel sharing structure as shown in FIG. 12 described above, in which a MOS (Metal-Oxide-Semiconductor) capacitor can be used as the capacitor 68, and the capacitor 68 is disposed on the base layer 141.

[0123] Thus, in the twelfth planar layout using a MOS capacitor as the capacitor 68, the first series active area 201[0] to the first series active area 201[3] and the second series active area 202 are arranged parallel to each other. Also, in the twelfth planar layout, the pair of the first series active area 201[0] and the first series active area 201[1] is arranged in series on a straight line, and the pair of the first series active area 201[2] and the first series active area 201[3] is arranged in series on a straight line. This allows the pixel 31a to have an efficient layout.

[0124] Furthermore, in the twelfth planar layout, the capacitor 68 is arranged so that its positional relationship with the SR gate 63 and the SD gate 64 is line-symmetric. That is, the center of the capacitor 68 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows the pixel 31a to have a more efficient layout.

[0125] <Plane Layout of Pixel with Single-Layer Structure> The plane layout of the pixel 31 with a single-layer structure will be described with reference to FIGS.

[0126] 3 and 4 described above, the pixel 31 is not limited to being configured in a two-layer structure in which various elements constituting the pixel circuit 41 are provided on the first semiconductor substrate 101 and various elements constituting the sample and hold circuit 42 are provided on the second semiconductor substrate 102. That is, the pixel 31 may adopt a single-layer structure in which various elements constituting the pixel circuit 41 are provided on the first semiconductor substrate 101 and various elements constituting the sample and hold circuit 42 are provided on the second semiconductor substrate 102, both on one semiconductor substrate.

[0127] FIG. 23 is a diagram showing an example of a thirteenth planar layout of a pixel 31 having a single-layer structure.

[0128] As shown in FIG. 23, in one pixel region of a pixel 31, a transfer gate 52, an FD gate 53, a reset gate 54, an amplification gate 56, and a switch gate 57 that constitute the pixel circuit 41, as well as an SR gate 63, an SD gate 64, an RB gate 65, an amplification gate 66, and a selection gate 67 that constitute the sample-and-hold circuit 42 are arranged.

[0129] In this thirteenth planar layout of the pixel 31, the first series active area 201 in which the SR gate 63 and the SD gate 64 are provided and the second series active area 202 in which the amplifier gate 66 and the select gate 67 are provided are arranged parallel to each other. Furthermore, in the thirteenth planar layout of the pixel 31, the amplifier gate 66 is arranged on a straight line (indicated by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows the pixel 31 to have a more efficient layout.

[0130] Fig. 24 shows an example of a circuit diagram of a pixel 31b, which is a third configuration example. In the pixel 31b shown in Fig. 24, components common to those of the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0131] As shown in FIG. 24, the pixel 31b has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41b and a sample-and-hold circuit 42 and is connected to a constant current source 44 via a vertical signal line 43.

[0132] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, and a switch gate 57. Furthermore, the pixel circuit 41b is configured to include an overflow gate 58.

[0133] The overflow gate 58 is connected between the photoelectric conversion unit 51 and the power supply VDD, and discharges to the power supply VDD any charge that overflows from the photoelectric conversion unit 51. The overflow gate 58 is driven in accordance with a control signal OFG supplied from the vertical scanning circuit 23, and when the overflow gate 58 is turned on, the charge accumulated in the photoelectric conversion unit 51 is discharged to the power supply VDD to reset the photoelectric conversion unit 51, and exposure of the pixel 31b is started.

[0134] FIG. 25 is a diagram showing an example of a fourteenth planar layout of pixel 31b.

[0135] As shown in FIG. 25, in the fourteenth planar layout of the pixel 31b, the drain of the overflow gate 58 and the drain of the amplification gate 66 are shared, thereby making it possible to improve the efficiency of the layout.

[0136] In the fourteenth planar layout of pixel 31b, the first series active area 201 and the second series active area 202 are also arranged parallel to each other. Furthermore, the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows pixel 31b to achieve a more efficient layout.

[0137] FIG. 26 is a diagram showing an example of a fifteenth planar layout of pixel 31b.

[0138] As shown in FIG. 26, in the fifteenth planar layout of the pixel 31b, the drain of the reset gate 54 and the drain of the amplifier gate 66 are shared, thereby making it possible to improve the efficiency of the layout.

[0139] In the fifteenth planar layout of pixel 31b, the first series active area 201 and the second series active area 202 are also arranged parallel to each other. Furthermore, the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows pixel 31b to achieve a more efficient layout.

[0140] FIG. 27 is a diagram showing an example of a sixteenth planar layout of pixel 31b.

[0141] As shown in FIG. 27, in the sixteenth planar layout of the pixel 31b, the drain of the reset gate 54 and the drain of the overflow gate 58 are shared, thereby making it possible to improve the efficiency of the layout.

[0142] In the sixteenth planar layout of pixel 31b, the first series active area 201 and the second series active area 202 are also arranged parallel to each other. Furthermore, the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows pixel 31b to achieve a more efficient layout.

[0143] FIG. 28 is a diagram showing an example of a seventeenth planar layout of pixel 31b.

[0144] As shown in FIG. 28, in the seventeenth planar layout of the pixel 31b, the drain of the reset gate 54, the overflow gate 58, and the drain of the amplifier gate 66 are shared, thereby making it possible to improve the efficiency of the layout.

[0145] In the seventeenth planar layout of pixel 31b, the first series active area 201 and the second series active area 202 are also arranged parallel to each other. Furthermore, the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows pixel 31b to achieve a more efficient layout.

[0146] FIG. 29 is a diagram showing an example of an 18th planar layout of four pixels 31b[0] to 31b[3] arranged in a 2×2 array.

[0147] In the 18th planar layout shown in Fig. 29, the drain of the overflow gate 58 and the drain of the amplifier gate 66 are common to each other, as in the 14th planar layout of the pixel 31b shown in Fig. 25 above. Furthermore, in the 18th planar layout, the drain of the overflow gate 58 and the drain of the amplifier gate 66 are common to each other even between pixels 31b adjacent in the vertical direction, thereby making it possible to improve the efficiency of the layout. Furthermore, as shown in Fig. 27, the drain of the reset gate 54 may also be common to each other.

[0148] Also in the 18th planar layout, the first series active area 201 and the second series active area 202 are arranged parallel to each other. Furthermore, the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows the pixel 31b to have a more efficient layout.

[0149] FIG. 30 is a diagram showing an example of a nineteenth planar layout of pixel 31b.

[0150] 30, the drain of the reset gate 54 and the drain of the overflow gate 58 are common to each other, as in the 16th planar layout of the pixel 31b shown in FIG. 27. Furthermore, in the 19th planar layout, the drain of the reset gate 54 and the drain of the overflow gate 58 are common to each other, and the well contacts WC are common to each other, even between horizontally adjacent pixels 31b, thereby improving the efficiency of the layout. Furthermore, as shown in FIG. 28, the drain of the amplifier gate 66 may also be common to each other.

[0151] Also in the nineteenth planar layout, the first series active area 201 and the second series active area 202 are arranged parallel to each other. Furthermore, the amplifier gate 66 is arranged on a straight line (shown by a dashed line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is perpendicular to the longitudinal direction in which the SR gate 63 and the SD gate 64 are arranged in series. This allows the pixel 31b to have a more efficient layout.

[0152] <Fourth to Tenth Configuration Examples of Pixel> Fourth to tenth configuration examples of the pixel 31 will be described with reference to FIGS.

[0153] Fig. 31 shows an example of a circuit diagram of a pixel 31c which is a fourth configuration example. In the pixel 31c shown in Fig. 31, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0154] 31, pixel 31c is configured with a pixel circuit 41c and a sample-and-hold circuit 42c, and has a configuration common to pixel 31 in Fig. 2 in that it is connected to a constant current source 44 via a vertical signal line 43. Like sample-and-hold circuit 42 in Fig. 2, sample-and-hold circuit 42c is configured with capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplifier gate 66, selection gate 67, and capacitor 68.

[0155] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, a reset gate 54, an amplification gate 56, and a switch gate 57. Furthermore, the pixel circuit 41c includes an overflow gate 58 and a CLP gate 74.

[0156] As shown in FIG. 31, the CLP gate 74 is connected in parallel to the amplifier gate 56 and forms a source follower circuit similar to the amplifier gate 56 .

[0157] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixel 31c configured in this way, the use of each of the planar layouts described above can improve the layout efficiency.

[0158] Fig. 32 shows an example of a circuit diagram of a pixel 31d, which is a fifth configuration example. In the pixel 31d shown in Fig. 32, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0159] As shown in FIG. 32, the pixel 31d is configured with a pixel circuit 41d and a sample-and-hold circuit 42d, and has a configuration common to the pixel 31 in FIG. 2 in that it is connected to a constant current source 44 via a vertical signal line 43.

[0160] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, but differs from the pixel circuit 41 in that it does not include a switch gate 57. Note that the pixel circuit 41d differs from the pixel circuit 41 in that the drain of the amplification gate 56, together with the drain of the reset gate 54, is connected to the power supply VDD.

[0161] The sample-and-hold circuit 42 d includes a switch gate 57 , a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0162] The drain of the switch gate 57 is connected to the source of the amplifier gate 56 and one end of a capacitor 68, and this connection point serves as the V1 node. The source of the switch gate 57 is connected to the V2 node, which is connected to the drain of the SR gate 63, the drain of the SD gate 64, and the gate electrode of the amplifier gate 66. The source of the SR gate 63 is connected to one end of a capacitor 61, and the other end of the capacitor 61 is grounded. The source of the SD gate 64 is connected to one end of a capacitor 62, and the other end of the capacitor 62 is grounded. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0163] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixel 31d configured in this way, the layout can be made more efficient by adopting each of the planar layouts described above.

[0164] Fig. 33 shows an example of a circuit diagram of a pixel 31e, which is a sixth configuration example. In the pixel 31e shown in Fig. 33, components common to those of the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0165] 33, pixel 31e has a configuration common to pixel 31 in Fig. 2 in that it is configured by a pixel circuit 41 and a sample-and-hold circuit 42e. Furthermore, pixel 31e is connected to a constant current source 44-1 via a vertical signal line 43-1, and is connected to a constant current source 44-2 via a vertical signal line 43-2.

[0166] The sample-and-hold circuit 42 e includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplification gate 66 - 1 and an amplification gate 66 - 2 , a selection gate 67 - 1 and a selection gate 67 - 2 , and a capacitor 68 .

[0167] The drain of the SR gate 63 is connected to the V1 node, and the source of the SR gate 63 is connected to one end of the capacitor 61 and the gate electrode of the amplifier gate 66-1. The drain of the amplifier gate 66-1 is connected to the power supply VDD, and the source of the amplifier gate 66-1 is connected to the drain of the select gate 67-1, and the source of the select gate 67-1 is connected to the vertical signal line 43-1. The drain of the SD gate 64 is connected to the V1 node, and the source of the SD gate 64 is connected to one end of the capacitor 62 and the gate electrode of the amplifier gate 66-2. The drain of the amplifier gate 66-2 is connected to the power supply VDD, and the source of the amplifier gate 66-2 is connected to the drain of the select gate 67-2, and the source of the select gate 67-2 is connected to the vertical signal line 43-2.

[0168] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixel 31e configured in this way, the layout can be made more efficient by adopting each of the planar layouts described above.

[0169] Fig. 34 shows an example of a circuit diagram of a pixel 31f which is a seventh configuration example. In the pixel 31f shown in Fig. 34, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0170] As shown in FIG. 34, a pixel 31f is configured with a pixel circuit 41 and a sample-and-hold circuit 42f, and has a configuration common to the pixel 31 in FIG. 2 in that it is connected to a constant current source 44 via a vertical signal line 43.

[0171] The sample-and-hold circuit 42 f includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0172] The drain of the SR gate 63 is connected to the V1 node, which is connected to one end of a capacitor 68. The source of the SR gate 63 is connected to one end of a capacitor 61 and one end of a capacitor 62. The other end of the capacitor 62 is connected to the V2 node, which is connected to the drain of the SD gate 64 and the gate electrode of an amplifier gate 66. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of a select gate 67, which is connected to the vertical signal line 43.

[0173] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixels 31f configured in this way, the layout can be made more efficient by adopting the planar layouts described above.

[0174] Fig. 35 shows an example of a circuit diagram of a pixel 31g, which is an eighth configuration example. In the pixel 31g shown in Fig. 35, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0175] As shown in FIG. 35, a pixel 31g is configured with a pixel circuit 41g and a sample-and-hold circuit 42g, and has a configuration common to the pixel 31 in FIG. 2 in that it is connected to a constant current source 44 via a vertical signal line 43.

[0176] The pixel circuit 41g is configured similarly to the pixel circuit 41 of Figure 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, but differs from the pixel circuit 41 of Figure 2 in that it does not include a switch gate 57.

[0177] The sample-and-hold circuit 42 g includes a switch gate 57 , a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0178] The drain of the switch gate 57 is connected to the source of the amplifier gate 56 and one end of a capacitor 68, and this connection point serves as the V1 node. The source of the switch gate 57 is connected to the V2 node, which is connected to the drain of the SR gate 63, the drain of the SD gate 64, and the gate electrode of the amplifier gate 66. The source of the SR gate 63 is connected to one end of a capacitor 61, and the other end of the capacitor 61 is grounded. The source of the SD gate 64 is connected to one end of a capacitor 62, and the other end of the capacitor 62 is grounded. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0179] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixels 31g configured in this way, the layout can be made more efficient by adopting each of the planar layouts described above.

[0180] Fig. 36 shows an example of a circuit diagram of a pixel 31h, which is a ninth configuration example. In the pixel 31h shown in Fig. 36, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0181] As shown in FIG. 36, a pixel 31h has a common configuration with the pixel 31 in FIG. 2 in that it is composed of a pixel circuit 41 and a sample-and-hold circuit 42h and is connected to a constant current source 44 via a vertical signal line 43.

[0182] The sample-and-hold circuit 42 h includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0183] The drain of the SR gate 63 is connected to the V1 node, and one end of a capacitor 68 is connected to the V1 node. The source of the SR gate 63 is connected to the drain of the SD gate 64 and one end of the capacitor 61. The source of the SD gate 64 is connected to the gate electrode of the amplifier gate 66 and one end of the capacitor 62. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0184] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixel 31h configured in this way, the layout efficiency can be improved by adopting each of the planar layouts described above.

[0185] Fig. 37 shows an example of a circuit diagram of a pixel 31i, which is an eleventh configuration example. In the pixel 31i shown in Fig. 37, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0186] As shown in FIG. 37, the pixel 31i has a common configuration with the pixel 31 in FIG. 2 in that it is composed of a pixel circuit 41 and a sample-and-hold circuit 42i and is connected to a constant current source 44 via a vertical signal line 43.

[0187] The sample-and-hold circuit 42 i includes a capacitor 61 , a capacitor 62 , an RB gate 65 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0188] One end of the capacitor 61 is connected to the V1 node, and one end of a capacitor 68 is connected to the V1 node. The other end of the capacitor 61 is connected to one end of the capacitor 62, the source of the RB gate 65, and the gate electrode of the amplifier gate 66. The drain of the RB gate 65 is connected to the power supply VREG, and the drain of the amplifier gate 66 is connected to the power supply VDD. The source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0189] Even in the voltage-domain global shutter solid-state imaging device 13 having the pixels 31i configured in this way, the layout can be made more efficient by adopting the planar layouts described above.

[0190] The pixel 31 may have various configurations other than those shown in FIGS. 31 to 37, as long as it has a configuration that employs each of the planar layouts described above.

[0191] As described above, in the sample-and-hold circuit 42 of the global shutter solid-state imaging device 13 using the voltage-domain method, in the pixel 31 having the capacitor 68 as the Capacitive-Current-Source of the first-stage source follower, the use of the above-described planar layout of the base layer 141 can improve the layout efficiency. This allows the pixel 31 to have a smaller pixel size.

[0192] Therefore, a global shutter type solid-state imaging element 13 using a voltage-domain method and equipped with such pixels 31 can be made smaller in size if the number of pixels is constant, and can improve image quality by increasing the number of pixels if the size is constant.

[0193] <Example of Use of Image Sensor> FIG. 38 is a diagram showing an example of use of the image sensor (imaging element) described above.

[0194] The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0195] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0196] <Examples of Combinations of Configurations> The present technology can also be configured as follows. (1) A pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding a voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal of a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and constituting a source follower circuit together with a first amplification gate of the pixel circuit; a second amplification gate that generates a pixel signal according to charges accumulated in a second node connected to a gate electrode of the third capacitor; a selection gate that selects a pixel to output the pixel signal generated by the second amplification gate; a third node that is a connection point with the other end of the first capacitor and the second node; a first gate that connects the third node and the second node; a fourth node that is a connection point with the other end of the second capacitor and the second node; a third gate that resets charges accumulated in the second node, the third node, and the fourth node; and a sample-and-hold circuit having at least the third gate that resets charges accumulated in the second node, the third node, and the fourth node; wherein an active area that constitutes the first gate and an active area that constitutes the second gate are formed in a continuous straight line, and a first series active area that is a single active area provided by arranging the first gate and the second gate in series, and an active area that constitutes the second amplification gate and an active area that constitutes the selection gate are formed in a continuous straight line, and a second series active area that is a single active area provided by arranging the second amplification gate and the selection gate in series are arranged in parallel to each other.(2) The solid-state imaging device according to (1), wherein the second amplifying gate or the source of the third gate is arranged on a line that passes through a midpoint between the first gate and the second gate and is perpendicular to the longitudinal direction in which the first gate and the second gate are arranged in series. (3) The solid-state imaging device according to (2), wherein a repeating unit in a layer in which the first capacitor, the second capacitor, and the third capacitor are arranged does not match a repeating unit in a layer in which the second amplifying gate, the select gate, the first gate, the second gate, and the third gate are arranged. (4) The solid-state imaging device according to any of (1) to (3), wherein adjacent pixels share a well contact for fixing the potential of a semiconductor layer. (5) The solid-state imaging device according to any of (1) to (4), wherein adjacent pixels share a drain of the third gate and a drain of the second amplifying gate. (6) The solid-state imaging device according to any of (1) to (5) above, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and at least one pair of the first series active areas is arranged in series on a straight line between adjacent pixels. (7) The solid-state imaging device according to any of (1) to (6) above, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and at least one pair of the first series active areas is arranged parallel to each other between adjacent pixels. (8) The solid-state imaging device according to any of (1) to (7) above, wherein a MOS (Metal-Oxide-Semiconductor) capacitor is used as the third capacitor, and the third capacitor is arranged so that its positional relationship with the first gate and the second gate is line-symmetric. (9) The solid-state imaging device according to any one of (1) to (8), wherein the pixel has a two-layer structure in which a first substrate on which elements constituting the pixel circuit are provided and a second substrate on which elements constituting the sample-and-hold circuit are provided are stacked.(10) The solid-state imaging device according to any one of (1) to (9), wherein the pixel has a single-layer structure in which elements constituting the pixel circuit and elements constituting the sample-and-hold circuit are provided on the same substrate. (11) The solid-state imaging device according to (10), wherein the elements constituting the pixel circuit include an FD gate that changes a storage capacitance that holds charge transferred from the photoelectric conversion unit, a reset gate that resets an FD (Floating Diffusion) node that holds charge transferred from the photoelectric conversion unit, and an overflow gate that discharges charge overflowing from the photoelectric conversion unit. (12) The solid-state imaging device according to (11), wherein two or three of the overflow gate, the second amplification gate, and the drain of the reset gate are shared. (13) The solid-state imaging device according to (12), wherein two or three of the overflow gate, the second amplification gate, and the drain of the reset gate, or a well contact for fixing the potential of a semiconductor layer, are shared between adjacent pixels.(14) A pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding a voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal of a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and constituting a source follower circuit together with an amplifier gate of the pixel circuit; an amplifier gate that generates a pixel signal according to charges accumulated in a second node connected to a gate electrode of the third capacitor; a select gate that selects a pixel to output the pixel signal generated by the amplifier gate; a first gate that connects a third node that is a connection point with the other end of the first capacitor and the second node; and a third gate that resets charges accumulated in the second node, the third node, and the fourth node, and a sample and hold circuit having at least the third gate, wherein an active area constituting the first gate and an active area constituting the second gate are formed in a continuous straight line, and a first series active area is a single active area provided by arranging the first gate and the second gate in series, and an active area constituting the amplifying gate and an active area constituting the selecting gate are formed in a continuous straight line, and a second series active area is a single active area provided by arranging the amplifying gate and the selecting gate in series, and are arranged in parallel to each other.

[0197] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0198] REFERENCE SIGNS LIST 11 imaging device, 12 optical system, 13 solid-state imaging element, 14 imaging control circuit, 15 signal processing circuit, 16 monitor, 17 memory, 21 pixel array section, 22 timing control circuit, 23 vertical scanning circuit, 24 DAC, 25 load MOS circuit block, 26 column signal processing circuit, 31 pixel, 41 pixel circuit, 42 sample and hold circuit, 43 vertical signal line, 44 constant current source, 51 photoelectric conversion section, 52 transfer gate, 53 FD gate, 54 reset gate, 55 capacitor, 56 amplification gate, 57 switch gate, 61 capacitor, 62 capacitor, 63 SR gate, 64 SD gate, 64, 65 RB gate, 66 amplification gate, 67 selection gate, 68 capacitor

Claims

1. A pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding the voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding the voltage of a pixel signal of a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, the third capacitor constituting a source follower circuit together with a first amplification gate of the pixel circuit; a second amplification gate that generates a pixel signal according to charges accumulated in a second node connected to a gate electrode of the third capacitor; a selection gate that selects a pixel to output the pixel signal generated by the second amplification gate; a third node that is a connection point with the other end of the first capacitor and the second node; a first gate that connects the third node and the second node; a fourth node that is a connection point with the other end of the second capacitor and the second node; a third gate that resets charges accumulated in the second node, the third node, and the fourth node; and a sample-and-hold circuit having at least the third gate that resets charges accumulated in the second node, the third node, and the fourth node; wherein an active area that constitutes the first gate and an active area that constitutes the second gate are formed in a continuous straight line, and a first series active area that is a single active area provided by arranging the first gate and the second gate in series, and an active area that constitutes the second amplification gate and an active area that constitutes the selection gate are formed in a continuous straight line, and a second series active area that is a single active area provided by arranging the second amplification gate and the selection gate in series are arranged in parallel to each other.

2. The solid-state imaging device according to claim 1, wherein the second amplification gate is arranged on a straight line that passes through the midpoint between the first gate and the second gate and is perpendicular to the longitudinal direction in which the first gate and the second gate are arranged in series, or the source of the third gate is arranged.

3. The solid-state imaging device according to claim 2, wherein the repeating unit in the layer in which the first capacitor, the second capacitor, and the third capacitor are arranged does not match the repeating unit in the layer in which the second amplification gate, the selection gate, the first gate, the second gate, and the third gate are arranged.

4. The solid-state imaging device according to claim 1, wherein adjacent pixels share a well contact for fixing the potential of the semiconductor layer.

5. The solid-state imaging device according to claim 1, wherein the drains of the third gates and the drains of the second amplifying gates are shared between adjacent pixels.

6. The solid-state imaging device according to claim 1, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and at least one pair of the first series active areas between adjacent pixels are arranged in series on a straight line.

7. The solid-state imaging device according to claim 1, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and at least one pair of the first series active areas between adjacent pixels are arranged parallel to each other.

8. The solid-state imaging device according to claim 1, wherein a MOS (Metal-Oxide-Semiconductor) capacitor is used as the third capacitor, and the third capacitor is arranged so that its positional relationship with the first gate and the second gate is line-symmetric.

9. The solid-state imaging device according to claim 1, wherein the pixel has a two-layer structure in which a first substrate on which elements constituting the pixel circuit are provided and a second substrate on which elements constituting the sample-and-hold circuit are provided are stacked.

10. The solid-state imaging device according to claim 1, wherein the pixel has a single-layer structure in which elements constituting the pixel circuit and elements constituting the sample-and-hold circuit are provided on the same substrate.

11. A solid-state imaging device according to claim 10, comprising, as elements constituting the pixel circuit, an FD gate that changes a storage capacitance that holds the charge transferred from the photoelectric conversion unit, a reset gate that resets an FD (Floating Diffusion) node that holds the charge transferred from the photoelectric conversion unit, and an overflow gate that discharges the charge that has overflowed from the photoelectric conversion unit.

12. The solid-state imaging device according to claim 11, wherein two or three of the drains of the overflow gate, the second amplifying gate, and the reset gate are common.

13. The solid-state imaging device according to claim 12, wherein two or three of the drains of the overflow gate, the second amplification gate and the reset gate, or a well contact for fixing the potential of the semiconductor layer, are shared between adjacent pixels.

14. A pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding the voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding the voltage of a pixel signal of a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and constituting a source follower circuit together with a first amplification gate of the pixel circuit; a second amplification gate that generates a pixel signal according to charges accumulated at a second node connected to a gate electrode of the third capacitor; a selection gate that selects a pixel to output the pixel signal generated by the second amplification gate; a third node that is a connection point with the other end of the first capacitor and the second node; a first gate that connects the third node and the second node; a fourth node that is a connection point with the other end of the second capacitor and the second node; and a sample and hold circuit having at least a third gate that resets charges accumulated in the second node, the third node, and the fourth node, wherein an active area constituting the first gate and an active area constituting the second gate are formed in a continuous straight line, and a first series active area is a single active area provided by arranging the first gate and the second gate in series, and an active area constituting the second amplification gate and an active area constituting the selection gate are formed in a continuous straight line, and a second series active area is a single active area provided by arranging the second amplification gate and the selection gate in series, are arranged in parallel to each other.

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