Electronic device

Abstract

An electronic device (100) comprises: a conductor (1); a first terminal (41); and a second terminal (42). The conductor has a main surface (10a). The first terminal is connected to the conductor. The second terminal is connected to the conductor. The second terminal is positioned opposite to the first terminal in an extending direction (x direction) in which the conductor extends. A plurality of slits (13) are provided in the main surface. The main surface includes a phonon trap region (11) and a communication region (12). The phonon trap region is defined by the plurality of slits. The communication region is continuous to the phonon trap region. The plurality of slits include inclined parts (13c). The inclined parts are inclined relative to the extending direction in a plan view of the main surface. The minimum width (L2) of the communication region is not more than three times a first mean free path of phonons in the conductor. The minimum width of the communication region is equal to or greater than a second mean free path of carriers in the conductor.

Description

Electronic Devices

[0001] The present disclosure relates to electronic devices.

[0002] Conventionally, electronic devices that generate electromotive force by the Seebeck effect by utilizing the temperature difference between terminals provided at both ends of a conductive material have been known (see, for example, JP 2017-54975 A). By suppressing thermal conduction without inhibiting electrical conduction in the conductive material, the power generation efficiency of the electronic device using the Seebeck effect is improved. In JP 2017-54975 A, a plurality of rod-shaped structures that scatter phonons in a conductor are arranged inside the conductor, which is a conductive material.

[0003] JP 2017-54975 A

[0004] However, there is room for improvement in suppressing thermal conductivity without inhibiting electrical conduction in the conductor.

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide an electronic device in which thermal conductivity is suppressed without inhibiting electrical conduction.

[0006] An electronic device according to the present disclosure comprises a conductor, a first terminal, and a second terminal. The conductor has a main surface. The first terminal is connected to the conductor. The second terminal is connected to the conductor. The second terminal is located opposite the first terminal in the extension direction of the conductor. A plurality of slits are provided in the main surface. The main surface includes a phonon trapping region and a communication region. The phonon trapping region is defined by the plurality of slits. The communication region is connected to the phonon trapping region. The plurality of slits include inclined portions. The inclined portions are inclined with respect to the extension direction in a plan view of the main surface. The minimum width of the communication region is three times or less the first mean free path of phonons in the conductor. The minimum width of the communication region is equal to or greater than the second mean free path of carriers in the conductor.

[0007] According to the above, an electronic device having reduced thermal conductivity without impeding electrical conduction can be obtained.

[0008] 11 is a schematic plan view of an electronic device according to a first embodiment. FIG. 12 is a schematic partially enlarged plan view of a region II of FIG. 1 . FIG. 13 is a schematic cross-sectional view of an electronic device according to a first embodiment. FIG. 14 is a schematic cross-sectional view showing a step of a method for manufacturing an electronic device according to a first embodiment. FIG. 15 is a schematic cross-sectional view showing a step of a method for manufacturing an electronic device according to a first embodiment. FIG. 16 is a schematic cross-sectional view showing a step of a method for manufacturing an electronic device according to a first embodiment. FIG. 17 is a schematic plan view of an electronic device according to a first modified example of the first embodiment. FIG. 18 is a schematic partially enlarged plan view of a region X of FIG. 9 . FIG. 19 is a schematic plan view of an electronic device according to a third embodiment. FIG. 19 is a schematic partially enlarged plan view of a region XII of FIG. 11 . FIG. 19 is a schematic plan view of an electronic device according to a third modified example of the third embodiment. FIG. 20 is a schematic plan view of an electronic device according to a fourth modified example of the third embodiment. FIG. 21 is a schematic plan view of an electronic device according to a fifth modified example of the third embodiment. FIG. 22 is a schematic plan view of an electronic device according to a sixth modified example of the third embodiment. FIG. 23 is a schematic plan view of an electronic device according to a seventh modified example of the third embodiment. FIG. 24 is a schematic plan view of an electronic device according to an eighth modified example of the third embodiment. FIG. 25 is a schematic plan view of an electronic device according to a ninth modified example of the third embodiment. 30 is a schematic plan view of an electronic device according to a tenth modification of the third embodiment. 31 is a schematic plan view of an electronic device according to an eleventh modification of the third embodiment. 32 is a schematic plan view of an electronic device according to a twelfth modification of the third embodiment. 33 is a schematic plan view of an electronic device according to a thirteenth modification of the third embodiment. 34 is a schematic plan view of an electronic device according to a fourteenth modification of the third embodiment. 35 is a schematic plan view of an electronic device according to a fifteenth modification of the third embodiment. 36 is a schematic plan view of an electronic device according to a sixteenth modification of the third embodiment. 37 is a schematic plan view of an electronic device according to a seventeenth modification of the third embodiment. 38 is a schematic plan view of an electronic device according to an eighteenth modification of the third embodiment. 39 is a schematic plan view of an electronic device according to a nineteenth modification of the third embodiment. 40 is a schematic plan view of an electronic device according to the fourth embodiment. 41 is a schematic partial enlarged plan view of an area XXXI in FIG. 30. 42 is a schematic partial enlarged plan view of an area XXXII in FIG. 40. 43 is a schematic plan view of an electronic device according to a twentieth modification of the fourth embodiment.1 is a schematic plan view of an electronic device according to a twenty-first modification of the fourth embodiment. 2 is a schematic plan view of an electronic device according to a twenty-second modification of the fourth embodiment. 3 is a schematic plan view of an electronic device according to a fifth embodiment. 4 is a schematic cross-sectional view of an electronic device according to the fifth embodiment. 5 is a schematic cross-sectional view of an electronic device according to the fifth embodiment. 6 is a schematic cross-sectional view of an electronic device according to the sixth embodiment. 7 is a schematic cross-sectional view of an electronic device according to the seventh embodiment. 8 is a schematic cross-sectional view of an electronic device according to a twenty-fourth modification of the seventh embodiment. 9 is a schematic cross-sectional view of an electronic device according to the ninth embodiment. 10 is a schematic cross-sectional view of an electronic device according to the ninth embodiment. 11 is a schematic cross-sectional view of an electronic device according to the ninth embodiment. 10 is a schematic plan view of an electronic device according to a tenth embodiment; FIG. 11 is a schematic plan view of an electronic device according to a twenty-sixth modification of the tenth embodiment; FIG. 12 is a schematic plan view of an electronic device according to an eleventh embodiment; FIG. 13 is a schematic plan view of an electronic device according to a twenty-seventh modification of the eleventh embodiment;

[0009] Hereinafter, embodiments of the present disclosure will be described. Unless otherwise specified, the same or corresponding parts in the following drawings will be denoted by the same reference numerals, and the description thereof will not be repeated.

[0010] First Embodiment <Configuration of Electronic Device> Fig. 1 is a schematic plan view of an electronic device 100 according to a first embodiment. Fig. 2 is a schematic enlarged partial plan view of region II in Fig. 1. Fig. 3 is a schematic cross-sectional view of the electronic device 100 according to the first embodiment.

[0011] The electronic device 100 shown in Figures 1 to 3 is an electronic device 100 used, for example, as a thermoelectric power generation device and an infrared sensor, and mainly comprises a substrate 3, an insulating layer 2, a conductor 1, a first terminal 41, and a second terminal 42.

[0012] The substrate 3 is, for example, a silicon substrate. As shown in Fig. 3, an insulating layer 2 is formed on a surface 3a of the substrate 3. The insulating layer 2 is, for example, a silicon oxide film. The thickness of the insulating layer 2 in the z direction may be, for example, 100 nm to 900 nm, 200 nm to 800 nm, or 300 nm to 700 nm.

[0013] 3 , a groove H is provided in a part of the insulating layer 2. A part of the surface 3 a of the substrate 3 is exposed in the groove H. The inner peripheral surface of the groove H may extend along the z direction or may be inclined with respect to the z direction. In other words, the inner peripheral surface of the groove H may extend in a direction perpendicular to the surface 3 a of the substrate 3 or may be inclined with respect to the surface 3 a of the substrate 3.

[0014] As shown in Figure 3, the conductor 1 has a principal surface 10a and a back surface 10b. The back surface 10b is located opposite the principal surface 10a in the z direction. The conductor 1 is connected to the insulating layer 2 at the back surface 10b. The direction perpendicular to the principal surface 10a is defined as the z direction. The directions in which the principal surface 10a extends are defined as the x direction and the y direction. The y direction is perpendicular to the x direction.

[0015] 3 , in the region where groove H is formed, a portion of conductor 1 is held in the air by insulating layer 2. From a different perspective, in a plan view of main surface 10a, conductor 1 overlaps insulating layer 2 in the region where groove H is not formed (region where insulating layer 2 is in contact with surface 3a of substrate 3). In a plan view of main surface 10a, conductor 1 does not overlap insulating layer 2 in the region where groove H is formed (region where surface 3a is exposed from insulating layer 2). In this way, conductor 1 is held by substrate 3.

[0016] The conductor 1 is, for example, a silicon substrate. The conductor 1 may be, for example, a thin film material in which thermal conduction occurs by phonons. The thickness of the conductor 1 in the z direction may be, for example, 100 nm to 900 nm, 200 nm to 800 nm, or 300 nm to 700 nm. The thickness of the conductor 1 in the z direction may be the same as that of the insulating layer 2.

[0017] The first terminal 41 and the second terminal 42 are each connected to the conductor 1. The second terminal 42 is located opposite the first terminal 41 in the x direction. Although the first terminal 41 and the second terminal 42 are shown as the two ends of the conductor 1 in the x direction in FIG. 1 , the first terminal and the second terminal may be separate members from the conductor 1 and connected to both ends of the conductor 1.

[0018] During rated operation of the electronic device 100, the temperature of the first terminal 41 is higher than the temperature of the second terminal 42. When a temperature gradient exists between the first terminal 41 and the second terminal 42, a potential difference occurs between the first terminal 41 and the second terminal 42 due to the Seebeck effect. This potential difference is used as the electromotive force of the electronic device 100. Here, during rated operation of the electronic device 100 means, for example, a state in which the electronic device 100 is operated by applying a rated voltage to the electronic device 100.

[0019] The "extension direction" is the direction of heat flow when there is a temperature gradient between the first terminal 41 and the second terminal 42. Specifically, the "extension direction" is the direction along the macroscopic movement path of phonons and carriers in the conductor 1, and is the direction in which the conductor 1 extends from the first terminal 41 to the second terminal 42. The "vertical direction" is the direction perpendicular to the extension direction in a plan view of the main surface 10a. In the present embodiment 1, the extension direction is the x direction, and the perpendicular direction is the y direction.

[0020] The conductor 1 has a nanostructure. Specifically, a plurality of slits 13 are provided on the main surface 10a. As shown in Fig. 3, the slits 13 penetrate the conductor 1 so as to reach the back surface 10b from the main surface 10a. Note that the slits 13 do not have to penetrate the conductor 1, and may be grooves having a bottom surface 10c (see Fig. 51).

[0021] Main surface 10a includes phonon trapping regions 11 and connecting regions 12. Connecting regions 12 are continuous with phonon trapping regions 11. In the first embodiment, phonon trapping regions 11 and connecting regions 12 are defined by a plurality of slits 13 that are rectangular in shape when viewed in plan of main surface 10a.

[0022] The shapes of the slits 13, the phonon trapping regions 11, and the connecting regions 12 in a planar view of the main surface 10a are appropriately changed depending on the first mean free path, which is the mean free path of phonons in the conductor 1, and the second mean free path, which is the mean free path of carriers.

[0023] In the first embodiment, the first mean free path is the mean free path of phonons in the conductor 1 at the lowest possible temperature of the first terminal 41 and the second terminal 42 during rated operation of the electronic device 100. When the lowest possible temperature of the first terminal 41 and the second terminal 42 during rated operation of the electronic device 100 is 300° C. (room temperature) and the material constituting the conductor 1 is silicon, the mean free path of phonons of the silicon at room temperature is, for example, not less than 100 nm and not more than 1000 nm.

[0024] Furthermore, in the first embodiment, the second mean free path may be the mean free path of carriers in the conductor 1 at the lowest possible temperature of the first terminal 41 and the second terminal 42 during rated operation of the electronic device 100. When the lowest possible temperature of the first terminal 41 and the second terminal 42 during rated operation of the electronic device 100 is 300° C. (room temperature) and the material constituting the conductor 1 is silicon, the mean free path of carriers in the silicon at room temperature is, for example, 10 nm or more and 100 nm or less.

[0025] 1 and 2 , each of the multiple slits 13 has a rectangular shape in a plan view of the main surface 10a. The length of a long side s1 of the slit 13 (the length W1 of the slit 13 in the direction in which the slit 13 extends) is greater than the first mean free path of phonons in the conductor 1. The length of a short side s2 of the slit 13 (the width W2 of the slit 13 in the direction perpendicular to the direction in which the slit 13 extends) is less than the first mean free path of phonons in the conductor 1. The first mean free path of phonons is greater than the second mean free path of carriers.

[0026] The plurality of slits 13 include inclined portions 13c and parallel portions 13e. The parallel portions 13e extend along the extension direction (the x direction in the first embodiment) of the main surface 10a in a plan view.

[0027] On the other hand, the inclined portion 13c is inclined with respect to the extension direction in a planar view of the main surface 10a. The inclination angle θ of the inclined portion 13c with respect to the extension direction is greater than 0° and less than or equal to 90°. In other words, the inclination angle θ may be 90°. The multiple slits 13 may include vertical portions 13d. As shown in FIGS. 1 and 2, the vertical portions 13d are inclined perpendicularly with respect to the extension direction (x direction in the first embodiment) in a planar view of the main surface 10a. Note that in FIG. 1, the inclination angle θ of the inclined portion 13c is defined as the angle of the long side of the inclined portion 13c with respect to the extension direction (x direction). However, the inclination angle θ may also be defined as the angle formed by the central axis of the inclined portion 13c (an axis passing through the center in the width direction perpendicular to the extension direction of the inclined portion 13c and aligned with the extension direction of the inclined portion 13c) with respect to the extension direction (x direction).

[0028] The multiple slits 13 are arranged at a distance from one another. The extending directions of the multiple slits 13 intersect with one another. The long side s1 of one slit 13 faces the short side s2 of the other slit 13 adjacent to the first slit 13.

[0029] The phonon trapping region 11 is defined by four slits 13. Specifically, the phonon trapping region 11 is a region surrounded by the long sides s1 of the four slits 13.

[0030] The communication region 12 is defined by two slits 13. Specifically, the communication region 12 is a region sandwiched between a long side s1 of one slit 13 and a short side s2 of the other slit 13 adjacent to the first slit 13.

[0031] The plurality of slits 13 include slit portions 13a and slit portions 13b. In the first embodiment, the slit portions 13a extend along the x direction. The slit portions 13b extend along the y direction.

[0032] 1 , the width W3 of phonon trapping region 11 in the vertical direction (y direction in the first embodiment) is larger than the width L of communication region 12 in the vertical direction. Width W3 of phonon trapping region 11 is the distance between the long sides s1 of two opposing slit portions 13a. Width L of communication region 12 is the distance between slit portion 13a and slit portion 13b adjacent to slit portion 13a. Width L of communication region 12 is, for example, the distance between the long side s1 of slit portion 13a and the short side s2 of slit portion 13b.

[0033] Here, the electronic device 100 according to the first embodiment is characterized in that the minimum width L2 of the communication region 12 is three times or less the first mean free path of phonons in the conductor 1 and is equal to or greater than the second mean free path of carriers in the conductor 1. The minimum width L2 is the smallest width within the width L of the communication region 12, and is, for example, the shortest distance between the long side s1 of the slit portion 13a and the short side s2 of the slit portion 13b. The direction in which the slit portion 13a extends is perpendicular to the direction in which the slit portion 13b extends. Therefore, in the first embodiment, the long side s1 of the slit portion 13a and the short side s2 of the slit portion 13b are parallel to each other. In other words, the minimum width L2 coincides with the width L.

[0034] In this way, heat conduction by phonons can be suppressed without inhibiting electrical conduction by carriers in conductor 1. Specifically, phonons that have entered communication region 12 are reflected and scattered by the interface with slit 13. The reflected and scattered phonons travel in a direction inclined with respect to the x direction, and are again reflected and scattered by the interface with slit 13. In this way, phonons that have entered communication region 12 are repeatedly reflected and scattered by the interface with slit 13.

[0035] Phonons that are repeatedly reflected and scattered in communication region 12 enter phonon trap region 11. Phonons that are reflected and scattered in communication region 12 are less likely to flow out of phonon trap region 11. As a result, the thermal conduction of phonons can be suppressed, and as will be described later, the apparent thermal conductivity κ of conductor 1 can be reduced.

[0036] On the other hand, if the minimum width L2 of the communication region 12 is greater than three times the first mean free path of phonons in the conductor 1, the suppression of thermal conduction of phonons is reduced. Also, if the minimum width L2 of the communication region 12 is smaller than the second mean free path of carriers in the conductor 1, the carriers are repeatedly reflected and scattered at the interface with the slits 13 in the communication region 12. As a result, electrical conduction by the carriers is hindered.

[0037] From the above, if the minimum width L2 of the communication region 12 is less than three times the first mean free path of phonons in the conductor 1 and is greater than or equal to the second mean free path of carriers in the conductor 1, thermal conduction by phonons can be suppressed without impeding electrical conduction by carriers.

[0038] The minimum width L2 may be 0.05 to 1.2 times the first mean free path, which makes it possible to further suppress heat conduction by phonons without impeding electrical conduction by carriers.

[0039] The communication region 12 includes a region that extends perpendicular to the vertical direction (the y direction in the first embodiment) of the main surface 10a in a plan view. Specifically, the communication region 12 includes a plurality of communication portions 12a and 12b.

[0040] 1 and 2, the communication portion 12a is a region sandwiched between the short side s2 of the slit portion 13b extending in the y direction and the long side s1 of the slit portion 13a extending in the x direction. In other words, the communication portion 12a extends in the extension direction (the x direction in the first embodiment).

[0041] 1, the communicating portion 12b is a region sandwiched between a short side s2 of the slit portion 13a extending in the x direction and a long side s1 of the slit portion 13b extending in the y direction. In other words, the communicating portion 12b extends in the vertical direction (the y direction in the first embodiment).

[0042] As shown in Figure 2, the length L1 of the communicating portion 12a in the extension direction is equal to the length of the short side s2 of the slit portion 13b (the width W2 of the slit 13 in a direction perpendicular to the extension direction of the slit 13).

[0043] 1, the phonon trap region 11 includes a plurality of phonon trap portions 11a. The plurality of phonon trap portions 11a may be arranged in a matrix when viewed in plan on the main surface 10a. Adjacent phonon trap portions 11a are connected by a communication region 12. In this manner, the plurality of phonon trap portions 11a and the plurality of communication portions 12a, 12b are periodically arranged in the extension direction and the vertical direction, thereby further suppressing heat conduction due to phonons.

[0044] <Method of Manufacturing Electronic Device> A method of manufacturing the electronic device 100 according to the first embodiment will now be described. Figures 4 to 6 are schematic cross-sectional views showing steps of the method of manufacturing the electronic device 100 according to the first embodiment.

[0045] First, a step (S1a) of preparing a conductor 1 is performed. In this step (S1a), as shown in Fig. 4, a conductor 1 is prepared as an SOI (Silicon On Insulator) wafer, in which the conductor 1 is disposed on a substrate 3 via an insulating layer 2. The conductor 1 may be a silicon substrate that has been polished to be thin.

[0046] The substrate 3 is, for example, a silicon substrate. An insulating layer 2 is formed on a surface 3a of the substrate 3. The insulating layer 2 is, for example, a silicon oxide film. The conductor 1 is connected to the insulating layer 2 on a back surface 10b.

[0047] Next, a step (S2a) of forming a photoresist 5 is performed. In this step (S2a), as shown in FIG. 5 , the photoresist 5 is applied onto the conductor 1 and finely patterned. The patterned photoresist 5 is formed using an exposure device such as an electron beam lithography device or an EUV (Extreme Ultra Violet) exposure device. In this manner, a nanoscale fine pattern can be formed in the photoresist 5. An opening 5h is provided in the patterned photoresist 5. A portion of the conductor 1 is exposed from the photoresist 5 at the opening 5h in the photoresist 5.

[0048] Next, a step (S3a) of forming slits 13 is performed. In this step (S3a), as shown in FIG. 6, photoresist 5 is used as a mask to form slits 13 in conductor 1 exposed from photoresist 5 at openings 5h in photoresist 5. Conductor 1 is etched using a DRIE (Deep Reactive-Ion Etching) device. In this way, slits 13 with a high aspect ratio can be formed in the direction perpendicular to main surface 10a. Thereafter, photoresist 5 is removed.

[0049] Next, a step (S4a) is performed to form grooves H in insulating layer 2. In this step (S4a), grooves H are formed by etching insulating layer 2. Insulating layer 2 is etched by wet etching using a hydrogen fluoride (HF) aqueous solution or dry etching using hydrogen fluoride vapor.

[0050] It may be difficult to etch the insulating layer 2 by making the hydrogen fluoride penetrate the fine slits 13. For this reason, vent holes (not shown) that communicate with the insulating layer 2 may be formed in the conductor 1, and the hydrogen fluoride may penetrate through the vent holes to etch the insulating layer 2. The inner periphery width of the vent holes is, for example, 1 μm or more. In this manner, the electronic device 100 shown in FIGS. 1 to 3 can be obtained.

[0051] <Effects> An electronic device 100 according to the present disclosure includes a conductor 1, a first terminal 41, and a second terminal 42. The conductor 1 has a main surface 10a. The first terminal 41 is connected to the conductor 1. The second terminal 42 is connected to the conductor 1. The second terminal 42 is located opposite the first terminal 41 in the extension direction (x direction) of the conductor 1. A plurality of slits 13 are provided in the main surface 10a. The main surface 10a includes a phonon trapping region 11 and a communicating region 12. The phonon trapping region 11 is defined by the plurality of slits 13. The communicating region 12 is connected to the phonon trapping region 11. The plurality of slits 13 include inclined portions 13c. The inclined portions 13c are inclined with respect to the extension direction (x direction) of the main surface 10a in a plan view. The minimum width L2 of the communication region 12 is three times or less the first mean free path of phonons in the conductor 1. The minimum width L2 of the communication region 12 is equal to or greater than the second mean free path of carriers in the conductor 1.

[0052] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0053] In the electronic device 100, the length W1 of the slit 13 in the direction in which the slit 13 extends in a plan view of the main surface 10 a is greater than the first mean free path. The width W2 of the slit 13 in the direction perpendicular to the direction in which the slit 13 extends in a plan view of the main surface 10 a is equal to or less than the first mean free path.

[0054] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0055] According to the electronic device 100, the first mean free path is the mean free path of phonons in the conductor 1 at the lowest possible temperature of the first terminal 41 and the second terminal 42 when the electronic device 100 is operating at rated speed.

[0056] In this way, the shape of the slits 13 can be set so as to suppress heat conduction by phonons without impeding electrical conduction by carriers in the conductor 1 .

[0057] According to the electronic device 100, the second mean free path is the mean free path of carriers in the conductor 1 at the lowest possible temperature of the first terminal 41 and the second terminal 42 when the electronic device 100 is operating at rated speed.

[0058] In this way, the shape of the slits 13 can be set so as to suppress heat conduction by phonons without impeding electrical conduction by carriers in the conductor 1 .

[0059] According to the electronic device 100, the minimum width L2 is not less than 0.05 times and not more than 1.2 times the first mean free path.

[0060] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0061] According to the electronic device 100, the plurality of slits 13 include vertical portions 13d. The vertical portions 13d extend perpendicular to the extension direction (x direction).

[0062] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0063] According to the electronic device 100, the plurality of slits 13 include parallel portions 13e. The parallel portions 13e extend along the extension direction (x direction).

[0064] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0065] According to the electronic device 100, the communication region 12 includes a plurality of communication portions 12 a and 12 b. The direction perpendicular to the extension direction (x direction) of the main surface 10 a in a plan view is defined as the vertical direction (y direction). The communication portions 12 a and 12 b are periodically arranged in the vertical direction (y direction).

[0066] In this way, it is possible to further suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 in which the thermal conductivity is further suppressed without inhibiting the electrical conduction.

[0067] According to the electronic device 100, the plurality of communication portions 12a, 12b are periodically arranged in the extension direction (x direction).

[0068] In this way, it is possible to further suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 in which the thermal conductivity is further suppressed without inhibiting the electrical conduction.

[0069] According to the electronic device 100 , the temperature of the first terminal 41 is higher than the temperature of the second terminal 42 during rated operation of the electronic device 100 .

[0070] In this way, when the electronic device 100 is operating at rated speed, the heat conduction caused by phonons is suppressed without impeding the electrical conduction caused by carriers in the conductor 1 .

[0071] According to the electronic device 100, the phonon trap region 11 includes a plurality of phonon trap portions 11a. The plurality of phonon trap portions 11a are arranged in a matrix. Adjacent phonon trap portions 11a are connected by a communication region 12.

[0072] In this way, the heat conduction caused by phonons is further suppressed without impeding the electrical conduction caused by carriers in the conductor 1 .

[0073] According to the electronic device 100, the width W3 of the phonon trapping region 11 in a direction perpendicular to the extension direction (x direction) in a planar view of the main surface 10a is greater than the width L of the communicating region 12 in a direction perpendicular to the extension direction (x direction) in a planar view of the main surface 10a.

[0074] In this way, the heat conduction caused by phonons is further suppressed without impeding the electrical conduction caused by carriers in the conductor 1 .

[0075] <First Modification of Electronic Device> Fig. 7 is a schematic plan view of an electronic device 100 according to a first modification of the first embodiment. Fig. 7 corresponds to Fig. 1. The electronic device 100 shown in Fig. 7 basically has the same configuration as the electronic device 100 shown in Figs. 1 to 3 and can obtain the same effects, but differs in that the multiple slits 13 extend at an angle with respect to the extension direction.

[0076] Specifically, the inclined portion 13c is inclined with respect to the extending direction of the main surface 10a in a plan view. The inclination angle θ of the inclined portion 13c with respect to the extending direction is greater than 0° and less than 90°.

[0077] From a different perspective, the plurality of slits 13 may include straight line portions 13f. The straight line portions 13f are inclined with respect to the extension direction. The inclined portions 13c included in the plurality of slits 13 include at least two types of slits 13 having different inclination angles θ with respect to the extension direction (x direction). In the conductor 1, the slits 13 having different inclination angles θ are alternately arranged in the extension direction (x direction).

[0078] In this way, communication region 12 may include region 12c that extends at an angle relative to the vertical direction (the y direction in the first embodiment) in a plan view of main surface 10a.

[0079] <Effects> In the electronic device 100, the direction perpendicular to the extension direction (x direction) of the main surface 10 a in a plan view is defined as the vertical direction (y direction). The communication region 12 includes a region 12 c that extends at an angle to the vertical direction (y direction) in a plan view of the main surface 10 a.

[0080] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0081] According to the electronic device 100, the plurality of slits 13 include straight line portions 13f, which are inclined with respect to the extending direction (x direction).

[0082] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0083] <Modification 2 of Electronic Device> Fig. 8 is a schematic plan view of an electronic device 100 according to Modification 2 of Embodiment 1. Fig. 8 corresponds to Fig. 1. The electronic device 100 shown in Fig. 8 basically has the same configuration as the electronic device 100 shown in Figs. 1 to 3 and can obtain the same effects, but differs in that the multiple slits 13 do not have slit portions 13a extending along the x direction.

[0084] Specifically, all of the multiple slits 13 extend along the y direction. The multiple slits 13 are periodically arranged in the y direction. The short side s2 of one slit 13 faces the short side s2 of the other slit 13 adjacent to the one slit 13 in the y direction. Multiple rows of slits 13 (slit rows) are formed along the y direction, with communication regions 12 interposed between them. These multiple slit rows are arranged at intervals from each other in the extension direction (x direction). The multiple slit rows are arranged to extend parallel to each other.

[0085] The phonon trapping region 11 may be a region sandwiched between the long side s1 of one slit 13 and the long side s1 of the other slit 13 adjacent to the one slit 13 in the x direction.

[0086] The communication region 12 may be a region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the one slit 13 in the y direction. In other words, all of the multiple communication portions 12a extend in the extension direction (x direction). The minimum width L2 of the communication region 12 is the shortest distance between the short sides s2 of the two slits 13 facing each other. The positions in the y direction of the communication regions 12 in one slit row are different from the positions in the y direction of the communication regions 12 in another slit row adjacent to the one slit row in the extension direction (x direction). Note that the positions in the y direction of the communication regions 12 in one slit row may overlap the positions in the y direction of the communication regions 12 in the other slit row.

[0087] <Operation and Effect> According to the electronic device 100, the communication region 12 includes a plurality of communication portions 12a. All of the plurality of communication portions 12a extend in the extension direction (x direction).

[0088] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0089] Second Embodiment <Configuration of Electronic Device> Fig. 9 is a schematic plan view of an electronic device 100 according to a second embodiment. Fig. 9 corresponds to Fig. 1. Fig. 10 is a schematic partial enlarged plan view of region X in Fig. 9. Fig. 10 corresponds to Fig. 2. The electronic device 100 shown in Figs. 9 and 10 basically has the same configuration as the electronic device 100 shown in Figs. 1 to 3 and can obtain the same effects, but differs in that the shape of the slits 13 in the main surface 10a in plan view is hexagonal.

[0090] The multiple slits 13 extend at an angle to the extension direction (x direction). A side s3 of one slit 13 faces a side s3 of the other slit 13 adjacent to the one slit 13 in the y direction. Each phonon trapping region 11 is surrounded by four slits 13. The multiple phonon trapping regions 11 are arranged in a triangular lattice pattern.

[0091] The communicating portion 12a may be a region sandwiched between a side s3 of one slit 13 and a side s3 of the other slit 13 adjacent to the one slit 13 in the y direction. The minimum width L2 of the communicating portion 12a is the shortest distance in the y direction between the sides s3 of the two slits 13 facing each other.

[0092] In one slit 13, the other side s3 continuing to the side s3 facing the communicating portion 12a faces the side s3 of the other slit 13 adjacent to the one slit 13 in the x direction.

[0093] The communicating portion 12b may be a region sandwiched between a side s3 of one slit 13 and a side s3 of the other slit 13 adjacent to the first slit 13 in the x-direction. The minimum width L2 of the communicating portion 12b is the shortest distance in the x-direction between the sides s3 of the two slits 13 facing each other. The length L1 of the communicating portions 12a and 12b is equal to the length of the side s3 of the slit 13.

[0094] Third Embodiment <Configuration of Electronic Device> Fig. 11 is a schematic plan view of an electronic device 100 according to a third embodiment. Fig. 11 corresponds to Fig. 9 . Fig. 12 is a schematic partial enlarged plan view of region XII in Fig. 11 . Fig. 12 corresponds to Fig. 10 . The electronic device 100 shown in Figs. 11 and 12 basically has the same configuration as the electronic device 100 shown in Figs. 11 and 12 and can achieve the same effects, but differs in that the slit 13 includes a bent portion 13g.

[0095] 11 and 12 , the shape of the slit 13 in a plan view of the main surface 10a may be V-shaped. Specifically, the slit 13 includes a first portion 31 and a second portion 32. The first portion 31 and the second portion 32 each extend at an angle with respect to the x-direction. The first portion 31 and the second portion 32 are connected via a bent portion 13g.

[0096] The first portion 31 may extend at an inclination of, for example, 45° with respect to the x-direction. The second portion 32 may extend at an inclination of, for example, 135° with respect to the x-direction. That is, the second portion 32 may extend at an inclination of 90° with respect to the direction in which the first portion 31 extends from the first portion 31. In this way, the slit 13 may be formed in a V-shape when viewed in plan of the main surface 10a.

[0097] The two V-shaped slits 13 are adjacent to each other in the y direction at a bent portion 13g. At the bent portion 13g, a side s4 of one slit 13 faces a side s4 of the other slit 13 adjacent to the one slit 13 in the y direction. The side s4 extends in the x direction.

[0098] Communication region 12 may be a region sandwiched between side s4 of one slit 13 and side s4 of the other slit 13 adjacent to the first slit 13 in the y direction at bent portion 13g. In other words, minimum width L2 of communication region 12 may be the shortest distance in the y direction between the opposing sides s4 of the two slits 13. The end of one slit 13 farthest from bent portion 13g faces the corresponding end of the other slit 13 adjacent to it in the y direction. Therefore, phonon trapping region 11 is surrounded by two slits 13 each having a bent portion 13g. The multiple phonon trapping regions 11 are arranged in a triangular lattice pattern.

[0099] <Operation and Effect> According to the electronic device 100, the plurality of slits 13 include the bent portions 13g.

[0100] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0101] <Electronic Device Modification 3> FIG. 13 is a schematic plan view of an electronic device 100 according to Modification 3 of Embodiment 3. FIG. 13 corresponds to FIG. 11 . The electronic device 100 shown in FIG. 13 basically has the same configuration as the electronic device 100 shown in FIGS. 11 and 12 and can achieve the same effects, but differs in that the shape of the multiple slits 13 in a plan view of the main surface 10 a is cross-shaped. Specifically, the first portion 31 and the second portion 32 intersect at a bent portion 13 g. In other words, there is no communication region 12 adjacent to the bent portion 13 g shown in FIGS. 11 and 12 , and the bent portions 13 g of two slits 13 adjacent in the y direction in FIG. 11 are connected to form the cross-shaped slit 13.

[0102] A plurality of cross-shaped slits 13 may be arranged in a matrix pattern. Specifically, a plurality of cross-shaped slits 13 may be arranged periodically (in a grid pattern) in the x and y directions.

[0103] <Fourth Modification of Electronic Device> Fig. 14 is a schematic plan view of an electronic device 100 according to a fourth modification of the third embodiment. Fig. 14 corresponds to Fig. 13 . The electronic device 100 shown in Fig. 14 basically has the same configuration as the electronic device 100 shown in Fig. 13 and can achieve the same effects, but differs in that the multiple cross-shaped slits 13 are arranged in a staggered pattern in a plan view of the main surface 10a. In other words, the multiple cross-shaped slits 13 do not have to be arranged side by side (continuously) along the x direction.

[0104] <Fifth Modification of Electronic Device> Fig. 15 is a schematic plan view of an electronic device 100 according to a fifth modification of the third embodiment. Fig. 15 corresponds to Fig. 11. The electronic device 100 shown in Fig. 15 basically has the same configuration as the electronic device 100 shown in Fig. 11 and can obtain the same effects, but differs in that the first portion 31 extends along the x direction and the second portion 32 extends along the y direction.

[0105] The second portion 32 may extend from the first portion 31 at an angle of 90° with respect to the extending direction of the first portion 31. In this manner, the slits 13 may be formed in a V-shape when viewed in plan of the main surface 10a. In FIG. 15 , the first portions 31 of the multiple slits 13 are arranged to line up along the x direction. The second portions 32 of the multiple slits 13 are arranged to line up along the y direction. As a result, the phonon trapping region 11 is surrounded by three slits 13: one slit 13, another slit 13 located in the x direction relative to the first slit 13, and yet another slit 13 located in the y direction relative to the first slit 13.

[0106] The communication region 12 may be a region sandwiched between the long side s1 of the first portion 31 of one slit 13 and the short side s2 of the second portion 32 of the other slit 13 adjacent to the one slit 13 in the y direction. In other words, the minimum width L2 of the communication portion 12a as the communication region 12 may be the shortest distance in the y direction between the long side s1 and the short side s2 of the two slits 13 facing each other. The minimum width of the communication portion 12b as the communication region 12 may be the shortest distance between an end of the first portion 31 of one slit 13 and the opposing end of the first portion 31 of another slit 13 adjacent to the one slit 13 in the x direction.

[0107] <Sixth Modification of Electronic Device> Fig. 16 is a schematic plan view of an electronic device 100 according to a sixth modification of the third embodiment. Fig. 16 corresponds to Fig. 15. The electronic device 100 shown in Fig. 16 basically has the same configuration as the electronic device 100 shown in Fig. 15 and can obtain the same effects as the electronic device 100, but differs in that the shape of the slits 13 in the plan view of the main surface 10a is U-shaped.

[0108] Specifically, the slit 13 includes a first portion 31, a pair of second portions 32, and a pair of bent portions 13g. In the x direction, each of the pair of second portions 32 is connected to the first portion 31 via the bent portion 13g. The pair of second portions 32 are arranged to sandwich the first portion 31 in the x direction. In this manner, the slit 13 may be formed in a U-shape in a plan view of the main surface 10a. A plurality of U-shaped slits 13 are arranged in a lattice pattern. Therefore, one phonon trapping region 11 is surrounded by one slit 13 and the first portion 31 of another slit 13 adjacent to that one slit 13 in the y direction.

[0109] <Seventh Modification of Electronic Device> Fig. 17 is a schematic plan view of an electronic device 100 according to a seventh modification of the third embodiment. Fig. 17 corresponds to Fig. 16. The electronic device 100 shown in Fig. 17 basically has the same configuration as the electronic device 100 shown in Fig. 16 and can obtain the same effects, but differs in that two adjacent slits 13 are arranged so as to be mirror-symmetric.

[0110] As shown in Figure 17, two U-shaped slits 13 adjacent in the y direction are arranged so as to be mirror-symmetric. Such two U-shaped slits 13 are arranged periodically in the x and y directions. That is, the multiple slits 13 aligned in the y direction are arranged with the orientation of the U-shape in the y direction alternately reversed. Furthermore, the multiple slits 13 aligned in the x direction all have the same orientation of the U-shape in the y direction. The communication region 12 is the region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the first slit 13 in the y direction.

[0111] <Electronic Device Variation 8> Figure 18 is a schematic plan view of an electronic device 100 according to Variation 8 of Embodiment 3. Figure 18 corresponds to Figure 17. The electronic device 100 shown in Figure 18 basically has the same configuration as the electronic device 100 shown in Figure 17 and can achieve the same effects, but in a plan view of the main surface 10a, the multiple slits 13 aligned in the x direction are arranged such that the orientations of the U-shaped slits in the y direction are alternately inverted. In this case, the phonon trapping regions 11 are arranged in a triangular lattice or staggered pattern.

[0112] <Ninth Modification of Electronic Device> Figure 19 is a schematic plan view of an electronic device 100 according to a ninth modification of the third embodiment. Figure 19 corresponds to Figure 16. The electronic device 100 shown in Figure 19 basically has the same configuration as the electronic device 100 shown in Figure 16 and can achieve the same effects, but differs in that the shape of the slit 13 in a plan view of the main surface 10a is H-shaped. The slit 13 extends in the y direction and includes two second portions 32 arranged at an interval in the x direction, and a first portion 31 connecting the two second portions 32.

[0113] The first portion 31 is connected to the center of the second portion 32 in the y direction. In this way, the slits 13 may be formed in an H-shape when viewed from above on the main surface 10a. Such H-shaped slits 13 are periodically arranged in the x and y directions. The communication region 12 is a region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the first slit 13 in the y direction. The region surrounded by two slits 13 lined up in the y direction forms the phonon trap region 11.

[0114] <Electronic Device Modification 10> Fig. 20 is a schematic plan view of an electronic device 100 according to Modification 10 of Embodiment 3. Fig. 20 corresponds to Fig. 19 . The electronic device 100 shown in Fig. 20 basically has the same configuration as the electronic device 100 shown in Fig. 19 and can achieve the same effects, but differs in that the H-shaped slits 13 are arranged in a staggered pattern in a plan view of the main surface 10a. In other words, the multiple H-shaped slits 13 do not have to be arranged continuously in the x direction.

[0115] <Eleventh Modification of Electronic Device> Fig. 21 is a schematic plan view of an electronic device 100 according to an eleventh modification of embodiment 3. Fig. 21 corresponds to Fig. 16. The electronic device 100 shown in Fig. 21 basically has the same configuration as the electronic device 100 shown in Fig. 16 and can obtain the same effects, but differs in that a plurality of U-shaped slits 13 are connected to each other in the x direction when viewed in plan on the main surface 10a.

[0116] Specifically, the slit 13 includes a first portion 31, a plurality of second portions 32, and a plurality of bent portions 13g. The plurality of second portions 32 are connected to the first portion 31 via the bent portions 13g. The first portion 31 extends along the x direction. One end of the plurality of second portions 32 is connected to the first portion 31, and the plurality of second portions 32 extend in the y direction. In FIG. 21 , four second portions 32 are connected to one first portion 31. In this manner, U-shaped slits 13 may be connected in the x direction in a plan view of the main surface 10a. Alternatively, a plurality of slits 13 having the shape shown in FIG. 21 may be arranged in a line along the x direction. In other words, the plurality of slits 13 shown in FIG. 21 may be arranged in a lattice pattern.

[0117] As shown in FIG. 21 , two adjacent slits 13 in the y direction are arranged so as to be mirror-symmetric. Such two slits 13 are arranged periodically in the y direction. A plurality of slits 13 are arranged side by side in the y direction. A plurality of slits 13 arranged side by side in the y direction are arranged so that the positional relationship between the first portions 31 and the second portions 32 in the y direction alternates. The second portions 32 and a part of the first portions 31 surround the phonon trapping region 11. The communication region 12 is a region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the first slit 13 in the y direction. A plurality of communication portions 12a and a plurality of phonon trapping portions 11a are formed by two slits 13 adjacent to each other in the y direction.

[0118] <Modification 12 of Electronic Device> Fig. 22 is a schematic plan view of an electronic device 100 according to Modification 12 of Embodiment 3. Fig. 22 corresponds to Fig. 19. The electronic device 100 shown in Fig. 22 basically has the same configuration as the electronic device 100 shown in Fig. 19 and can obtain the same effects, but differs in that the plurality of H-shaped slits 13 are connected to each other in the x direction when viewed in plan on the main surface 10a.

[0119] Specifically, the slit 13 includes a first portion 31, a plurality of second portions 32, and a plurality of bent portions 13g. The plurality of second portions 32 are connected to the first portion 31 via the bent portions 13g. The first portion 31 extends along the x direction. The plurality of second portions 32 extend along the y direction and are arranged at intervals from one another in the x direction. The first portion 31 is connected to the center of each of the plurality of second portions 32 in the y direction. In this manner, H-shaped slits 13 may be arranged in the x direction in a plan view of the main surface 10a. Alternatively, a plurality of slits 13 having the shape shown in FIG. 22 may be arranged in a line along the x direction. In other words, the plurality of slits 13 shown in FIG. 22 may be arranged in a lattice pattern.

[0120] 22 , the multiple slits 13 aligned in the y direction are periodically arranged in the y direction. The communication region 12 is a region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the first slit 13 in the y direction. Two slits 13 adjacent to each other in the y direction form multiple communication portions 12a and multiple phonon trap portions 11a.

[0121] <Modification 13 of Electronic Device Configuration> Figure 23 is a schematic plan view of an electronic device 100 according to Modification 13 of Embodiment 3. Figure 23 corresponds to Figure 11. The electronic device 100 shown in Figure 23 basically has the same configuration as the electronic device 100 shown in Figures 11 and 12 and can obtain the same effects, but differs in that the angle between the first portion 31 and the second portion 32 is an acute angle.

[0122] As shown in FIG. 23 , the slits 13 have a V-shape in a plan view of the main surface 10a. The first portions 31 extend along the x-direction. The second portions 32 extend at an angle relative to the x-direction. That is, the second portions 32 are inclined at an acute angle relative to the direction in which the first portions 31 extend from the first portions 31. That is, the angle between the first portions 31 and the second portions 32 is less than 90°. In this manner, the slits 13 may be formed in a V-shape in a plan view of the main surface 10a. Such V-shaped slits 13 are arranged periodically in the x-direction and the y-direction, i.e., in a grid pattern.

[0123] The side s3 of one slit 13 faces the long side s1 of the other slit 13 adjacent to the one slit 13 in the y direction. The side s3 is located at the end of the second portion 32. The communicating portion 12a may be a region sandwiched between the side s3 of one slit 13 and the long side s1 of the other slit 13 adjacent to the one slit 13 in the y direction. The minimum width L2 of the communicating portion 12a is the shortest distance in the y direction between the side s3 and the long side s1 of the two slits 13 facing each other. The minimum width of the communicating portion 12b as the communicating region 12 may be the shortest distance between the end of the first portion 31 of one slit 13 and the opposing end of the first portion 31 of another slit 13 adjacent to the one slit 13 in the x direction.

[0124] <Modification 14 of Electronic Device> Fig. 24 is a schematic plan view of an electronic device 100 according to Modification 14 of Embodiment 3. Fig. 24 corresponds to Fig. 23. The electronic device 100 shown in Fig. 24 basically has the same configuration as the electronic device 100 shown in Fig. 23 and can obtain the same effects, but differs in that two slits 13 adjacent to each other in the y direction are arranged to be mirror-symmetric.

[0125] As shown in Figure 24, two V-shaped slits 13 adjacent in the y direction are arranged so as to be mirror-symmetric. That is, multiple slits 13 are arranged side by side in the y direction. Multiple slots 13 arranged side by side in the y direction are arranged so that the positional relationship in the y direction between the first portion 31 and the second portion 32 is alternately reversed. Such two V-shaped slits 13 are arranged periodically in the x direction and the y direction. The communication portion 12a is a region sandwiched between the side s3 of one slit 13 and the side s3 of the other slit 13 adjacent to the one slit 13 in the y direction.

[0126] <Modification 15 of Electronic Device Configuration> Fig. 25 is a schematic plan view of an electronic device 100 according to Modification 15 of Embodiment 3. Fig. 25 corresponds to Fig. 23. The electronic device 100 shown in Fig. 25 basically has the same configuration as the electronic device 100 shown in Fig. 23 and can obtain the same effects as the electronic device 100, but differs in that the shape of the slits 13 is arrow-shaped when viewed in plan of the main surface 10a.

[0127] Specifically, the slit 13 includes a first portion 31, a pair of second portions 32, and a pair of bent portions 13g. The pair of second portions 32 are connected to the end of the first portion 31 via the bent portions 13g. The pair of second portions 32 are arranged so as to be mirror images of each other when viewed from the first portion 31. In other words, the pair of second portions 32 extend in different directions. In this way, the slit 13 may be formed in an arrow shape when viewed in plan of the main surface 10a. Such arrow-shaped slits 13 are arranged periodically in the x direction and the y direction.

[0128] The side s3 of one slit 13 faces the side s3 of the other slit 13 adjacent to the one slit 13 in the y direction. The communicating portion 12a may be a region sandwiched between the side s3 of one slit 13 and the side s3 of the other slit 13 adjacent to the one slit 13 in the y direction. The minimum width L2 of the communicating portion 12a is the shortest distance in the y direction between the sides s3 of the two slits 13 facing each other.

[0129] <Modification 16 of Electronic Device Configuration> Fig. 26 is a schematic plan view of an electronic device 100 according to Modification 16 of Embodiment 3. Fig. 26 corresponds to Fig. 23. The electronic device 100 shown in Fig. 26 basically has the same configuration as the electronic device 100 shown in Fig. 23 and can obtain the same effects, but differs in that the second portions 32 are a pair.

[0130] Specifically, the slit 13 includes a first portion 31, a pair of second portions 32, and a pair of bent portions 13g. The first portion 31 extends along the x direction. One of the second portions 32 is connected to one end of the first portion 31 via the bent portion 13g. The other of the second portions 32 is connected to the other end of the first portion 31, which is located opposite the one end in the x direction, via the bent portion 13g. The pair of second portions 32 extend in the same direction. However, the pair of second portions 32 may extend in different directions. In this way, the slit 13 may be formed in a U-shape when viewed from above on the main surface 10a. Such U-shaped slits 13 are periodically arranged in the x direction and the y direction.

[0131] The side s3 of one slit 13 faces the long side s1 of the other slit 13 adjacent to the one slit 13 in the y direction. The communication region 12 may be a region sandwiched between the side s3 of one slit 13 and the long side s1 of the other slit 13 adjacent to the one slit 13 in the y direction. The minimum width L2 of the communication region 12 is the shortest distance in the y direction between the side s3 and the long side s1 of the two slits 13 facing each other.

[0132] <Modification 17 of Electronic Device Configuration> Fig. 27 is a schematic plan view of an electronic device 100 according to Modification 17 of Embodiment 3. Fig. 27 corresponds to Fig. 26. The electronic device 100 shown in Fig. 27 basically has the same configuration as the electronic device 100 shown in Fig. 26 and can obtain the same effects, but differs in that two slits 13 adjacent to each other in the y direction are arranged to be mirror-symmetric.

[0133] 27 , two U-shaped slits 13 adjacent to each other in the y direction are arranged so as to be mirror-symmetric. That is, the multiple slits 13 aligned in the y direction are arranged so that the positional relationship between the first portions 31 and the second portions 32 in the y direction is alternately reversed. Such two U-shaped slits 13 are arranged periodically in the x and y directions. The communication region 12 is a region sandwiched between the side s3 of one slit 13 and the side s3 of the other slit 13 adjacent to the one slit 13 in the y direction.

[0134] <Modification 18 of Electronic Device Configuration> Figure 28 is a schematic plan view of an electronic device 100 according to Modification 18 of Embodiment 3. Figure 28 corresponds to Figure 27. The electronic device 100 shown in Figure 28 basically has the same configuration as the electronic device 100 shown in Figure 27 and can obtain the same effects, but differs in that the directions in which the pair of second portions 32 extend are different from each other.

[0135] 28 , two U-shaped slits 13 adjacent in the y direction are arranged so as to be mirror-symmetric. Such two U-shaped slits 13 are periodically arranged in the x and y directions. The communication region 12 is a region sandwiched between a side s3 of one slit 13 and a side s3 of the other slit 13 adjacent to the first slit 13 in the y direction.

[0136] <Modification 19 of Electronic Device Configuration> Fig. 29 is a schematic plan view of an electronic device 100 according to Modification 19 of Embodiment 3. Fig. 29 corresponds to Fig. 25. The electronic device 100 shown in Fig. 29 basically has the same configuration as the electronic device 100 shown in Fig. 25 and can obtain the same effects, but differs in that a plurality of arrow-shaped slits 13 are connected to each other in the x direction when seen in a plan view of the main surface 10a.

[0137] Specifically, the slit 13 includes a first portion 31, a plurality of second portions 32, and a plurality of bent portions 13g. The first portion 31 extends along the x direction. A pair of second portions 32 are connected to the first portion 31 via bent portions 13g periodically in the x direction. The pair of second portions 32 are arranged so as to be mirror images of each other when viewed from the first portion 31. In other words, the pair of second portions 32 extend in different directions. In this way, arrow-shaped slits 13 may be connected in the x direction in a plan view of the main surface 10a. Such slits 13 are arranged periodically in the y direction.

[0138] The side s3 of one slit 13 faces the side s3 of the other slit 13 adjacent to the one slit 13 in the y direction. The communication region 12 may be a region sandwiched between the side s3 of one slit 13 and the side s3 of the other slit 13 adjacent to the one slit 13 in the y direction. The minimum width L2 of the communication region 12 is the shortest distance in the y direction between the sides s3 of the two slits 13 facing each other. Two slits 13 adjacent to each other in the y direction form multiple communication portions 12a and multiple phonon trap portions 11a.

[0139] Fourth Embodiment <Configuration of Electronic Device> Fig. 30 is a schematic plan view of an electronic device 100 according to a fourth embodiment. Fig. 30 corresponds to Fig. 1. Fig. 31 is a schematic partial enlarged plan view of region XXXI in Fig. 30. Fig. 32 is a schematic partial enlarged plan view of region XXXII in Fig. 30. Figs. 31 and 32 correspond to Fig. 2. The electronic device 100 shown in Figs. 30 to 32 basically has the same configuration as the electronic device 100 shown in Figs. 1 to 3 and can achieve the same effects, but differs in that the slit 13 includes a curved portion 13h.

[0140] 30 , the shape of the slit 13 in a plan view of the main surface 10a may be curved. Specifically, the slit 13 includes a curved portion 13h. The curved portion 13h may be arc-shaped or semicircular in the y direction. In this way, the slit 13 may be formed in an arc-shaped shape in a plan view of the main surface 10a.

[0141] The multiple arc-shaped slits 13 are adjacent to each other in the y direction. As shown in Figure 30, two adjacent arc-shaped slits 13 in the y direction are arranged so as to be mirror symmetric. In other words, the multiple slits 13 lined up in the y direction are arranged so that the directions of the arc openings in the y direction are alternately reversed. Such two arc-shaped slits 13 are arranged periodically in the x direction and y direction.

[0142] The phonon trap region 11 includes a plurality of phonon trap portions 11 a and 11 c. The communication region 12 includes a plurality of communication portions 12 a and 12 c. The phonon trap portion 11 a is a region sandwiched between the curved portions 13 h of two arc-shaped slits 13. The phonon trap portion 11 c is a region sandwiched between the curved portions 13 h of four arc-shaped slits 13.

[0143] 30 and 31 , the communication portion 12a is a region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the first slit 13 in the y direction. The communication portion 12a is continuous with the phonon trap portion 11a. The short side s2 extends in the x direction. In other words, the minimum width L2 is equal to the width L.

[0144] 30 and 32, communicating portion 12c is a region sandwiched between curved portion 13h of one slit 13 and curved portion 13h of the other slit 13 adjacent to the first slit 13 in the y direction. Communicating portion 12c is connected to phonon trapping portion 11c. As shown in Fig. 32, the minimum width L2 of communicating portion 12c is the shortest distance in the y direction between curved portions 13h of the two slits 13 facing each other.

[0145] The phonon trap region 11 may be sandwiched between two communicating portions 12a in the extension direction. Specifically, the phonon trap portion 11a is sandwiched between two communicating portions 12a in the x direction. The phonon trap portion 11c is sandwiched between two communicating portions 12c in the x direction. In this way, the two communicating portions 12a are connected to the curved portion 13h. The two communicating portions 12c are connected to the curved portion 13h.

[0146] <Operation and Effect> According to the electronic device 100, the plurality of slits 13 include the curved portions 13h.

[0147] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0148] According to the electronic device 100, the communication region 12 includes two communication portions 12a. The two communication portions 12a are connected to the curved portion 13h.

[0149] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0150] According to the electronic device 100, the communication region 12 includes two communication parts 12a. The phonon trapping region 11 is sandwiched between the two communication parts 12a in the extension direction.

[0151] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0152] <Modification 20 of Electronic Device Configuration> Fig. 33 is a schematic plan view of an electronic device 100 according to Modification 20 of Embodiment 4. Fig. 33 corresponds to Fig. 30. The electronic device 100 shown in Fig. 33 basically has the same configuration as the electronic device 100 shown in Figs. 30 to 32 and can obtain the same effects, but differs in that the slit 13 includes a parallel portion 13e.

[0153] Specifically, the slit 13 includes a curved portion 13h and a parallel portion 13e. The parallel portion 13e extending along the x direction is connected to a pair of curved portions 13h. In the x direction, the parallel portion 13e is arranged so as to be sandwiched between the pair of curved portions 13h. Specifically, one curved portion 13h is connected to one end of the parallel portion 13e. The other end of the parallel portion 13e located opposite the one end in the x direction is connected to the other curved portion 13h. In this manner, the area of ​​the phonon trapping region 11 may be adjusted.

[0154] <Modification 21 of Electronic Device Configuration> Figure 34 is a schematic plan view of an electronic device 100 according to Modification 21 of Embodiment 4. Figure 34 corresponds to Figure 30. The electronic device 100 shown in Figure 34 basically has the same configuration as the electronic device 100 shown in Figures 30 to 32 and can obtain the same effects, but differs in that a plurality of arc-shaped slits 13 are connected to each other in the x direction in a plan view of the main surface 10a.

[0155] 34, two adjacent slits 13 in the y direction are arranged so as to be mirror-symmetric. Such two slits 13 are arranged periodically in the y direction. A plurality of communication portions 12 a, 12 c and a plurality of phonon trap portions 11 a, 11 c are formed by two adjacent slits 13 in the y direction.

[0156] <Modification 22 of Electronic Device Configuration> Fig. 35 is a schematic plan view of an electronic device 100 according to Modification 22 of Embodiment 4. Fig. 35 corresponds to Fig. 33. The electronic device 100 shown in Fig. 35 basically has the same configuration as the electronic device 100 shown in Fig. 33 and can obtain the same effects as the electronic device 100, but differs in that the plurality of slits 13 are connected to each other in the x direction when seen in a plan view of the main surface 10a.

[0157] 35 , two adjacent slits 13 in the y direction are arranged so as to be mirror-symmetric. Such two slits 13 are arranged periodically in the y direction. A plurality of communication portions 12 a and a plurality of phonon trap portions 11 a, 11 c are formed by two adjacent slits 13 in the y direction.

[0158] Fifth Embodiment <Configuration of Electronic Device> Fig. 36 is a schematic plan view of an electronic device 100 according to a fifth embodiment. Fig. 36 corresponds to Fig. 7 . Fig. 37 is a schematic cross-sectional view of the electronic device 100 according to the fifth embodiment. Fig. 37 corresponds to Fig. 3 . The electronic device 100 shown in Figs. 36 and 37 basically has the same configuration as the electronic device 100 shown in Fig. 7 and can achieve the same effects, but differs in that a filling portion 6 is disposed in the slit 13.

[0159] The electronic device 100 includes a filling portion 6. The filling portion 6 fills the inside of the slit 13. The material constituting the filling portion 6 may be different from the material constituting the conductor 1. In other words, the third mean free path, which is the mean free path of phonons in the material constituting the filling portion 6, is different from the first mean free path of phonons in the material constituting the conductor 1.

[0160] When the material constituting the conductor 1 is silicon, the material constituting the filling portion 6 may be, for example, a silicon oxide film, germanium (Ge), or aluminum (Al).

[0161] In this way, phonons in the conductor 1 are reflected and scattered by the interface between the conductor 1 and the filling portion 6. As a result, heat conduction by phonons can be suppressed without impeding electrical conduction by carriers in the conductor 1.

[0162] In the fifth embodiment, the third mean free path is the mean free path of phonons in the filling portion 6 at the lowest possible temperature of the first terminal 41 and the second terminal 42 during rated operation of the electronic device 100 .

[0163] <Method of Manufacturing Electronic Device> A method of manufacturing the electronic device 100 according to the fifth embodiment will now be described. Figures 38 and 39 are schematic cross-sectional views showing one step of the method of manufacturing the electronic device 100 according to the fifth embodiment.

[0164] 4 to 6 in the manufacturing method of the electronic device 100 according to the first embodiment are performed. That is, a step (S1b) of preparing a conductor 1 is first performed. In this step (S1b), as shown in FIG. 4, a conductor 1 is prepared as an SOI (Silicon On Insulator) wafer, with an insulating layer 2 interposed between the substrate 3 and the conductor 1. The conductor 1 may be a silicon substrate that has been polished to be thin.

[0165] The substrate 3 is, for example, a silicon substrate. An insulating layer 2 is formed on a surface 3a of the substrate 3. The insulating layer 2 is, for example, a silicon oxide film. The conductor 1 is connected to the insulating layer 2 on a back surface 10b.

[0166] Next, a step (S2b) of forming a photoresist 5 is performed. In this step (S2b), as shown in FIG. 5 , a finely patterned photoresist 5 is formed on the conductor 1. The patterned photoresist 5 is formed using an exposure device such as an electron beam lithography device or an EUV (Extreme Ultra Violet) exposure device. In this manner, a fine nanoscale pattern can be formed in the photoresist 5. An opening 5h is provided in the patterned photoresist 5. A portion of the conductor 1 is exposed from the photoresist 5 through the opening 5h in the photoresist 5. Note that the photoresist 5 is made of a material that can be removed by lift-off in a step (S5b) of removing the photoresist 5, which will be described later.

[0167] Next, a step (S3b) of forming slits 13 is performed. In this step (S3b), as shown in FIG. 6, photoresist 5 is used as a mask to form slits 13 in the conductor 1 exposed from the photoresist 5 at openings 5h in the photoresist 5. The conductor 1 is etched using a DRIE (Deep Reactive-Ion Etching) device. In this way, slits 13 with a high aspect ratio can be formed in the direction perpendicular to the main surface 10a. However, the photoresist 5 is not removed immediately after the slits 13 are formed.

[0168] Next, a step (S4b) of forming a filling portion 6 is carried out. In this step (S4b), as shown in FIG. 38 , the filling portion 6 is formed on the surface of the photoresist 5. In this way, the filling portion 6 is also formed on the surface of the insulating layer 2 exposed from the conductor 1 in the slit 13 of the conductor 1. As a result, the filling portion 6 is filled inside the slit 13.

[0169] Next, a step (S5b) of removing photoresist 5 is performed. In this step (S5b), as shown in FIG. 39 , photoresist 5 formed on insulating layer 2 is removed. In this manner, photoresist 5 can be removed together with filling portion 6 formed on the surface of photoresist 5. If the material constituting photoresist 5 can be removed using lift-off, photoresist 5 may be removed using, for example, acetone.

[0170] Next, a step (S6b) is performed to form grooves H in insulating layer 2. In this step (S6b), grooves H are formed by etching insulating layer 2. Insulating layer 2 is etched by wet etching using a hydrogen fluoride (HF) aqueous solution or dry etching using hydrogen fluoride.

[0171] It is difficult to etch insulating layer 2 by causing hydrogen fluoride to penetrate fine slits 13. For this reason, vent holes (not shown) communicating with insulating layer 2 may be formed in conductor 1, and hydrogen fluoride may penetrate through the vent holes to etch insulating layer 2. The inner periphery width of the vent holes is, for example, 1 μm or more. In this manner, electronic device 100 as shown in FIGS. 38 and 39 can be obtained.

[0172] <Operation and Effect> The electronic device 100 includes the filling portion 6. The filling portion 6 fills the slit 13. The third mean free path of phonons in the material that constitutes the filling portion 6 is different from the first mean free path.

[0173] In this way, it is possible to suppress the thermal conduction caused by phonons without inhibiting the electrical conduction caused by carriers in the conductor 1. As a result, it is possible to obtain the electronic device 100 having a suppressed thermal conductivity without inhibiting the electrical conduction.

[0174] Sixth Embodiment <Configuration of Electronic Device> Fig. 40 is a schematic cross-sectional view of an electronic device 100 according to a sixth embodiment. Fig. 40 corresponds to Fig. 3. The electronic device 100 shown in Fig. 40 basically has the same configuration as the electronic device 100 shown in Figs. 1 to 3 and can obtain the same effects, but differs in that the conductor 1 is directly connected onto the substrate 3.

[0175] 40 , a groove H is provided in a part of the substrate 3. The conductor 1 is connected at the back surface 10b directly to the front surface 3a of the substrate 3 without going through the insulating layer 2. In the region where the groove H is formed, a part of the conductor 1 is held in the air by the substrate 3.

[0176] The conductor 1 may be a thin film material formed on the surface 3 a of the substrate 3 instead of a silicon substrate.

[0177] <Method of Manufacturing Electronic Device> A method of manufacturing the electronic device 100 according to the sixth embodiment will now be described. Figures 41 to 43 are schematic cross-sectional views showing one step of the method of manufacturing the electronic device 100 according to the sixth embodiment.

[0178] First, a step (S1c) of preparing a substrate 3 is performed. In this step (S1c), a substrate 3 such as a silicon substrate is prepared as shown in Fig. 41. An insulating layer 2 may or may not be formed on the substrate 3.

[0179] Next, a step (S2c) of forming a conductor 1 is performed. In this step (S2c), as shown in FIG. 42 , the conductor 1 is formed on the surface 3 a of the substrate 3. The material constituting the conductor 1 may be, for example, germanium (Ge). The conductor 1 is, for example, a thin film material in which thermal conduction occurs by phonons. The conductor 1 is formed using vapor deposition, sputtering, MBE (Molecular Beam Epitaxy), or the like. The thickness of the thin film material constituting the conductor 1 is adjusted according to the electrical resistance required for the electronic device 100.

[0180] Next, a step (S3c) of forming a photoresist 5 is performed. In this step (S3c), as shown in FIG. 43 , a finely patterned photoresist 5 is formed on the conductor 1. The patterned photoresist 5 is formed using an exposure device such as an electron beam lithography device or an EUV (Extreme Ultra Violet) exposure device. In this manner, a fine nanoscale pattern can be formed in the photoresist 5. An opening 5h is provided in the patterned photoresist 5. A portion of the conductor 1 is exposed from the photoresist 5 at the opening 5h in the photoresist 5.

[0181] Next, a step (S4c) of forming slits 13 is performed. In this step (S4c), photoresist 5 is used as a mask to form slits 13 in conductor 1 exposed from photoresist 5 at openings 5h in photoresist 5. Conductor 1 may be etched using an RIE (Reactive-Ion Etching) device or a DRIE (Deep Reactive-Ion Etching) device. After forming slits 13, photoresist 5 is removed as shown in FIG.

[0182] Next, a step (S5c) of forming grooves H in the substrate 3 is performed. In this step (S5b), the grooves H are formed by etching the substrate 3. When the material constituting the substrate 3 is silicon and the material constituting the conductor 1 is germanium, the substrate 3 is etched by wet etching using an alkaline solution that has a high selectivity for silicon relative to germanium. The alkaline solution may be, for example, a potassium hydroxide (KOH) aqueous solution or a tetramethylammonium hydroxide (TMAH) aqueous solution.

[0183] It is difficult to etch the substrate 3 by infiltrating an alkaline solution into the fine slits 13. Therefore, vent holes (not shown) that connect to the substrate 3 may be formed in the conductor 1, and the alkaline solution may be allowed to infiltrate through the vent holes to etch the substrate 3. The inner periphery width of the vent holes is, for example, 1 μm or more. In this manner, an electronic device 100 such as that shown in FIG. 40 can be obtained.

[0184] Seventh Embodiment <Structure of Electronic Device> Fig. 45 is a schematic plan view of an electronic device 100 according to a seventh embodiment. The electronic device 100 shown in Fig. 45 is, for example, a thermoelectric generator. As shown in Fig. 45, the surface 3a of the substrate 3 includes a high-temperature region 3H and a low-temperature region 3L. A pair of electrodes 71, 72 are formed in the high-temperature region 3H.

[0185] A heat dissipation structure 81 may be formed in the low temperature region 3L. The heat dissipation structure 81 may be, for example, a metal thin film. The material forming the heat dissipation structure 81 may be, for example, gold (Au) or aluminum (Al).

[0186] The low temperature region 3L is disposed so as to be separated from the high temperature region 3H via the groove portion H. The low temperature region 3L is surrounded by the groove portion H.

[0187] The conductor 1 includes a p-type conductor 1p and an n-type conductor 1n. The conductivity type of the p-type conductor 1p is p-type. The conductivity type of the n-type conductor 1n is n-type. The p-type conductor 1p and the n-type conductor 1n are the conductors 1 having the nanostructure shown in any of the first to sixth embodiments. The conductor 1 may be a dielectric thin film that generates the Seebeck effect, such as silicon or germanium.

[0188] The p-type conductor 1p and the n-type conductor 1n each connect the high temperature region 3H and the low temperature region 3L. The p-type conductor 1p and the n-type conductor 1n may each be connected to the high temperature region 3H via a first terminal 41 (not shown) and to the low temperature region 3L via a second terminal 42 (not shown), for example. The n-type conductor 1n extends from the high temperature region 3H where the electrode 71 is formed toward the low temperature region 3L. The p-type conductor 1p extends from the high temperature region 3H where the electrode 72 is formed toward the low temperature region 3L. In this way, the conductor 1 is held in midair by the substrate 3 in the region where the groove H is formed.

[0189] 45, the low-temperature region 3L is disposed so as to be sandwiched between the p-type conductor 1p and the n-type conductor 1n. In other words, the low-temperature region 3L is disposed so as to be sandwiched between the pair of electrodes 71 and 72.

[0190] When the heating element is brought into contact with the rear surface (not shown) of the substrate 3, the temperature of the high-temperature region 3H rises. Meanwhile, the temperature of the low-temperature region 3L, which is spaced apart from the high-temperature region 3H, is cooled by the outside air and radiation. In other words, the temperature of the low-temperature region 3L becomes lower than that of the high-temperature region 3H, and a temperature gradient occurs within the conductor 1. As a result, a potential difference occurs within the conductor 1 due to the Seebeck effect. This potential difference is extracted from the electrodes 71 and 72 formed in the high-temperature region 3H.

[0191] The power generation efficiency due to the Seebeck effect can be expressed by the following equation (1) using the figure of merit Z (unit: / K) and the temperature gradient T (unit: K). Note that ZT is dimensionless.

[0192]

[0193] The Seebeck coefficient S (unit: V / K) is a physical property value and is an inherent value of the material constituting the conductor 1. σ (unit: Ω·m) indicates the electrical conductivity of the dielectric (conductor 1). κ (unit: W / (K·m)) indicates the thermal conductivity of the dielectric (conductor 1). In other words, by reducing the thermal conductivity κ without reducing the electrical conductivity σ, the power generation efficiency of the electronic device 100 due to the Seebeck effect can be improved.

[0194] If the conductivity type of the conductor 1 connecting the high-temperature region 3H where the electrode 71 is formed and the low-temperature region 3L is n-type, and the conductivity type of the conductor 1 connecting the high-temperature region 3H where the electrode 72 is formed and the low-temperature region 3L is p-type, carriers will flow due to the Seebeck effect, and as a result, the voltage generated in the conductor 1 can be extracted.

[0195] By having the p-type conductor 1p and the n-type conductor 1n have the nanostructure shown in any one of the first to sixth embodiments, the thermal conductivity κ can be reduced without reducing the electrical conductivity σ. In other words, the power generation efficiency of the electronic device 100 due to the Seebeck effect can be improved.

[0196] <Modification 23 of Electronic Device Configuration> Figure 46 is a schematic plan view of an electronic device 100 according to Modification 23 of the seventh embodiment. Figure 46 corresponds to Figure 45. The electronic device 100 shown in Figure 46 basically has the same configuration as the electronic device 100 shown in Figure 45 and can obtain the same effects as the electronic device 100, but differs in that the electronic device 100 is a thermal infrared sensor.

[0197] As shown in Figure 46, a light-receiving and heat-generating portion 82 is formed in the low-temperature region 3L. The material constituting the light-receiving and heat-generating portion 82 may be any material that corresponds to the wavelength range of light to be detected, and may be a material that has a high absorptivity for infrared rays, for example. When the light to be detected is long-wavelength infrared rays in the wavelength range of 8 μm or more and 14 μm or less, the material constituting the light-receiving and heat-generating portion 82 is a material with a high absorptivity for infrared rays, such as silicon oxide (SiO ２ ), silicon nitride (SiN), vanadium oxide, or the like.

[0198] The conductors 1 may be configured as a pair. The conductors 1 are the conductors 1 having the nanostructure shown in any of the first to sixth embodiments. The conductors 1 may be semiconductor materials such as silicon or germanium, or may be thin metal films such as titanium nitride (TiN) in which thermal conduction occurs due to phonons.

[0199] Each of the pair of conductors 1 serves as a support leg and connects the high temperature region 3H and the low temperature region 3L. In this way, the conductor 1 is held in midair by the substrate 3 in the region where the groove H is formed.

[0200] In a thermal infrared sensor, the detection element heats up when it absorbs incident infrared rays. This heat generation changes the electrical characteristics of the detection element, allowing the sensor to detect the incident infrared rays.

[0201] When the detecting element is a PN junction diode or a resistive bolometer, the detecting element may be disposed in the light-receiving and heat-generating portion 82. When the electronic device 100 is a thermopile-type infrared sensor, the pair of conductors 1 function as the detecting element because it can detect light using the Seebeck effect.

[0202] When the conductor 1 has the nanostructure shown in any one of the first to sixth embodiments, the thermal conductivity κ can be reduced without reducing the electrical conductivity σ. In other words, changes in electrical characteristics due to heat generation can be efficiently detected without increasing the power consumption of the electronic device 100.

[0203] <Modification 24 of Electronic Device Configuration> Figure 47 is a schematic plan view of an electronic device 100 according to Modification 24 of Embodiment 7. Figure 47 corresponds to Figure 46. The electronic device 100 shown in Figure 47 basically has the same configuration as the electronic device 100 shown in Figure 46 and can obtain the same effects, but differs in that the conductors 1 serving as supporting legs extend while folding back from the high temperature region 3H toward the low temperature region 3L.

[0204] The electronic device 100 can be made smaller by folding the conductor 1 up and down as shown in FIG. 47 as a long, thin wiring and extending the conductor 1 from the high temperature region 3H toward the low temperature region 3L.

[0205] Eighth Embodiment <Configuration of Electronic Device> Figure 48 is a schematic plan view of an electronic device 100 according to an eighth embodiment. Figure 48 corresponds to Figure 9. The electronic device 100 shown in Figure 48 basically has the same configuration as the electronic device 100 shown in Figure 9 and can achieve the same effects, but differs in that an intermediate slit portion 33 is provided in the phonon trapping region 11.

[0206] Specifically, the multiple slits 13 include an intermediate slit portion 33. The intermediate slit portion 33 is disposed between the pair of communicating portions 12a in the extension direction (x direction). The intermediate slit portion 33 extends in the y direction. A width W4 of the intermediate slit portion 33 in a direction (y direction) perpendicular to the extension direction in a plan view of the main surface 10a is greater than the minimum width L2.

[0207] By doing so, phonons that pass through communication region 12 in a direction (0°) parallel to the extension direction (x direction) are reflected and scattered by the interface with intermediate slit portion 33. In other words, even if phonons are not reflected and scattered by the interface with slit 13 in communication region 12 and enter phonon trap region 11, they are reflected and scattered by the interface with intermediate slit portion 33.

[0208] <Modification 25 of Electronic Device> Figure 49 is a schematic plan view of an electronic device 100 according to Modification 25 of Embodiment 8. Figure 49 corresponds to Figure 48. The electronic device 100 shown in Figure 49 basically has the same configuration as the electronic device 100 shown in Figure 48 and can obtain the same effects, but differs in that the intermediate slit portion 33 includes a bent portion 13g. In other words, the shape of the intermediate slit portion 33 may be V-shaped.

[0209] <Effects> According to the electronic device 100, the communicating region 12 includes a plurality of communicating portions 12a. The plurality of slits 13 includes an intermediate slit portion 33. The intermediate slit portion 33 is disposed between the plurality of communicating portions 12a. In a plan view of the main surface 10a, the width W3 of the intermediate slit portion 33 in the direction (y direction) perpendicular to the extension direction (x direction) is greater than the minimum width L2.

[0210] In this way, phonons that pass through communication region 12 in a direction (0°) parallel to the extension direction (x direction) are reflected and scattered by the interface with intermediate slit portion 33. In other words, even if phonons enter phonon trap region 11 without being reflected and scattered by the interface with slit 13 in communication region 12, they are reflected and scattered by the interface with intermediate slit portion 33.

[0211] Ninth Embodiment <Configuration of Electronic Device> Fig. 50 is a schematic plan view of an electronic device 100 according to a ninth embodiment. Fig. 50 corresponds to Fig. 7. Fig. 51 is a schematic cross-sectional view of the electronic device 100 according to the ninth embodiment. Fig. 51 corresponds to Fig. 3. The electronic device 100 shown in Figs. 50 and 51 basically has the same configuration as the electronic device 100 shown in Fig. 7 and can obtain the same effects, but differs in that the slits 13 do not penetrate the conductor 1.

[0212] Specifically, the conductor 1 has a bottom surface 10c. The bottom surface 10c is disposed between the main surface 10a and the back surface 10b in the z direction. The bottom surface 10c forms a slit 13.

[0213] The conductor 1 includes a remaining portion 13i. The remaining portion 13i is a region between the back surface 10b and the bottom surface 10c. The remaining portion 13i is formed by stopping the etching of the conductor 1 midway during the step (S4d) of forming the slits 13 and the grooves H, which will be described later, so that the conductor 1 does not penetrate through. In other words, the material constituting the remaining portion 13i is the same as the material constituting the conductor 1.

[0214] The thickness T1 of the remaining portion 13i (the distance between the bottom surface 10c and the back surface 10b in the z direction) is three times or less the first mean free path of phonons in the conductor 1. Furthermore, the thickness T1 of the remaining portion 13i (the distance between the bottom surface 10c and the back surface 10b in the z direction) is equal to or greater than the second mean free path of phonons in the conductor 1. In this way, the remaining portion 13i can suppress heat conduction by phonons. In other words, the remaining portion 13i has the same function as the communicating region 12.

[0215] <Method of Manufacturing Electronic Device> A method of manufacturing the electronic device 100 according to the ninth embodiment will now be described. Figures 52 and 53 are schematic cross-sectional views showing one step of the method of manufacturing the electronic device 100 according to the ninth embodiment.

[0216] 4 and 5 in the manufacturing method of the electronic device 100 according to the first embodiment are performed. That is, a step (S1d) of preparing a conductor 1 is first performed. In this step (S1d), as shown in FIG. 4, a conductor 1 is prepared as an SOI (Silicon On Insulator) wafer, with an insulating layer 2 interposed between the substrate 3 and the conductor 1. The conductor 1 may be a silicon substrate that has been polished to be thin.

[0217] The substrate 3 is, for example, a silicon substrate. An insulating layer 2 is formed on a surface 3a of the substrate 3. The insulating layer 2 is, for example, a silicon oxide film. The conductor 1 is connected to the insulating layer 2 on a back surface 10b.

[0218] Next, a step (S2d) of forming a photoresist 5 is performed. In this step (S2d), as shown in FIG. 5 , a finely patterned photoresist 5 is formed on the conductor 1. The patterned photoresist 5 is formed using an exposure device such as an electron beam lithography device or an EUV (Extreme Ultra Violet) exposure device. In this manner, a fine nanoscale pattern can be formed in the photoresist 5. An opening 5h is provided in the patterned photoresist 5. A portion of the conductor 1 is exposed from the photoresist 5 at the opening 5h in the photoresist 5.

[0219] Next, a step (S3d) of forming oxide film 13j is performed. In this step (S3d), as shown in FIG. 52 , conductor 1 is oxidized on main surface 10a exposed through opening 5h. In this manner, oxide film 13j is formed on main surface 10a exposed through opening 5h. Oxide film 13j having a desired thickness can be formed as a thermal oxide film by heat treatment in an oxygen atmosphere or a hydrogen atmosphere.

[0220] Next, a step (S4d) of removing photoresist 5 is performed. In this step (S4d), as shown in Fig. 53, the photoresist 5 formed on the conductor 1 is removed. The photoresist 5 may be removed by ashing with oxygen plasma or by acetone.

[0221] Next, a step (S5d) of forming slits 13 and grooves H is performed. In this step (S5d), oxide film 13j and insulating layer 2 are etched to form slits 13 and grooves H. Oxide film 13j and insulating layer 2 are etched by wet etching using a hydrogen fluoride (HF) aqueous solution or dry etching using hydrogen fluoride vapor.

[0222] When forming the grooves H, vent holes (not shown) that communicate with the insulating layer 2 may be formed in the conductor 1, and hydrogen fluoride may be allowed to penetrate through the vent holes to etch the insulating layer 2. The inner periphery width of the vent holes is, for example, 1 μm or more. In this manner, the electronic device 100 shown in FIG. 51 can be obtained.

[0223] <Effects> According to the electronic device 100, the conductor 1 has a back surface 10b and a bottom surface 10c. The back surface 10b is located opposite the main surface 10a. The bottom surface 10c forms a slit 13. The distance T1 between the bottom surface 10c and the back surface 10b is three times the first mean free path or less. The distance T1 between the bottom surface 10c and the back surface 10b is equal to or greater than the second mean free path.

[0224] In this way, the remaining portion 13 i can suppress heat conduction due to phonons. In other words, the remaining portion 13 i has the same function as the communication region 12 .

[0225] Tenth Embodiment <Configuration of Electronic Device> Fig. 54 is a schematic plan view of an electronic device 100 according to a tenth embodiment. Fig. 54 corresponds to Fig. 19. The electronic device 100 shown in Fig. 54 basically has the same configuration as the electronic device 100 shown in Fig. 19 and can obtain the same effects, except that the area occupied by the multiple slits 13 on the main surface 10a changes from the first terminal 41 to the second terminal 42.

[0226] Specifically, the main surface 10a includes a first region A1, a second region A2, a third region A3, and a fourth region A4. The first region A1, the second region A2, the third region A3, and the fourth region A4 each have the same width in the extension direction. As shown in Figure 54, the first region A1, the second region A2, the third region A3, and the fourth region A4 are arranged in this order along the extension direction from the left side (the first terminal 41 side) toward the second terminal 42.

[0227] The slits 13 are periodically arranged in the vertical direction (y direction). That is, the first region A1, the second region A2, the third region A3, and the fourth region A4 each have a plurality of slits 13 arranged in the y direction. On the other hand, the first region A1, the second region A2, the third region A3, and the fourth region A4 each have only one slit 13 arranged in the x direction, not a plurality of slits 13 arranged in the x direction.

[0228] The number of slits 13 arranged in the first region A1 is greater than the number of slits 13 arranged in the second region A2. The number of slits 13 arranged in the second region A2 is greater than the number of slits 13 arranged in the third region A3. The number of slits 13 arranged in the third region A3 is greater than the number of slits 13 arranged in the fourth region A4.

[0229] In this way, the number of slits 13 decreases from the first terminal 41 toward the second terminal 42. In this way, the area occupied by the slits 13 in each of the first region A1 to the fourth region A4 decreases without increasing along the way.

[0230] Phonons that enter communication region 12, which has a small minimum width L2 and a narrow spacing between slits 13, are repeatedly reflected and scattered by the interface with slits 13. Phonons that have been repeatedly reflected and scattered in communication region 12 enter phonon trap region 11. Phonons that have been reflected and scattered in communication region 12 are less likely to flow out of phonon trap region 11. As a result, the thermal conduction of phonons can be suppressed, and the apparent thermal conductivity κ of conductor 1 can be reduced.

[0231] On the other hand, phonons that enter the communication region 12, which has a large width L and a large spacing between the slits 13, are less likely to be reflected and scattered by the interface with the slits 13. This reduces the effect of suppressing the thermal conduction of phonons.

[0232] In this way, by providing a region where the spacing between the plurality of slits 13 is narrow and a region where the spacing between the plurality of slits 13 is wide, it is possible to change the apparent thermal conductivity κ of the conductor 1. As a result, it is possible to improve the rectification of the heat flow in the extension direction.

[0233] The number of slits 13 may increase from the first terminal 41 toward the second terminal 42. In other words, the area occupied by the slits 13 in each of the first region A1 to the fourth region A4 may increase without decreasing along the way.

[0234] <Modification 26 of Electronic Device> Fig. 55 is a schematic plan view of an electronic device 100 according to Modification 26 of Embodiment 10. Fig. 55 corresponds to Fig. 22. The electronic device 100 shown in Fig. 55 basically has the same configuration as the electronic device 100 shown in Fig. 22 and can obtain the same effects, except that the area occupied by the plurality of slits 13 on the main surface 10a changes from the first terminal 41 to the second terminal 42.

[0235] Specifically, the slit 13 includes a first portion 31, a plurality of second portions 32, and a plurality of bent portions 13g. The plurality of second portions 32 are connected to the first portion 31 via the bent portions 13g. The first portion 31 extends along the extension direction, i.e., the x-direction. The plurality of second portions 32 extend along the y-direction and are spaced apart from one another in the x-direction. The first portion 31 is connected to the center of each of the plurality of second portions 32 in the y-direction.

[0236] The distance between adjacent second portions 32 increases without decreasing along the way from the first terminal 41 to the second terminal 42. In this way, the area occupied by the slits 13 in each of the first region A1 to the fourth region A4 decreases without increasing along the way.

[0237] 55, the multiple slits 13 aligned in the y direction are periodically arranged in the y direction. The communication region 12 is a region sandwiched between the short side s2 of one slit 13 and the short side s2 of the other slit 13 adjacent to the first slit 13 in the y direction. Two slits 13 adjacent to each other in the y direction form multiple communication portions 12a and multiple phonon trap portions 11a.

[0238] Phonons that enter communication region 12, which has a small minimum width L2 and a narrow spacing between slits 13, are repeatedly reflected and scattered by the interface with slits 13. Phonons that have been repeatedly reflected and scattered in communication region 12 enter phonon trap region 11. Phonons that have been reflected and scattered in communication region 12 are less likely to flow out of phonon trap region 11. As a result, the thermal conduction of phonons can be suppressed, and the apparent thermal conductivity κ of conductor 1 can be reduced.

[0239] On the other hand, phonons that enter the communication region 12, which has a large width L and a large spacing between the slits 13, are less likely to be reflected and scattered by the interface with the slits 13. This reduces the effect of suppressing the thermal conduction of phonons.

[0240] In this way, by providing a region where the spacing between the plurality of slits 13 is narrow and a region where the spacing between the plurality of slits 13 is wide, it is possible to change the apparent thermal conductivity κ of the conductor 1. As a result, it is possible to improve the rectification of the heat flow in the extension direction.

[0241] The distance between adjacent second portions 32 may decrease without increasing along the way from the first terminal 41 to the second terminal 42. In this way, the area occupied by the slits 13 in each of the first region A1 to the fourth region A4 may decrease without increasing along the way.

[0242] Eleventh Embodiment <Configuration of Electronic Device> Fig. 56 is a schematic plan view of an electronic device 100 according to an eleventh embodiment. Fig. 56 corresponds to Fig. 54. The electronic device 100 shown in Fig. 56 basically has the same configuration as the electronic device 100 shown in Fig. 54, except that the size of the slit 13 is different from that of the first terminal 41 toward the second terminal 42.

[0243] As shown in Figure 56, the slits 13 located on the right side (the second terminal 42 side) are larger than the slits 13 located on the left side (the first terminal 41 side). Furthermore, the distance between adjacent slits 13 in the extension direction increases from the first terminal 41 to the second terminal 42 without decreasing along the way. Furthermore, the distance (width L) between adjacent slits 13 in the vertical direction increases from the first terminal 41 to the second terminal 42 without decreasing along the way. In this way, the area of ​​the interface of the slits 13 relative to the volume of the conductor 1 increases from the first terminal 41 to the second terminal 42 without decreasing along the way.

[0244] In this way, when the interface area of ​​the slit 13 is large relative to the volume of the conductor 1, the probability of reflection and scattering of phonons at the interface of the slit 13 increases. As a result, the thermal conduction of phonons is suppressed, and the apparent thermal conductivity κ of the conductor 1 can be reduced. As a result, the rectification of the heat flow in the extension direction can be improved.

[0245] From a different perspective, the interfacial areas of the slits 13 in the first region A1, the second region A2, the third region A3, and the fourth region A4 are different from one another. As in the electronic device 100 according to the eleventh embodiment, the interfacial areas of the slits 13 in the first region A1, the second region A2, the third region A3, and the fourth region A4 from the first terminal 41 to the second terminal 42 may increase without decreasing along the way, or may decrease without increasing along the way.

[0246] If the slits 13 are small and the intervals between the slits 13 are narrow, the area of ​​the interface of the slits 13 relative to the volume of the conductor 1 increases in each region (first region A1, second region A2, third region A3, and fourth region A4) of the main surface 10a, resulting in a decrease in the apparent thermal conductivity κ of the conductor 1.

[0247] On the other hand, if the slits 13 are large and the intervals between the slits 13 are wide, the area of ​​the interface of the slits 13 relative to the volume of the conductor 1 decreases in each region (first region A1, second region A2, third region A3, and fourth region A4) of the main surface 10a, and as a result, the apparent thermal conductivity κ of the conductor 1 increases.

[0248] In this way, by providing a region where large slits 13 are arranged and a region where small slits 13 are arranged, it is possible to change the apparent thermal conductivity κ of the conductor 1. As a result, it is possible to improve the rectification of the heat flow in the extension direction.

[0249] <Modification 27 of Electronic Device Configuration> Figure 57 is a schematic plan view of an electronic device 100 according to Modification 27 of Embodiment 11. Figure 57 corresponds to Figure 56. The electronic device 100 shown in Figure 57 basically has the same configuration as the electronic device 100 shown in Figure 56 and can obtain the same effects, but differs in that the shapes of the slits 13 adjacent to each other in the extension direction are different.

[0250] Specifically, the shape of the slits 13 arranged in the first region A1 in a plan view of the main surface 10a is H-shaped. The shape of the slits 13 arranged in the second region A2 in a plan view of the main surface 10a is cross-shaped. The shape of the slits 13 arranged in the third region A3 in a plan view of the main surface 10a is V-shaped. The shape of the slits 13 arranged in the fourth region A4 in a plan view of the main surface 10a is I-shaped.

[0251] In this way, the shapes of the slits 13 are different in each region (first region A1, second region A2, third region A3, and fourth region A4) of the main surface 10a, so that even if the sizes of the plurality of slits 13 adjacent to each other in the extension direction are the same, the areas of the interfaces of the slits 13 are different.

[0252] Specifically, the area of ​​the interface of the slit 13 arranged on the right side (the second terminal 42 side) is smaller than the area of ​​the interface of the slit 13 arranged on the left side (the first terminal 41 side). In other words, the area of ​​the interface of the slits 13 arranged in order from the left side to the right side decreases without increasing along the way.

[0253] This makes it possible to change the apparent thermal conductivity κ of the conductor 1. As a result, it is possible to improve the rectification of the heat flow in the extending direction.

[0254] The area of ​​the interface of the slit 13 arranged on the right side (the second terminal 42 side) may be larger than the area of ​​the interface of the slit 13 arranged on the left side (the first terminal 41 side). In other words, the area of ​​the interface of the slits 13 arranged in order from the left side to the right side may increase without decreasing in between.

[0255] <Effects> According to the electronic device 100, the main surface 10a includes a first region A1 and a second region A2. The second region A2 has the same width as the first region A1 in the extension direction (x direction). The area of ​​the interface of the slit 13 in the second region A2 is different from the area of ​​the interface of the slit 13 in the first region A1.

[0256] This makes it possible to change the apparent thermal conductivity κ of the conductor 1. As a result, it is possible to improve the rectification of the heat flow in the extending direction.

[0257] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The basic scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0258] 1 Conductor, 1n n-type conductor, 1p p-type conductor, 2 Insulating layer, 3 Substrate, 3a Surface, 3H High temperature region, 3L Low temperature region, 5 Photoresist, 5h Opening, 6 Filling portion, 10a Main surface, 10b Back surface, 10c Bottom surface, 11 Phonon trap region, 11a Phonon trap portion, 11c Phonon trap portion, 12 Connecting region, 12a Connecting portion, 12b Connecting portion, 12c Connecting portion, 13 Slit, 13a Slit portion, 13b Slit portion, 13c Inclined portion, 13d Vertical portion, 13e Parallel portion, 13f Straight portion, 13g Bent portion, 13h Curved portion, 13i Remaining portion, 13j Oxide film, 31 First portion, 32 Second portion, 33 Intermediate slit portion, 41 First terminal, 42 Second terminal, 71 electrode, 72 electrode, 81 heat dissipation structure, 82 light-receiving and heat-generating portion, 100 electronic device, A1 first region, A2 second region, A3 third region, A4 fourth region, H groove portion, L width, L1 length, L2 minimum width, S Seebeck coefficient, s1 long side, s2 short side, s3 side, s4 side, T temperature gradient, W2 width, W3 width, T1 thickness, Z figure of merit, θ inclination angle, κ thermal conductivity, σ electrical conductivity.

Claims

1. An electronic device comprising: a conductor having a main surface; a first terminal connected to the conductor; and a second terminal connected to the conductor and located opposite the first terminal in an extension direction of the conductor; wherein the main surface is provided with a plurality of slits, the main surface includes phonon trapping regions defined by the plurality of slits and communication regions connected to the phonon trapping regions, the plurality of slits include inclined portions that are inclined with respect to the extension direction in a planar view of the main surface, and the minimum width of the communication region is three times or less the first mean free path of phonons in the conductor and is equal to or greater than the second mean free path of carriers in the conductor.

2. The electronic device according to claim 1, wherein the length of the slit in the direction in which the slit extends in a planar view of the principal surface is greater than the first mean free path, and the width of the slit in a direction perpendicular to the direction in which the slit extends in a planar view of the principal surface is less than or equal to the first mean free path.

3. An electronic device according to claim 1 or claim 2, wherein the first mean free path is the mean free path of phonons in the conductor at the lowest possible temperature of the first terminal and the second terminal during rated operation of the electronic device.

4. An electronic device according to any one of claims 1 to 3, wherein the second mean free path is the mean free path of carriers in the conductor at the lowest possible temperature of the first terminal and the second terminal during rated operation of the electronic device.

5. An electronic device according to any one of claims 1 to 4, wherein, when a direction perpendicular to the extension direction in a planar view of the main surface is defined as a vertical direction, the communication region includes a region that extends at an angle with respect to the vertical direction in a planar view of the main surface.

6. An electronic device according to any one of claims 1 to 5, wherein the minimum width is not less than 0.05 times and not more than 1.2 times the first mean free path.

7. The electronic device according to any one of claims 1 to 6, wherein the plurality of slits include vertical portions extending perpendicular to the extension direction.

8. The electronic device according to any one of claims 1 to 7, wherein the plurality of slits include parallel portions extending along the extension direction.

9. An electronic device according to any one of claims 1 to 8, wherein the plurality of slits include straight portions that are inclined with respect to the extending direction.

10. The electronic device according to any one of claims 1 to 9, wherein the plurality of slits include curved portions.

11. The electronic device according to claim 10, wherein the communication region includes two communication portions, and the two communication portions are connected to the curved portion.

12. The electronic device according to any one of claims 1 to 11, wherein the plurality of slits include bent portions.

13. An electronic device according to any one of claims 1 to 12, wherein the communication region includes a plurality of communication portions, and when a direction perpendicular to the extension direction in a planar view of the main surface is defined as a vertical direction, the communication portions are periodically arranged in the vertical direction.

14. An electronic device according to any one of claims 1 to 13, wherein the communication region includes a plurality of communication portions, and the plurality of communication portions are periodically arranged in the extension direction.

15. An electronic device according to any one of claims 1 to 14, wherein the communication region includes a plurality of communication portions, and all of the plurality of communication portions extend in the extension direction.

16. An electronic device according to any one of claims 1 to 15, comprising a filling portion filled in the slit, wherein a third mean free path of phonons in a material constituting the filling portion is different from the first mean free path.

17. An electronic device according to any one of claims 1 to 16, wherein the temperature of the first terminal is higher than the temperature of the second terminal during rated operation of the electronic device.

18. An electronic device according to any one of claims 1 to 17, wherein the communication region includes two communication portions, and the phonon trapping region is sandwiched between the two communication portions in the extension direction.

19. An electronic device according to any one of claims 1 to 18, wherein the phonon trap region includes a plurality of phonon trap portions, the plurality of phonon trap portions are arranged in a matrix, and adjacent phonon trap portions are connected by the communication region.

20. An electronic device described in any one of claims 1 to 19, wherein the width of the phonon trapping region in a direction perpendicular to the extension direction in a planar view of the main surface is greater than the width of the communicating region in a direction perpendicular to the extension direction in a planar view of the main surface.

21. An electronic device according to any one of claims 1 to 20, wherein the communication region includes a plurality of communication portions, the plurality of slits include intermediate slit portions arranged between the plurality of communication portions, and the width of the intermediate slit portions in a direction perpendicular to the extension direction in a plan view of the main surface is greater than the minimum width.

22. The electronic device according to any one of claims 1 to 21, wherein the conductor has a back surface located opposite the main surface and a bottom surface forming the slit, the distance between the bottom surface and the back surface being three times the first mean free path or less, and the distance between the bottom surface and the back surface being equal to or greater than the second mean free path.

23. An electronic device according to any one of claims 1 to 22, wherein the main surface includes a first region and a second region having the same width as the width of the first region in the extension direction, and the area of ​​the interface of the slit in the second region is different from the area of ​​the interface of the slit in the first region.

Images