Passive electronic component and mounting structure of passive electronic component

Abstract

A passive electronic component 1 comprises: a substrate 10; and two or more passive elements 21, 22 arranged separated from each other on the substrate 10. An exposed part 10c of the substrate 10 is present in at least a portion between adjacent passive elements 21, 22 among the two or more passive elements 21, 22.

Description

Passive electronic components and passive electronic component mounting structures

[0001] The present invention relates to a passive electronic component and a mounting structure for the passive electronic component.

[0002] Patent Document 1 discloses an electronic component with built-in passive elements, in which a plurality of thin-film capacitors, inductors, and resistors are mounted on an insulating substrate, and the thin-film capacitors are formed by forming a plurality of dielectric layers on the insulating substrate, with electrodes sandwiching both sides of the dielectric film in the stacking direction, and the dielectric layers are composed of inorganic dielectric layers and organic dielectric layers.

[0003] Japanese Patent Application Laid-Open No. 2002-280261

[0004] In the electronic component with built-in passive elements described in Patent Document 1, the spaces between the thin-film capacitor, inductor, and resistor are filled with organic dielectric layers, which causes electrical coupling between the elements due to the dielectric material, resulting in power loss.

[0005] The present invention has been made to solve the above problems, and has an object to provide a passive electronic component and a mounting structure for a passive electronic component that can reduce power loss.

[0006] In a first aspect, the passive electronic component of the present invention comprises a substrate and two or more passive elements arranged on the substrate at a distance from each other, and is characterized in that an exposed portion of the substrate exists at least partially between adjacent passive elements of the two or more passive elements.

[0007] In a second aspect, the passive electronic component of the present invention comprises a substrate and two or more passive elements arranged on the substrate at a distance from each other, and is characterized in that a groove portion of the substrate is provided in at least a portion between adjacent passive elements of the two or more passive elements.

[0008] In a third aspect, the passive electronic component of the present invention comprises a substrate, two or more passive elements arranged on the substrate at a distance from each other, an insulating film provided between each of the two or more passive elements, and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon, and an exposed portion of the polycrystalline silicon layer is present in at least a portion between adjacent passive elements of the two or more passive elements.

[0009] In a fourth aspect, the passive electronic component of the present invention comprises a substrate, two or more passive elements arranged on the substrate at a distance from each other, an insulating film provided between each of the two or more passive elements, and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon, and a groove portion of the polycrystalline silicon layer is provided in at least a portion between adjacent passive elements of the two or more passive elements.

[0010] The mounting structure of a passive electronic component of the present invention comprises a passive electronic component of the present invention, a mounting substrate having a substrate main body with a mounting surface and a land electrode formed on the mounting surface, wherein an external electrode of the passive electronic component is electrically connected to the land electrode, and the area between the passive electronic component and the mounting surface is sealed with a molded resin.

[0011] According to the present invention, it is possible to provide a passive electronic component and a mounting structure for a passive electronic component that can reduce power loss.

[0012] FIG. 1 is a plan view schematic diagram showing an example of a passive electronic component according to embodiment 1 of the present invention. FIG. 2 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 1 taken along line segment A-A. FIG. 3 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 1 taken along line segment B-B or line segment C-C. FIG. 4 is a cross-sectional view schematic diagram showing a portion of an example of a passive electronic component according to comparative form 1. FIG. 5 is a cross-sectional view schematic diagram showing a portion of the passive electronic component shown in FIG. 2. FIG. 6 is a plan view schematic diagram showing modified example 1 of the passive electronic component according to embodiment 1 of the present invention. FIG. 7 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 6 taken along line segment D-D. FIG. 8 is a cross-sectional view schematic diagram showing a portion of the passive electronic component shown in FIG. 7. FIG. 9 is a plan view schematic diagram showing modified example 2 of the passive electronic component according to embodiment 1 of the present invention. FIG. 10 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 9 taken along line segment E-E. FIG. 11 is a cross-sectional view schematically illustrating an example of a cross section taken along line F-F or line G-G of the passive electronic component shown in FIG. 9 . FIG. 12 is a cross-sectional view schematically illustrating a portion of the passive electronic component shown in FIG. 10 . FIG. 13 is a cross-sectional view schematically illustrating a portion of an example of a passive electronic component of Comparative Form 2. FIG. 14 is a cross-sectional view schematically illustrating Modification 3 of the passive electronic component of Embodiment 1 of the present invention. FIG. 15 is a cross-sectional view schematically illustrating a portion of an example of a passive electronic component of Comparative Form 3. FIG. 16 is a cross-sectional view schematically illustrating Modification 4 of the passive electronic component of Embodiment 1 of the present invention. FIG. 17 is a cross-sectional view schematically illustrating a portion of the passive electronic component shown in FIG. 16 . FIG. 18 is a cross-sectional view schematically illustrating a step of preparing a substrate in an example of a method for manufacturing a passive electronic component of Embodiment 1 of the present invention. FIG. 19 is a cross-sectional view schematically illustrating a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component of Embodiment 1 of the present invention. FIG. 20 is a cross-sectional view schematically illustrating a step of forming an insulating film in an example of a method for manufacturing a passive electronic component of Embodiment 1 of the present invention. Fig. 21 is a cross-sectional view schematically illustrating a step of forming a first internal electrode in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. Fig. 22 is a cross-sectional view schematically illustrating a step of forming a dielectric layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. Fig. 23 is a cross-sectional view schematically illustrating a step of forming a dielectric film in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention.FIG. 24 is a cross-sectional view schematically illustrating a step of forming a second internal electrode in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 25 is a cross-sectional view schematically illustrating a step of forming a moisture-resistant layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 26 is a cross-sectional view schematically illustrating a step of forming a moisture-resistant film in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 27 is a cross-sectional view schematically illustrating a step of forming a resin layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 28 is a cross-sectional view schematically illustrating a step of forming a groove in a substrate in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 29 is a plan view schematically illustrating an example of a passive electronic component according to Embodiment 2 of the present invention. FIG. 30 is a cross-sectional view schematically illustrating an example of a cross section taken along line H-H of the passive electronic component shown in FIG. 29. FIG. 31 is a cross-sectional view schematically illustrating a portion of an example of a passive electronic component according to Comparative Form 4. FIG. 32 is a cross-sectional view schematically illustrating a portion of the passive electronic component shown in FIG. 30. FIG. 33 is a plan view schematic showing a first modified example of the passive electronic component according to the second embodiment of the present invention. FIG. 34 is a cross-sectional view schematic showing an example of a cross section of the passive electronic component shown in FIG. 33 taken along line J-J. FIG. 35 is a cross-sectional view schematic showing a step of preparing a substrate in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 36 is a cross-sectional view schematic showing a step of forming a groove in a substrate in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 37 is a cross-sectional view schematic showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 38 is a cross-sectional view schematic showing a step of forming an insulating film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 39 is a cross-sectional view schematic showing a step of forming a first internal electrode in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 40 is a cross-sectional view schematic showing a step of forming a dielectric layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 41 is a cross-sectional view schematic showing a step of forming a dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 42 is a cross-sectional view schematically illustrating a step of forming a second internal electrode in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.FIG. 43 is a cross-sectional view schematically illustrating a step of forming a moisture-resistant layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 44 is a cross-sectional view schematically illustrating a step of forming a moisture-resistant film in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 45 is a cross-sectional view schematically illustrating a step of forming a resin layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. FIG. 46 is a plan view schematically illustrating an example of a passive electronic component according to Embodiment 3 of the present invention. FIG. 47 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in FIG. 46 taken along line K-K. FIG. 48 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in FIG. 46 taken along line L-L or line M-M. FIG. 49 is a plan view schematically illustrating a first modified example of the passive electronic component according to Embodiment 3 of the present invention. FIG. 50 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in FIG. 49 taken along line N-N. FIG. 51 is a cross-sectional view schematically illustrating a passive electronic component according to Embodiment 4 of the present invention. Fig. 52 is a cross-sectional view schematically illustrating an example of a passive electronic component mounting structure according to Embodiment 5 of the present invention. Fig. 53 is a cross-sectional view schematically illustrating an example of another cross section (a cross section perpendicular to the cross section of Fig. 52) of the passive electronic component shown in Fig. 52. Fig. 54 is a cross-sectional view schematically illustrating Modification 1 of the passive electronic component mounting structure according to Embodiment 5 of the present invention.

[0013] The passive electronic component and the passive electronic component mounting structure of the present invention are described below. Note that the present invention is not limited to the following configurations and may be modified as appropriate within the scope of the present invention. Furthermore, a combination of multiple individual preferred configurations described below also constitutes the present invention.

[0014] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From embodiment 2 onwards, descriptions of matters common to embodiment 1 will be omitted, and differences will be mainly described. In particular, similar effects resulting from similar configurations will not be mentioned one after the other for each embodiment.

[0015] In the following description, when there is no need to particularly distinguish between the embodiments, they will simply be referred to as "the passive electronic component of the present invention" or "the passive electronic component mounting structure of the present invention."

[0016] In the following, an electronic component having a capacitor will be shown as an example of the passive electronic component of the present invention. The passive electronic component of the present invention may be a capacitor itself.

[0017] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, scale, etc. may differ from those of the actual product.

[0018] In this specification, unless otherwise specified, terms indicating the relationship between elements (e.g., "parallel," "perpendicular," etc.) and terms indicating the shape of elements not only mean the literal strict form, but also mean a range that is substantially equivalent, for example, a range that includes a difference of about a few percent.

[0019] [Embodiment 1] In a first aspect, a passive electronic component of the present invention comprises a substrate and two or more passive elements arranged on the substrate at a distance from each other, and is characterized in that an exposed portion of the substrate is present in at least a portion between adjacent passive elements of the two or more passive elements.

[0020] Hereinafter, an example of the first aspect of the passive electronic component of the present invention will be described as a passive electronic component of embodiment 1 of the present invention.

[0021] Fig. 1 is a plan view schematic diagram showing an example of a passive electronic component according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view schematic diagram showing an example of a cross-section of the passive electronic component shown in Fig. 1 taken along line segment A-A. Fig. 3 is a cross-sectional view schematic diagram showing an example of a cross-section of the passive electronic component shown in Fig. 1 taken along line segment B-B or line segment C-C. Note that the cross-sections of the passive electronic component shown in Fig. 1 taken along line segment B-B and line segment C-C may be substantially identical to each other, and therefore a common cross-section is shown in Fig. 3.

[0022] A passive electronic component 1 shown in FIGS. 1, 2 and 3 includes a substrate 10 and two capacitors 21 and 22 as passive elements.

[0023] The substrate 10 is arranged parallel to a first direction D1 and a second direction D2 that are perpendicular to each other, and has a first main surface 10a and a second main surface 10b that face a third direction D3 that is perpendicular to the first direction D1 and the second direction D2.

[0024] The two capacitors 21 and 22 are arranged spaced apart from each other on the substrate 10. Here, the capacitors 21 and 22 are arranged on the first main surface 10a of the substrate 10 and are spaced apart from each other in the first direction D1.

[0025] In the passive electronic component of the present invention, the number of passive elements arranged spaced apart from one another on the substrate is not particularly limited as long as it is two or more.

[0026] Furthermore, in the passive electronic component of the present invention, when two passive elements are arranged spaced apart from each other on a substrate, this means that at least the internal electrodes of the two passive elements (first internal electrodes and second internal electrodes in the case where the passive elements are capacitors) are arranged spaced apart from each other on the substrate.

[0027] In addition, in this specification, the term "passive element" refers to the region consisting of each internal electrode of the passive element and the insulator portion sandwiched between adjacent internal electrodes. That is, if the passive element is a capacitor, it refers to the region consisting of the first internal electrode, the second internal electrode, and the portion of the dielectric film sandwiched between the first and second internal electrodes (for example, the region surrounded by the dashed line in FIGS. 1 to 3 and 9 to 11).

[0028] Each of the capacitors 21, 22 includes a first internal electrode 31 provided on the first main surface 10a of the substrate 10, a dielectric film 32 provided on the first internal electrode 31, and a second internal electrode 33 provided on the dielectric film 32. The passive electronic component 1 also includes a moisture-resistant film 34 provided on the dielectric film 32 and second internal electrode 33 of each of the capacitors 21, 22, and a resin layer 35 provided on each moisture-resistant film 34. The passive electronic component 1 also includes a first external electrode 36 that penetrates the dielectric film 32, the moisture-resistant film 34, and the resin layer 35 and is connected to the first internal electrode 31 of each of the capacitors 21, 22, and a second external electrode 37 that penetrates the moisture-resistant film 34 and the resin layer 35 and is connected to the second internal electrode 33 of each of the capacitors 21, 22.

[0029] In each of the capacitors 21 and 22, a first internal electrode 31, a dielectric film 32, and a second internal electrode 33 are laminated in this order to form an MIM capacitor structure. In each of the capacitors 21 and 22, a charge can be stored in the dielectric film 32 by applying a voltage between the first internal electrode 31 and the second internal electrode 33.

[0030] 1 and 2, in the passive electronic component 1, an exposed portion 10c of the substrate 10 exists in at least a portion between adjacent capacitors 21 and 22. In other words, all of the material between the capacitors 21 and 22 has been removed by etching, dicing, or the like, and air (relative dielectric constant = 1) exists between the capacitors 21 and 22 on the substrate 10. This reduces electrical coupling due to the material between the capacitors 21 and 22, allowing for reduced power loss.

[0031] In this way, in the passive electronic component 1, the adjacent capacitors 21 and 22 are not connected to each other by any material other than the substrate 10, but are connected to each other by the substrate 10.

[0032] Fig. 4 is a schematic cross-sectional view showing a part of an example of a passive electronic component of Comparative Form 1. Fig. 5 is a schematic cross-sectional view showing a part of the passive electronic component shown in Fig. 2 .

[0033] As shown in FIG. 4, if the substrate 10 is not exposed between adjacent capacitors 21 and 22 and another material, such as a dielectric film 32, is present, capacitive coupling due to the dielectric film 32 and capacitive coupling due to the substrate 10 will occur between the capacitors 21 and 22.

[0034] In contrast, as shown in FIG. 5, if an exposed portion 10c of the substrate 10 is provided between adjacent capacitors 21 and 22 to create a space, the capacitive coupling caused by the material between the capacitors 21 and 22, for example, the dielectric film 32, is eliminated, thereby reducing power loss.

[0035] In the first aspect of the passive electronic component of the present invention, the exposed portion of the substrate may be present in at least a part of the region where the internal electrodes of two adjacent passive elements face each other when the substrate is viewed in a plan view (the region sandwiched between the internal electrodes, hereinafter also referred to as the inter-element region).

[0036] 1 , in the passive electronic component 1, the exposed portion 10c may be present in at least a part of the inter-element region 40 where the first internal electrode 31 and the second internal electrode 33 of the capacitor 21 and the first internal electrode 31 and the second internal electrode 33 of the capacitor 22 face each other when the substrate 10 is viewed in plan view. The exposed portion 10c preferably extends from one end to the other end of the inter-element region 40 in the second direction D2, i.e., in a direction perpendicular to the direction in which the two capacitors 21 and 22 are adjacent to each other, and more preferably extends from one end to the other end of the substrate 10 beyond the inter-element region 40 in the second direction D2.

[0037] The width of exposed portion 10c (dimension in first direction D1) can be set appropriately within a range that does not adversely affect capacitors 21 and 22, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0038] The planar shape of the exposed portion 10c may be, for example, a rectangular shape as shown in FIG. 1, or may have a shape having bent or curved portions.

[0039] In this specification, the term "planar shape" refers to the shape of the substrate when viewed from above.

[0040] Each component will be described in detail below.

[0041] The substrate 10 is not particularly limited, but is preferably a semiconductor substrate such as a silicon substrate or a gallium arsenide substrate, or an insulating substrate such as glass or alumina. In particular, the substrate 10 is preferably a silicon substrate, i.e., made of silicon.

[0042] The first internal electrode 31 has a rectangular planar shape and is arranged so that its long sides are parallel to the second direction D2. The planar shape of the first internal electrode 31 may be a shape in which at least one of the four corners (usually all four corners) of the rectangle is rounded.

[0043] The material constituting the first internal electrode 31 is not particularly limited, but is preferably Cu, Ag, Au, Al, Ni, Cr, or Ti, or an alloy containing at least one of these metals.

[0044] The dielectric film 32 is provided so as to cover the first internal electrodes 31 except for the openings. As shown in Fig. 1, the dielectric films 32 may be arranged in island shapes (e.g., rectangular shapes) each large enough to encompass the corresponding first internal electrode 31 when the substrate 10 is viewed in plan.

[0045] The material for the dielectric film 32 is not particularly limited, but is preferably SiO ２ , SiN, Al ２ O ３ , HfO ２ , Ta ２ O ５ Examples of oxides or nitrides include those mentioned above.

[0046] The second internal electrode 33 is provided opposite the first internal electrode 31 with the dielectric film 32 sandwiched therebetween. The second internal electrode 33 has a rectangular planar shape and is arranged so that its long sides are parallel to the second direction D2. The region of the second internal electrode 33 from the center to the end opposite to the second direction D2 faces the region of the first internal electrode 31 from the center to the end on the second direction D2 side. Note that the planar shape of the second internal electrode 33 may be a shape in which at least one of the four corners (usually all four corners) of the rectangular shape is rounded.

[0047] The material constituting the second internal electrode 33 is not particularly limited, but is preferably Cu, Ag, Au, Al, Ni, Cr, or Ti, or an alloy containing at least one of these metals.

[0048] The moisture-resistant film 34 is provided so as to cover the dielectric film 32 and the second internal electrode 33 except for the opening. The provision of the moisture-resistant film 34 enhances the moisture resistance of the dielectric film 32. As shown in Fig. 1, the moisture-resistant film 34 may be arranged in an island shape (e.g., rectangular shape) large enough to encompass the corresponding dielectric film 32 and second internal electrode 33 when the substrate 10 is viewed in plan. Note that the moisture-resistant film 34 does not necessarily have to be provided.

[0049] The material for forming the moisture-resistant film 34 is not particularly limited, but is preferably SiO ２ , SiN, or other moisture-resistant materials.

[0050] The resin layer 35 is provided so as to cover the moisture-resistant film 34 except for the openings. The resin layer 35 has openings at positions overlapping the openings of the dielectric film 32 and the moisture-resistant film 34 (openings overlapping the first internal electrode 31) and at positions overlapping the opening of the moisture-resistant film 34 (openings overlapping the second internal electrode 33). The provision of the resin layer 35 protects the dielectric film 32 from external moisture and impact. As shown in FIG. 1 , the resin layers 35 may be arranged in island shapes (e.g., rectangular shapes) each large enough to encompass the corresponding moisture-resistant film 34 when the substrate 10 is viewed in plan.

[0051] The material constituting the resin layer 35 is not particularly limited, but preferable examples include resin materials such as polyimide resin and resin in solder resist.

[0052] The material constituting the first external electrode 36 and the second external electrode 37 is not particularly limited, but preferably includes Cu, Ni, Ag, Au, Al, SnAg, etc. The first external electrode 36 and the second external electrode 37 may have a single-layer structure or a multi-layer structure. The outermost surfaces of the first external electrode 36 and the second external electrode 37 are preferably made of Au, Sn, or SnAg.

[0053] Fig. 6 is a plan view schematic diagram showing a first modified example of the passive electronic component according to the first embodiment of the present invention. Fig. 7 is a cross-sectional view schematic diagram showing an example of a cross section taken along line DD of the passive electronic component shown in Fig. 6. Fig. 8 is a cross-sectional view schematic diagram showing a part of the passive electronic component shown in Fig. 7.

[0054] 6 and 7, in the passive electronic component 1, a groove 10d may be provided in at least a part of the exposed portion 10c of the substrate 10. This lengthens the path of capacitive coupling caused by the substrate 10 between the capacitors 21 and 22, as shown in Fig. 8, and reduces this capacitive coupling, thereby enabling further reduction in power loss.

[0055] 6, similar to the exposed portion 10c, the groove portion 10d may be present in at least a part of the inter-element region 40 when the substrate 10 is viewed in plan view. The groove portion 10d preferably extends from one end to the other end of the inter-element region 40 in the second direction D2, and more preferably extends from one end to the other end of the substrate 10 beyond the inter-element region 40 in the second direction D2.

[0056] The width of the groove 10d (dimension in the first direction D1) is not particularly limited as long as it is smaller than the width of the exposed portion 10c, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0057] The depth of the groove 10d (the dimension in the third direction D3) can be set appropriately within a range that does not adversely affect the strength of the substrate 10, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0058] The planar shape of the groove 10d may be, for example, a shape having bent portions or curved portions, but is preferably a rectangular shape as shown in Fig. 6. This allows the groove 10d to be easily formed by a method such as half-cut dicing, dry etching, or wet etching.

[0059] FIG. 9 is a plan view schematic diagram showing a second modified example of the passive electronic component according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 9 taken along line segment E-E. FIG. 11 is a cross-sectional view schematic diagram showing an example of a cross section of the passive electronic component shown in FIG. 9 taken along line segment F-F or line segment G-G. Note that the cross sections of the passive electronic component shown in FIG. 9 taken along line segment F-F and line segment G-G may be substantially identical to each other, and therefore a common cross section is shown in FIG. 11. FIG. 12 is a cross-sectional view schematic diagram showing a portion of the passive electronic component shown in FIG. 10. FIG. 13 is a cross-sectional view schematic diagram showing a portion of an example of a passive electronic component according to comparative form 2.

[0060] The substrate 10 may be a silicon substrate as described above, that is, may be made of silicon, and as shown in Figures 9, 10 and 11, the passive electronic component 1 may further include insulating films 51 and 52 provided between the substrate 10 and the capacitors 21 and 22, respectively. In this case, however, the insulating films 51 and 52 (e.g., SiO ２ ) attracts free electrons in the substrate 10, generating a low-resistance layer at the interface between the insulating films 51 and 52 and the substrate 10. Therefore, as shown in Fig. 13, if a common insulating film 50 is provided between the capacitors 21 and 22 and the substrate 10, a leakage current will occur between the capacitors 21 and 22 through the low-resistance layer generated at the interface between the insulating film 50 and the substrate 10, resulting in power loss.

[0061] 12, it is preferable that the insulating films 51 and 52 are not provided in at least a portion between the adjacent capacitors 21 and 22. In other words, it is preferable that the insulating films 51 and 52 are not provided in the exposed portion 10c of the substrate 10. This eliminates the low-resistance layer between the capacitors 21 and 22, making it possible to prevent leakage current from occurring between the capacitors 21 and 22, thereby reducing power loss.

[0062] As shown in Figure 9, the insulating films 51 and 52 may be arranged in an island shape (e.g., rectangular shape) when the substrate 10 is viewed in a plane, with the size sufficient to encompass the first internal electrode 31 and the second internal electrode 33 of the corresponding capacitors 21 and 22, respectively.

[0063] Note that, as long as the insulating films 51 and 52 are not provided in the exposed portion 10c of the substrate 10, they may be present in part of the inter-element region 40 when the substrate 10 is viewed in plan view. However, it is preferable that the insulating films 51 and 52 are not present at least from one end to the other end of the inter-element region 40 in the second direction D2, and it is more preferable that the insulating films 51 and 52 are not present in the second direction D2 beyond the inter-element region 40 from one end to the other end of the substrate 10. For example, the insulating films 51 and 52 may be connected to each other in a region of the substrate 10 excluding the exposed portion 10c. In other words, the substrate 10 may be exposed by partially removing an insulating film common to the capacitors 21 and 22 between the capacitors 21 and 22.

[0064] The material for forming the insulating films 51 and 52 is not particularly limited, but is preferably SiO ２ , SiN, Al ２ O ３ , HfO ２ , Ta ２ O ５ , ZrO ２ etc.

[0065] When the substrate 10 is an insulating substrate such as glass or alumina, the insulating films 51 and 52 may not be provided.

[0066] FIG. 14 is a cross-sectional view showing a third modified example of the passive electronic component according to the first embodiment of the present invention.

[0067] As shown in FIG. 14, when insulating films 51 and 52 are provided, a groove 10d may be provided in at least a part of the exposed portion 10c of the substrate 10 as described above.

[0068] FIG. 15 is a schematic cross-sectional view showing a part of an example of a passive electronic component of Comparative Example 3. As shown in FIG.

[0069] As described above, when the substrate 10 is made of silicon and a common insulating film 50 is provided, a polycrystalline silicon layer 60 may be disposed between the substrate 10 and the insulating film 50 as shown in FIG. 15 as a countermeasure against leakage current caused by the low-resistivity layer. This can immobilize free electrons at the trap level of the polycrystalline silicon, thereby reducing leakage current caused by the low-resistivity layer. However, polycrystalline silicon has a large dielectric loss (tan δ), which leads to power loss. This is because power loss is expressed as the sum of dielectric loss and conductive loss.

[0070] Fig. 16 is a cross-sectional view showing a fourth modified example of the passive electronic component according to the first embodiment of the present invention, and Fig. 17 is a cross-sectional view showing a part of the passive electronic component shown in Fig. 16 .

[0071] Therefore, when the substrate 10 is made of silicon and the insulating films 51 and 52 and the polycrystalline silicon layer 60 are provided as described above, it is preferable that the polycrystalline silicon layer 60 is not provided in at least a portion between the adjacent capacitors 21 and 22, as shown in Figures 16 and 17. This makes it possible to reduce power loss due to the dielectric loss (tan δ) of polycrystalline silicon.

[0072] In this case, it is preferable that a groove 11 that penetrates the polycrystalline silicon layer 60 and reaches the substrate 10 is provided in at least a portion between the adjacent capacitors 21 and 22. This makes it possible to more reliably remove the polycrystalline silicon layer 60 from between the adjacent capacitors 21 and 22 by a method such as half-cut dicing, dry etching, or wet etching.

[0073] In this modification 4, the substrate 10 is exposed by removing the polycrystalline silicon layer 60 by a method such as half-cut dicing, dry etching, or wet etching, and the exposed portion 10c is formed. Therefore, the removed portion of the polycrystalline silicon layer 60 and the groove portion 11 are located in the same place as the exposed portion 10c of the substrate 10.

[0074] The grooves 11 can be provided in the same manner as the grooves 10d. That is, like the grooves 10d, the grooves 11 may be present in at least a part of the inter-element region 40 when the substrate 10 is viewed in plan, but preferably extend from one end to the other end of the inter-element region 40 in the second direction D2, and more preferably extend from one end to the other end of the substrate 10 beyond the inter-element region 40 in the second direction D2.

[0075] The width of the groove 11 (the dimension in the first direction D1) can be set appropriately within a range that does not adversely affect the capacitors 21 and 22, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0076] The depth of the groove portion 11 (dimension in the third direction D3) can be set appropriately within a range that reaches the substrate 10 and does not adversely affect the strength of the substrate 10, but it is preferably 1 μm or more, and more preferably 15 μm or more.

[0077] The planar shape of the groove 11 may be, for example, a shape having bent portions or curved portions, but is preferably a rectangular shape similar to the groove 10d shown in Fig. 6. This makes it possible to easily form the groove 11 and the exposed portion 10c by a method such as half-cut dicing, dry etching, or wet etching.

[0078] The passive electronic component 1 is manufactured, for example, by the following method.

[0079] <Step of Preparing a Substrate> FIG. 18 is a schematic cross-sectional view showing the step of preparing a substrate in an example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0080] As shown in FIG. 18, a substrate 10 is prepared.

[0081] The polycrystalline silicon layer 60 may be formed on the first main surface 10a of the substrate 10 by a CVD (Chemical Vapor Deposition) method or the like.

[0082] 19 is a schematic cross-sectional view showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. Fig. 20 is a schematic cross-sectional view showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention.

[0083] 19, an insulating layer 71 made of an insulating material is formed on the first main surface 10a of the substrate 10 by a method such as CVD or PVD (Physical Vapor Deposition). Then, the insulating layer 71 is patterned using a combination of photolithography and etching to form insulating films 51 and 52 as shown in Fig. 20. At this time, the insulating layer 71 is removed at least in the region overlapping the inter-element region 40 so that a portion of the first main surface 10a of the substrate 10 is exposed.

[0084] It should be noted that these steps for forming the insulating films 51 and 52 may be omitted.

[0085] <Step of Forming First Internal Electrode> FIG. 21 is a cross-sectional view schematically illustrating the step of forming a first internal electrode in the example of the method for manufacturing the passive electronic component according to the first embodiment of the present invention.

[0086] An electrode layer made of a conductive material is formed by a CVD method, a PVD method, or the like so as to cover the structure shown in Fig. 20 from the first main surface 10a side of the substrate 10. Thereafter, this electrode layer is patterned by a combination of photolithography and etching methods to form a first internal electrode 31 as shown in Fig. 21.

[0087] <Step of forming dielectric film> Fig. 22 is a schematic cross-sectional view showing a step of forming a dielectric layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. Fig. 23 is a schematic cross-sectional view showing a step of forming a dielectric film in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention.

[0088] As shown in Fig. 22, a dielectric layer 72 made of a dielectric material is formed by CVD, PVD, or the like so as to cover the structure shown in Fig. 21 from the first main surface 10a side of the substrate 10. Thereafter, the dielectric layer 72 is patterned by a combination of photolithography and etching to form the dielectric film 32 as shown in Fig. 23. Specifically, the dielectric film 32 is formed so as to cover the first internal electrode 31 from the first main surface 10a side of the substrate 10. At this time, the dielectric layer 72 is removed in a region overlapping the inter-element region 40 so as to expose a portion of the first main surface 10a of the substrate 10.

[0089] <Step of Forming Second Internal Electrode> FIG. 24 is a cross-sectional view schematically illustrating the step of forming a second internal electrode in the example of the method for manufacturing the passive electronic component according to the first embodiment of the present invention.

[0090] An electrode layer made of a conductive material is formed by a CVD method, a PVD method, or the like so as to cover the structure shown in Fig. 23 from the first main surface 10a side of the substrate 10. Thereafter, this electrode layer is patterned by a combination of photolithography and etching to form a second internal electrode 33 as shown in Fig. 24. Specifically, the second internal electrode 33 is formed so as to be adjacent to the first internal electrode 31 in the third direction D3, with the dielectric film 32 sandwiched between them.

[0091] Thereafter, a through-hole is formed by combining photolithography and etching, penetrating the dielectric film 32 in the third direction D3 so as to expose a portion of the first internal electrode 31.

[0092] <Step of forming moisture-resistant film> Fig. 25 is a schematic cross-sectional view showing a step of forming a moisture-resistant layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. Fig. 26 is a schematic cross-sectional view showing a step of forming a moisture-resistant film in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention.

[0093] As shown in Fig. 25, a moisture-resistant layer 73 made of a moisture-resistant material is formed by CVD, PVD, or the like so as to cover the structure shown in Fig. 24 from the first main surface 10a side of the substrate 10. Thereafter, the moisture-resistant layer 73 is patterned using a combination of photolithography and etching to form the moisture-resistant film 34 as shown in Fig. 26. Specifically, the moisture-resistant film 34 is formed so as to cover the second internal electrode 33 and the dielectric film 32 from the first main surface 10a side of the substrate 10. At this time, the moisture-resistant layer 73 is removed in a region overlapping the inter-element region 40 so as to expose a portion of the first main surface 10a of the substrate 10. Furthermore, a through-hole is provided through the moisture-resistant film 34 in the third direction D3 so as to expose a portion of the second internal electrode 33. Furthermore, a through hole is provided through the moisture-resistant film 34 in the third direction D3 at a position overlapping the through hole of the dielectric film 32 in the third direction D3 so that a part of the first internal electrode 31 is exposed.

[0094] <Step of Forming Resin Layer> FIG. 27 is a schematic cross-sectional view showing the step of forming a resin layer in the example of the method for manufacturing the passive electronic component according to the first embodiment of the present invention.

[0095] A resin layer made of a resin material is formed by spin coating or the like so as to cover the structure shown in FIG. 26 from the first main surface 10a side of the substrate 10. Thereafter, the resin layer is patterned using only photolithography if the resin material of the resin layer is photosensitive, or by a combination of photolithography and etching if the resin material of the resin layer is non-photosensitive, to form a resin layer 35 as shown in FIG. 27 . Specifically, the resin layer 35 is formed so as to cover the substrate 10 and the moisture-resistant film 34 from the first main surface 10a side of the substrate 10. At this time, the resin layer 35 is removed in a region overlapping the inter-element region 40 so as to expose a portion of the first main surface 10a of the substrate 10. Furthermore, a through-hole is formed through the resin layer 35 in the third direction D3 at a position overlapping the through-hole of the moisture-resistant film 34 in the third direction D3 so as to expose a portion of the second internal electrode 33. Furthermore, a through hole is provided through the resin layer 35 in the third direction D3 at a position that overlaps with the through hole of the dielectric film 32 and the through hole of the moisture-resistant film 34 in the third direction D3 so that a portion of the first internal electrode 31 is exposed.

[0096] The above steps form the exposed portion 10c of the substrate 10. Also, a through hole is formed by connecting the through hole of the moisture-resistant film 34 and the through hole of the resin layer 35 in the third direction D3 so as to expose a part of the second internal electrode 33. Furthermore, a through hole is formed by connecting the through hole of the dielectric film 32, the through hole of the moisture-resistant film 34, and the through hole of the resin layer 35 in the third direction D3 so as to expose a part of the first internal electrode 31.

[0097] <Process for forming first external electrode and second external electrode> Thereafter, the first external electrode 36 and the second external electrode 37 are formed by a lift-off method, a plating method, an etching method, etc. More specifically, the first external electrode 36 is formed so as to fill the through hole formed by the through hole of the dielectric film 32, the through hole of the moisture-resistant film 34, and the through hole of the resin layer 35 communicating in the third direction D3, and the second external electrode 37 is formed so as to fill the through hole formed by the through hole of the moisture-resistant film 34 and the through hole of the resin layer 35 communicating in the third direction D3.

[0098] Through the above steps, the capacitors 21 and 22 are formed.

[0099] <Step of Forming Grooves in Substrate> FIG. 28 is a cross-sectional view schematically illustrating a step of forming grooves in a substrate in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0100] As shown in FIG. 28, the exposed portion 10c of the substrate 10 between the capacitors 21 and 22 is partially cut (excavated) by half-cut dicing, dry etching, wet etching, or the like to form a groove portion 10d (or groove portion 11) in the substrate 10.

[0101] The step of forming the groove 10d (or the groove 11) may be omitted.

[0102] The substrate 10 may then be thinned to a desired device thickness by back grinding.

[0103] In this way, the passive electronic component 1 is manufactured.

[0104] [Embodiment 2] In a second aspect, the passive electronic component of the present invention comprises a substrate and two or more passive elements arranged on the substrate at a distance from each other, and is characterized in that a groove portion of the substrate is provided in at least a portion between adjacent passive elements of the two or more passive elements.

[0105] Hereinafter, an example of the second aspect of the passive electronic component of the present invention will be described as a passive electronic component of embodiment 2 of the present invention.

[0106] Fig. 29 is a plan view schematically illustrating an example of a passive electronic component according to embodiment 2 of the present invention. Fig. 30 is a cross-sectional view schematically illustrating an example of a cross section of the passive electronic component shown in Fig. 29 taken along line HH.

[0107] 29 and 30 includes, similarly to the passive electronic component 1, a substrate 10 and two capacitors 21A and 22A as passive elements disposed on the substrate 10. The two capacitors 21A and 22A are spaced apart from each other in the first direction D1.

[0108] In the passive electronic component 1A, a groove 10e is provided in the substrate 10 at least partially between adjacent capacitors 21A and 22A. This lengthens the path of capacitive coupling caused by the substrate 10 between the capacitors 21A and 22A, thereby reducing the capacitive coupling caused by the substrate 10. The dielectric constant of the material of the substrate 10 (e.g., silicon has a dielectric constant of 12) is generally higher than the dielectric constant of other materials formed on the substrate 10. Therefore, by providing the groove 10e and reducing the capacitive coupling caused by the substrate 10, the power loss of the entire passive electronic component 1A can be reduced.

[0109] Fig. 31 is a schematic cross-sectional view showing a part of an example of a passive electronic component of Comparative Form 4. Fig. 32 is a schematic cross-sectional view showing a part of the passive electronic component shown in Fig. 30.

[0110] As shown in FIG. 31, in addition to the capacitive coupling due to the substrate 10, capacitive coupling due to other materials, such as the dielectric film 32A, occurs between adjacent capacitors 21A and 22A. However, if there is no groove in the substrate 10 between the capacitors 21A and 22A, the capacitive coupling due to the substrate 10 will occur along the shortest path between the capacitors 21A and 22A.

[0111] 32, if a groove 10e is provided in the substrate 10 at least partially between the adjacent capacitors 21A and 22A, the path of capacitive coupling by the substrate 10 becomes longer, and it is possible to reduce the capacitive coupling by the substrate 10. As a result, it is possible to reduce power loss.

[0112] In the passive electronic component 1A, as shown in FIG. 30, the substrate 10 does not need to be exposed between adjacent capacitors 21A and 22A, and other materials (excluding electrode materials) necessary for the capacitors 21A and 22A are present between the capacitors 21A and 22A.

[0113] In the second aspect of the passive electronic component of the present invention, the groove in the substrate may be present in at least a part of an inter-element region where the electrodes of two adjacent passive elements face each other when the substrate is viewed in plan.

[0114] That is, in the passive electronic component 1A, the groove 10e may be present in at least a part of the inter-element region 40 where the first internal electrode 31 and the second internal electrode 33 of the capacitor 21A and the first internal electrode 31 and the second internal electrode 33 of the capacitor 22A face each other when the substrate 10 is viewed in plan as shown in Fig. 29. The groove 10e preferably extends from one end to the other end of the inter-element region 40 in the second direction D2, i.e., in a direction perpendicular to the direction in which the two capacitors 21A and 22A are adjacent to each other, and more preferably extends from one end to the other end of the substrate 10 beyond the inter-element region 40 in the second direction D2.

[0115] The width of the groove 10e (the dimension in the first direction D1) can be set appropriately within a range that does not adversely affect the capacitors 21A and 22A, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0116] The planar shape of the groove 10e may be, for example, a shape having bent or curved portions, but is preferably a rectangular shape as shown in Fig. 29. This allows the groove 10e to be easily formed by a method such as half-cut dicing, dry etching, or wet etching.

[0117] The passive electronic component 1A includes a dielectric film 32A, a moisture-resistant film 34A, and a resin layer 35A, which are provided in common to the capacitors 21A and 22A.

[0118] 29 , the dielectric film 32A may be arranged in an island shape (e.g., rectangular) large enough to encompass the first internal electrodes 31 of the capacitors 21A and 22A when the substrate 10 is viewed in a plan view. The moisture-resistant film 34A may be arranged in an island shape (e.g., rectangular) large enough to encompass the dielectric film 32A and the second internal electrodes 33 of the capacitors 21A and 22A when the substrate 10 is viewed in a plan view. The resin layer 35A may be arranged in an island shape (e.g., rectangular) large enough to encompass the moisture-resistant film 34A when the substrate 10 is viewed in a plan view. In this manner, the dielectric film 32A, the moisture-resistant film 34A, and the resin layer 35A may each be provided between adjacent capacitors 21A and 22A, or may be provided in the groove portion 10e of the substrate 10.

[0119] Fig. 33 is a plan view schematically illustrating a first modified example of the passive electronic component according to the second embodiment of the present invention. Fig. 34 is a cross-sectional view schematically illustrating an example of a cross section taken along line J-J of the passive electronic component shown in Fig. 33.

[0120] As in the first embodiment, the substrate 10 may be a silicon substrate, i.e., may be made of silicon, and the passive electronic component 1A may further include an insulating film 50A provided between the substrate 10 and each of the capacitors 21A and 22A, as shown in Figures 33 and 34. In this case, the insulating film 50A may also be provided between the adjacent capacitors 21A and 22A, or may be provided in the groove portion 10e of the substrate 10.

[0121] As shown in Figure 33, the insulating film 50A may be arranged in an island shape (e.g., rectangular shape) when the substrate 10 is viewed in a plane, with the size sufficient to encompass the first internal electrode 31 and the second internal electrode 33 of adjacent capacitors 21A and 22A.

[0122] The insulating film 50A does not have to be provided at least partially between the adjacent capacitors 21A and 22A, and does not have to be provided in the groove 10e of the substrate 10.

[0123] The passive electronic component according to the second aspect of the present invention may further include a polycrystalline silicon layer provided between the substrate and the insulating film. In this case, the polycrystalline silicon layer may be provided between adjacent passive elements, or may not be provided in at least a portion of the space between adjacent passive elements. The polycrystalline silicon layer may be provided within a groove in the substrate, or may not be provided within a groove in the substrate.

[0124] The passive electronic component 1A is manufactured, for example, by the following method.

[0125] <Step of Preparing a Substrate> FIG. 35 is a schematic cross-sectional view showing the step of preparing a substrate in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.

[0126] As shown in FIG. 35, a substrate 10 is prepared.

[0127] A polycrystalline silicon layer may be formed by CVD or the like on the first main surface 10a of the substrate 10. The polycrystalline silicon layer may be formed after the groove 10e of the substrate 10 is formed.

[0128] <Step of Forming Grooves in Substrate> FIG. 36 is a cross-sectional view schematically illustrating a step of forming grooves in a substrate in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.

[0129] As shown in FIG. 36, the substrate 10 is partially cut (excavated) in the region between the capacitors 21A and 22A by half-cut dicing, dry etching, wet etching or the like, to form a groove 10e in the substrate 10.

[0130] <Step of forming insulating film> Fig. 37 is a schematic cross-sectional view showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to embodiment 2 of the present invention. Fig. 38 is a schematic cross-sectional view showing a step of forming an insulating film in an example of a method for manufacturing a passive electronic component according to embodiment 2 of the present invention.

[0131] As in the first embodiment, after forming the insulating layer 71 as shown in Fig. 37, the insulating film 50A is formed as shown in Fig. 38. At this time, the insulating film 50A may be formed in the groove 10e of the substrate 10.

[0132] These steps for forming the insulating film 50A may be omitted.

[0133] <Step of Forming First Internal Electrode> FIG. 39 is a cross-sectional view schematically showing the step of forming a first internal electrode in the example of the method for manufacturing the passive electronic component according to the second embodiment of the present invention.

[0134] As in the case of the first embodiment, the first internal electrode 31 as shown in FIG. 39 is formed.

[0135] <Step of forming dielectric film> Figure 40 is a schematic cross-sectional view showing a step of forming a dielectric layer in an example of a method for manufacturing a passive electronic component according to embodiment 2 of the present invention. Figure 41 is a schematic cross-sectional view showing a step of forming a dielectric film in an example of a method for manufacturing a passive electronic component according to embodiment 2 of the present invention.

[0136] As in the first embodiment, after forming the dielectric layer 72 as shown in Fig. 40, the dielectric film 32A as shown in Fig. 41 is formed. At this time, the dielectric film 32A may be formed in the groove 10e of the substrate 10.

[0137] <Step of Forming Second Internal Electrode> FIG. 42 is a cross-sectional view schematically illustrating the step of forming a second internal electrode in the example of the method for manufacturing the passive electronic component according to the second embodiment of the present invention.

[0138] As in the case of the first embodiment, the second internal electrode 33 as shown in FIG. 42 is formed.

[0139] Thereafter, a through-hole is formed by combining photolithography and etching, penetrating the dielectric film 32A in the third direction D3 so as to expose a portion of the first internal electrode 31.

[0140] <Step of forming moisture-resistant film> Fig. 43 is a schematic cross-sectional view showing a step of forming a moisture-resistant layer in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention. Fig. 44 is a schematic cross-sectional view showing a step of forming a moisture-resistant film in an example of a method for manufacturing a passive electronic component according to Embodiment 1 of the present invention.

[0141] As in the first embodiment, after forming the moisture-resistant layer 73 as shown in Fig. 43, the moisture-resistant film 34A is formed as shown in Fig. 44. At this time, the moisture-resistant film 34A may be formed in the groove 10e of the substrate 10.

[0142] <Step of Forming Resin Layer> FIG. 45 is a schematic cross-sectional view showing the step of forming a resin layer in the example of the method for manufacturing the passive electronic component according to the first embodiment of the present invention.

[0143] 45 is formed in the same manner as in the first embodiment. At this time, the resin layer 35A may be formed in the groove 10e of the substrate 10.

[0144] <Step of Forming First External Electrode and Second External Electrode> Thereafter, similarly to the first embodiment, the first external electrode 36 and the second external electrode 37 are formed.

[0145] Through the above steps, the capacitors 21A and 22A are formed.

[0146] The substrate 10 may then be thinned to a desired device thickness by back grinding.

[0147] In this way, the passive electronic component 1A is manufactured.

[0148] In the first and second embodiments of the passive electronic component of the present invention, although a single passive electronic component is formed on a substrate, multiple passive electronic components may be formed on a substrate. In this case, the substrate on which the multiple passive electronic components are formed is thinned to a desired device thickness by back grinding, and then singulated by blade dicing, stealth dicing, plasma dicing, or the like. In other words, the aggregate substrate is cut into pieces the size of individual passive electronic components.

[0149] [Embodiment 3] In a third aspect, the passive electronic component of the present invention comprises a substrate, two or more passive elements arranged on the substrate at a distance from each other, an insulating film provided between each of the two or more passive elements, and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon, and an exposed portion of the polycrystalline silicon layer is present in at least a portion between adjacent passive elements of the two or more passive elements.

[0150] Hereinafter, an example of the third aspect of the passive electronic component of the present invention will be described as a passive electronic component of embodiment 3 of the present invention.

[0151] Fig. 46 is a plan view schematic diagram showing an example of a passive electronic component according to embodiment 3 of the present invention. Fig. 47 is a cross-sectional schematic diagram showing an example of a cross-section of the passive electronic component shown in Fig. 46 taken along line segment K-K. Fig. 48 is a cross-sectional schematic diagram showing an example of a cross-section of the passive electronic component shown in Fig. 46 taken along line segment L-L or line segment M-M. Note that the cross-sections of the passive electronic component shown in Fig. 46 taken along line segment L-L and line segment M-M may be substantially identical to each other, and therefore a common cross-section is shown in Fig. 48.

[0152] 46, 47, and 48, like the passive electronic component 1, includes a substrate 10 and two capacitors 21 and 22 as passive elements arranged on the substrate 10. The two capacitors 21 and 22 are spaced apart from each other in the first direction D1.

[0153] Furthermore, the substrate 10 is a silicon substrate, i.e., made of silicon, and as shown in Figures 46, 47 and 48, the passive electronic component 1B further includes insulating films 51 and 52 provided between the substrate 10 and each of the capacitors 21 and 22, and a polycrystalline silicon layer 60 provided between the substrate 10 and each of the insulating films 51 and 52.

[0154] In the passive electronic component 1B, an exposed portion 60c of the polycrystalline silicon layer 60 exists in at least a portion between the adjacent capacitors 21 and 22. In other words, all of the material between the capacitors 21 and 22 has been removed by etching, dicing, or the like, and air (dielectric constant = 1) exists between the capacitors 21 and 22 on the polycrystalline silicon layer 60. This reduces electrical coupling due to the material between the capacitors 21 and 22, thereby reducing power loss.

[0155] In this embodiment, power loss occurs due to the dielectric loss (tan δ) of polycrystalline silicon, but the electrical coupling due to the material between capacitors 21 and 22 is still reduced, so power loss can be reduced compared to when the material between capacitors 21 and 22 is not removed.

[0156] In the third aspect of the passive electronic component of the present invention, the exposed portion of the polycrystalline silicon layer may be present in at least a part of an inter-element region where the electrodes of two adjacent passive elements face each other when the substrate is viewed in plan.

[0157] 46 , in the passive electronic component 1B, the exposed portion 60c may be present in at least a part of the inter-element region 40 where the first internal electrode 31 and the second internal electrode 33 of the capacitor 21 and the first internal electrode 31 and the second internal electrode 33 of the capacitor 22 face each other when the substrate 10 is viewed in plan view. The exposed portion 60c preferably extends from one end to the other end of the inter-element region 40 in the second direction D2, i.e., in a direction perpendicular to the direction in which the two capacitors 21 and 22 are adjacent to each other, and more preferably extends from one end to the other end of the substrate 10 beyond the inter-element region 40 in the second direction D2.

[0158] The width of the exposed portion 60c (the dimension in the first direction D1) can be set appropriately within a range that does not adversely affect the capacitors 21 and 22, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0159] The planar shape of the exposed portion 60c may be, for example, a rectangular shape as shown in FIG. 46, or may have a shape with bent or curved portions.

[0160] 47 , it is preferable that the insulating films 51 and 52 are not provided in at least a part of the space between the adjacent capacitors 21 and 22. That is, it is preferable that the insulating films 51 and 52 are not provided in the exposed portion 60c of the polycrystalline silicon layer 60. This eliminates the low resistance layer between the capacitors 21 and 22, making it possible to prevent the occurrence of a leak current between the capacitors 21 and 22.

[0161] As shown in Figure 46, the insulating films 51 and 52 may be arranged in an island shape (e.g., rectangular shape) when the substrate 10 is viewed in a plane, with the size sufficient to encompass the first internal electrode 31 and the second internal electrode 33 of the corresponding capacitors 21 and 22, respectively.

[0162] Note that the insulating films 51 and 52 may be present in part of the inter-element region 40 when the substrate 10 is viewed in plan view, as long as they are not provided in the exposed portion 60c of the polycrystalline silicon layer 60. However, it is preferable that the insulating films 51 and 52 are not present at least from one end to the other end of the inter-element region 40 in the second direction D2, and it is more preferable that the insulating films 51 and 52 are not present in the second direction D2 beyond the inter-element region 40 from one end to the other end of the substrate 10. For example, the insulating films 51 and 52 may be connected to each other in a region excluding the exposed portion 60c of the polycrystalline silicon layer 60. In other words, the insulating film common to the capacitors 21 and 22 may be partially removed between the capacitors 21 and 22, thereby exposing the polycrystalline silicon layer 60.

[0163] Like the passive electronic component 1, the passive electronic component 1B includes a moisture-resistant film 34, a resin layer 35, a first external electrode 36, and a second external electrode 37 provided for each of the capacitors 21 and 22.

[0164] Fig. 49 is a plan view schematically illustrating a first modified example of the passive electronic component according to the third embodiment of the present invention. Fig. 50 is a cross-sectional view schematically illustrating an example of a cross section taken along line N-N of the passive electronic component shown in Fig. 49.

[0165] 49 and 50 , in a passive electronic component 1B, a groove 60d may be provided in at least a part of an exposed portion 60c of a polycrystalline silicon layer 60. This reduces the volume of the polycrystalline silicon layer 60, thereby reducing power loss due to the dielectric loss (tan δ) of polycrystalline silicon.

[0166] 49 , similar to the exposed portion 60c, the groove portion 60d may be present in at least a part of the inter-element region 40 when the substrate 10 is viewed in plan view. The groove portion 60d preferably extends from one end to the other end of the inter-element region 40 in the second direction D2, and more preferably extends from one end to the other end of the substrate 10 beyond the inter-element region 40 in the second direction D2.

[0167] The width of the groove 60d (dimension in the first direction D1) is not particularly limited as long as it is smaller than the width of the exposed portion 60c, but is preferably 1 μm or more, and more preferably 15 μm or more.

[0168] The depth of the groove 60d (the dimension in the third direction D3) can be set as appropriate within a range that does not adversely affect the strength of the substrate 10, but is preferably 1 μm or more, and more preferably 15 μm or more. However, the depth of the groove 60d is set within a range that does not allow the groove 60d to penetrate the polycrystalline silicon layer 60 and reach the substrate 10.

[0169] The planar shape of the groove 60d may be, for example, a shape having bent or curved portions, but is preferably a rectangular shape as shown in Fig. 49. This allows the groove 60d to be easily formed by a method such as half-cut dicing, dry etching, or wet etching.

[0170] The passive electronic component 1B can be manufactured by, for example, the same manufacturing method as that for the passive electronic component 1.

[0171] [Embodiment 4] In a fourth aspect, the passive electronic component of the present invention comprises a substrate, two or more passive elements arranged on the substrate at a distance from each other, an insulating film provided between each of the two or more passive elements, and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon, and a groove portion of the polycrystalline silicon layer is provided in at least a portion between adjacent passive elements of the two or more passive elements.

[0172] Hereinafter, an example of the fourth aspect of the passive electronic component of the present invention will be described as a passive electronic component of embodiment 4 of the present invention.

[0173] FIG. 51 is a cross-sectional view showing a passive electronic component according to a fourth embodiment of the present invention.

[0174] 51 includes a substrate 10 and two capacitors 21C and 22C as passive elements arranged on the substrate 10, similar to the passive electronic component 1. The two capacitors 21C and 22C are spaced apart from each other in the first direction D1.

[0175] Furthermore, the substrate 10 is a silicon substrate, i.e., made of silicon, and as shown in FIG. 51, the passive electronic component 1C, like the passive electronic component 1B, further comprises insulating films 51 and 52 provided between the substrate 10 and each of the capacitors 21C and 22C, and a polycrystalline silicon layer 60 provided between the substrate 10 and each of the insulating films 51 and 52.

[0176] Furthermore, in passive electronic component 1C, similar to passive electronic component 1B, a groove 60d is provided in polycrystalline silicon layer 60 at least partially between capacitors 21C and 22C, which reduces the volume of polycrystalline silicon layer 60 and thereby reduces power loss due to the dielectric loss (tan δ) of polycrystalline silicon.

[0177] The passive electronic component 1C can also be provided with a groove 60d, similar to the passive electronic component 1B.

[0178] On the other hand, in the passive electronic component 1C, unlike the passive electronic component 1B, a dielectric film 32C provided in common to the capacitors 21C and 22C exists between the capacitors 21C and 22C. Therefore, the dielectric film 32C covers the polycrystalline silicon layer 60 between the capacitors 21C and 22C, and the polycrystalline silicon layer 60 is not exposed. In other words, the dielectric film 32C is provided in the groove portion 60d of the polycrystalline silicon layer 60.

[0179] In the passive electronic component 1C, a groove 60d is provided in the polycrystalline silicon layer 60 at least partially between adjacent capacitors 21C and 22C. This lengthens the path of capacitive coupling caused by the polycrystalline silicon layer 60 between the capacitors 21C and 22C, thereby reducing the capacitive coupling caused by the polycrystalline silicon layer 60. The dielectric constant of the material of the polycrystalline silicon layer 60 (dielectric constant of silicon = 12) is generally higher than the dielectric constant of other materials formed on the substrate 10. Therefore, by providing the groove 60d and reducing the capacitive coupling caused by the polycrystalline silicon layer 60, power loss throughout the passive electronic component 1C can be reduced.

[0180] The passive electronic component 1C can be manufactured by, for example, the same manufacturing method as that for the passive electronic component 1.

[0181] [Embodiment 5] A mounting structure of a passive electronic component of the present invention comprises a passive electronic component of the present invention, and a mounting board including a substrate main body having a mounting surface and land electrodes formed on the mounting surface, wherein external electrodes of the passive electronic component are electrically connected to the land electrodes, and the area between the passive electronic component and the mounting surface is sealed with a molded resin.

[0182] Hereinafter, an example of a passive electronic component mounting structure of the present invention will be described as a passive electronic component mounting structure according to a fifth embodiment of the present invention.

[0183] Fig. 52 is a cross-sectional view schematically illustrating an example of a mounting structure of a passive electronic component according to Embodiment 5 of the present invention. Fig. 53 is a cross-sectional view schematically illustrating another example of a cross section (a cross section perpendicular to the cross section of Fig. 52) of the passive electronic component shown in Fig. 52.

[0184] The passive electronic component mounting structure 100 shown in FIGS. 52 and 53 includes the passive electronic component 1 of the first embodiment and a mounting substrate 110 .

[0185] The mounting substrate 110 includes a substrate body 111 having a mounting surface 111a, and a pair of land electrodes 112 and a pair of land electrodes 113 formed on the mounting surface 111a. The substrate body 111 is formed of, for example, a resin such as glass epoxy or a ceramic such as glass ceramic. The substrate body 111 may be formed of a plurality of laminated insulator layers. The mounting surface 111a is provided on one main surface of the substrate body 111. Each of the land electrodes 112, 113 is, for example, an electrode having a rectangular or circular shape in a plan view, and is disposed on the mounting surface 111a.

[0186] The first external electrodes 36 of the capacitors 21, 22 of the passive electronic component 1 are electrically connected to the land electrodes 112 via the solder 120 or the SnAg of the external electrodes. The second external electrodes 37 of the capacitors 21, 22 of the passive electronic component 1 are electrically connected to the land electrodes 113 via the solder 120 or the SnAg of the external electrodes. In this way, the land electrodes 112, 113 are provided corresponding to the external electrodes 36, 37, and the corresponding external electrodes 36 or 37 and the land electrodes 112 or 113 are connected and fixed to each other via the solder 120 or the SnAg of the external electrodes.

[0187] When the passive electronic component 1 is mounted on the mounting substrate 110, the periphery thereof is sealed with molded resin 130, and in the mounting structure 100, the region between the passive electronic component 1 and the mounting surface 111a is sealed with molded resin 130. Here, the molded resin 130 seals the entire passive electronic component 1. Although capacitive coupling may occur between the capacitors 21 and 22 of the passive electronic component 1 due to the molded resin 130, the relative dielectric constant of the molded resin is generally lower than the relative dielectric constant of the material of the passive electronic component 1, and therefore power loss can be reduced.

[0188] The material that constitutes the mold resin 130 is not particularly limited, but preferable examples include resin materials such as epoxy resin, silicone resin, and urethane resin.

[0189] FIG. 54 is a cross-sectional view showing a first modified example of the passive electronic component mounting structure according to the fifth embodiment of the present invention.

[0190] 54 , a passive electronic component mounting structure 100 may include a passive electronic component 1A of embodiment 2 instead of the passive electronic component 1 of embodiment 1. In the passive electronic component 1A, a resin layer 35A may be filled into the groove 10e of the substrate 10, but even in this case, the power loss can be reduced because the dielectric constant of the resin layer 35A (e.g., the dielectric constant of polyimide=5) is lower than the dielectric constant of the material of the substrate 10 (e.g., the dielectric constant of silicon=12).

[0191] The passive electronic component mounting structure 100 may include the passive electronic component 1B of the third embodiment or the passive electronic component 1C of the fourth embodiment instead of the passive electronic component 1 of the first embodiment.

[0192] Furthermore, in the passive electronic component and the passive electronic component mounting structure of the present invention, although the passive elements are illustrated as capacitors in the first to fifth embodiments, the passive electronic component and the passive electronic component mounting structure of the present invention may include, for example, resistors or inductors as passive elements, or may include at least two types of elements selected from a capacitor, a resistor, and an inductor as passive elements.

[0193] The present specification discloses the following:

[0194] <1> A passive electronic component comprising: a substrate; and two or more passive elements arranged on the substrate at a distance from each other, wherein an exposed portion of the substrate is present in at least a portion between adjacent passive elements of the two or more passive elements.

[0195] <2> The passive electronic component according to <1>, wherein a groove is provided in at least a part of the exposed portion of the substrate.

[0196] <3> A passive electronic component comprising: a substrate; and two or more passive elements arranged on the substrate at a distance from each other, wherein a groove portion of the substrate is provided in at least a portion between adjacent passive elements of the two or more passive elements.

[0197] <4> The passive electronic component according to any one of <1> to <3>, wherein the substrate is made of silicon.

[0198] <5> The passive electronic component according to any one of <1> to <3>, wherein the substrate is made of silicon, and further comprises an insulating film provided between the substrate and each of the two or more passive elements, and the insulating film is not provided in at least a portion between the adjacent passive elements.

[0199] <6> The passive electronic component according to <5>, further comprising a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the polycrystalline silicon layer is not provided in at least a portion between the adjacent passive elements.

[0200] <7> The passive electronic component according to <6>, wherein a groove portion that penetrates the polycrystalline silicon layer and reaches the substrate is provided at least in a portion between the adjacent passive elements.

[0201] <8> A passive electronic component comprising: a substrate; two or more passive elements arranged on the substrate at a distance from each other; an insulating film provided between each of the two or more passive elements; and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon; and an exposed portion of the polycrystalline silicon layer is present in at least a portion between adjacent passive elements of the two or more passive elements.

[0202] <9> The passive electronic component according to <8>, wherein a groove is provided in at least a part of the exposed portion of the polycrystalline silicon layer.

[0203] <10> A passive electronic component comprising: a substrate; two or more passive elements arranged on the substrate at a distance from each other; an insulating film provided between each of the two or more passive elements; and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon; and a groove portion of the polycrystalline silicon layer is provided in at least a portion between adjacent passive elements of the two or more passive elements.

[0204] <11> A mounting structure for a passive electronic component, comprising: the passive electronic component according to any one of <1> to <10>; and a mounting substrate including a substrate body having a mounting surface and land electrodes formed on the mounting surface, wherein external electrodes of the passive electronic component are electrically connected to the land electrodes, and an area between the passive electronic component and the mounting surface is sealed with a mold resin.

[0205] 1, 1A, 1B, 1C Passive electronic component 10 Substrate 10a First main surface of substrate 10b Second main surface of substrate 10c Exposed portion of substrate 10d Groove portion of substrate 10e Groove portion of substrate 11 Groove portion 21, 22, 21A, 22A, 21C, 22C Capacitor 31 First internal electrode 32, 32A, 32C Dielectric film 33 Second internal electrode 34, 34A Moisture-resistant film 35, 35A Resin layer 36 First external electrode 37 Second external electrode 40 Inter-element region 50, 50A, 51, 52 Insulating film 60 Polycrystalline silicon layer 60c Exposed portion of polycrystalline silicon layer 60d Groove portion of polycrystalline silicon layer 71 Insulating layer 72 Dielectric layer 73 Moisture-resistant layer 100 Mounting structure of passive electronic component 110 Mounting substrate 111 Substrate body 111a Mounting surface 112, 113 Land electrodes 120 Solder 130 Molding resin D1 First direction D2 Second direction D3 Third direction

Claims

1. A passive electronic component comprising: a substrate; and two or more passive elements arranged on the substrate at a distance from each other, wherein an exposed portion of the substrate exists in at least a portion between adjacent passive elements of the two or more passive elements.

2. The passive electronic component according to claim 1, wherein a groove is provided in at least a portion of said exposed portion of said substrate.

3. A passive electronic component comprising: a substrate; and two or more passive elements arranged on the substrate at a distance from each other, wherein a groove portion of the substrate is provided in at least a portion between adjacent passive elements of the two or more passive elements.

4. A passive electronic component according to any one of claims 1 to 3, wherein the substrate is made of silicon.

5. A passive electronic component according to any one of claims 1 to 3, wherein the substrate is made of silicon, and further comprises an insulating film provided between the substrate and each of the two or more passive elements, and the insulating film is not provided in at least a portion of the space between the adjacent passive elements.

6. The passive electronic component according to claim 5, further comprising a polycrystalline silicon layer provided between said substrate and said insulating film, said polycrystalline silicon layer being not provided in at least a portion of the space between said adjacent passive elements.

7. The passive electronic component according to claim 6, wherein a groove is provided between at least a portion of the adjacent passive elements, the groove penetrating the polycrystalline silicon layer and reaching the substrate.

8. A passive electronic component comprising: a substrate; two or more passive elements arranged on the substrate at a distance from each other; an insulating film provided between each of the two or more passive elements; and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon, and an exposed portion of the polycrystalline silicon layer is present in at least a portion between adjacent passive elements of the two or more passive elements.

9. The passive electronic component according to claim 8, wherein a groove is provided in at least a portion of said exposed portion of said polycrystalline silicon layer.

10. A passive electronic component comprising: a substrate; two or more passive elements arranged on the substrate at a distance from each other; an insulating film provided between each of the two or more passive elements; and a polycrystalline silicon layer provided between the substrate and the insulating film, wherein the substrate is made of silicon; and a groove portion of the polycrystalline silicon layer is provided in at least a portion of the space between adjacent passive elements of the two or more passive elements.

11. A mounting structure for a passive electronic component comprising: a passive electronic component according to any one of claims 1 to 10; and a mounting substrate comprising a substrate body having a mounting surface and land electrodes formed on said mounting surface, wherein external electrodes of said passive electronic component are electrically connected to said land electrodes, and the area between said passive electronic component and said mounting surface is sealed with a molded resin.

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