Semiconductor manufacturing device member and method for regenerating same

Abstract

The present invention addresses the problem of providing a semiconductor manufacturing device member capable of obtaining high electrostatic adsorption force. Provided is a semiconductor manufacturing device member which is provided with: a first ceramic part that has an upper surface including a wafer mounting surface and that has a lower surface located on the opposite side thereof from the upper surface; a second ceramic part that is joined to the lower surface of the first ceramic part; a first amorphous layer that is present at the joining interface between the first ceramic part and the second ceramic part; and an electrostatic adsorption electrode that is disposed on the first ceramic part, on the second ceramic part, or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a higher relative permittivity than the second ceramic part.

Description

Semiconductor manufacturing equipment components and their regeneration method

[0001] The present invention relates to a semiconductor manufacturing equipment member and a method for recycling the same.

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for wafer holding, temperature control, transport, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract a wafer by electrostatic force.

[0003] A known example of such a semiconductor manufacturing equipment component is a ceramic substrate having an upper surface with a wafer mounting surface and a lower surface opposite the upper surface, the ceramic substrate having a built-in electrostatic chucking electrode. The wafer mounting surface can be formed, for example, by the upper surfaces of a plurality of protrusions provided on the upper surface of the ceramic substrate.

[0004] Known types of ceramics that can be used to form ceramic substrates include aluminum oxide, magnesium oxide, yttrium oxide, and aluminum nitride (Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2023-31112

[0006] There are cases where semiconductor manufacturing equipment components are required to have a stronger electrostatic attraction force for wafers. However, there is still room for improvement in the electrostatic attraction force for wafers of conventional semiconductor manufacturing equipment components.

[0007] Furthermore, if the quality of a semiconductor manufacturing equipment component deteriorates, the deteriorated semiconductor manufacturing equipment component can be discarded. However, from the perspective of reducing waste, making effective use of resources, and promoting a circular economy, it is desirable to be able to repair and regenerate semiconductor manufacturing equipment components.

[0008] In view of the above circumstances, an object of the present invention is to provide, in one embodiment, a semiconductor manufacturing equipment member that is capable of obtaining a high electrostatic adsorption force. Also, an object of the present invention is to provide, in another embodiment, a method for recycling a semiconductor manufacturing equipment member.

[0009] The present inventors conducted extensive research to solve the above-mentioned problems and have devised the present invention, as exemplified below. [Aspect 1] A semiconductor manufacturing equipment component comprising: a first ceramic part having an upper surface with a wafer mounting surface and a lower surface located opposite the upper surface; a second ceramic part bonded to the lower surface of the first ceramic part; a first amorphous layer present at the bonding interface between the first ceramic part and the second ceramic part; and an electrostatic chucking electrode disposed in the first ceramic part, the second ceramic part, or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a higher dielectric constant than the second ceramic part. [Aspect 2] The semiconductor manufacturing equipment component according to Aspect 1, wherein the first ceramic part has a dielectric constant greater than 10. [Aspect 3] The semiconductor manufacturing equipment component according to Aspect 1 or 2, wherein the electrode is built into the second ceramic part. [Aspect 4] The semiconductor manufacturing equipment component according to any one of Aspects 1 to 3, wherein the first ceramic part is a plate having a plurality of protrusions on its upper surface that have the wafer mounting surface. [Aspect 5] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 3, wherein the upper surface of the first ceramic part itself is a plurality of protrusions that constitute the wafer mounting surface. [Aspect 6] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 5, comprising: a first deteriorated layer present on a side of the first ceramic part that contacts the first amorphous layer; and a second deteriorated layer present on a side of the second ceramic part that contacts the first amorphous layer. [Aspect 7] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 6, comprising: a third ceramic part bonded to a lower surface of the second ceramic part; and a second amorphous layer present at a bonding interface between the second ceramic part and the third ceramic part. [Aspect 8] The semiconductor manufacturing equipment member according to Aspect 7, wherein a refrigerant flow path through which a refrigerant flows or a gas flow path for supplying gas to the wafer mounting surface is provided at a position of the second ceramic part facing the second amorphous layer and / or at a position of the third ceramic part facing the second amorphous layer.[Aspect 9] The semiconductor manufacturing equipment member according to Aspect 7 or 8, comprising: a third affected layer present on a side of the second ceramic portion that contacts the second amorphous layer; and a fourth affected layer present on a side of the third ceramic portion that contacts the second amorphous layer. [Aspect 10] A method for regenerating a semiconductor manufacturing equipment member, comprising: processing the top surface of the first ceramic portion of the semiconductor manufacturing equipment member according to any one of Aspects 1 to 9 to form a processed surface on the first ceramic portion from which the wafer-mounting surface has been removed; and further processing the processed surface to form a new wafer-mounting surface. [Aspect 11] A method for regenerating a semiconductor manufacturing equipment member, comprising: processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member described in any of Aspects 1 to 9 to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed, and directly bonding a regenerative ceramic part, which has a higher dielectric constant than the second ceramic part, to the processed surface. [Aspect 12] A method for regenerating a semiconductor manufacturing equipment member, comprising: processing the first ceramic part of the semiconductor manufacturing equipment member described in any of Aspects 1 to 9 to remove the second ceramic part so as to expose the second ceramic part, and form a processed surface on the second ceramic part, and directly bonding a regenerative ceramic part, which has a higher dielectric constant than the second ceramic part, to the processed surface of the second ceramic part.

[0010] A semiconductor manufacturing equipment member according to one embodiment of the present invention includes a first ceramic part having a high dielectric constant, thereby enabling it to obtain a high electrostatic adsorption force. The semiconductor manufacturing equipment member also includes a second ceramic part having a lower dielectric constant than the first ceramic part, enabling it to exhibit characteristics different from those of the first ceramic part. The material of the second ceramic part can be changed as appropriate depending on the required performance. Therefore, the semiconductor manufacturing equipment member can achieve not only a high electrostatic adsorption force but also other required performances.

[0011] Furthermore, even if the quality of the semiconductor manufacturing equipment component deteriorates due to shedding of ceramic particles that make up the protrusions on the wafer-mounting surface, the component can be repaired and recycled without having to be newly manufactured from scratch. Therefore, this recycling method significantly contributes to reducing waste, making effective use of resources, and promoting a circular economy.

[0012] [Correction based on Rule 91 21.04.2025] FIG. 1 is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to embodiment A of the present invention. FIG. 1 is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to embodiment B of the present invention. FIG. 1 is another schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to embodiment B of the present invention. FIG. 1 is a schematic partial enlarged view of a portion surrounded by a thick frame shown in FIG. 1A. FIG. 1C is a schematic partial enlarged view of a portion surrounded by a thick frame shown in FIG. 1C. FIG. 1C is a schematic plan view of a wafer mounting surface of a semiconductor manufacturing equipment member according to embodiment A of the present invention. FIG. 1D is a schematic plan view of a wafer mounting surface of a semiconductor manufacturing equipment member according to embodiment B of the present invention. FIG. 1E is a diagram for explaining an example of a manufacturing method for a semiconductor manufacturing equipment member. FIG. 1F is a diagram for explaining regeneration method A according to one embodiment of the present invention. FIG. 1G is a diagram for explaining regeneration method B according to one embodiment of the present invention. FIG. 1H is a diagram for explaining regeneration method C according to one embodiment of the present invention. FIG. 1I is a schematic perspective view of a polishing apparatus for performing lapping.

[0013] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when a semiconductor manufacturing equipment component is placed on a horizontal surface with the wafer-mounting surface facing up, and do not represent an absolute positional relationship. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0014] 1. Basic Configuration of a Semiconductor Manufacturing Equipment Member A semiconductor manufacturing equipment member according to one embodiment of the present invention includes a first ceramic part having an upper surface with a wafer mounting surface and a lower surface opposite the upper surface, a second ceramic part bonded to the lower surface of the first ceramic part, a first amorphous layer present at the bonding interface between the first ceramic part and the second ceramic part, and an electrostatic chucking electrode built into the first ceramic part or the second ceramic part, wherein the first ceramic part has a higher dielectric constant than the second ceramic part. This semiconductor manufacturing equipment member can be used, for example, when performing processes such as CVD or etching on a wafer W using plasma.

[0015] In one embodiment, the first ceramic part can be provided in the form of a plate having a plurality of protrusions on its upper surface, the protrusions having a wafer mounting surface. In another embodiment, the first ceramic part can be provided in the form of a plurality of protrusions, the upper surface of which itself constitutes the wafer mounting surface.

[0016] The electrostatic force F of a capacitor is generally expressed by the following formula: F = 1 / 2 x Q 2 / (ε0S) ...Equation 1 (where Q is the quantity of electricity, ε0 ​​is the dielectric constant in a vacuum, and S is the area of ​​the electrode plate.) The quantity of electricity Q is generally expressed by Equation 2: Q = CV (where C is the capacitance of the capacitor, and V is the voltage between the electrodes.) The capacitance C is generally expressed by Equation 3: C = ε r ε0S / d...Formula 3 (In the formula, ε r is the relative dielectric constant, and d is the distance between the electrodes.) From Equation 1, Equation 2, and Equation 3, F = 1 / 2 × ε r 2 ε S × (V / d) 2

[0017] In this way, the electrostatic force F of a capacitor is proportional to the relative dielectric constant ε of the ceramic material that makes up the capacitor. r In semiconductor manufacturing equipment components, the space between the electrostatic chucking electrode and the wafer mounting surface can be regarded as a pseudo-capacitor, so the electrostatic chucking force to the wafer depends on the relative dielectric constant ε of the ceramic material present between the electrostatic chucking electrode and the wafer mounting surface. rTherefore, the relative dielectric constant ε of the first ceramic portion having the wafer mounting surface is r By increasing the value, it is possible to obtain a high electrostatic adsorption force.

[0018] The electrostatic chucking electrode may be embedded in either the first ceramic part or the second ceramic part, but is preferably embedded in a position where the electrode will remain and not be removed during the recycling of the semiconductor manufacturing equipment component. When the thickness of the first ceramic part is extremely thin, it is difficult to embed the electrode. Furthermore, if the electrode is embedded in the first ceramic part, there is a risk that the electrode will be accidentally removed during the recycling of the semiconductor manufacturing equipment component. In such cases, it is preferable that the electrode be embedded in the second ceramic part, not in the first ceramic part.

[0019] The dielectric constant of the first ceramic part is preferably greater than 10, more preferably 12 or greater, and even more preferably 15 or greater. No particular upper limit is set for the dielectric constant of the first ceramic part, but from the viewpoint of availability, it is preferably 100 or less, more preferably 50 or less, and even more preferably 30 or less. Therefore, the dielectric constant of the first ceramic part is, for example, preferably greater than 10 and 100 or less, more preferably 12 or greater and 50 or less, and even more preferably 15 or greater and 50 or less.

[0020] Examples of ceramics having a relative dielectric constant greater than 10 include zirconia, yttria, and barium titanate. The first ceramic portion may contain one type of ceramic, or a combination of two or more types of ceramic. The relative dielectric constant of the first ceramic portion as a whole is required to be greater than that of the second ceramic portion, and the first ceramic portion may partially contain ceramics having a relative dielectric constant smaller than that of the second ceramic portion.

[0021] The second ceramic portion has a lower dielectric constant than the first ceramic portion. For example, the second ceramic portion may have a dielectric constant of 10 or less, or may have a dielectric constant of 7 or more and 10 or less.

[0022] Examples of the ceramics constituting the second ceramic portion include alumina and aluminum nitride. The second ceramic portion may contain one type of ceramic or a combination of two or more types of ceramics.

[0023] The second ceramic portion may have a dielectric constant smaller than that of the first ceramic portion as a whole, and the second ceramic portion may be partially blended with a ceramic having a dielectric constant equal to or larger than that of the first ceramic portion.

[0024] In this specification, the relative permittivity of the first ceramic part and the second ceramic part is measured at a frequency of 1 MHz using an impedance analyzer (for example, an impedance analyzer 4291A manufactured by Keysight Technologies) in a room temperature and normal humidity environment by sandwiching test pieces taken from the first ceramic part and the second ceramic part between a pair of electrodes. When it is difficult to take test pieces, test pieces made of the same material as the first ceramic part and the second ceramic part may be prepared and used for measurement.

[0025] The first ceramic part and the second ceramic part are preferably bonded via a first amorphous layer. In this case, the bonding layer between the first ceramic part and the second ceramic part can be made extremely thin, thereby reducing the thermal resistance between the first ceramic part and the second ceramic part. In this case, the first ceramic part may have a first altered layer present on the side in contact with the first amorphous layer, and the second ceramic part may have a second altered layer present on the side in contact with the first amorphous layer.

[0026] Furthermore, a third ceramic part may be bonded to the underside of the second ceramic part. In this case, it is also preferable that the second ceramic part and the third ceramic part are bonded via a second amorphous layer. In this case, the second ceramic part may have a third altered layer present on the side in contact with the second amorphous layer, and the third ceramic part may have a fourth altered layer present on the side in contact with the second amorphous layer.

[0027] Although there is no particular limitation on the relative dielectric constant of the third ceramic portion, when an electrode is disposed in the third ceramic portion, it is preferable that the relative dielectric constant of the third ceramic portion be lower than that of the first ceramic portion. For example, the relative dielectric constant of the third ceramic portion may be 10 or less, or may be 7 or more and 10 or less.

[0028] Examples of ceramics constituting the third ceramic portion include alumina, aluminum nitride, and forsterite. The third ceramic portion may contain one type of ceramic or a combination of two or more types of ceramics. The third ceramic portion preferably has a lower dielectric constant than the first ceramic as a whole, but the third ceramic portion may contain a ceramic having a dielectric constant equal to or higher than that of the first ceramic portion.

[0029] In one embodiment, a refrigerant flow path through which a refrigerant flows or a gas flow path for supplying gas to the wafer mounting surface can be provided at a position of the second ceramic part facing the second amorphous layer and / or at a position of the third ceramic part facing the second amorphous layer.

[0030] When the first ceramic part and the second ceramic part are joined via a first amorphous layer, the first amorphous layer preferably contains at least one element constituting the first ceramic part and at least one element constituting the second ceramic part. Similarly, when the second ceramic part and the third ceramic part are joined via a second amorphous layer, the second amorphous layer preferably contains at least one element constituting the second ceramic part and at least one element constituting the third ceramic part.

[0031] When a longitudinal cross section of a semiconductor manufacturing equipment component near the interface between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part) is observed at 4 million times magnification using a transmission electron microscope (TEM), the first amorphous layer (the second amorphous layer) is observed as a thin band-like portion. The first amorphous layer (the second amorphous layer) may be formed as a single layer or as multiple layers (e.g., three layers). The average thickness of the first amorphous layer (the second amorphous layer) is preferably 0.1 nm or more, more preferably 1 nm or more, to increase the bonding strength between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part). Furthermore, the average thickness of the first amorphous layer (the second amorphous layer) is preferably 30 nm or less, more preferably 20 nm or less, to prevent the incorporation of different materials. Therefore, the average thickness of the first amorphous layer (second amorphous layer) is, for example, preferably 0.1 nm or more and 30 nm or less, and more preferably 1 nm or more and 20 nm or less. Note that when the first amorphous layer (second amorphous layer) is composed of multiple layers, the thickness of the first amorphous layer (second amorphous layer) refers to the total thickness of the multiple layers.

[0032] The average thickness of the first amorphous layer (second amorphous layer) at the bonding interface between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part) is measured by TEM observation using the following procedure. On a TEM photograph (magnification: 4,000,000 times) of one field of view in a longitudinal cross section including the bonding interface, the thickness of the first amorphous layer (second amorphous layer) is measured at five locations at 10 nm intervals along the bonding interface, and the average thickness of the first amorphous layer (second amorphous layer) in one field of view is calculated. This thickness measurement by TEM observation is performed evenly across five fields of view, including near the center, near the outer periphery, and near the center of the radius when the semiconductor manufacturing equipment component is viewed in plan. The average thickness of the first amorphous layer (second amorphous layer) in the five fields of view is then taken as the measured value.

[0033] The fact that the thin strip observed by TEM is an amorphous layer can be confirmed by observing, when an X-ray diffraction pattern is obtained by XRD for the thin strip, a broader peak is observed inside the thin strip than in the part of the first ceramic part (second ceramic part) that is sufficiently distant from the bonding interface.

[0034] It can be confirmed by EDS (Energy Dispersive X-ray Spectroscopy) or EPMA (Electron Probe Micro Analyzer) that the first amorphous layer (second amorphous layer) contains at least one element constituting the first ceramic portion and the second ceramic portion (second ceramic portion and third ceramic portion) and at least one element constituting the ceramic plate 70. In a preferred embodiment, the first amorphous layer (second amorphous layer) contains at least one amorphous material (e.g., amorphous zirconia, amorphous aluminum nitride, amorphous alumina, etc.) constituting the first ceramic portion and the second ceramic portion (second ceramic portion and third ceramic portion).

[0035] The first altered layer is present on the side of the first ceramic part that contacts the first amorphous layer, and the second altered layer is present on the side of the second ceramic part that contacts the first amorphous layer. In the TEM photograph described above, they are observed as layered discolored portions adjacent to the above-mentioned thin strip-shaped portion. The thickness of the first and second altered layers is preferably 10 nm or more, more preferably 100 nm or more and 1 μm or less. The presence of the first altered layer (second altered layer) can be confirmed by observing, when an X-ray diffraction pattern is obtained by XRD near the bonding interface, a peak adjacent to the above-mentioned thin strip-shaped portion that is sharper than the first amorphous layer but broader than the portion of the first ceramic part (second ceramic part) sufficiently distant from the bonding interface.

[0036] The third altered layer is present on the side of the second ceramic part that contacts the second amorphous layer, and the fourth altered layer is present on the side of the third ceramic part that contacts the second amorphous layer. In the TEM photograph described above, they are observed as layered discolored portions adjacent to the above-mentioned thin strip-shaped portion. The thickness of the third and fourth altered layers is preferably 10 nm or more, more preferably 100 nm or more and 1 μm or less. The presence of the third altered layer (fourth altered layer) can be confirmed by observing, when an X-ray diffraction pattern is obtained by XRD near the bonding interface, a peak adjacent to the above-mentioned thin strip-shaped portion that is sharper than the second amorphous layer but broader than the portion of the second ceramic part (third ceramic part) sufficiently distant from the bonding interface.

[0037] 1A , a semiconductor manufacturing equipment member 10A includes a ceramic plate 70 having an upper surface 71 with a plurality of protrusions 72 on which a wafer W can be placed and a lower surface 73 located opposite the upper surface 71, a ceramic substrate 20 bonded to the lower surface 73 of the ceramic plate 70, an amorphous layer 80 present at the bonding interface between the ceramic plate 70 and the ceramic substrate 20, and an electrostatic adsorption electrode 26a built into the ceramic plate 70 or the ceramic substrate 20. The semiconductor manufacturing equipment member 10A also includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0038] In embodiment A, the ceramic plate 70 corresponds to the first ceramic portion described above, and the ceramic substrate 20 corresponds to the second ceramic portion described above. The amorphous layer 80 corresponds to the first amorphous layer described above. The ceramic plate 70 has a higher dielectric constant than the ceramic substrate 20, and therefore can obtain a strong electrostatic adsorption force.

[0039] The ceramic substrate 20 includes a central portion 201 having a circular upper surface 21 in a planar view, and an outer peripheral portion 202 having an annular upper surface 27 in a planar view, located around the central portion 201. The central portion 201 of the ceramic substrate 20 may have a diameter of 130 to 450 mm and a thickness of 1 to 5 mm, for example. The height of the protrusions 72 may be 5 to 100 μm, for example. A wafer W can be placed on the upper surface 71 of a ceramic plate 70 bonded to the upper surface 21 of the central portion 201. A focus ring (not shown) can be placed on the upper surface 27 of the outer peripheral portion 202 of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 202 is one step lower than the upper surface 21 of the central portion 201. The lower surfaces 23 of the central portion 201 and the outer peripheral portion 202 may be flush with each other. The illustrated ceramic substrate 20 may have a central portion 201 but no outer peripheral portion 202, that is, no lower upper surface 27.

[0040] The upper surface 71 of the ceramic plate 70 is provided with a plurality of protrusions 72 for mounting a wafer W thereon, with the upper surfaces 71a of the protrusions 72 constituting the wafer mounting surface. The upper surface 71 may also have a seal band 75 formed along its outer edge, in which case the upper surface 71c of the seal band 75 can also constitute the wafer mounting surface. It is preferable that the seal band 75 and the plurality of protrusions 72 are of the same height. As shown in FIG. 3A , in one embodiment, the upper surface 71 of the ceramic plate 70 is formed with an annular seal band 75 along its outer edge, with the plurality of protrusions 72 formed across the entire inner surface of the seal band 75.

[0041] 2A is a schematic enlarged view of the portion enclosed by the bold frame in FIG. 1A, showing a schematic structure of protrusions 72 provided on the upper surface 71 of the ceramic plate 70. The number density per unit area of ​​the protrusions 72 in a plan view is, for example, 1 to 150 pieces / mm 2 and the number of particles per mm can be set to 10 to 150. 2The shape of the protrusions 72 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 72 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 72 is, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 72 refers to the circle-equivalent diameter when the protrusions 72 are viewed in plan. The portion of the upper surface 71 of the ceramic plate 70 on which the seal band 75 and the protrusions 72 are not provided is referred to as the reference surface 71b.

[0042] At least the upper surfaces 71 a of the plurality of protrusions 72 may be coated with a coating film. Similarly, at least the upper surface 71 c of the seal band 75 may be coated with a coating film. Examples of the coating film include a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0043] The electrode 26a is a planar electrode used as an electrostatic chucking electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26a is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26a, the wafer W is electrostatically attracted and fixed to the wafer mounting surface, specifically, the upper surface 71c of the seal band 75 and the upper surface 71a of the protrusions 72. When the DC voltage is removed, the wafer W is released from the wafer mounting surface. The electrode 26a may be embedded in either the ceramic plate 70 or the ceramic substrate 20, but is preferably embedded in a position where the electrode 26a will remain when the semiconductor manufacturing equipment component 10A is remanufactured.

[0044] In addition to the electrode for electrostatic attraction, another electrode 26b may be provided. For example, a heater electrode (resistive heating element) or an RF electrode for plasma generation may be built in. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may have one layer of electrodes built in, or two or more layers of electrodes spaced apart.

[0045] The base plate 30 may be, for example, disk-shaped. The base plate 30 may have an annular flange portion on its lower surface that is used to clamp the semiconductor manufacturing equipment member 10A to a jig inside the chamber. The thickness of the base plate 30 may be 20 to 40 mm, typically 25 to 35 mm. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0046] The base plate 30 may be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include a fluorine-based inert liquid. The refrigerant flow path 32 may be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port of an external refrigerant device (not shown), respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0047] The base plate 30 can be made of, for example, a metal material or a composite material of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also known as SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material for the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, which have a thermal expansion coefficient similar to that of alumina.

[0048] As shown in FIG. 1A , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be formed, for example, by a metal layer made of solder or a metal brazing material. The bonding layer 40 may be formed, for example, by thermal compression bonding (TCB). TCB refers to a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of the metal layer. The resin bonding layer may be formed, for example, by a cured product of a silicone resin adhesive, an epoxy resin adhesive, an acrylic resin adhesive, or a urethane resin adhesive. Furthermore, by directly bonding the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the base plate 30, the bonding layer 40 can be formed of an amorphous layer.

[0049] At least one of the side surface of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered with an insulating film 35. The insulating film 35 may be, for example, a thermally sprayed film of alumina, yttria, or the like.

[0050] The semiconductor manufacturing equipment component 10A may have multiple holes penetrating the ceramic plate 70 and the ceramic substrate 20 in the vertical direction. These holes include multiple gas holes 50 opening in the upper surface 71 and lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see FIG. 3A ). The gas holes 50 communicate with a gas flow path provided inside the base plate 30 and can supply a thermally conductive gas, such as He gas, that has passed through the gas flow path. Typically, the gas holes 50 can be provided so as to open to a portion of the upper surface 71 where the seal band 75 and multiple protrusions 72 are not provided (reference surface 71b). Furthermore, the gas holes 50 are formed at a position that does not overlap with the electrodes 26a and 26b. When a thermally conductive gas is supplied to the gas holes 50, the thermally conductive gas fills the space on the backside of the wafer W placed on the upper surface 71. A plug 55 having a gas flow path may be embedded in the gas hole 50. A plurality of lift pin holes may be provided at equal intervals along concentric circles on the upper surface 71 when the upper surface 71 is viewed in plan.

[0051] 1B-1 and 1B-2, the semiconductor manufacturing equipment member 10B has a two-layer structure of a first ceramic substrate 20a and a second ceramic substrate 20b, whereas the semiconductor manufacturing equipment member 10A has a single-layer ceramic substrate 20. More specifically, the semiconductor manufacturing equipment member 10B includes a first ceramic substrate 20a bonded to a lower surface 73 of a ceramic plate 70, a first amorphous layer 80a present at the bonding interface between the ceramic plate 70 and the first ceramic substrate 20a, an electrostatic chucking electrode 26a built in the ceramic plate 70 or the first ceramic substrate 20a, a second ceramic substrate 20b bonded to a lower surface 23a of the first ceramic substrate 20a, and a second amorphous layer 80b present at the bonding interface between the first ceramic substrate 20a and the second ceramic substrate 20b. The semiconductor manufacturing equipment member 10B also includes a base plate 30 located on the lower surface 23b side of the second ceramic substrate 20b and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded together via a bonding layer 40.

[0052] In embodiment B, the ceramic plate 70 corresponds to the first ceramic portion described above, the first ceramic substrate 20a corresponds to the second ceramic portion described above, and the second ceramic substrate 20b corresponds to the third ceramic portion described above. The first amorphous layer 80a corresponds to the first amorphous layer described above, and the second amorphous layer 80b corresponds to the second amorphous layer described above. The ceramic plate 70 has a higher dielectric constant than the first ceramic substrate 20a, and therefore can obtain a strong electrostatic chucking force.

[0053] In addition, in embodiment B, as shown in FIG. 1B-1 , a refrigerant flow path 28 through which a refrigerant flows may be provided in a position of the first ceramic substrate 20a facing the second amorphous layer 80b and / or a position of the second ceramic substrate 20b facing the second amorphous layer 80b. The refrigerant flow path 28 can be formed, for example, in a single stroke from one end (inlet) to the other end (outlet) across the entire wafer mounting surface in a plan view. A supply port and a recovery port of an external refrigerant device (not shown) can be connected to one end and the other end of the refrigerant flow path 28, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 28 passes through the refrigerant flow path 28, returns from the other end of the refrigerant flow path 28 to the recovery port of the external refrigerant device, and can be temperature-adjusted before being supplied again from the supply port to one end of the refrigerant flow path 28.

[0054] In addition, in embodiment B, as shown in FIG. 1B-2, a gas flow path 29 for supplying gas to the wafer mounting surface may be provided at a position of the first ceramic substrate 20a facing the second amorphous layer 80b and / or at a position of the second ceramic substrate 20b facing the second amorphous layer 80b. The gas flow path 29 may be an annular flow path concentric with the first ceramic substrate 20a in a planar view. In this case, the semiconductor manufacturing equipment member 10B may include a gas inlet path 29a extending from the underside of the base plate 30 to the gas flow path 29, and gas supply paths 29b extending from multiple locations on the gas flow path 29 to gas supply ports 74 provided in the reference surface 71b. The gas (e.g., a thermally conductive gas such as He gas) supplied from the gas inlet path 29a to the gas flow path 29 passes through the gas supply path 29b and fills the space below the wafer W. The filled gas improves thermal conduction between the wafer W and the wafer mounting surface.

[0055] Among the reference numerals shown in FIGS. 1B-1 and 1B-2, the same reference numerals as those in FIGS. 1A and 2A are as described in the description of embodiment A, and therefore, redundant description will be omitted.

[0056] 1C , a semiconductor manufacturing equipment member 10C includes a plurality of protrusions 92 each having an upper surface 92a and a lower surface 92b for supporting a wafer W thereon, a ceramic substrate 20 bonded to the lower surfaces 92b of the plurality of protrusions 92, an amorphous layer 80 present at the bonding interface between the plurality of protrusions 92 and the ceramic substrate 20, and an electrostatic adsorption electrode 26a built into the ceramic substrate 20. The semiconductor manufacturing equipment member 10B also includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0057] In embodiment C, the plurality of protrusions 92 correspond to the first ceramic portion described above, and the ceramic substrate 20 corresponds to the second ceramic portion described above. Furthermore, the amorphous layer 80 corresponds to the first amorphous layer described above. The plurality of protrusions 92 have a higher dielectric constant than the ceramic substrate 20, and therefore can obtain a strong electrostatic adsorption force.

[0058] The ceramic substrate 20 includes a central portion 201 having a circular upper surface 21 in a planar view, and an outer peripheral portion 202 having an annular upper surface 27 in a planar view, located around the periphery of the central portion 201. The central portion 201 of the ceramic substrate 20 may have a diameter of 130 to 450 mm and a thickness of 1 to 5 mm, for example. A wafer W can be placed on the upper surfaces 92a of the plurality of protrusions 92 bonded to the upper surface 21 of the central portion 201. A focus ring (not shown) can be placed on the upper surface 27 of the outer peripheral portion 202 of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 202 is one step lower than the upper surface 21 of the central portion 201. The lower surfaces 23 of the central portion 201 and the outer peripheral portion 202 may be flush with each other. The illustrated ceramic substrate 20 may have the central portion 201 but not the outer peripheral portion 202, i.e., it may not have the one-step lower upper surface 27.

[0059] [Correction pursuant to Rule 91, April 21, 2025] A plurality of protrusions 92 for supporting a wafer W are bonded to the upper surface 21 of the ceramic substrate 20 via an amorphous layer 80, with the upper surfaces 92a of the protrusions 92 (i.e., the upper surface of the first ceramic portion itself) constituting the wafer support surface. A seal band 95 formed along the outer edge of the upper surface 21 may also be bonded via the amorphous layer 80. In this case, the upper surface 95a of the seal band 95 can also constitute the wafer support surface. The seal band 95 and the plurality of protrusions 92 are preferably of the same height. As shown in FIG. 3B , in one embodiment, an annular seal band 95 is bonded to the upper surface 21 of the ceramic substrate 20 along the outer edge, with a plurality of protrusions 92 bonded to the entire inner surface of the seal band 95.

[0060] [Correction based on Rule 91 21.04.2025] Figure 2B is a schematic enlarged partial view of the part surrounded by the bold frame shown in Figure 1C, and shows a schematic structure of the protrusions 92 bonded to the upper surface 21 of the ceramic substrate 20. The number density per unit area of ​​the protrusions 92 in a plan view is, for example, 1 to 150 pieces / mm 2 and the number of particles per mm can be set to 10 to 150. 2 The shape of the protrusions 92 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 92 may be, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 92 may be, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 92 refers to the circle-equivalent diameter when the protrusions 92 are viewed in plan.

[0061] At least the upper surfaces 92 a of the plurality of protrusions 92 may be coated with a coating film. Similarly, at least the upper surface 95 a of the seal band 95 may be coated with a coating film. Examples of the coating film include a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0062] [Amendment based on Rule 91 21.04.2025] Of the reference numerals shown in Figures 1C and 2B, the same reference numerals as those in Figures 1A and 2A have been described in the description of embodiment A, and therefore, redundant description will be omitted.

[0063] 1B-1 and 1B-2, the ceramic substrate 20 may also have a two-layer structure of a first ceramic substrate 20a and a second ceramic substrate 20b. A coolant flow path 28 through which a coolant flows may be provided in a position of the first ceramic substrate 20a facing the second amorphous layer 80b and / or a gas flow path 29 for supplying a gas to the wafer mounting surface may be provided in a position of the second ceramic substrate 20a facing the second amorphous layer 80b and / or a position of the second ceramic substrate 20b facing the second amorphous layer 80b.

[0064] 3. Method of Using a Semiconductor Manufacturing Equipment Component Next, a method of using a semiconductor manufacturing equipment component according to one embodiment of the present invention will be described using the semiconductor manufacturing equipment component 10A as an example. First, the semiconductor manufacturing equipment component 10A is placed in a chamber (not shown). A focus ring is placed on the upper surface 27 of the semiconductor manufacturing equipment component 10A, and a disk-shaped wafer W is placed on the wafer mounting surface, i.e., the upper surface 71a of the protrusion 72 and the upper surface 71c of the seal band 75. The chamber is then depressurized using a vacuum pump to adjust the chamber to a predetermined vacuum level, and a voltage is applied to the electrode 26a to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface.

[0065] Next, a process gas is supplied from a showerhead (not shown) to create a reaction gas atmosphere at a predetermined pressure (several tens to several hundreds of Pa) inside the chamber. In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling of the chamber and the base plate 30, or between the upper electrode and the high-frequency electrode. This generates plasma between the wafer W and the showerhead. The plasma is then used to process the wafer W (by CVD film formation or etching).

[0066] A refrigerant circulates through the refrigerant flow path 32 of the base plate 30. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant flow path 32 via refrigerant piping, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0067] A gas flow path (not shown) is formed inside the base plate 30, and a backside gas can be introduced from a gas cylinder (not shown). A thermally conductive gas (e.g., He gas) can be used as the backside gas. After passing through the gas flow path inside the base plate 30, the backside gas flows out through the gas holes 50 and fills the space on the backside of the wafer W.

[0068] The focus ring also wears out as the wafers W are plasma processed. However, since the focus ring is thicker than the wafers W, the focus ring is replaced after processing a plurality of wafers W.

[0069] The semiconductor manufacturing equipment members 10B and 10C can also be used in a similar manner.

[0070] 4. Manufacturing Method of a Semiconductor Manufacturing Equipment Component Next, a manufacturing method of a semiconductor manufacturing equipment component according to one embodiment of the present invention will be described with reference to FIG. 4, using the semiconductor manufacturing equipment component 10A shown in FIG. 1A as an example. First, a disk-shaped ceramic sintered body 120, which is the basis for the ceramic plate 70, and a disk-shaped ceramic sintered body 121, which is the basis for the ceramic substrate 20, are each produced by hot-press sintering a ceramic powder compact (FIG. 4A). The ceramic sintered body 120 has a higher dielectric constant than the ceramic sintered body 121. The compacts may be produced by stacking multiple tape compacts, by mold casting, or by compressing ceramic powder. The ceramic sintered body 121 incorporates electrodes 26a and 26b.

[0071] Next, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are polished to form flat surfaces. There are no particular limitations on the polishing method, but lapping is preferred, for example. The flat surfaces preferably have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less (e.g., 0.2 to 1 nm) measured with a non-contact surface roughness meter in accordance with ISO 25178.

[0072] For example, a polishing apparatus 60 shown in FIG. 6 can be used for lapping. The polishing apparatus 60 includes a large-diameter disc-shaped polishing table 62 equipped with a polishing pad 64, a small-diameter disc-shaped carrier 66, and a pipe 68 for supplying a slurry containing abrasive grains to the polishing pad 64. The polishing table 62 includes a shaft 67 at the center of its underside, which is rotated by a drive motor (not shown), thereby rotating about its axis (spinning). The carrier 66 includes a shaft 69 at the center of its upper surface, which is rotated by a drive motor (not shown), thereby rotating about its axis (spinning). The carrier 66 is positioned off-center from the center of the polishing table 62.

[0073] To polish the underside of the ceramic sintered body 120 using this polishing apparatus 60, the ceramic sintered body 120 is attached to the underside of the carrier 66, and the ceramic sintered body 120 is sandwiched between the polishing pad 64 of the polishing table 62 and the carrier 66 so that the underside of the ceramic sintered body 120 comes into contact with the polishing pad 64. Then, a slurry containing abrasive grains is supplied from the pipe 68 to the polishing pad 64. This supplies the slurry between the ceramic sintered body 120 and the polishing pad 64 of the polishing table 62. In this state, the polishing table 62 and the carrier 66 are rotated while the carrier 66 presses the ceramic sintered body 120 against the polishing pad 64, thereby performing polishing. A modified layer is formed on the underside of the ceramic sintered body 120 due to polishing.

[0074] The upper surface of the ceramic sintered body 121 can also be lapped in a similar manner. A modified layer is also formed on the upper surface of the ceramic sintered body 121 by the lapping.

[0075] Next, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are subjected to surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are, for example, set to a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. This removes oxides and adsorbed molecules from the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121, and activates these surfaces by forming amorphous layers. Next, while maintaining the high vacuum condition, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are stacked so that their faces face each other, and they are directly bonded while applying pressure, preferably at room temperature. The load applied during pressing can be set to, for example, 0.1 to 50 kN. This results in a ceramic bonded body 122 in which the ceramic sintered body 120 and the ceramic sintered body 121 are bonded via an amorphous layer ( FIG. 4B ). After room temperature bonding, the ceramic bonded body 122 may be heated at about 100° C. for one hour or more in order to increase the bonding strength.

[0076] Next, the plurality of protrusions 72 and the seal band 75 are formed on the upper surface of the ceramic bonded body 122 by laser processing ( FIG. 4C ). The plurality of protrusions 72 and the seal band 75 may be formed after the ceramic bonded body 122 and the base plate 30 are bonded to each other.

[0077] In parallel with this, two MMC disk members 131 and 136 are fabricated ( FIG. 4D ). Then, grooves 132 that will eventually become the coolant flow paths 32 are formed in the lower surface of the upper MMC disk member 131 by machining ( FIG. 4E ). Through-holes 133 for introducing the coolant and through-holes 134 for discharging the coolant are drilled in the lower MMC disk member 136. When the ceramic sintered body 121 that forms the lower layer of the ceramic bonded body 122 is made of alumina, the MMC disk members 131 and 136 are preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is generally the same as that of SiSiCTi or AlSiC.

[0078] The SiSiCTi disk member can be fabricated, for example, as follows: First, silicon carbide, metallic Si, and metallic Ti are mixed to prepare a powder mixture. Next, the resulting powder mixture is uniaxially pressed to prepare a disk-shaped compact, which is then hot-press sintered in an inert atmosphere to obtain the SiSiCTi disk member.

[0079] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disk member 131 and the upper surface of the lower MMC disk member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disk member 131. The ceramic bonded body 122 is then placed on the metal bonding material 137 placed on the upper surface of the upper MMC disk member 131. This results in a laminate 110 in which the lower MMC disk member 136, the metal bonding material 135, the upper MMC disk member 131, the metal bonding material 137, and the ceramic bonded body 122 are stacked in this order from bottom to top ( FIG. 4F ). The laminate 110 is then heated and pressurized (TCB) to obtain a bonded body. The bonded body is formed by bonding the ceramic bonded body 122 to the upper surface of the MMC block 130, which serves as the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disk member 131 and a lower MMC disk member 136 via a metal joining layer. The MMC block 130 has a coolant flow path 32, a coolant inlet 36, and a coolant outlet 38.

[0080] TCB is performed, for example, as follows. That is, the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature. As a result, the metal bonding material becomes a metal bonding layer. As the metal bonding material, an Al-Mg based bonding material or an Al-Si-Mg based bonding material can be used. For example, when TCB is performed using an Al-Si-Mg based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of about 100 μm.

[0081] Next, the outer periphery of the ceramic bonded body 122 is cut to form a step, thereby forming a ceramic substrate 20 having a central portion 201 and an outer periphery 202. In this way, a semiconductor manufacturing equipment member 10A is obtained (FIG. 4G).

[0082] 1 is shown as an integrated product, it may have a structure in which two members are bonded with a metal bonding layer as shown in FIG. 4G , or a structure in which three or more members are bonded with a metal bonding layer. When forming the bonding layer 40 using a metal bonding material 137, the insulating film 35 can be formed on the base plate 30 by thermal spraying either before or after bonding to the ceramic substrate 20. When forming the bonding layer 40 using a resin adhesive sheet, the resin melts, so the insulating film 35 is formed by thermal spraying before bonding to the ceramic bonded body 122.

[0083] The above describes an exemplary method for manufacturing the semiconductor manufacturing equipment component 10A shown in FIG. 1A. When manufacturing the semiconductor manufacturing equipment component 10B shown in FIGS. 1B-1 and 1B-2, instead of the disk-shaped ceramic sintered body 121 that forms the ceramic substrate 20, a disk-shaped first ceramic sintered body that forms the first ceramic substrate 20a and a disk-shaped second ceramic sintered body that forms the second ceramic substrate 20b are prepared. Then, grooves that serve as the refrigerant flow path 28 or the gas flow path 29 are formed in the first ceramic sintered body and / or the second ceramic sintered body by machining, and then the two are directly bonded together using the procedure described above to produce a ceramic bonded body. Furthermore, through holes that serve as the gas supply path 29b can be formed in the ceramic sintered body 120 and the ceramic bonded body by machining. Furthermore, when manufacturing the base plate 30, through holes that serve as the gas introduction passages 29a can be formed in the upper MMC disk member 131 and the lower MMC disk member 136 by machining.

[0084] 1C , instead of the disk-shaped ceramic sintered body 120 that is the base of the ceramic plate 70, multiple protrusion-forming components that are the base of the multiple protrusions 72 are prepared. Then, the two components are directly bonded together using the procedure described above to produce a ceramic bonded body. When the upper surface of the ceramic sintered body 121 and the lower end surfaces of the multiple protrusion-forming components are stacked so that they face each other, a die having multiple holes corresponding to the positions where the multiple protrusion-forming components should be placed is prepared, and the multiple protrusion-forming components are placed in the multiple holes, followed by removing the die and performing room-temperature bonding.

[0085] 5. Method for Regenerating Semiconductor Manufacturing Equipment Components According to one embodiment of the present invention, a method for regenerating semiconductor manufacturing equipment components is provided. Even if the quality of a semiconductor manufacturing equipment component deteriorates due to, for example, shedding of ceramic particles that constitute the protrusions on the wafer mounting surface, by using this regeneration method, the semiconductor manufacturing equipment component can be reused without being discarded. Several examples of the method for regenerating semiconductor manufacturing equipment components according to the present invention will be described with reference to the drawings.

[0086] (5-1. Regeneration Method A) Regeneration method A according to one embodiment of the present invention includes step 1 of processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member according to one embodiment of the present invention to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed, and step 2 of further processing the processed surface to form a new wafer mounting surface.

[0087] 5A , for example, when reclaiming the semiconductor manufacturing equipment component 10A shown in FIG. 1A using the reclaiming method A, first, the upper surface 71 of the ceramic plate 70 is processed to form a processed surface 90 on the ceramic plate 70 from which the wafer mounting surface has been removed (step 1). The processing method is not particularly limited, but examples include grinding and polishing. Other processing methods include blasting. By performing the blasting after masking the reference surface 71b, the multiple protrusions 72 and seal band 75 that constitute the wafer mounting surface can also be selectively removed.

[0088] Next, the processing surface 90 is subjected to laser processing or blast processing to form a plurality of protrusions 72 and a seal band 75 (wafer mounting surface) (step 2). The positions, shapes, and dimensions of the plurality of protrusions 72 and the seal band 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment member 10A before recycling, but may be changed as appropriate. At this time, the processing is performed so that the ceramic plate 70, which has a higher dielectric constant than the ceramic substrate 20, remains.

[0089] Regeneration method A is advantageous in that it is a simple method for regenerating semiconductor manufacturing equipment components. It also has the advantage of being able to completely maintain the material properties before and after regeneration. However, the thickness of the ceramic plate 70 after regeneration is thinner than that before regeneration. Therefore, there is a limit to the number of times it can be regenerated.

[0090] (5-2. Regeneration Method B) Regeneration method B according to one embodiment of the present invention includes step 1 of processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member according to one embodiment of the present invention to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed, and step 2 of directly bonding a regeneration ceramic part having a higher dielectric constant than the second ceramic part to the processed surface.

[0091] 5B , for example, when reclaiming the semiconductor manufacturing equipment component 10A shown in FIG. 1A using the reclaiming method B, first, the upper surface 71 of the ceramic plate 70 is processed to form a processed surface 90 on the ceramic plate 70 from which the wafer mounting surface has been removed (step 1). The processing method is not particularly limited, but examples include grinding or polishing. Other processing methods include blasting and laser processing. By performing the blasting process after masking the reference surface 71b, the multiple protrusions 72 and seal band 75 that constitute the wafer mounting surface can also be selectively removed.

[0092] Next, the processed surface 90 of the ceramic plate 70 is directly bonded (preferably by room-temperature bonding) to the underside of the recycled ceramic plate 79 (Step 2). The direct bonding method is as described above. There is no problem as long as the recycled ceramic plate 79 has a higher dielectric constant than the ceramic substrate 20. However, in order to reproduce the performance of the semiconductor manufacturing equipment member 10A, it is preferable that the recycled ceramic plate 79 be made of the same material as the ceramic plate 70.

[0093] Prior to direct bonding, it is preferable to polish the processed surface 90 of the ceramic plate 70 and the underside of the ceramic plate for recycling 79. There are no particular limitations on the polishing method, but lapping is preferred, for example. It is preferable that the processed surface 90 of the ceramic plate 70 and the underside of the ceramic plate for recycling 79 have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less (e.g., 0.2 to 1 nm) measured with a non-contact surface roughness meter in accordance with ISO 25178.

[0094] Before or after direct bonding, a plurality of protrusions 72 and a seal band 75 (wafer mounting surface) can be formed by laser processing on the upper surface of the recycled ceramic plate 79. The positions, shapes, and dimensions of the plurality of protrusions 72 and the seal band 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment member 10A before recycling, but may be changed as appropriate.

[0095] According to the regeneration method B, the regenerated ceramic plate 79 can be used with a desired thickness, so that the total thickness of the ceramic plate 70 and the regenerated ceramic plate 79 in the semiconductor manufacturing equipment member 10A after regeneration can be made to match the thickness of the ceramic plate 70 before regeneration. Therefore, there is no particular limit to the number of times the regeneration can be performed.

[0096] (5-3. Regeneration Method C) Regeneration method C according to one embodiment of the present invention includes step 1 of processing the first ceramic part of the semiconductor manufacturing equipment member according to one embodiment of the present invention, removing it so as to expose the second ceramic part, and forming a processed surface on the second ceramic part, and step 2 of directly bonding a regeneration ceramic part having a higher dielectric constant than the second ceramic part to the processed surface of the second ceramic part.

[0097] 5C, for example, when the semiconductor manufacturing equipment component 10A shown in FIG. 1A is regenerated by the regeneration method C, the ceramic plate 70 is first processed and removed to expose the ceramic substrate 20. This forms a processed surface 90 on the ceramic substrate 20 (step 1). There are no particular limitations on the processing method, but examples include grinding or polishing. Other processing methods include blasting and laser processing. Note that, since removing the electrode 26a in step 1 requires a step of embedding the electrode 26a again, it is preferable to leave the electrode 26a in place.

[0098] Next, the processed surface 90 of the ceramic substrate 20 is directly bonded (preferably by room-temperature bonding) to the underside of the recycling ceramic plate 79 (Step 2). The direct bonding method is as described above. There is no problem if the recycling ceramic plate 79 has a higher dielectric constant than the ceramic substrate 20. However, in order to reproduce the performance of the semiconductor manufacturing equipment member 10A, it is preferable that the recycling ceramic plate 79 be made of the same material as the ceramic plate 70.

[0099] Prior to direct bonding, it is preferable to polish the processed surface 90 of the ceramic substrate 20 and the underside of the ceramic plate 79 for recycling. There are no particular limitations on the polishing method, but lapping is preferred, for example. It is preferable that the processed surface 90 of the ceramic plate 70 and the underside of the ceramic plate 79 for recycling have a surface roughness (arithmetic mean roughness) Ra of 1 nm (e.g., 0.2 to 1 nm) or less as measured with a non-contact surface roughness meter in accordance with ISO 25178.

[0100] Before or after direct bonding, a plurality of protrusions 72 and a seal band 75 (wafer mounting surface) can be formed by laser processing on the upper surface of the recycled ceramic plate 79. The positions, shapes, and dimensions of the plurality of protrusions 72 and the seal band 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment member 10A before recycling, but may be changed as appropriate.

[0101] According to regeneration method C, the ceramic plate 70 is completely removed from the semiconductor manufacturing equipment component 10A before regeneration, so the ceramic plate 79 to be regenerated does not need to be selected taking into consideration the material of the ceramic plate 70 in the semiconductor manufacturing equipment component 10A before regeneration. This allows for a wider range of options for the ceramic plate 79 to be regenerated. Therefore, regeneration method C is advantageous when a semiconductor manufacturing equipment component with different performance than the semiconductor manufacturing equipment component 10A before regeneration is desired.

[0102] Below, experimental data is presented to demonstrate the superiority of the bonding strength of the amorphous layer.

[0103] (Experimental Example 1: Formation of AD film) A plate (20 mm × 20 mm × 5 mm) made of SiSiCTi, a type of MMC, was prepared. An aerosol deposition film (AD film) was formed on the entire upper surface of the plate by aerosol deposition using an alumina powder raw material (purity 99.9%). Next, the plate was cut in the thickness direction along a cutting line passing near the center of the upper surface of the plate to expose the longitudinal cross section. The thickness of the AD film was measured at 3000x magnification using a scanning electron microscope (SEM), and was found to be approximately 3 μm.

[0104] (Experimental Example 2: Formation of a Thermal Sprayed Film) A plate made of the same SiSiCTi material as in Experimental Example 1 was prepared. A thermal sprayed film was formed on the entire upper surface of the plate by thermal spraying using an alumina powder raw material (purity 99.9%). Next, the plate was cut in the thickness direction along a cutting line passing through the vicinity of the center of the upper surface of the plate to expose a longitudinal cross section, which was observed at 500x magnification using a scanning electron microscope (SEM). The thickness of the thermal sprayed film was measured to be approximately 50 μm.

[0105] (Experimental Example 3: Formation of Amorphous Layer) Two dense alumina plates with a diameter of 10 mm, a thickness of 1 mm, and a purity of 99.9% or higher were prepared. Next, both dense alumina plates were polished using a polishing device to a surface roughness Ra of 0.7 μm or less. Next, each polished surface was irradiated with an Ar beam (FAB) under high vacuum. The two plates were then overlapped with their polished surfaces facing each other and bonded under pressure to obtain a bonded structure. The plates were cut in the thickness direction along a cutting line passing near the center of the top surface of the bonded structure to expose the longitudinal cross section. The cross section was observed under a transmission electron microscope (TEM) at 4,000,000 magnification, and the thickness of the amorphous layer was measured to be approximately 5 nm.

[0106] (Tensile Test) The tip of a stud pin (φ2.7 mm, length 15 mm) was fixed with adhesive to the top surface of each of the AD film-coated plate, thermal spray film-coated plate, and pair of plates bonded by an amorphous layer produced in Experimental Examples 1, 2, and 3. The stud pin was then pulled perpendicular to the top surface of the plate (vertically upward) using a tensile testing device (manufactured by Shimadzu Corporation) to remove it from the plate. As a result, the stud pin came off in the plates of Experimental Examples 1 and 2 at a tensile stress of about 60 MPa. After the tensile test, visual inspection of the fracture site revealed that in both Experimental Examples 1 and 2, fracture did not occur at the interface between the stud pin and the adhesive, but rather occurred within the film.

[0107] On the other hand, the stud pin came off the plate in Experimental Example 3 when a tensile stress of around 70 MPa was applied. After the tensile test, the fracture location was visually inspected and it was found to have occurred at the interface between the stud pin and the adhesive. Since the amorphous layer did not fracture even when a tensile stress higher than the film strength of the AD film and the thermal spray film was applied, it was confirmed that the bonding strength via the amorphous layer is higher than that of the AD film and the thermal spray film.

[0108] DESCRIPTION OF SYMBOLS 10A: Semiconductor manufacturing equipment member 10B: Semiconductor manufacturing equipment member 10C: Semiconductor manufacturing equipment member 20: Ceramic substrate 20a: First ceramic substrate 20b: Second ceramic substrate 21: Upper surface 23: Lower surface 23a: Lower surface 23b: Lower surface 26a: Electrode 26b: Electrode 27: Upper surface 28: Coolant flow path 29: Gas flow path 29a: Gas inlet path 29b: Gas supply path 30: Base plate 31: Upper surface 32: Coolant flow path 35: Insulating film 36: Coolant inlet portion 38: Coolant outlet portion 40: Bonding layer 50: Gas hole 55: Plug 60: Polishing device 62: Polishing surface plate 64: Polishing pad 66: Carrier 67: Shaft 68 : Pipe 69 : Shaft 70 : Ceramic plate 71 : Upper surface 71a : Upper surface 71b : Reference surface 71c : Upper surface 72 : Projection 73 : Lower surface 74 : Gas supply port 75 : Seal band 79 : Reclaimed ceramic plate 80 : Amorphous layer 80a : First amorphous layer 80b : Second amorphous layer 90 : Processing surface 92 : Projection 92a : Upper surface 92b : Lower surface 95 : Seal band 95a : Upper surface 110 : Laminated body 120 : Sintered ceramic body 121 : Sintered ceramic body 122 : Ceramic bonded body 130 : MMC block 131 : Disk member 132 : Groove 133 : Through hole 134 : Through hole 135: Metal bonding material 136: Disc member 137: Metal bonding material 201: Center portion 202: Outer peripheral portion

Claims

1. A component for semiconductor manufacturing equipment, comprising: a first ceramic part having an upper surface with a wafer mounting surface and a lower surface located opposite the upper surface; a second ceramic part bonded to the lower surface of the first ceramic part; a first amorphous layer present at the bonding interface between the first ceramic part and the second ceramic part; and an electrostatic chucking electrode disposed in the first ceramic part, the second ceramic part, or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a higher dielectric constant than the second ceramic part.

2. A semiconductor manufacturing equipment member according to claim 1, wherein the first ceramic portion has a relative dielectric constant of greater than 10.

3. A semiconductor manufacturing equipment member according to claim 1 or 2, wherein the electrode is embedded in the second ceramic portion.

4. A semiconductor manufacturing equipment member according to claim 1 or 2, wherein the first ceramic part is a plate having a plurality of protrusions on the upper surface thereof, the protrusions having the wafer mounting surface.

5. A semiconductor manufacturing equipment member according to claim 1 or 2, wherein the upper surface of the first ceramic portion itself is a plurality of protrusions that constitute the wafer-mounting surface.

6. A semiconductor manufacturing equipment component according to claim 1 or 2, comprising: a first deteriorated layer present on the side of said first ceramic part that contacts said first amorphous layer; and a second deteriorated layer present on the side of said second ceramic part that contacts said first amorphous layer.

7. A semiconductor manufacturing equipment component according to claim 1 or 2, comprising: a third ceramic part bonded to the underside of the second ceramic part; and a second amorphous layer present at the bonding interface between the second ceramic part and the third ceramic part.

8. A semiconductor manufacturing equipment component according to claim 7, wherein a refrigerant flow path through which a refrigerant circulates or a gas flow path for supplying gas to the wafer mounting surface is provided at a position of the second ceramic part facing the second amorphous layer and / or at a position of the third ceramic part facing the second amorphous layer.

9. A semiconductor manufacturing equipment component according to claim 7, comprising: a third altered layer present on the side of said second ceramic part that contacts said second amorphous layer; and a fourth altered layer present on the side of said third ceramic part that contacts said second amorphous layer.

10. A method for recycling a semiconductor manufacturing equipment component, comprising the steps of: processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment component described in claim 1 to form a processed surface on the first ceramic part from which the wafer-mounting surface has been removed; and further processing the processed surface to form a new wafer-mounting surface.

11. A method for recycling a semiconductor manufacturing equipment component, comprising the steps of: processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment component described in claim 1 to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; and directly bonding a recycling ceramic part having a higher dielectric constant than the second ceramic part to the processed surface.

12. A method for recycling a semiconductor manufacturing equipment component, comprising the steps of: processing the first ceramic part of the semiconductor manufacturing equipment component described in claim 1, removing it so as to expose the second ceramic part, and forming a processed surface on the second ceramic part; and directly bonding a recycling ceramic part having a higher dielectric constant than the second ceramic part to the processed surface of the second ceramic part.

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