Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a first insulating layer including an upper surface and a lower surface; and a circuit pattern disposed on the upper surface of the first insulating layer, wherein the circuit pattern includes a first region in which the width gradually increases from the upper surface toward the lower surface, and a second region in which the width gradually decreases from the first region toward the lower surface of the circuit pattern.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices like servers and PCs have led to larger package sizes. Furthermore, as the number of functions required from processors increases, there is a growing need for separate processor chips for each function, along with circuit boards for mounting and interconnecting these processor chips. Furthermore, even when the processor is split into two processor chips for each function, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] Recently, due to factors such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal capacity. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. Increased circuit board area and thickness make it difficult to miniaturize products, and can lead to issues such as increased reliability, yield, and product price due to circuit board warpage. Furthermore, miniaturization of circuit patterns is required to align the pitch between processor chips and circuit boards for interconnection. In other words, increasing circuit pattern density is more advantageous than increasing circuit board area and thickness in terms of product price, reliability (warpage), and product characteristics. Therefore, miniaturization of circuit patterns and through-hole electrodes is required.

[0006] Additionally, there is a difficulty in reducing reliability due to reduced bonding strength resulting from forming fine line widths or small circuit patterns.

[0007] In addition, when forming a fine pattern, there is a problem that a thick core layer is required or it is difficult to form a structure in which the fine pattern layer is laminated on multiple insulating layers.

[0008] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, which improve bonding strength by increasing the contact area between the circuit pattern and the insulating layer through the shape of the circuit pattern.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved heat dissipation effect and support capacity through a filler located under a protrusion of a circuit pattern.

[0010] The embodiment forms the via electrodes of a first insulating layer in which the direction of increase in the width of the via electrode changes and a second insulating layer (or a third insulating layer) adjacent thereto so that the thicknesses of the via electrodes are different, thereby providing a circuit board having an improved input / output count and a semiconductor package including the same, by having a structure in which a pattern portion, which is a micro-pattern, is laminated on a plurality of insulating layers.

[0011] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which facilitates formation of a micropattern by positioning the first pattern portion and the third pattern portion, which are micropatterns, out of alignment with the first via of the first insulating layer.

[0012] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which the formation of a via electrode is easily achieved by controlling the thickness of the first insulating layer and miniaturization is easily achieved.

[0013] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0014] A circuit board according to an embodiment of the present invention includes a first insulating layer including an upper surface and a lower surface; a circuit pattern disposed on an upper surface of the first insulating layer, wherein the circuit pattern includes a first region whose width gradually increases from the upper surface toward the lower surface, and a second region whose width gradually decreases from the first region toward the lower surface of the circuit pattern.

[0015] The width of the circuit pattern may be a maximum width at the boundary between the first region and the second region.

[0016] The thickness of the second region may be greater than the thickness of the first region.

[0017] The second angle formed by the bottom surface and the side surface of the circuit pattern in the second region may be different from the first angle formed by the top surface and the side surface of the circuit pattern in the first region.

[0018] The first angle may be greater than the second angle.

[0019] The area of ​​the upper surface of the circuit pattern may be different from the area of ​​the lower surface of the circuit pattern.

[0020] The area of ​​the upper surface of the circuit pattern may be larger than the area of ​​the lower surface of the circuit pattern.

[0021] The upper surface of the circuit pattern may not overlap at least partially with the lower surface of the circuit pattern.

[0022] The bottom surface of the circuit pattern may not overlap at least partially with the top surface of the circuit pattern.

[0023] It may include a second insulating layer disposed on the first insulating layer.

[0024] The second insulating layer may surround at least a portion of the circuit pattern.

[0025] The second insulating layer may include a first portion that overlaps the second region of the circuit pattern in a vertical direction, and a second portion that is misaligned with the second region of the circuit pattern in a vertical direction.

[0026] The second insulating layer may include a plurality of fillers.

[0027] The plurality of fillers may have a thickness in the first portion and a diameter smaller than the thickness in the second portion.

[0028] The average diameter of the filler arranged in the first portion may be smaller than the average diameter of the filler arranged in the second portion.

[0029] The above circuit pattern may include a first circuit pattern and a second circuit pattern that are arranged adjacently.

[0030] The gap between the upper surface of the first circuit pattern and the upper surface of the second circuit pattern may be 1.5 to 2 um.

[0031] The thickness from the bottom surface to the edge in the above first circuit pattern may be different from the thickness from the bottom surface to the edge in the above second circuit pattern.

[0032] The distance between the bottom surface of the first circuit pattern and the bottom surface of the second circuit pattern may be smaller than the distance between the contact portion of the first circuit pattern and the contact portion of the second circuit pattern.

[0033] A circuit board according to an embodiment includes a first insulating layer; a circuit pattern disposed on the first insulating layer; and a second insulating layer covering the circuit pattern on the first insulating layer, wherein the circuit pattern has a protrusion extending outwardly, and the second insulating layer includes a first portion located between the protrusion and the first insulating layer and a second portion other than the first portion, wherein an average diameter of a filler disposed in the first portion of the second insulating layer is smaller than an average diameter of a filler disposed in the second portion.

[0034] A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a first electrode layer disposed between an upper surface of the first insulating layer and an upper surface of the second insulating layer; a second electrode layer disposed on an upper surface of the second insulating layer; a first via electrode penetrating an upper surface and a lower surface of the first insulating layer; and a second via electrode disposed between the first electrode layer and the second electrode layer, wherein a ratio of a thickness of the second insulating layer to a thickness of the first insulating layer is 1:0.8 to 1:1.2, and vertical thicknesses of the first via electrode and the second via electrode are different from each other.

[0035] The width of the first via electrode may gradually increase from the upper surface to the lower surface of the first insulating layer, and the width of the second via electrode may gradually decrease from the upper surface to the lower surface of the second insulating layer.

[0036] The first electrode layer includes a first pattern portion, the second electrode layer includes a second pattern portion, and the first pattern portion and the second pattern portion can have a line width of 5 μm or less.

[0037] The above first via electrode may not vertically overlap the first pattern portion and the second pattern portion between the first pattern portion and the second pattern portion.

[0038] A third insulating layer is disposed on the lower surface of the first insulating layer; and the first insulating layer, the second insulating layer, and the third insulating layer may be made of the same material.

[0039] A third insulating layer disposed on the lower surface of the first insulating layer; wherein the second insulating layer and the third insulating layer are made of a photocurable resin, and the first insulating layer may be made of a thermocurable resin.

[0040] The first electrode layer includes a first via land disposed on an upper surface of the first insulating layer, and the first via land may have a width greater than that of the first pattern portion.

[0041] It may include a semiconductor element connected to the first pattern portion or the second pattern portion on the second insulating layer.

[0042] A third insulating layer disposed on a lower surface of the first insulating layer; a third electrode layer disposed between a lower surface of the first insulating layer and a lower surface of the third insulating layer; wherein the third electrode layer includes a third pattern portion; and the first pattern portion and the third pattern portion may be horizontally misaligned with respect to the first via electrode.

[0043] A third insulating layer disposed on a lower surface of a first insulating layer; a third electrode layer disposed between a lower surface of the first insulating layer and a lower surface of the third insulating layer; a fourth electrode layer disposed on a lower surface of the third insulating layer; and a third via electrode between the third electrode layer and the fourth electrode layer; further comprising: a width of the third via electrode gradually increasing from the upper surface toward the lower surface of the first insulating layer, and a width of the second via electrode gradually decreasing from the upper surface toward the lower surface of the second insulating layer.

[0044] The third electrode layer includes a third pattern portion; the fourth electrode layer includes a fourth pattern portion; and the first pattern portion, the second pattern portion, the third pattern portion, and the fourth pattern portion can be vertically overlapped.

[0045] The thickness of the first via electrode may be greater than the thickness of the second via electrode.

[0046] The minimum width of the first via electrode may be smaller than the minimum width of the second via electrode.

[0047] The first electrode layer may include a first via land connected to the first via electrode and disposed between the upper surface of the second insulating layer and the upper surface of the first insulating layer.

[0048] A third insulating layer disposed on a lower surface of a first insulating layer; a third electrode layer disposed between a lower surface of the first insulating layer and a lower surface of the third insulating layer; the second electrode layer may include a second via land disposed on an upper surface of the second insulating layer; and the third electrode layer may include a third via land disposed between a lower surface of the first insulating layer and a lower surface of the third insulating layer.

[0049] The upper surface of the first via electrode and the lower surface of the second via electrode can overlap each other in a vertical direction.

[0050] The bottom surface of the second via electrode may include an overlapping portion that vertically overlaps the top surface of the first via electrode and a non-overlapping portion that does not vertically overlap.

[0051] A circuit board and a semiconductor package including the same are implemented to improve bonding strength by increasing the contact area between the circuit pattern and the insulating layer through the shape of the circuit pattern of the present invention.

[0052] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved heat dissipation effect and support capacity through a filler located under a protrusion of a circuit pattern.

[0053] The embodiment forms the via electrodes of the first insulating layer and the second insulating layer (or third insulating layer) adjacent thereto so that the thicknesses of the via electrodes are different, thereby having a structure in which a pattern portion, which is a micro-pattern, is laminated on a plurality of insulating layers, thereby enabling implementation of a circuit board with improved input / output counts and a semiconductor package including the same.

[0054] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which are easy to form a micropattern, by having the first pattern portion and the third pattern portion, which are micropatterns, arranged out of alignment with the first via of the first insulating layer.

[0055] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, in which the formation of a via electrode is easily achieved by controlling the thickness of the first insulating layer and miniaturization is easily implemented.

[0056] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0057] Figure 1 is a drawing showing a cross-sectional view of a circuit board according to the first embodiment,

[0058] Figure 2 is a perspective view of the circuit pattern in Figure 1,

[0059] Figure 3 is an enlarged view of part K in Figure 1,

[0060] Figure 4 is another example of Figure 3,

[0061] FIG. 5a is a drawing showing another example of a circuit pattern of a circuit board according to the first embodiment;

[0062] Fig. 5b is a photograph of a circuit pattern of a circuit board according to the first embodiment;

[0063] FIGS. 6 to 9 are drawings explaining a method for manufacturing a circuit board according to the first embodiment of the present invention.

[0064] Fig. 10 is a schematic diagram of a circuit board according to another embodiment;

[0065] FIG. 11 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0066] Figure 12 is an enlarged view of K1 in Figure 1,

[0067] Figure 13 is a plan view schematically showing the surface of the first insulating layer,

[0068] Figure 14 is a plan view schematically showing the surface of the second insulating layer,

[0069] Figure 15 is an enlarged view of K2 in Figure 1,

[0070] Fig. 16 is an enlarged view of K3 in Fig. 1,

[0071] Figure 17 is an enlarged view of K4 in Figure 1,

[0072] FIG. 18 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0073] Figure 19 is an enlarged view of K5 in Figure 18,

[0074] FIG. 20 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention.

[0075] Figure 21 is an enlarged view of K6 in Figure 20,

[0076] Figures 22a to 22e are drawings illustrating a method for manufacturing a circuit board according to the second embodiment.

[0077] FIG. 23 is a drawing of a circuit board and a laminated semiconductor element according to a second embodiment of the present invention.

[0078] Fig. 24 is a drawing illustrating the arrangement of semiconductor elements on a circuit board according to the second embodiment.

[0079] Fig. 25 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0080] Fig. 26 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0081] Fig. 27 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0082] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0083] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0084] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0085] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Furthermore, when a component is referred to as being disposed "on" or "under" another component, it should be understood that it may be directly connected to that other component, or that there may be other components in between.

[0086] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0087] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0088] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0089] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0090] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0091] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0092] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0093] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0094] FIG. 1 is a cross-sectional view of a circuit board according to the first embodiment, FIG. 2 is a perspective view of a circuit pattern in FIG. 1, FIG. 3 is an enlarged view of a portion K in FIG. 1, FIG. 4 is another example of FIG. 3, FIG. 5a is a view showing another example of a circuit pattern of a circuit board according to the first embodiment, and FIG. 5b is a photograph of a circuit pattern of a circuit board according to the first embodiment.

[0095] Referring to FIG. 1, a circuit board (100) according to the first embodiment may include a build-up structure (110) and an electrode portion (120). In the following embodiments of the present invention, the build-up structure (110) may be provided with a structure in which a plurality of insulating layers are laminated. The wiring or electrode portion (120) may be disposed by being embedded in each insulating layer of the build-up structure (110), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. Such a circuit board may be divided into an outer laminated region and an inner laminated region, and the inner laminated region may correspond to a core layer. When the circuit board includes a core layer, the outer laminated region disposed above the core layer may be referred to as an upper build-up layer, and the outer laminated region disposed below the core layer may be referred to as a lower build-up layer. As described above, the upper build-up layer and / or the lower build-up layer may be provided by laminating a plurality of insulating layers.

[0096] As an example, the build-up structure (110) may be formed of a plurality of insulating layers laminated between the upper surface of the upper build-up layer and the lower surface of the lower build-up layer. For example, the build-up structure (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (112'). Additionally, a protective layer (not shown) may be disposed on the build-up structure (110).

[0097] The build-up structure (110) of the circuit board (100) may be rigid or flexible. For example, the build-up structure (110) of the circuit board (100) may include glass or plastic. For example, the build-up structure (110) of the circuit board or each insulating layer forming the build-up structure (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the build-up structure (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the build-up structure (110) of the circuit board may include sapphire. For example, the build-up structure (110) of the circuit board may include an optically isotropic film. For example, the build-up structure (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the build-up structure (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the build-up structure (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a silver thermosetting resin or a thermoplastic resin.

[0098] The build-up structure (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0099] In one embodiment, the build-up structure (110) may include a core layer including a reinforcing member. Here, the core layer may mean an insulating layer including the reinforcing member and having a thickness exceeding 30 μm in the vertical direction (X-axis direction or lamination direction) thereof. In addition, the upper build-up layer (112) and the lower build-up layer (112') may include a plurality of layers that are respectively disposed above and below the core layer and do not include a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. Hereinafter, the description will be made based on the upper build-up layer (112). In addition, when the upper build-up layer in the drawing includes only a 'first insulating layer', the upper build-up layer may be used interchangeably with the first insulating layer (112).

[0100] The reinforcing member may refer to a glass fiber material extending along the horizontal direction (Y-axis direction) of the insulation layer, and may have a different meaning from the spaced-apart fillers.

[0101] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0102] And the upper build-up layer (112) or the lower build-up layer (112') can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin can be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and can include an inorganic filler such as silica. When the insulating resin is used as a core, it can include a reinforcing material provided with glass fiber or aramid fiber. For example, when manufacturing a build-up structure (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the build-up structure (110) can be provided by laminating ABF without a core layer.

[0103] A protective layer (not shown) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining a semiconductor element and / or a main board and a circuit board, the protective layer (not shown) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material that has insulating properties for electrical connection. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (not shown) may have at least one opening for connection between a terminal of a semiconductor element and a pad of a circuit board.

[0104] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and includes a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode portion' or an 'electrode', an 'electrode pattern', or a 'pattern'. In the embodiment, the electrode portion (120) may include a pad, a first pattern, a second pattern, and a via electrode.

[0105] In the electrode portion (120), the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor element, and is arranged within each insulating layer of the laminated build-up structure (110).

[0106] In the electrode section (120), a via electrode (121a) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer. That is, the insulating layer may include a via hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for optimization of impedance or heat dissipation, but is not limited thereto and may be freely designed.

[0107] In the electrode portion (120), pads (121b) may be arranged on each insulating layer. And the pads (121b) may be electrically connected to circuit patterns. In addition, the pads (121b) may be connected to each via electrode (121a). And the pads (121b) arranged on the upper and lower surfaces of the build-up structure (110) may be electrically connected to semiconductor elements and / or main boards or substrates.

[0108] According to an embodiment, the circuit pattern of the electrode portion (120) may include a circuit pattern (122) having a fine pitch (or used in combination with the first pattern (122)) and a second pattern (not shown) having a pitch larger than the circuit pattern (122). Referring to FIG. 1, the circuit pattern (122) and the second pattern (not shown) may be arranged on the upper build-up layer (112). The second pattern (not shown) represents a circuit pattern connected to the first pad (121b). Although not shown, the width of the second pattern (not shown) in the horizontal direction (Y-axis direction) is larger than the width of the circuit pattern (122) in the horizontal direction (Y-axis direction). The second pattern (not shown) may refer to a pattern having the same width and spacing as a pattern used in a conventional circuit board, and the circuit pattern (122) refers to a microcircuit pattern having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor elements, impedance matching, or formation of an inductor. For example, the line width and spacing (LXS, Line and Space) of the circuit pattern (122) may be 5 ㎛ X 5 ㎛ or less.

[0109] In particular, the pads arranged on the outermost side of the build-up structure (110) among the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0110] And the pads arranged on the inside have the function of connecting the via electrodes and the circuit patterns. When the via electrodes are arranged with a wider width than the circuit patterns, pads having a wider width than the circuit patterns are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0111] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating the circuit board into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package board and the fine pattern size of the terminals of the semiconductor devices.

[0112] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0113] In this embodiment, the core layer (111) may be arranged at the center in the vertical direction of the build-up structure (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be positioned at the center of the build-up structure (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (112') may be positioned below the core layer (111).

[0114] Referring further to FIGS. 2 and 3, the upper build-up layer (112) according to the embodiment may include an upper surface and a lower surface. According to the embodiment, the upper surface of the upper build-up layer (112) may directly contact the lower surface (BS) of the circuit pattern (122). In addition, the lower surface of the upper build-up layer (112) may directly contact the upper surface of the core layer.

[0115] Additionally, the circuit pattern (122) may be located on the upper build-up layer (112). The circuit pattern (122) may include a first region (AR1) and a second region (AR2).

[0116] In an embodiment, the circuit pattern (122) may be divided into a first region (AR1) and a second region (AR2) according to the direction of increase or decrease in the width (W). The first region (AR1) may be a region in which the width gradually increases from the upper surface (US) of the circuit pattern (122) toward the lower surface (BS). And the second region (AR2) may be a region other than the first region (AR1). In addition, the second region (AR2) may be a region in which the width gradually decreases from the first region (AR1) toward the lower surface (BS) of the circuit pattern (122).

[0117] And the width (W) of the circuit pattern (122) in the first region (AR1) may be different at the upper surface (US) of the circuit pattern (122) and the lower surface (BS) of the first region (AR1). In an embodiment, the circuit pattern (122) may have a width (W) at the boundary (BP) of the first region (AR1) and the second region (AR2). m ) can be the maximum. That is, the width of the circuit pattern (122) can be the maximum width at the boundary (BP).

[0118] As an example, the maximum width (W) in the circuit pattern (122) m ) may be greater than the width (Wu) of the circuit pattern (122) on the upper surface (US) in the first region (AR1). The width (W) of the circuit pattern in the first region (AR1) may decrease from the maximum width toward the upper surface (US).

[0119] Additionally, the maximum width (W) in the circuit pattern (122) m ) is the width (W) of the circuit pattern (122) on the lower surface (BS) in the second region (AR2). B ) can be greater than the maximum width (W) of the boundary (BP) in the second region (AR2). The width (W2) of the circuit pattern in the second region (AR2) is greater than the maximum width (W) of the boundary (BP). m ) can decrease as it moves towards BS.

[0120] In addition, as an embodiment, the circuit pattern (122) may include a side surface (SS) positioned between the upper surface (US) and the lower surface or bottom surface (BS). The side surface (SS) may be partitioned based on the boundary (BP). The side surface (SS) may include a first side surface (SS1) and a second side surface (SS2). The first side surface (SS1) may be a side surface of the circuit pattern (122) in the first region (AR1). The second side surface (SS2) may be a side surface of the circuit pattern (122) in the second region (AR2).

[0121] As an example, in the circuit pattern (122), the upper surface (US) and the lower surface (BS) may have different angles with respect to the contacting side surface (SS).

[0122] In the second region (AR2), the second angle (θ2) formed by the bottom surface (BS) and the second side surface (SS2) of the circuit pattern (122) may be different from the first angle (θ1) formed by the top surface (US) and the first side surface (SS1) of the circuit pattern (122) in the first region (AR1).

[0123] The width (Wu) on the upper surface (US) of the circuit pattern (122) is greater than the width (W) on the lower surface (BS) of the circuit pattern (122). B ) can be greater than the first angle (θ1). That is, the first angle (θ1) can be greater than the second angle (θ2).

[0124] Additionally, the area (S1) of the upper surface (US) of the circuit pattern (122) may be different from the area (S2) of the lower surface (BS). For example, the area (S1) of the upper surface (US) of the circuit pattern (122) may be larger than the area (S2) of the lower surface (BS).

[0125] By this configuration, the width (Wu) of the upper surface of the circuit pattern (122) can be formed smaller than the length in the vertical direction (X-axis direction) of the circuit pattern (122). This allows the spacing between adjacent circuit patterns (122) to be reduced. Accordingly, the line width and spacing of the circuit pattern in the electrode section can be made finer.

[0126] In an embodiment, the upper surface (US) of the circuit pattern (122) may not overlap at least partially with the lower surface (BS) of the circuit pattern (122) in the vertical direction (X-axis direction). In addition, the lower surface (BS) of the circuit pattern (122) may not overlap at least partially with the upper surface (US) of the circuit pattern (122).

[0127] The width (WU) on the upper surface (US) of the circuit pattern (122) is the width (W) on the lower surface (BS) of the circuit pattern (122). B ) may be greater than the width (WU) on the upper surface (US) of the circuit pattern (122). Or, the width (W) on the lower surface (BS) of the circuit pattern (122) may be greater than the width (W) on the lower surface (BS) of the circuit pattern (122). B ) may be less than.

[0128] In the embodiment, by arranging the boundary (BP) of the first region (AR1) and the second region (AR2) of the circuit pattern (122) adjacent to the lower surface (BS) of the circuit pattern (122), the issue of undercut of the circuit pattern (122) due to etching is reduced, and the excessive reduction in the contact area between the circuit pattern (122) and the first insulating layer is suppressed, thereby improving the physical bonding strength. According to the embodiment, in the process of arranging the circuit pattern (122), after arranging the seed layer (not shown), the circuit pattern (122) is arranged by using an electroplating method. Therefore, the circuit pattern (122) includes a seed layer (not shown) and an electroplating layer by electroplating. When a process of removing the seed layer (not shown) is performed after forming the circuit pattern (122), the etching rate over time may be different due to the difference in grains between the seed layer (not shown) and the electroplating layer. In the embodiment, since the etching rate of the seed layer (not shown) is greater than the etching rate of the electroplating layer, the undercut issue described above occurs. Therefore, by arranging the boundary (BP) of the first region (AR1) and the second region (AR2) adjacent to the lower surface (BS) of the circuit pattern (122), the undercut issue described above can be reduced.

[0129] Referring further to FIG. 4, as described above, the upper build-up layer (112) may include a first insulating layer (112a) and a second insulating layer (112b) disposed on the first insulating layer (112a).

[0130] An additional pad & via electrode (123) or circuit pattern (124) may be further arranged on the second insulating layer (112b). Here, the electrode portion may additionally include a pad & via electrode (123) or a circuit pattern (124). In addition, the circuit pattern (124) on the second insulating layer (112b) may be equally applied to the description of the circuit pattern described above.

[0131] The second insulating layer (112b) may surround at least a portion of the circuit pattern (122). The second insulating layer (112b) may be positioned over the first insulating layer (112) and the circuit pattern (122).

[0132] Additionally, as an example, the second insulating layer (112b) may include a first portion (P1) that overlaps the second region (AR2) of the circuit pattern (122) along the vertical direction and a second portion (P2) that is misaligned in the vertical direction from the second region (AR2) of the circuit pattern (122) or from a region other than the first region (AR1).

[0133] Furthermore, the second insulating layer (112b) may include a third portion (P3) that overlaps the second region (AR2) of the circuit pattern (122) along the horizontal direction and a fourth portion (P4) that overlaps the first region (AR1) of the circuit pattern (122) along the horizontal direction.

[0134] The second insulating layer (112b) may include a resin and a plurality of fillers (FI) distributed within the resin. For example, the plurality of fillers may be inorganic, and may be, for example, an inorganic material having a predetermined dielectric constant, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0135] The thickness (or diameter) of the plurality of fillers in the third portion (P3) may be smaller than the thickness (or diameter) of the plurality of fillers in the second region or the fourth portion (P4). In addition, the thickness (or diameter) of the plurality of fillers (FI) in the first portion (P1) may be smaller than the thickness (or diameter) in the second portion (P2).

[0136] And the average diameter (r1) of the filler placed in the third portion (P3) may be smaller than the average diameter (r2) of the filler placed in the fourth portion (P4).

[0137] By this configuration, the heat dissipation effect for the circuit pattern can be maximized by positioning the filler with a small size or diameter below the boundary (BP) of the circuit pattern (122) or adjacent to the side of the second region (AR2) of the circuit pattern (122). Furthermore, by positioning the filler with a small diameter, the support force by the filler can be further maximized, thereby improving the support force for the circuit pattern and the bonding force with the insulating layer. Therefore, the circuit board according to the embodiment can have improved reliability.

[0138] In other words, the circuit pattern (122) may have a protrusion extending outward, such as a boundary (BP). Here, the protrusion may correspond to an area that does not vertically overlap with the upper or lower surface of the circuit pattern (122). Accordingly, the width (or diameter) of the protrusion in the circuit pattern may be larger than the width (or diameter) of the upper or lower surface of the circuit pattern (122). In addition, the first portion (P1) may correspond to a portion located between the protrusion and the first insulating layer (112).

[0139] Referring further to FIG. 5a, there may be a plurality of circuit patterns (122) according to the embodiment. For example, the circuit pattern (122) may include adjacent first circuit patterns (122a) and second circuit patterns (122b).

[0140] The gap between the upper surface (US) of the first circuit pattern (122a) and the upper surface (US) of the second circuit pattern (122b) may have a predetermined distance. For example, the gap (gap3) between the upper surface (US) of the first circuit pattern (122a) and the upper surface (US) of the second circuit pattern (122b) may be 1.5 μm to 2 μm. With this configuration, the integration degree can be improved and the influence between adjacent circuit patterns can be reduced.

[0141] Additionally, in the embodiment, the thickness from the bottom surface (BS) to the edge (boundary, BP) in the first circuit pattern (122a) may be different from the thickness from the bottom surface (BS) to the edge (boundary, BP) in the second circuit pattern (122b). In other words, adjacent circuit patterns may have different thicknesses from the bottom surface to the area having the maximum width.

[0142] Furthermore, the distance (gap1) between the bottom surfaces of the adjacent first circuit pattern (122a) and second circuit pattern (122b) may be greater than the distance (gap2) between the contact portions. In an embodiment, the contact portion of each circuit pattern means an area where the first side in the first region (AR1) and the second side in the second region (AR2) are in contact with each other. Accordingly, the distance (gap1) between the bottom surface of the first circuit pattern (122a) and the bottom surface of the second circuit pattern (122b) is greater than the distance (gap2) between the contact portion of the first circuit pattern (122a) and the contact portion of the second circuit pattern (122b), thereby improving the bonding strength between the first insulating layer and the second electrode portion (or circuit pattern). Therefore, the circuit board according to the embodiment can provide improved reliability.

[0143] Referring to FIG. 5b, as described above, the circuit pattern according to the embodiment, particularly the fine pattern (e.g., 5umX5um or less), may have a large aspect ratio. For example, length (a) / width (b) may be greater than 1. In an embodiment, the length (or height, a) of the circuit pattern (122) may be greater than the width (or width, b). In addition, the aspect ratio (width:height) of the circuit pattern (122) may be greater than 0.5:1. Preferably, the aspect ratio (width:height) of the circuit pattern (122) may be 0.5:1 to 0.1:1.

[0144] FIGS. 6 to 9 are drawings explaining a method for manufacturing a circuit board according to the first embodiment of the present invention.

[0145] A circuit board according to an embodiment may include a step of forming a core layer, a first insulating layer, and an electrode portion (a pad or a second pattern), a step of forming a mask and a mask pattern on the first insulating layer, a step of forming a circuit pattern, a step of removing the mask, and a step of removing a seed electrode layer. Except for the contents described below, the description of each component may be applied to the above-described contents.

[0146] Referring to FIG. 6, a core layer (111) is formed, and a via electrode & pad (121) can be formed on the core layer (111). In addition, the core layer (111) can form a cavity (not shown) according to a circuit board or a package board. For the cavity, laser light can be irradiated onto the core layer (111).

[0147] And an upper build-up layer (112) may be formed on the core layer (111). Here, the upper build-up layer (112) may be formed of a plurality of insulating layers, but will be described based on the 'first insulating layer (112)'. Accordingly, the first insulating layer (112) may be formed on the core layer (111). The first insulating layer (112) is formed, and a pattern (including vias, etc.) may be formed on the first insulating layer (112) by a mask and etching, etc. Here, the pattern formed on the first insulating layer (112) may be a pattern for forming a circuit pattern (122), which is a fine pattern.

[0148] The circuit pattern in the electrode section can be formed using a manufacturing process for printed circuit boards, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP). In addition, the pattern can be formed using a dry film, etc.

[0149] A seed electrode layer (SE) may be formed on the first insulating layer (112), and a mask (DF) may be formed on the seed electrode layer (SE). The mask (DF) may include, for example, a dry film. The mask (DF) may form a pattern by exposure or the like.

[0150] At this time, the pattern can be formed into a Gaussian structure of the laser by controlling the exposure amount through the exposure material. For example, the pattern can be formed into a structure that increases the width of the lower portion corresponding to the structure of the circuit pattern described above.

[0151] In other words, the pattern of the mask (DF) has a hole shape at a location where the circuit pattern (122) is formed, and the hole can correspond to the structure of the circuit pattern described above. That is, the hole (or groove) can have a first region whose width gradually decreases toward the upper side (top surface) and a second region whose width gradually decreases toward the lower side (bottom surface).

[0152] Referring to FIG. 7, a circuit pattern (122) may be formed on a pattern of a mask (DF). For example, the circuit pattern (122) may be formed through copper plating. Plating may be performed with copper or the like in the pattern or hole of the mask (DF) described above. At this time, the mask (DF) may have a groove corresponding to the protruding structure of the circuit pattern (122). For example, the mask (DF) may have a concave structure on an outer surface adjacent to or in contact with the circuit pattern (122). As a result, as described above, formation of the circuit pattern (122) can be easily achieved, and the reliability of the circuit pattern (122) can be improved.

[0153] Referring to Fig. 8, the mask (DF) located between the upper portion of the first insulating layer (112) and the circuit pattern (122) can be removed. For example, the mask (DF) can be removed through exposure.

[0154] Referring to Fig. 9, after removing the mask, the seed electrode layer (SD) can be removed.

[0155] The seed electrode layer (SD) may be, for example, a seed layer for chemical plating. At this time, the seed electrode layer (SD) is completely connected on the first insulating layer (112), so that the removal of the seed electrode layer can be performed corresponding to the upper plated circuit pattern. At this time, even if the removal of the seed electrode layer is performed by etching or the like according to the pattern of the mask (DF), the occurrence of undercut at the bottom of the circuit pattern can be minimized. In other words, the bonding force between the circuit pattern and the first insulating layer can be maintained. Furthermore, since the upper surface of the circuit pattern has a width smaller than the width of the boundary, the line width between the circuit patterns can also be reduced. In other words, the implementation of a fine line width can be provided. Furthermore, in order for the upper build-up layer to be composed of a plurality of insulating layers, a plurality of insulating layers can be further formed on the first insulating layer. Furthermore, a lower build-up layer can also be formed. In various semiconductor packages described below, the above-described circuit substrate may be located in a certain area or correspond to one substrate.

[0156] Figure 10 is a schematic diagram of a circuit board according to another embodiment.

[0157] Referring to Fig. 10, the circuit board according to the present embodiment may be applied with the above-described contents except for the contents described below. The circuit board may include an upper build-up layer (112, 113, 114, 115) disposed on a core layer (111) and a lower build-up layer (116, 117, 118) disposed below the core layer.

[0158] Furthermore, via electrodes & pads (121) may also be placed on the upper build-up layers (112, 113, 114, 115). In addition, the circuit pattern (122) according to the above-described embodiment may also be placed on the upper build-up layers (112, 113, 114, 115).

[0159] For example, the upper build-up layers (112, 113, 114, 115) may be formed of a plurality of insulating layers. The upper build-up layer may include a first insulating layer (112), a third insulating layer (113) disposed on the first insulating layer (112), a fourth insulating layer (114) disposed on the third insulating layer (113), and a fifth insulating layer (115) disposed on the fourth insulating layer. The following description will be made based on the first insulating layer (112) and the second insulating layer (112), but the description may be applied to all of the upper build-up layers (112, 113, 114, 115).

[0160] The circuit pattern (122) may be arranged on the upper surface of each insulating layer, such as the first insulating layer (112) and the second insulating layer (112). In addition, the via electrode & pad (121) may also be arranged on each insulating layer, such as the first insulating layer (112) and the second insulating layer (112). Here, the pad may be in direct contact with the via electrode penetrating each insulating layer, such as the first insulating layer (112) and the second insulating layer (112).

[0161] The circuit pattern (122) may be located between the upper surface of the first insulating layer (112) and the upper surface of each insulating layer, such as the second insulating layer (112b). Furthermore, the circuit pattern (122) may not be directly connected to the via electrode.

[0162] The circuit pattern (122) may correspond to the circuit pattern described above. Accordingly, the circuit pattern (122) may include a first region whose width gradually increases from the upper surface toward the lower surface, and a second region whose width gradually decreases from the first region toward the lower surface of the circuit pattern. This circuit pattern (122) may be spaced apart from the lower surface of the upper insulating layer (the second insulating layer) by a predetermined distance.

[0163] In addition, unlike the circuit pattern (122), the via electrode & pad (121) may not have a region in which the width gradually increases from the top surface to the bottom surface. For example, the via electrode & pad (121) may have a region in which the width gradually decreases toward the core layer (or toward the central layer of the circuit board). For example, the via electrode and pad (121) may have only a second region while penetrating each insulating layer (e.g., the first insulating layer). That is, the via electrode & pad (121) may have a region in which the width gradually decreases toward the core layer (or toward the central layer of the circuit board) while penetrating each insulating layer. In other words, among the via electrode & pad (121), the via electrode in particular may be formed in a structure in which the width gradually decreases toward the core layer (or toward the central layer of the circuit board).

[0164] Additionally, the circuit pattern (122) may have a structure that partially penetrates from the upper surface of each insulating layer toward the upper surface. However, as described above, the circuit pattern (122) may not penetrate from the upper surface of each insulating layer to the lower surface.

[0165] Furthermore, the circuit pattern (122) may overlap horizontally with the via electrode of the first electrode portion. In addition, at least a portion of the via electrode of the first electrode portion may not overlap horizontally with the circuit pattern (122).

[0166] FIG. 11 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, FIG. 12 is an enlarged view of K1 in FIG. 1, FIG. 13 is a plan view schematically showing the surface of a first insulating layer, FIG. 14 is a plan view schematically showing the surface of a second insulating layer, FIG. 15 is an enlarged view of K2 in FIG. 1, FIG. 16 is an enlarged view of K3 in FIG. 1, and FIG. 17 is an enlarged view of K4 in FIG. 1.

[0167] Referring to FIG. 11, a circuit board (100A) according to the second embodiment may include an insulating layer (110) and an electrode portion (120). Furthermore, the circuit board (100A) may further include a protective layer (not shown) disposed on the uppermost or lowermost surface of the insulating layer (110). In addition, the circuit board (100A) may include a semiconductor element disposed on the uppermost surface of the insulating layer (110). This will be described later. The insulating layer (110) may correspond to the build-up structure described above.

[0168] The insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0169] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0170] And the insulating layer (110) may include a plurality of insulating layers. The insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). The third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be sequentially arranged in the first direction or the vertical direction (X-axis direction or lamination direction).

[0171] The first insulating layer (111) may be positioned between the second insulating layer (112) and the third insulating layer (113). The second insulating layer (112) may be positioned on the upper surface (US1) of the first insulating layer (111). The lower surface (BS2) of the second insulating layer (112) and the upper surface (US1) of the first insulating layer (111) may form the same surface. The lower surface (BS1) of the first insulating layer (111) may be positioned spaced apart from each other and corresponding to each other in the first insulating layer (111). The third insulating layer (113) may be positioned on the lower surface (BS1) of the first insulating layer (111). The upper surface (US3) of the third insulating layer (113) may form the same surface as the lower surface (BS1) of the first insulating layer (111).

[0172] And the upper surface (US2) of the second insulating layer (112) can be positioned to be spaced apart from and correspond to the lower surface (BS2) of the second insulating layer (112). In addition, the lower surface (BS3) of the third insulating layer (113) can be positioned to be spaced apart from and correspond to the upper surface (US3) of the third insulating layer (113).

[0173] The multiple insulating layers may be made of the same or different materials. The first insulating layer (111) to the third insulating layer (113) may be made of the same or different materials.

[0174] As an example, the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be made of the same material. For example, the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be made of a thermosetting resin or a photocurable resin.

[0175] As another example, the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be made of different materials. For example, the second insulating layer (112) and the third insulating layer (113) may be made of a photocurable resin. And the first insulating layer (111) may be made of a thermocurable resin.

[0176] The electrode portion (120) may include a circuit pattern (or circuit pattern layer, wiring), pads, and via electrodes. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0177] In an embodiment, the electrode portion (120) may include a plurality of electrode layers and via electrodes. Alternatively, the electrode portion (120) may include a wiring electrode and a via electrode. The wiring electrode may include a wiring (or circuit pattern, pattern) and a pad arranged in an insulating layer. The via electrode may be located within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0178] The pads arranged on the outside of the electrode portion (120) can be bonded to semiconductor elements, substrates, boards, etc. with solder, wires, conductive adhesives, etc., and may be arranged with a width larger than the width of the circuit pattern in order to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. In addition, the pads arranged on the inside function to connect the via electrodes and the circuit pattern. When the via electrodes are arranged with a width wider than the circuit pattern, pads having a width wider than the circuit pattern are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad directly in contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad directly in contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, but should also be understood as a concave or convex surface that may appear depending on various processes.

[0179] As an example, the electrode portion (120) may include a first electrode layer (121), a first via electrode (VE1), a second electrode layer (122), a second via electrode (VE2), a third electrode layer (123), a third via electrode (VE3), and a fourth electrode layer (124). Each electrode layer may include a via land and a pattern portion.

[0180] As an example, the first electrode layer (121) may be positioned on the upper surface (US1) of the first insulating layer (111). The first electrode layer (121) may be positioned between the upper surface (US1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112).

[0181] The first electrode layer (121) may include a first via land (121a) and a first pattern portion (121b).

[0182] The first via land (121a) may be arranged on the upper surface (US1) of the first insulating layer (111). The first via land (121a) may be connected to the first via electrode (VE1) and may be arranged between the upper surface (US2) of the second insulating layer (112) and the upper surface (US1) of the first insulating layer (111). At least a portion of the first via land (121a) may overlap the first via electrode (VE1) in the vertical direction (X-axis direction).

[0183] The first pattern portion (121b) may be arranged on the upper surface (US1) of the first insulating layer (111). The first pattern portion (121b) may be arranged spaced apart from the first via land (121a). The first pattern portion (121b) may be smaller than the width (e.g., line width) or interval of the first via land (121a). For example, the first pattern portion (121b) may be a fine pattern.

[0184] The first pattern portion (121b) may have a different shape, such as a size, compared to the first via land (121a). The first pattern portion (121b) and the first via land (121a) may overlap in the horizontal direction (Y-axis direction). The horizontal direction may be a direction perpendicular to the vertical direction (X-axis direction).

[0185] Furthermore, the first electrode layer (121) may have a general pattern whose width and spacing are at least 1.5 times larger than those of the first pattern portion (121b). This can be equally applied to the second electrode layer (122), third electrode layer (123), and fourth electrode layer (124) described below.

[0186] The second electrode layer (122) may be disposed on the upper surface (US2) of the second insulating layer (112). The first electrode layer (121) and the second electrode layer (122) may be disposed to be spaced apart from each other in the vertical direction (X-axis direction).

[0187] The second electrode layer (122) may include a second via land (122a) and a second pattern portion (122b).

[0188] The second via land (122a) may be arranged on the upper surface (US2) of the second insulating layer (112). The second via land (122a) may be arranged to be spaced apart from the first via land (121a) in the vertical direction. Furthermore, since the second via land (122a) is connected to the second via electrode (VE2), the second via land (122a) and the second via electrode (VE2) may at least partially overlap each other in the vertical direction.

[0189] The second pattern portion (122b) may be disposed on the upper surface (US2) of the second insulating layer (112). The second pattern portion (122b) may be disposed spaced apart from the second via land (122a). The second pattern portion (122b) may have a smaller width (or line width) or spacing than the second via land (122b). For example, the second pattern portion (122b) may be a fine pattern. In addition, the second pattern portion (122b) may have a different shape, such as a size, compared to the second via land (122a). In addition, the second pattern portion (122b) and the second via land (122a) may overlap in the horizontal direction (Y-axis direction).

[0190] The third electrode layer (123) may be positioned below the bottom surface of the first insulating layer (111). The third electrode layer (123) may be positioned between the bottom surface (BS1) of the first insulating layer (111) and the bottom surface (BS3) of the third insulating layer (113).

[0191] The third electrode layer (123) may include a third via land (123a) and a third pattern portion (123b).

[0192] The third via land (123a) may be arranged on the bottom surface (BS1) of the first insulating layer (111). The third via land (123a) may be connected to the third via electrode (VE3) and may be arranged between the bottom surface (BS3) of the third insulating layer (113) and the bottom surface (BS1) of the first insulating layer (111). At least a portion of the third via land (123a) may overlap the third via electrode (VE3) in the vertical direction (X-axis direction).

[0193] The third pattern portion (123b) may be arranged on the bottom surface (BS1) of the first insulating layer (111). The third pattern portion (123b) may be arranged spaced apart from the third via land (123a). The third pattern portion (123b) may be smaller than the width (e.g., line width) or spacing of the third via land (123a). The third pattern portion (123b) may be a fine pattern. In addition, the shape, such as the size, of the third pattern portion (123b) may be different from that of the third via land (123a). In addition, the third pattern portion (123b) and the third via land (123a) may overlap in the horizontal direction (Y-axis direction).

[0194] The fourth electrode layer (124) may be placed on the bottom surface (BS3) of the third insulating layer (113). For example, the fourth electrode layer (124) may be positioned below the bottom surface (BS3) of the third insulating layer (113).

[0195] The fourth electrode layer (124) may include a fourth via land (124a) and a fourth pattern portion (124b).

[0196] The fourth electrode layer (124) may include a fourth via land (124a) and a fourth pattern portion (124b).

[0197] The fourth via land (124a) may be arranged on the bottom surface (BS3) of the third insulating layer (113). The fourth via land (124a) may be arranged to be spaced apart from the third via land (123a) in the vertical direction. Furthermore, since the fourth via land (124a) is connected to the third via electrode (VE3), the fourth via land (124a) and the third via electrode (VE3) may at least partially overlap each other in the vertical direction.

[0198] The fourth pattern portion (124b) may be arranged on the bottom surface (BS2) of the third insulating layer (113). The fourth pattern portion (124b) may be arranged to be spaced apart from the fourth via land (124a). The fourth pattern portion (124b) may have a smaller width (or line width) or spacing than the fourth via land (124b). For example, the fourth pattern portion (124b) may be a fine pattern. In addition, the fourth pattern portion (124b) may have a different shape, such as a size, compared to the fourth via land (124a). In addition, the fourth pattern portion (124b) and the fourth via land (124a) may overlap in the horizontal direction (Y-axis direction).

[0199] The first via electrode (VE1) can penetrate the first insulating layer (111). The first via electrode (VE1) can penetrate the upper surface (US1) of the first insulating layer (111) and the lower surface (BS1) of the first insulating layer (111). The first via electrode (VE1) can connect the first electrode layer (121) and the third electrode layer (123). For example, the first via electrode (VE1) can be connected to the first via land (121a) of the first electrode layer (121). In addition, the first via electrode (VE1) can be connected to the third via land (123a) of the third electrode layer (123).

[0200] The second via electrode (VE2) may be disposed between the first electrode layer (121) and the second electrode layer (122). The second via electrode (VE2) may penetrate at least a portion of the second insulating layer (112). The second via electrode (VE2) may connect the first electrode layer (121) and the second electrode layer (122). For example, the second via electrode (VE2) may connect the first via land (121a) of the first electrode layer (121) and the second via land (122a) of the second electrode layer (122). Accordingly, the first via land (121a) of the first electrode layer (121) may be a lower via land of the second via electrode (VE2). The second via land (122a) of the second electrode layer (122) may be an upper via land of the second via electrode (VE2).

[0201] The third via electrode (VE3) may be positioned between the third electrode layer (123) and the fourth electrode layer (124). The third via electrode (VE3) may penetrate at least a portion of the third insulating layer (113).

[0202] And the third via electrode (VE3) can connect the third electrode layer (123) and the fourth electrode layer (124). For example, the third via electrode (VE3) can connect the third via land (123a) of the third electrode layer (123) and the fourth via land (124a) of the fourth electrode layer (124). The third via land (123a) of the third electrode layer (123) can be an upper via land of the third via electrode (VE3). The fourth via land (124a) of the fourth electrode layer (124) can be a lower via land of the third via electrode (VE3).

[0203] Furthermore, semiconductor elements may be arranged on the upper surface of the upper insulating layer in the circuit board (100A). There may be multiple semiconductor elements. In addition, the pattern portion in the circuit board (100A) may perform a bridge function that connects multiple semiconductor elements to each other. For example, the first pattern portion (121a) and the second pattern portion (122b) may connect spaced-apart semiconductor elements to each other.

[0204] Furthermore, the circuit board (100A) according to the embodiment can function as an interposer positioned between a main board, such as a BGA board, and a semiconductor element. Accordingly, the thickness of the circuit board can be smaller than the thickness of the main board, etc.

[0205] Referring to Fig. 12, the ratio of the thickness of the second insulating layer (112) to the thickness (T1) of the first insulating layer (111) in the circuit board according to the embodiment may be 1:0.8 to 1:12. Since the ratio is in the range of 1:0.8 to 1:12, miniaturization and via formation are advantageous, and there is an advantage in that formation of each electrode layer is easy. Furthermore, unlike the core layer and the insulating layer on the core layer in the main board (e.g., BGA), the thickness difference between the first insulating layer (111), the second insulating layer (112), etc. may not be large.

[0206] For example, the thickness (T1) of the first insulating layer (111) may be the same as the thickness (T2) of the second insulating layer (112). In addition, the thickness (T1) of the first insulating layer (111) may be greater than the thickness (T2) of the second insulating layer (112). In addition, the thickness (T1) of the first insulating layer (111) may be smaller than the thickness (T2) of the second insulating layer (112).

[0207] In addition, the thickness (T3) of the first via electrode (VE1) may be different from the thickness of the second via electrode (VE2). The thickness (T3) of the first via electrode (VE1) may correspond to the thickness (T1) of the first insulating layer (111). For example, since the first via electrode (VE1) penetrates the upper surface (US1) and the lower surface (BS1) of the first insulating layer, the thickness (T3) of the first via electrode (VE1) may be the same as the thickness (T1) of the first insulating layer (111).

[0208] In contrast, the second via electrode (VE2) may be positioned between the first electrode layer and the second electrode layer in the second insulating layer (112). For example, the second via electrode (VE2) may be positioned on the first via land (121a) located between the upper surface (US2) and the lower surface (BS2) of the second insulating layer (112). Accordingly, the thickness (T4) of the second via electrode (VE2) may be smaller than the thickness (T2) of the second insulating layer (112).

[0209] And each electrode layer may be 0.3 to 0.6 times the thickness of each insulating layer. Accordingly, even if the thickness (T1) of the first insulating layer (111) is the same as the thickness (T2) of the second insulating layer (112) or smaller than the thickness (T2) of the second insulating layer (112), the thickness (T3) of the first via electrode (VE1) may be larger than the thickness (T4) of the second via electrode (VE2). In response to this thickness difference, the minimum width (W1a) of the first via electrode (VE1) may be smaller than the minimum width (W2a) of the second via electrode (VE2).

[0210] In addition, the thickness (T3) of the second via electrode (VE2) may correspond to the third via electrode (VE3). Similarly, the thickness (T2) of the second insulating layer (112) may correspond to the thickness of the third insulating layer (113). Accordingly, the ratio of the thickness of the third insulating layer (113) to the thickness (T1) of the first insulating layer (111) in the circuit board may be 1:0.8 to 1:.12. Similarly, since this ratio has a range of 1:0.8 to 1:.12, miniaturization and via formation are advantageous, and there is an advantage in that formation of each electrode layer is easy. Furthermore, unlike the core layer and the insulating layer on the core layer in the main board (e.g., BGA), the thickness difference between the first insulating layer (111), the third insulating layer (113), etc. may not be large.

[0211] And the thickness of the third via electrode (VE3) may be smaller than the thickness (T3) of the first via electrode (VE1). Corresponding to this thickness difference, the minimum width (W1a) of the first via electrode (VE1) may be smaller than the minimum width (W3a) of the third via electrode (VE3).

[0212] In addition, in the embodiment, the width (W1) of the first via electrode (VE1) may gradually increase from the upper surface (US1) of the first insulating layer (111) toward the lower surface (BS1). And the width (W2) of the second via electrode (VE2) may decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2). And the width (W3) of the third via electrode (VE3) may gradually increase from the upper surface of the first insulating layer or the third insulating layer toward the lower surface. In other words, the first via electrode (VE1) and the third via electrode (VE3) may have the same width expansion direction. In other words, the direction of expansion of the width of the first via electrode (VE1) and the third via electrode (VE3) can correspond to the direction from the upper surface (US1) of the first insulating layer (111) toward the lower surface (BS1).

[0213] And the second via electrode (VE2) may have an opposite direction of width expansion to the first via electrode (VE1) (or the third via electrode (VE3)). In addition, the first insulating layer (111) may be the first insulating layer in which the direction in which the width of the via electrode increases changes based on the direction from the uppermost insulating layer to the lower insulating layer on the circuit board. Pattern portions may be formed on the upper and lower surfaces based on the first insulating layer, and pattern portions may be sequentially formed on one surface of each insulating layer.

[0214] Referring to Fig. 13, as described above, the first pattern portion (121b) may have a line width (WL1) of 5 μm or less. Similarly, the spacing (WS1) between adjacent first pattern portions (121b) may also be 15 μm or less.

[0215] In contrast, the width (WL3) of the first via land (121a) on the upper surface of the first insulating layer may be larger than the line width (WL1) of the first pattern portion (121b). Furthermore, the width (WL2) of the general pattern of the first electrode layer (121) or the spacing (WS2) between adjacent general patterns may be larger than the line width (WL1) or the spacing (WS1) of the first pattern portion (121b) described above. By this configuration, electrical connection between the via land and the via electrode can be easily achieved. In other words, a decrease in electrical reliability due to electrical disconnection can be prevented. In addition, the input / output count (I / O count) can be improved through the first pattern portion (121b) which is a fine pattern. This configuration can be equally applied to the pattern portion and the via land of each electrode layer.

[0216] Referring to Fig. 14, the second pattern portion (122b) may have a line width (WL3) of 5 μm or less. Similarly, the spacing between adjacent second pattern portions (122b) may also be 15 μm or less. Conversely, the width (WL4) of the second via land (122a) on the upper surface of the second insulating layer may be greater than the line width (WL3) of the second pattern portion (122b). Furthermore, the width of the general pattern of the second electrode layer (122) or the spacing between adjacent general patterns may be greater than the line width (WL3) or the spacing of the second pattern portion (122b). By this configuration, electrical connection between the via land and the via electrode can be easily achieved. Furthermore, electrical connection or contact between the upper semiconductor element and the second pattern portion (122b) can be easily achieved through the second pattern portion (122b). In addition, the input / output count (I / O count) can be improved.

[0217] Referring to FIG. 15, in a circuit board according to an embodiment, a first via electrode (VE1) may be positioned between a first pattern portion (121b) and a second pattern portion (122b). In addition, the first via electrode (VE1) may not vertically overlap with the first pattern portion (121b) and the second pattern portion (122b). That is, with respect to the first insulating layer (111) in which the expansion direction of the via electrode changes, the first pattern portion (121a) positioned on the upper surface (US1) of the first insulating layer (111) may be horizontally spaced from the first via electrode (VE1) and may be vertically misaligned. In addition, the second pattern portion (122b) may also be horizontally spaced from the first via electrode (VE1) and may be vertically misaligned. In this way, there may not be a via connecting the first pattern portion (121a) and the second pattern portion (122b). As described above, the first pattern portion (121a) and the second pattern portion (122b) have fine line widths and spacings, so it may be difficult to form a via electrode connecting them. Alternatively, issues such as an electrical short circuit may occur when a pattern portion, which is a fine pattern with a small line width, is formed on the upper or lower surface of the via electrode. Furthermore, since a via hole or via electrode is not positioned between the first pattern portion (121a) and the second pattern portion (122b), the flatness of the surface of the insulating layer is improved, so that the formation of a pattern portion (such as a third pattern portion or a fourth pattern portion) which is a fine pattern located below can be easily achieved. In other words, a pattern portion which is a fine pattern can be easily formed on a plurality of insulating layers, thereby providing a greatly improved input / output count.

[0218] Accordingly, the upper surface (UB) of the first via electrode (VE1) and the lower surface (UA) of the second via electrode (VE2) may overlap each other in a vertical direction (X-axis direction). Furthermore, the lower surface (UA) of the second via electrode (VE2) may include an overlapping portion (OA) and a non-overlapping portion (IA) that vertically overlap with the upper surface (UB) of the first via electrode (VE1). The non-overlapping portion (IA) may be located on the outside of the overlapping portion (OA). The non-overlapping portion (IA) may surround the overlapping portion (OA).

[0219] Additionally, the thickness (T5) of the first via land (121a) may correspond to the thickness (T6) of the first pattern portion (121b). For example, the thickness (T5) of the first via land (121a) may be the same as the thickness (T6) of the first pattern portion (121b).

[0220] And the thickness (T6) of the first pattern portion (121b) may be 7㎛ or less. Accordingly, the size may be very small compared to the pattern portion on the core layer of the main substrate (e.g., BGA). Furthermore, the thickness (T6) of the first pattern portion (121b) may be 0.3 to 0.6 times the thickness of the first insulating layer (111) (or the second insulating layer). When the thickness (T6) of the first pattern portion (121b) is large, it may be greater than 0.5 times the thickness of the second insulating layer (112). Accordingly, the thickness (T6) of the first pattern portion (121b) may be greater than the thickness of the second via electrode (VE2). In addition, the thickness (T5) of the first via land (121a) may be greater than the thickness of the second via electrode (VE2). Furthermore, the gap between the first pattern portion (121b) and the second pattern portion (122b) may be smaller than the thickness of the first pattern portion or the second pattern portion.

[0221] In addition, the thickness (T7) of the second via land (122a) may correspond to the thickness (T8) of the second pattern portion (122b). For example, the thickness (T7) of the second via land (122a) may be the same as the thickness (T8) of the second pattern portion (122b). And the thickness (T8) of the second pattern portion (122b) may be 7 μm or less. Furthermore, the thickness (T8) of the second pattern portion (122b) may be 0.3 to 0.6 times the thickness of the second insulating layer.

[0222] This thickness can be equally applied to the third pattern portion and the fourth pattern portion. Accordingly, the total thickness of the first pattern portion (121b), the second pattern portion (122b), the third pattern portion, and the fourth pattern portion can be smaller than the thickness of the core layer of the main substrate. Furthermore, the thickness and shape of each pattern portion can be different from the thickness and shape of the pattern on the core layer.

[0223] Referring to Fig. 16, the first pattern portion (121b) and the third pattern portion (123b) may be positioned on the upper surface and the lower surface of the first insulating layer (111), respectively. Accordingly, the first pattern portion (121b) and the third pattern portion (123b) may not overlap with the first insulating layer (111) in the horizontal direction (Y-axis direction). In addition, the first pattern portion (121b) and the third pattern portion (123b) may not overlap with the first via electrode (VE1) in the horizontal direction (Y-axis direction). In other words, the first pattern portion (121b) and the third pattern portion (123b) may be misaligned with the first via electrode (VE1) in the horizontal direction (Y-axis direction). That is, the first insulating layer (111), which is an insulating layer in which an expansion direction different from the expansion direction of the via electrode in the upper insulating layer occurs, may have pattern portions formed on the upper and lower surfaces. In addition, there may not be any other electrodes that overlap horizontally with the first via electrode (VE1) in the first insulating layer (111). By this configuration, since no via electrodes or other pattern electrodes other than the first via electrode are positioned in the first insulating layer (111), the flatness of the surface (e.g., the bottom surface) of the first insulating layer (111) may be significantly improved. Accordingly, the pattern portion (such as the third pattern portion or the fourth pattern portion) which is a micro-pattern located on the bottom surface of the first insulating layer (111) may not be inclined along the curvature of the bottom surface of the first insulating layer (111). In other words, the formation of the pattern portion which is a micro-pattern can be easily achieved. Accordingly, since the pattern portion which is a micro-pattern is formed on a plurality of insulating layers in the circuit board, the input / output count can be greatly improved.

[0224] Referring to Fig. 17, the first pattern portion (121b), the second pattern portion (122b), the third pattern portion (123b), and the fourth pattern portion (124b) may overlap at least partially in the vertical direction. And as described above, each pattern portion is arranged on the upper or lower surface of each insulating layer, so that the pattern portions, which are fine patterns, may be laminated in multiple layers. The first pattern portion (121b), the second pattern portion (122b), the third pattern portion (123b), and the fourth pattern portion (124b) may have the same shape, etc. For example, the first pattern portion (121b), the second pattern portion (122b), the third pattern portion (123b), and the fourth pattern portion (124b) may have thicknesses that correspond to each other. Furthermore, the first pattern portion (121b), the second pattern portion (122b), the third pattern portion (123b), and the fourth pattern portion (124b) may not have electrodes such as via electrodes in the areas between adjacent pattern portions. As a result, issues such as electrical short circuits are prevented from occurring, and fine pattern formation can be more easily achieved as described above. Furthermore, since via electrodes are not formed in the vertical direction of each pattern portion, the flatness of the upper and lower surfaces of each insulating layer can be maintained. Accordingly, tilting of the spaced-apart patterns formed on one surface of the insulating layer is suppressed, and a decrease in the bonding strength formed in the insulating layer can also be prevented.

[0225] In addition, the separation distance (gap1) between the first pattern portion (121b) and the third pattern portion (123b) may be greater than the separation distances (gap2, gap3) between adjacent pattern portions. For example, the separation distance (gap1) between the first pattern portion (121b) and the third pattern portion (123b) may be greater than the separation distance (gap2) between the first pattern portion (121b) and the second pattern portion (122b). In addition, the separation distance (gap1) between the first pattern portion (121b) and the third pattern portion (123b) may be greater than the separation distance (gap3) between the third pattern portion (123b) and the fourth pattern portion (124b). By this configuration, the roughness, etc. of the bottom surface of the first insulating layer (111) is reduced, so that the formation of the third pattern portion and the fourth pattern portion, which are fine patterns, can be easily performed.

[0226] In addition, the gap 1 between the first pattern portion (121b) and the third pattern portion (123b) may be greater than the thickness of each pattern portion. The gap 2 between the first pattern portion (121b) and the second pattern portion (122b) or the gap 3 between the third pattern portion (123b) and the fourth pattern portion (124b) may be smaller than the thickness of each pattern portion. Accordingly, etching for pattern formation, etc. can be easily performed, thereby improving the ease of manufacturing, and miniaturization of the circuit board can be easily implemented.

[0227] FIG. 18 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, and FIG. 19 is an enlarged view of K5 in FIG. 18.

[0228] Referring to FIGS. 18 and 19, a circuit board (100B) according to the third embodiment may include an insulating layer (110) and an electrode portion (120). Furthermore, except for the following description of the circuit board (100B), the contents described in other embodiments may be equally applied.

[0229] In the circuit board (100B), the direction of expansion or width increase of the via electrode may change starting from the first insulating layer (111). At this time, the thickness (T1') of the first insulating layer (111) may be smaller than the thickness of other insulating layers. For example, the thickness (T1') of the first insulating layer (111) may be smaller than the thickness (T2') of the second insulating layer (112). As described above, the thickness (T1') of the first insulating layer (111) may be greater than 0.8 times the thickness (T2') of the second insulating layer (112).

[0230] Despite the difference in thickness between these insulating layers, the thickness (T3') of the first via electrode (VE1) may be greater than the thickness (T4') of the second via electrode (VE2).

[0231] And the distance between the first pattern portion (121b) and the second pattern portion (122b) may be smaller than the thickness (T1') of the first insulating layer (111) or the thickness (T3') of the first via electrode (VE1).

[0232] By this thickness configuration, the formation of the first via electrode (VE1) can be easily achieved, and miniaturization of the circuit board can also be easily achieved.

[0233] FIG. 20 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, and FIG. 21 is an enlarged view of K6 in FIG. 20.

[0234] Referring to FIGS. 20 and 21, a circuit board (100C) according to the fourth embodiment may include an insulating layer (110) and an electrode portion (120). Furthermore, except for the following description of the circuit board (100C), the contents described in other embodiments may be equally applied.

[0235] In the circuit board (100C), the direction of expansion or width increase of the via electrode may change starting from the first insulating layer (111). At this time, the thickness (T1'') of the first insulating layer (111) may be smaller than the thicknesses of other insulating layers. For example, the thickness (T1'') of the first insulating layer (111) may be larger than the thickness (T2'') of the second insulating layer (112). As described above, the thickness (T1'') of the first insulating layer (111) may be greater than at most 1.2 times the thickness (T2'') of the second insulating layer (112).

[0236] In addition, the thickness (T3'') of the first via electrode (VE1) may be greater than the thickness (T4'') of the second via electrode (VE2). In response to this thickness difference, when the diameters or maximum widths of the first via electrode (VE1) and the second via electrode (VE2) are the same, the minimum width of the first via electrode (VE1) may be smaller than the minimum width of the second via electrode (VE2).

[0237] By this thickness configuration, the formation of the first via electrode (VE1) can be easily achieved, and miniaturization of the circuit board can also be easily achieved.

[0238] Figures 22a to 22e are drawings illustrating a method for manufacturing a circuit board according to a second embodiment.

[0239] Referring to Fig. 22a, a carrier substrate can be prepared. For example, CCL (Copper Clad Laminate) can be used as the carrier board.

[0240] The carrier board may include a carrier insulating layer (10) and a carrier metal layer (10S) disposed on at least one surface of the carrier insulating layer. At this time, as illustrated in the drawing, the carrier metal layer (10S) may be disposed on both surfaces of the carrier insulating layer (10). However, the present invention is not limited to this manufacturing method.

[0241] The manufacturing processes for the insulating layer, electrode layer, and via electrode of the circuit board described below can be performed on both sides of the carrier board. For example, in the embodiment, the processes described below can be performed on the upper and lower sides of the carrier board, respectively, to form multiple substrate layers at once. This can improve the mass productivity of the circuit board. The following description will focus on one side.

[0242] Referring to Fig. 22b, the first electrode layer (121) can be formed by performing electrolytic plating, etc. on the carrier metal layer (10S). At this time, the carrier metal layer (10S) can serve as a seed layer. To form the first electrode layer (121), dry film lamination, exposure and development, plating, dry film peeling, etching, etc. can be performed. For example, a dry film, which is a mask, can be arranged to correspond to a via land and a pattern portion. Then, an opening can be formed in the dry film through an exposure and development process. Then, an electrode layer (e.g., corresponding to the first electrode layer) can be formed in the opening portion of the dry film. In other words, a via land and a pattern portion can be formed in the opening portion of the dry film. At this time, the first electrode layer can be formed by electrolytic plating, etc. And the dry film, which is a mask, can be removed by peeling, etc. Then, an area excluding an area corresponding to the first electrode layer can be removed by etching, etc.

[0243] Referring to FIG. 22c, a second insulating layer (112) can be formed on the first electrode layer. The second insulating layer (112) can be formed in various ways. The second insulating layer (112) can be formed by performing thermal curing (e.g., lamination) on ABF.

[0244] And, a plating layer that functions as a seed layer can be formed on the second insulating layer (112) by plating or the like. Furthermore, a via hole can be formed on the second insulating layer (112), and a plating layer that functions as a seed layer can be additionally formed by plating or the like. After that, a second via electrode can be formed by plating.

[0245] In addition, as described above, dry film lamination, exposure and development, plating, dry film peeling, etching, etc. may be performed to form a second electrode layer (122) on the second insulating layer (112). As a result, a second electrode layer may be formed on the upper surface of the second insulating layer (112).

[0246] Referring to FIG. 22d, the layers formed on both sides of the carrier board can be separated from the carrier board or carrier insulating layer (10). Accordingly, the first electrode layer (121), the second insulating layer (112), the second via electrode, and the second electrode layer (122) can be separated.

[0247] Referring to FIG. 22e, a first insulating layer (111) can be formed on the lower surface of the first electrode layer (121). Then, a first via electrode can be formed on the first insulating layer (111). As described above, the first via electrode can be formed through processes such as via hole formation, seed layer formation, and plating.

[0248] And a third electrode layer can be formed on the lower surface of the first insulating layer (111). The first insulating layer (111) can be formed in various ways. The first insulating layer (111) can be formed through thermal curing for ABF, etc.

[0249] In addition, as described above, there may be no electrode other than the first via electrode within the first insulating layer (111). In particular, there may be no via electrode beneath the first pattern portion (121b) of the first electrode layer (121) or the second pattern portion (122b) of the second electrode layer (122).

[0250] Thereafter, a third electrode layer (123) can be formed on the lower surface of the first insulating layer (111). To form the third electrode layer (123), dry film lamination, exposure and development, plating, dry film peeling, etching, etc. can be performed. As a result, the third electrode layer (123) can be formed on the lower surface of the first insulating layer (111).

[0251] And a third insulating layer (113) can be formed on the lower surface of the first insulating layer (111). In addition, a third insulating layer (113) can be formed under the third electrode layer (123). The third insulating layer (113) can be formed in various ways.

[0252] And, a plating layer that functions as a seed layer can be formed on the third insulating layer (113) or the bottom surface of the third insulating layer (113) by plating, etc. Furthermore, a via hole can be formed in the third insulating layer (113), and a plating layer that functions as a seed layer can be additionally formed by plating, etc. After that, a third via electrode can be formed by plating.

[0253] In addition, as described above, dry film lamination, exposure and development, plating, dry film peeling, etching, etc. can be performed to form the fourth electrode layer (124) on the lower surface of the third insulating layer (113). As a result, the fourth electrode layer (124) can be formed on the lower surface of the third insulating layer (113).

[0254] FIG. 23 is a drawing of a circuit board and a laminated semiconductor element according to a second embodiment of the present invention, and FIG. 24 is a drawing illustrating the arrangement of semiconductor elements in a circuit board according to the second embodiment.

[0255] Referring to FIGS. 23 and 24, a package substrate including a circuit substrate according to an embodiment may include a main substrate in addition to a semiconductor element and a circuit substrate (100).

[0256] In such a package substrate, the circuit board (100) according to the embodiment may be an interposer placed between the main substrate and the semiconductor element. Furthermore, the circuit board (100) may be a substrate that performs a bridge function for the semiconductor element. Thus, the circuit board can improve yield and serve as a buffer with a fine pattern size.

[0257] Specifically, a plurality of semiconductor elements (SD1, SD1', SD2) may be mounted on the second electrode layer, which is the outer layer of the circuit board (100). The circuit board (100) may be any of the various examples of circuit boards described above. In addition, the circuit board (100) may have a connection region (R) in which the plurality of semiconductor elements (SD1, SD1', SD2) are connected to each other at adjacent portions. The connection region (R) may be formed of a pattern portion (e.g., first and second pattern portions, etc.) which is a micro-pattern of the electrode layer as described above. In other words, a plurality of semiconductor elements may be connected to each other through the pattern portion (e.g., first and second pattern portions) of the circuit board.

[0258] Here, the plurality of semiconductor devices may include logic chips or memory chips as described above. In addition, the first semiconductor device (SD1, DI') and the second semiconductor device (SD2) may be heterogeneous semiconductor devices as described above.

[0259] Furthermore, a pattern for connection with the main substrate under the circuit board (100) may be formed on the lower portion of the third insulating layer (113). That is, the pattern portion, which is a fine pattern, may not be exposed on the lower portion of the circuit board (100). Furthermore, a protective layer may be additionally disposed on the upper surface of the uppermost insulating layer or the lower surface of the lowermost insulating layer.

[0260] Fig. 25 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 26 is a cross-sectional view showing a semiconductor package according to the second embodiment, and Fig. 27 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0261] In the various semiconductor packages described below, the circuit board described above may be located in a certain area or may correspond to one substrate. For example, the circuit board according to the various embodiments described above may be located on one substrate of the semiconductor package. In particular, the circuit board according to the various embodiments described above may be applied to a package having an FC-BGA (Flip Chip Ball Grid Array). In particular, the circuit board according to the various embodiments described above may be applied to a second substrate (1200) in the package. In particular, the circuit board according to the various embodiments described above may be applied to an interposer substrate. In addition, the circuit board according to the various embodiments described above may be applied to a bridge substrate. For example, the shape of the circuit pattern in the circuit board may also be applied to the connecting member (1210, FIG. 26) described below. Accordingly, the circuit board described above may be applied to an interposer substrate and / or a bridge substrate within a package substrate or a semiconductor package.

[0262] Referring to FIG. 25, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0263] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0264] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0265] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0266] A second substrate (1200) may be placed on the first substrate (1100).

[0267] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0268] In Fig. 25, two semiconductor elements (1310, 1320) are illustrated as being arranged on a second substrate (1200), but this is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0269] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0270] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may have the functions of a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. In addition, the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0271] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0272] The semiconductor device (1300) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0273] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0274] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0275] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0276] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0277] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0278] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0279] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0280] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0281] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0282] Additionally, looking further into FIG. 26, the semiconductor package of the second embodiment may further include a connecting member (1210).

[0283] The connecting member (1210) may be referred to as a bridge. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may function to electrically connect a plurality of semiconductor devices to each other. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size that is intermediate between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device.

[0284] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0285] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0286] Referring to FIG. 27, the semiconductor package of the third embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the third embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0287] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0288] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0289] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying power to semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0290] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0291] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0292] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0293] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A first insulating layer including the upper and lower surfaces; and including a circuit pattern disposed on the upper surface of the first insulating layer, A circuit board including a first region in which the width gradually increases from the upper surface toward the lower surface, and a second region in which the width gradually decreases from the first region toward the lower surface of the circuit pattern.

2. In paragraph 1, The width of the circuit pattern is the maximum width of the circuit board at the boundary between the first and second regions.

3. In paragraph 2, A circuit board wherein the thickness of the second region is greater than the thickness of the first region.

4. In paragraph 2, A circuit board in which a second angle formed by the bottom surface and the side surface of the circuit pattern in the second region is different from a first angle formed by the top surface and the side surface of the circuit pattern in the first region.

5. In paragraph 4, A circuit board wherein the first angle is greater than the second angle.

6. In paragraph 1, A circuit board in which the area of ​​the upper surface of the circuit pattern is different from the area of ​​the lower surface of the circuit pattern.

7. In paragraph 6, A circuit board in which the area of ​​the upper surface of the circuit pattern is larger than the area of ​​the lower surface of the circuit pattern.

8. In paragraph 1, A circuit board in which the upper surface of the circuit pattern does not overlap at least partially with the lower surface of the circuit pattern.

9. In paragraph 1, A circuit board in which the lower surface of the circuit pattern does not overlap at least partially with the upper surface of the circuit pattern.

10. In paragraph 2, A circuit board comprising a second insulating layer disposed on the first insulating layer.

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