Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a first build-up structure; a second build-up structure arranged on the first build-up structure; and a protective layer arranged on the second build-up structure, wherein a horizontal spacing between a plurality of wiring layers of the first build-up structure is greater than a horizontal spacing between a plurality of wiring layers of the second build-up structure, the plurality of wiring layers of the second build-up structure including an upper wiring layer most adjacent to the protective layer, wherein the upper wiring layer includes a first electrode layer and a second electrode layer arranged on the first electrode layer and further includes a bump part, which is arranged on the second electrode layer and includes a via part that penetrates the protective layer and a protrusion part that is arranged on the via part, the thickness of the first electrode layer being smaller than the thickness of the second electrode layer or the thickness of the protrusion part.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as circuit board warpage and product price increase. Therefore, increasing the circuit pattern density is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] However, the bump portion on this microcircuit pattern is also miniaturized, and the rigidity between multiple layers with different characteristics is reduced during formation, resulting in physical and electrical separation, and thus improvement in electrical and mechanical reliability is required.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which have improved mechanical and electrical reliability by not forming a plurality of layers even if the bump portion is fine due to a difference in width between the upper surface of the bump portion in the protective layer and the upper wiring layer at the top of the build-up structure, and easily suppressing the phenomenon of separation between the upper wiring layer, which is a fine pattern, and the bump portion when bonded.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which improve electrical reliability by increasing the bonding surface between sublayers through a protective layer in which the first sublayer penetrates the second sublayer, protect the substrate from moisture, contaminants, and chemical damage in the external environment, and enhance the durability of the substrate.

[0009] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0010] A circuit board according to an embodiment of the present invention comprises: a first build-up structure including a plurality of insulating layers stacked along a vertical direction, a plurality of wiring layers arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring layers along the vertical direction; a second build-up structure disposed on the first build-up structure and including a plurality of insulating layers stacked along a vertical direction, a plurality of wiring layers arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring layers along the vertical direction; And a protective layer disposed on the second build-up structure; wherein a horizontal distance between the plurality of wiring layers of the first build-up structure is greater than a horizontal distance between the plurality of wiring layers of the second build-up structure, the plurality of wiring layers of the second build-up structure includes an upper wiring layer that is most adjacent to the protective layer, the upper wiring layer includes a first electrode layer, a second electrode layer disposed on the first electrode layer, and further includes a bump portion that is disposed on the second electrode layer and includes a via portion that penetrates the protective layer, and a protrusion portion disposed on the via portion, and a thickness of the first electrode layer is smaller than a thickness of the second electrode layer or a thickness of the protrusion portion.

[0011] The maximum width of the first electrode layer may be greater than the maximum width of the bump portion.

[0012] The first electrode layer and the second electrode layer may have different widths.

[0013] The width of the first electrode layer may be greater than the width of the second electrode layer.

[0014] The first electrode layer may not overlap at least a portion of the bump portion and the second electrode layer in the lamination direction.

[0015] The above first electrode layer can overlap with the bump portion in the lamination direction.

[0016] The first electrode layer may be a chemical plating layer, the second electrode layer may be an electroplating layer, and the bump portion may be an electroplating layer.

[0017] The protective layer may include a first sub-layer and a second sub-layer disposed on the first sub-layer.

[0018] The second sub-layer can penetrate the first sub-layer.

[0019] The second sub-layer may be in contact with the upper surface of a plurality of insulating layers of the second build-up structure.

[0020] The second sub-layer may be positioned between adjacent first electrode layers.

[0021] The second sub-layer may include a first region horizontally overlapping with the first electrode layer, a second region horizontally overlapping with the first sub-layer, and a third region disposed on top of the first sub-layer.

[0022] The above first region may not overlap horizontally with the above first sub-layer.

[0023] The second region has an inclined outer surface and can overlap with the second electrode layer in a horizontal direction.

[0024] The above bump portion includes a via portion penetrating the protective layer and a protrusion portion arranged on the via portion, and the third region can be in contact with the protrusion portion.

[0025] The above protrusion can be embedded in the third region.

[0026] The upper surface of the third region may be located above the lower surface of the protrusion.

[0027] The third region may overlap at least partially with the protrusion in the horizontal direction.

[0028] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which the mechanical reliability and electrical reliability are improved by not forming the bump portion into multiple layers even if the bump portion is fine due to a difference in width between the upper surface of the bump portion in the protective layer and the upper wiring layer at the top of the build-up structure, and thus the phenomenon of separation between the upper wiring layer and the bump portion, which are fine patterns, being easily suppressed when combined, is improved.

[0029] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which improve electrical reliability by increasing the bonding surface between sublayers through a protective layer in which the first sublayer penetrates the second sublayer, protect the substrate from moisture, contaminants, and chemical damage in the external environment, and improve the durability of the substrate.

[0030] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0031] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention;

[0032] Figure 2 is an enlarged view of part K1 in Figure 1,

[0033] Figure 3 is a plan view of the upper wiring layer in the area where the protective layer has been removed in the circuit board according to the embodiment;

[0034] Figure 4 is an enlarged view of part K2 in Figure 1,

[0035] Figure 5 is another example of Figure 3,

[0036] Figure 6 is a drawing taken along line II' in Figure 5,

[0037] Figure 7 is a drawing taken along the line JJ' in Figure 5.

[0038] Figures 8 to 16 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0039] Fig. 17 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0040] Fig. 18 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0041] Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0042] Fig. 20 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0043] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0044] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0045] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0046] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0047] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0048] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0049] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0050] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0051] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0052] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0053] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0054] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. For example, these are referred to as a first horizontal direction (x-axis), a second horizontal direction (y-axis), and a vertical direction (z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0055] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0056] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0057] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0058] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0059] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0060] The circuit board may include a plurality of laminated insulating layers, wiring or circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the wiring or circuit patterns arranged within each of the insulating layers.

[0061] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of the above-mentioned. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0062] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and may be placed between the semiconductor elements and the circuit board. For example, the connecting member may be embedded in the circuit board, or may be placed on the circuit board. When embedded in the circuit board, it may have the advantage of being able to reduce the thickness of the semiconductor package. The connecting member may be formed of silicon, but is not limited thereto, and may be formed of an organic material. Since it functions to electrically interconnect a plurality of semiconductor elements, it may be referred to as a bridge.

[0063] Additionally, the connecting member may be positioned on a circuit board. When positioned on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a rewiring section may be positioned between the molding member and the semiconductor element.

[0064] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0065] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0066] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view of a portion K1 in FIG. 1, FIG. 3 is a plan view of an upper wiring layer in a region where a protective layer has been removed in a circuit board according to an embodiment, and FIG. 4 is an enlarged view of a portion K2 in FIG. 1.

[0067] Referring to FIG. 1, a circuit board (100) according to an embodiment may include an insulating layer (110) and an electrode portion (120). Furthermore, the circuit board (100) may further include a protective layer disposed on the electrode portion (120) or a core layer, which is an insulating layer disposed within the insulating layer (110). In addition, as illustrated, the circuit board may have a coreless structure.

[0068] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0069] In addition, the circuit board may include a first build-up structure (BT1) and a second build-up structure (BT2). For example, when the circuit board is a core board, the circuit board may include a core layer and a core electrode portion in either the first build-up structure (BT1) or the second build-up structure (BT2). In addition, when the circuit board is a coreless board, the insulating layer (110) may include the first build-up structure (BT1) and the second build-up structure (BT2) that are sequentially stacked in a stacking direction (Y-axis direction). The first build-up structure (BT1) may include a plurality of insulating layers, a plurality of wiring layers (PE1) disposed on the plurality of insulating layers, and a plurality of via electrodes (UE1) that connect the plurality of wiring layers (PE1) in a vertical direction (Y-axis direction). Additionally, the second build-up structure (BT2) may include a plurality of insulating layers, a plurality of wiring layers (PE2) arranged on the plurality of insulating layers, and a plurality of via electrodes (UE2) connected in a vertical direction (Y-axis direction) to the plurality of wiring layers (PE2).

[0070] In the present embodiment, the second build-up structure (BT2) may be positioned on the first build-up structure (BT1). The plurality of insulating layers of the first build-up structure (BT1) and the plurality of insulating layers of the second build-up structure (BT2) may include different materials. For example,

[0071] The plurality of insulating layers of the first build-up structure (BT1) and the plurality of insulating layers of the second build-up structure (BT2) may be formed of fillers having different sizes. The size of the filler in the plurality of insulating layers of the first build-up structure (BT1) may be larger than the size of the filler in the plurality of insulating layers of the second build-up structure (BT2). For example, the plurality of insulating layers of the second build-up structure (BT2) may include nano fillers. In addition, the width (or spacing) of the wiring layer (PE1) disposed on the plurality of insulating layers of the first build-up structure (BT1) may be larger than the width (or spacing) of the wiring layer (PE2) disposed on the plurality of insulating layers of the second build-up structure (BT2).

[0072] In addition, the plurality of via electrodes (UE1) of the first build-up structure (BT1) may include inclined via electrodes so that the width (Wa) varies along the vertical direction (Y-axis direction). The first build-up structure (BT1) may have a plurality of via electrodes having different inclined angles. In addition, when the core layer is disposed on the first build-up structure (BT1), the width of the via electrode may increase in some areas and decrease in other areas along the stacking direction.

[0073] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0074] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated.

[0075] In addition, the build-up layer or insulating layer (110) of the first and second build-up structures may be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material provided with glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF. And each insulating layer may be composed of the same or different materials.

[0076] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0077] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element. Furthermore, the wiring portion may include a plurality of wiring layers as described above.

[0078] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on the insulating layer. The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0079] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. The circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. The circuit pattern arranged on the upper and lower surfaces of the insulating layer may be electrically connected to a semiconductor element and / or a main board or substrate.

[0080] Furthermore, the electrode portion (120) may further include additional electrode portions arranged on the additional insulating layer when an additional insulating layer is present. Each electrode portion may include a wiring portion and a via electrode as described above.

[0081] In addition, the circuit board (100) may further include a protective layer (SR) disposed on the outside of the insulating layer (110). For example, a protective layer may be further disposed on the top or bottom. The protective layer (SR) may have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (SR) may be formed of a material that has insulating properties for electrical connection. The protective layer (SR) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler, which is a reinforcing member, and a resin.

[0082] A protective layer (SR) may be disposed on an insulating layer (110). And the protective layer (SR) may include a plurality of fillers.

[0083] And the insulating layer or protective layer (SR) located on the outside of the circuit board may have an opening. Through the opening, it can be electrically connected to other semiconductor elements, the circuit board, etc.

[0084] Furthermore, a bump portion (not shown) may be disposed on the outer side of the circuit board on the protective layer (SR). For example, the bump portion (not shown) may be disposed on the upper surface of the protective layer (SR). The bump portion (not shown) may include a protrusion portion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion portion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR).

[0085] A metal layer is additionally disposed on the bump portion (not shown) and can be electrically connected. Accordingly, the durability and reliability of the bump portion (not shown) can be further improved. For example, the metal layer can be formed of at least one metal layer. The metal layer can be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bump portion (not shown) is improved, the corrosion resistance and durability of the bump portion (not shown) are improved, and the loss of electrical signals can be minimized. The metal layer can be formed on the bump portion (not shown) by deposition, electroplating, or the like of various metals.

[0086] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0087] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0088] Referring further to FIGS. 2 to 4, as described above, the second build-up structure (BT2) may include a plurality of insulating layers, a plurality of wiring layers (PE2) disposed on the plurality of insulating layers, and a plurality of via electrodes (UE2) connecting the plurality of wiring layers (PE2) in the vertical direction (Y-axis direction). The plurality of wiring layers (PE2) may include an upper wiring layer (UUE) disposed at the uppermost portion of the second build-up structure (BT2). For example, the upper wiring layer (UUE) may be located on an upper surface of the uppermost insulation layer among the plurality of insulating layers in the second build-up structure (BT2). Accordingly, the upper wiring layer (UUE) may be a wiring layer that is closest to the protective layer (SR1) in the second build-up structure (BT2).

[0089] Additionally, the upper wiring layer (UUE) may include a first electrode layer (L1) and a second electrode layer (L2). The first electrode layer (L1) and the second electrode layer (L2) may have different widths. For example, the width (W1) of the first electrode layer (L1) may be greater than the width (W3) of the second electrode layer (L2). Alternatively, the maximum width (W1) of the first electrode layer (L1) may be greater than the maximum width (W3) of the second electrode layer (L2).

[0090] The first electrode layer (L1) can be in contact with the second electrode layer (L2). The first electrode layer (L1) can overlap with the second electrode layer (L2) in the lamination direction (Y-axis direction). And at least a portion of the first electrode layer (L1) may not overlap with the second electrode layer (L2) in the lamination direction (Y-axis direction). Hereinafter, the maximum width may correspond to the length in one direction perpendicular to the lamination direction.

[0091] Furthermore, the maximum width (W1) of the first electrode layer (L1) may be different from the maximum width (W2) of the bump portion (BP). For example, the maximum width (W1) of the first electrode layer (L1) may be greater than the maximum width (W2) of the bump portion (BP). In addition, the width of the bump portion (BP) at the protrusion (PP) may be greater than the width at the via portion (TP). Accordingly, the maximum width at the protrusion (PP) may correspond to the maximum width (W3) at the bump portion (BP).

[0092] And at least a portion of the first electrode layer (L1) may not overlap with the bump portion (BP) and the second electrode layer (L2) in the lamination direction (Y-axis direction). The first electrode layer (L1) may extend further outward from the lower portion of the second electrode layer (L2) on the upper side to the outer surface of the second electrode layer (L2).

[0093] In addition, the thickness (t1) of the first electrode layer (L1) may be smaller than at least one of the thickness (t2) of the second electrode layer (L2) and the thickness (t3) of the protrusion (PP). In this way, by increasing the thickness of the electroplating layer, the rigidity of the electrode can be significantly maintained when electrically connecting by penetrating the insulating layer between the micro-patterns on the upper part of the second build-up structure. Accordingly, the reliability of the circuit board can be improved.

[0094] In addition, the first electrode layer (L1) may be in contact with the second electrode layer (L2), and the second electrode layer (L2) may be in contact with the bump portion (BP) on the upper side. In an embodiment, the first electrode layer (L1) may overlap with the bump portion (BP) in the lamination direction (Y-axis direction). The first electrode layer (L1) and the bump portion (BP) that overlap in the lamination direction (Y-axis direction) may be electrically connected. In addition, in the first electrode layer (L1), the second electrode layer (L2), and the bump portion (BP) that are electrically connected, the second electrode layer (L2) may be located between the bump portion (BP) and the first electrode layer (L1).

[0095] In addition, in the embodiment, the first electrode layer (L1), the second electrode layer (L2), and the bump portion (BP) may be formed by plating. For example, at least two of the first electrode layer (L1), the second electrode layer (L2), and the bump portion (BP) may be different plating layers. The first electrode layer (L1) may be a chemical plating layer. And the second electrode layer (L2) and the bump portion (BP) may be electroplating layers. Accordingly, the average grain size of the first electrode layer (L1) may be smaller than the average grain size of the second electrode layer (L2) (bump portion).

[0096] By this configuration, the boundary between the upper wiring layer, which is a micro-pattern, and the bump portion can be formed by the same plating method, rather than the boundary between the chemical plating layer and the electroplating layer. In particular, the boundary between the upper wiring layer and the bump portion can be the boundary between the electroplating layers. Accordingly, improved rigidity can be maintained even in the connection between the upper wiring layer and the bump portion. Accordingly, the phenomenon of separation between the upper wiring layer, which is a micro-pattern, and the bump portion when joined can be easily suppressed. Accordingly, a circuit board with improved mechanical and electrical reliability can be provided.

[0097] The first electrode layer (L1) may overlap with the bump portion (BP) in the lamination direction (Y-axis direction). And at least a portion (NOV) of the first electrode layer (L1) may not overlap with the bump portion (BP) in the lamination direction (Y-axis direction).

[0098] Additionally, in an embodiment, the protective layer may include multiple layers. The first protective layer (SR1) may include a first sub-layer (SR1a) and a second sub-layer (SR1b).

[0099] The first sub-layer (SR1a) may be positioned below the first protective layer (SR1). The first sub-layer (SR1a) may be in contact with the second build-up structure (BT2). For example, the first sub-layer (SR1a) may be in contact with the upper surface of the second build-up structure (BT2). In addition, the first sub-layer (SR1a) may be in contact with the upper wiring layer (UUE). In addition, the first sub-layer (SR1a) may surround the via portion (TP). The first sub-layer (SR1a) may be in contact with the via portion (TP). The first sub-layer (SR1a) may be in contact with the protrusion portion (PP). For example, the first sub-layer (SR1a) may be in contact with the bottom surface of the protrusion portion (PP).

[0100] The second sublayer (SR1b) may be positioned on the first sublayer (SR1a). The second sublayer (SR1b) may surround the first sublayer (SR1a). Additionally, the second sublayer (SR1b) may penetrate the first sublayer (SR1a).

[0101] This configuration can improve electrical reliability by increasing the bonding surface between sublayers, protect the substrate from moisture, contaminants, and chemical damage in the external environment, and enhance the durability of the substrate.

[0102] The second sub-layer (SR1b) can penetrate the first sub-layer (SR1a) and contact the upper wiring layer (UUE) under the first sub-layer (SR1a). The second sub-layer (SR1b) can contact the upper surfaces of the multiple insulating layers of the second build-up structure. For example, the second sub-layer (SR1b) can contact the insulating layer on which the upper wiring layer (UUE) is formed.

[0103] Additionally, the second sub-layer (SR1b) may be in contact with the outer surface (ES2) of the upper wiring layer (UUE). Furthermore, the second sub-layer (SR1b) may be in contact with the outer surface (ES1) of the first sub-layer (SR1a). Additionally, the second sub-layer (SR1b) may be in contact with the lower surface (BS1) of the first sub-layer (SR1a).

[0104] Additionally, the second sub-layer (SR1b) may also be in contact with the bump portion (BP). The second sub-layer (SR1b) may be in contact with the outer surface (ES3) of the protrusion portion (PP). Furthermore, the second sub-layer (SR1b) may be spaced apart from the via portion (TP).

[0105] The second sub-layer (SR1b) may be positioned between adjacent first electrode layers (L1). The second sub-layer (SR1b) may penetrate the first sub-layer (SR1a) between adjacent first electrode layers (L1).

[0106] Specifically, the second sub-layer (SR1b) may include a first region (AR1), a second region (AR2), and a third region (AR3). The first region (AR1), the second region (AR2), and the third region (AR3) may be sequentially positioned in the stacking direction (Y-axis direction).

[0107] The second sub-layer (SR1b) may be positioned between adjacent first sub-layers (SR1a). In the second sub-layer (SR1b), the first region (AR1) may be positioned at the lowermost portion. Furthermore, the first region (AR1) may be in contact with the outer surface (ES2) of the upper wiring layer (UUE). The first region (AR1) may horizontally overlap with the upper wiring layer (UUE). In addition, at least a portion of the first region (AR1) may not horizontally overlap with the first sub-layer (SR1a). However, in various examples, at least a portion of the first region (AR1) may horizontally overlap with the first sub-layer (SR1a).

[0108] The second region (AR2) may be a region penetrating the first sub-layer (SR1a) in the second sub-layer (SR1b). In addition, the second region (AR2) may horizontally overlap the first sub-layer (SR1a) on the upper wiring layer (UUE).

[0109] In addition, the outer surface of the second region (AR2) may be in contact with the outer surface (ES1) of the first sub-layer (SR1a). For example, the outer surface of the second region (AR2) may correspond to the outer surface (ES1) of the first sub-layer (SR1a). And the outer surface of the second region (AR2) may be inclined. The width (W5) of the second region (AR2) may increase along the stacking direction (Y-axis direction). For example, the width on the upper surface of the second region (AR2) may be greater than the width on the lower surface of the second region (AR2).

[0110] Additionally, the second region (AR2) can overlap the second electrode layer (L2) in the horizontal direction (X-axis direction).

[0111] The third region (AR3) may be located on the second region (AR2). The third region (AR3) may be in contact with the outer surface (ES3) of the protrusion (PP). The third region (AR3) may be spaced apart from the via portion (TP). In addition, the third region (AR3) may not horizontally overlap with the via portion (TP). In addition, in a horizontal direction perpendicular to the stacking direction (Y-axis direction), the width (W4) of the first region (AR1) may be different from the width (W5) of the second region (AR2). For example, the width (W4) of the first region (AR1) may be greater than the minimum width of the second region (AR2). In addition, the width (W4) of the first region (AR1) may be less than the maximum width of the second region (AR2).

[0112] And the width (W6) of the third region (AR3) may be greater than the width (W4) of the first region (AR1). And the width (W6) of the third region (AR3) may be greater than the width (W5) of the second region (AR2).

[0113] In addition, the protrusion (PP) may be embedded in the third region (AR3). The third region (AR3) may be located between adjacent protrusions (PP). For example, the upper surface (TS) of the protrusion (PP) may be located below the upper surface (TS) of the third region (AR3). In addition, the upper surface (TS) of the third region (AR3) may be located above the lower surface of the protrusion (PP). In addition, the upper surface (TSS) of the second sub-layer (SR1b) and the upper surface (TS) of the bump portion (BP) may be spaced apart from each other by a predetermined distance (gap1). In this case, the predetermined distance (gap1) may be smaller than the thickness of the protrusion (PP).

[0114] Furthermore, the third region (AR3) may overlap at least partially with the protrusion (PP) in the horizontal direction (X-axis direction).

[0115] When the bump portion and the first protective layer (SR1) are removed, the upper wiring layer (UUE) may be exposed. A plurality of upper wiring layers (UUE) may be electrically isolated from each other. At this time, the first electrode layer (L1), which is a chemical plating layer, may have a larger area than the second electrode layer (L2). However, adjacent first electrode layers (L1) may be spaced apart from each other by a predetermined distance (gap).

[0116] The second electrode layer (L2) may be overlapped in the stacking direction on the first electrode layer (L1). And the width (W1) of the first electrode layer (L1) may be greater than the width (W3) of the second electrode layer (L2).

[0117] Fig. 5 is another example of Fig. 3, Fig. 6 is a drawing taken along line II' in Fig. 5, and Fig. 7 is a drawing taken along line JJ' in Fig. 5.

[0118] Referring to FIGS. 5 to 7, the above-described contents may be equally applied except for the contents described below in other examples.

[0119] In this example, the second sub-layer (SR1b) can be in contact with the outer surface (ES2) of the upper wiring layer (UUE).

[0120] Additionally, the first sub-layer (SR1a) may cover the upper wiring layer (UUE). For example, the first sub-layer (SR1a) may contact the outer surface (ES2) of the upper wiring layer (UUE) in some areas.

[0121] And the second sub-layer (SR1b) can be in contact with the outer surface (ES1) of the first sub-layer (SR1a). In addition, the second sub-layer (SR1b) can be in contact with the lower surface (BS1) of the first sub-layer (SR1a). At this time, the lower surface (BS1) of the first sub-layer (SR1a) in contact with the second sub-layer (SR1b) can be located on the upper wiring layer (UUE).

[0122] Furthermore, the outer surface (ES2') of the second electrode layer (L2) can be spaced apart from the second sub-layer (SR1b) in the horizontal direction.

[0123] Additionally, the second electrode layer (L2) may have the same width as the first electrode layer (L1) in some areas. That is, the outer surface (ES2') of the second electrode layer (L2) and the outer surface (ES2) of the first electrode layer (L1) may form the same surface at least in some areas.

[0124] Furthermore, the first electrode layer (L1) and the second electrode layer (L2) may have different areas. And the first electrode layer (L1) and the second electrode layer (L2) may have different widths in a direction perpendicular to the stacking direction (Y-axis direction).

[0125] Furthermore, a part of the first electrode layer (L1) may overlap with the second electrode layer (L2) in the lamination direction (Y-axis direction). And at least a part of the first electrode layer (L1) may not overlap with the second electrode layer (L2) in the lamination direction (Y-axis direction). In addition, at least a part of the second electrode layer (L2) may not overlap with the first electrode layer (L1) in the lamination direction (Y-axis direction). The area (S2) where the first electrode layer (L1) and the second electrode layer (L2) come into contact with each other may have a different area from the area (S1) of the second electrode layer (L2) that does not overlap with the first electrode layer (L1). For example, the area (S2) where the first electrode layer (L1) and the second electrode layer (L2) come into contact with each other may have a smaller area than the area (S1) of the second electrode layer (L2) that does not overlap with the first electrode layer (L1).

[0126] This configuration allows for enhanced rigidity to be maintained even in the connection between the upper wiring layer and the bump portion. Therefore, the phenomenon of separation between the finely patterned upper wiring layer and the bump portion during bonding can be easily suppressed. Furthermore, the first electrode layer can prevent electrical short-circuiting between adjacent wiring or bump portions. In other words, the electrical reliability of the circuit board can be improved.

[0127] Figures 8 to 16 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0128] First, referring to FIG. 8, a build-up layer or core layer for forming a build-up layer and an electrode portion can be first prepared. Hereinafter, the description will be based on the first build-up structure and the second build-up structure (BT2) being formed under the seed layer (SE). In addition, the first build-up structure will be described as being formed under the second build-up structure (BT2).

[0129] A seed layer (SE) may be formed on the second build-up structure (BT2). The seed layer (SE) may be formed by performing electroless plating. A seed layer (SE) film (DF) may be formed. For example, the film (DF) may be a dry film. In addition, the film (DF) may include various masks for performing masking. Furthermore, lamination may be performed on the film (DF) on the second build-up structure (BT2). For example, the film (DF) may be attached to the seed layer (SE) using heat and pressure. Before this lamination, cleaning may be performed on the surface of the seed layer (SE), etc. In addition, removal of air bubbles, etc. may be performed after the lamination.

[0130] Additionally, the film (DF) can be irradiated with light. This irradiation of light can form a desired pattern. For example, when the film (DF) is irradiated with light, a pattern can be formed in various ways. The pattern can be formed using a positive method or a negative method. For example, an opening (G1) can be formed in the film (DF).

[0131] Referring to FIG. 9, an electrode layer (EL1) can be formed on a seed layer (SE) by electroplating. The electrode layer (EL1) can correspond to a second electrode layer (L2) described later.

[0132] Referring to Fig. 10, the film (DF) can be removed. Then, a first sub-layer (SR1a) can be formed on the seed layer (SE) and the second electrode layer (L2).

[0133] Referring to FIG. 11, an opening or via (G2) can be formed in the first sub-layer (SR1a). Accordingly, the second electrode layer (L2) can be exposed by the via (G2).

[0134] Referring to Fig. 12, a patterned film or the like may be further formed on the first sub-layer (SR1a). As described above, various methods of patterned dry films may be applied to the patterned film.

[0135] And a via portion (TP) can be formed in the via (G2). The via portion (TP) can be formed by various methods. For example, it can be formed by various methods such as electroplating, deposition, and filling. In particular, the via portion (TP) can be formed by electroplating based on the underlying seed layer (SE) without a chemical plating layer. This can also be applied to the protrusion portion (PP).

[0136] Referring to FIG. 13, an opening or via (G3) may be formed in a portion of the first sub-layer (SR1a). The via (G3) may be located between adjacent second electrode layers (L2) or between adjacent bump portions (BP). The seed layer (SE) may be exposed by the via (G3).

[0137] Referring to FIG. 14, a portion of the seed layer may be removed. The opening (G3') may be further extended into the seed layer. Thus, a first electrode layer (L1) may be formed. A portion of the seed layer may be removed by various methods. For example, a portion of the seed layer may be removed by various etching methods. For example, the seed layer in contact with the adjacent bump portion (BP) may not be connected to each other by such etching.

[0138] Referring to FIG. 15, a second sub-layer (SR1b') may be formed on the first sub-layer (SR1a). Accordingly, the second sub-layer (SR1b') may be positioned in an opening of the first sub-layer (SR1a) and may penetrate the first sub-layer (SR1a). Furthermore, the second sub-layer (SR1b') may also be in contact with the upper wiring layer (UUE).

[0139] Referring to Fig. 16, a second sub-layer (SR1b) may be formed by thinning. The upper surface of the second sub-layer may contact the outer surface of the bump portion at an upper portion thereof. In other words, the upper surface of the second sub-layer (SR1b) may be located in the region between the upper surface of the bump portion (BP) and the upper surface of the first sub-layer (SR1a). Through this process, a circuit board may be manufactured.

[0140] Fig. 17 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 18 is a cross-sectional view showing a semiconductor package according to the second embodiment, Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 20 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0141] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0142] Referring to FIG. 17, the semiconductor package of the embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0143] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0144] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0145] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0146] A second substrate (1200) may be placed on the first substrate (1100).

[0147] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0148] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0149] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0150] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may function as an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between a second logic chip disposed thereon and the first substrate (1100).

[0151] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have a passive device function such as a resistor, a capacitor, or an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the embodiment, a second substrate (1200) may be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) may include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0152] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0153] Meanwhile, the semiconductor package of the embodiment may include a connection portion.

[0154] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0155] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0156] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0157] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0158] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0159] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0160] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0161] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0162] Additionally, looking further into FIG. 17, the semiconductor package of the embodiment may further include a connecting member (1210).

[0163] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution portion. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution portion. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution portion may include a function of performing a buffering function.

[0164] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0165] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0166] Referring to FIG. 18, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the embodiment.

[0167] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0168] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0169] Referring to FIG. 19, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0170] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the embodiment.

[0171] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0172] Referring to FIG. 20, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0173] In this way, the semiconductor package of the fourth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0174] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0175] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0176] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0177] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0178] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0179] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0180] The semiconductor package of the fourth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0181] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0182] Meanwhile, the third semiconductor element (1330) in the fourth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0183] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0184] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0185] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0186] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0187] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0188] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A first build-up structure including a plurality of insulating layers stacked along a vertical direction, a plurality of wiring layers arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring layers along the vertical direction; A second build-up structure including a plurality of insulating layers arranged on the first build-up structure and stacked along a vertical direction, a plurality of wiring layers arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring layers along the vertical direction; and A protective layer disposed on the second build-up structure; The horizontal spacing between the plurality of wiring layers of the first build-up structure is greater than the horizontal spacing between the plurality of wiring layers of the second build-up structure, The plurality of wiring layers of the second build-up structure include an upper wiring layer most adjacent to the protective layer, The upper wiring layer includes a first electrode layer and a second electrode layer disposed on the first electrode layer, It further includes a bump portion including a via portion disposed on the second electrode layer and penetrating the protective layer, and a protrusion disposed on the via portion, A circuit board wherein the thickness of the first electrode layer is smaller than the thickness of the second electrode layer or the thickness of the protrusion.

2. In paragraph 1, A circuit board wherein the maximum width of the first electrode layer is greater than the maximum width of the bump portion.

3. In paragraph 1, A circuit board in which the first electrode layer and the second electrode layer have different widths.

4. In paragraph 3, A circuit board wherein the width of the first electrode layer is greater than the width of the second electrode layer.

5. In paragraph 1, A circuit board in which at least a portion of the first electrode layer does not overlap with the bump portion and the second electrode layer in the lamination direction.

6. In paragraph 1, A circuit board in which the first electrode layer overlaps the bump portion in the stacking direction.

7. In paragraph 1, The above first electrode layer is a chemical plating layer, The above second electrode layer is an electroplated layer, The above bump portion is a circuit board with an electroplated layer.

8. In paragraph 1, A circuit board comprising a first sub-layer and a second sub-layer disposed on the first sub-layer.

9. In paragraph 8, The second sub-layer is a circuit board that penetrates the first sub-layer.

10. In paragraph 8, The second sub-layer is a circuit board in contact with the upper surface of the plurality of insulating layers of the second build-up structure.

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