Circuit board and semiconductor package comprising same

Abstract

An embodiment of the present invention provides a circuit board comprising: a first build-up layer; a (1-1)-th wiring part disposed on the first build-up layer; and a (1-2)-th wiring part having a line / interval greater than that of the (1-1)-th wiring part, wherein the line / interval of the (1-1)-th wiring part is 1.7 to 3 μm.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] Furthermore, the formation of micro-patterns is essential for connecting dies on substrates such as interposers without embedding bridge substrates, etc. However, when forming micro-patterns, there are limitations such as reduced reliability of the electrodes or difficulty in manufacturing them, depending on the line width and thickness / width ratio.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which are easy to manufacture and have improved mechanical reliability, while the width and spacing of circuit patterns in a circuit board to which semiconductor elements are connected are reduced as a result of miniaturization, and at the same time, the wiring density per unit area is increased by having a predetermined line / spacing.

[0008] In addition, the embodiment can easily satisfy the electrical characteristics required for high-density interposers, etc. by densely arranging micropatterns and forming a thickness / width ratio within a predetermined range, and can implement a circuit board and a semiconductor package including the same with improved input / output counts through micropatterns.

[0009] In addition, the embodiment can easily implement a circuit board and a semiconductor package including the same, which can be miniaturized by having a smaller thickness than other build-up layers.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention includes a first build-up layer; and a first-first wiring portion arranged on the first build-up layer and a first-second wiring portion having a larger line / spacing than the first-first wiring portion; wherein the line / spacing of the first-first wiring portion is 1.7 μm to 3 μm.

[0012] The above 1-1 wiring section may include a lower region in the stacking direction, a middle region on the lower region, and an upper region on the middle region.

[0013] The lower region, the middle region and the upper region may have a length in each of the stacking directions greater than 0.5 times the line / spacing of the first-first wiring section.

[0014] The above lower region may include a first sub-region from the upper surface to the first surface having the smallest width or diameter, and a second sub-region from the first surface to the lower surface.

[0015] The angle formed by the outer surface of the first sub-region with the first surface may be different from the angle formed by the outer surface of the second sub-region with the first surface.

[0016] The above lower region may have a convex surface that is convex upward on the lower surface.

[0017] The above convex surface may be located below the first surface.

[0018] The above lower region may decrease in width or diameter from the upper surface toward the lower surface.

[0019] The width or area on the upper surface of the lower region may be greater than the width or area on the lower surface of the lower region.

[0020] The thickness of the above 1-1 wiring portion and the above 1-2 wiring portion may be 6 μm to 15 μm.

[0021] The aspect ratio (thickness / width) of the above-mentioned 1-1 wiring section may be 2.3 to 8.9.

[0022] The Aspect Ratio (thickness / width) of the above 1-2 wiring portion may be smaller than the Aspect Ratio (thickness / width) of the above 1-1 wiring portion.

[0023] A core layer; further comprising the first build-up layer may be disposed on an upper surface of the core layer.

[0024] It may include a lower build-up layer disposed under the core layer; and a second electrode portion including a second wiring portion and a second via electrode disposed on the lower build-up layer.

[0025] The line / spacing of the above second wiring section may be larger than the line / spacing of the above first wiring section.

[0026] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, which are easy to manufacture and have improved mechanical reliability, while the width and spacing of circuit patterns in a circuit board to which semiconductor elements are connected are reduced as a result of miniaturization, and at the same time, the wiring density per unit area is increased by having a predetermined line / spacing.

[0027] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which can easily satisfy electrical characteristics required for high-density interposers, etc. by densely arranging micropatterns and forming a thickness / width ratio within a predetermined range, and have improved input / output counts through micropatterns.

[0028] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which can be easily implemented as a miniaturized circuit board by having a small thickness compared to other build-up layers.

[0029] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0030] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0031] Figure 2 is an enlarged view of K1 in Figure 1,

[0032] Figure 3 is a plan view of a first wiring portion and a first build-up layer in a circuit board according to an embodiment;

[0033] Figure 4 is an enlarged view of part K2 in Figure 1,

[0034] Figure 5 is a drawing explaining the line / spacing effect of the 1-1 wiring section in a circuit board according to an embodiment.

[0035] Fig. 6 is a drawing of a first example of a first-1 wiring section in a circuit board according to an embodiment;

[0036] Fig. 7 is a drawing of a second example of the 1-1 wiring section in a circuit board according to an embodiment;

[0037] Fig. 8 is a drawing of a third example of the 1-1 wiring section in a circuit board according to an embodiment;

[0038] Figures 9 and 10 are photographs of the first-1 wiring section in the circuit board according to the embodiment.

[0039] Figures 11 to 16 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0040] FIG. 17 is a drawing of a circuit board and a laminated semiconductor element according to an embodiment of the present invention.

[0041] Fig. 18 is a drawing illustrating the arrangement of semiconductor elements on a circuit board according to an embodiment.

[0042] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0043] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0044] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0045] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0046] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0047] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0048] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0049] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0050] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0051] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0052] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0053] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0054] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0055] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0056] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0057] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0058] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0059] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0060] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0061] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0062] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0063] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view of K1 in FIG. 1, FIG. 3 is a plan view of a first wiring portion and a first build-up layer in a circuit board according to an embodiment, FIG. 4 is an enlarged view of a portion of K2 in FIG. 1, FIG. 5 is a drawing explaining the effect of each line / spacing of a 1-1 wiring portion in a circuit board according to an embodiment, FIG. 6 is a drawing of a first example of a 1-1 wiring portion in a circuit board according to an embodiment, FIG. 7 is a drawing of a second example of a 1-1 wiring portion in a circuit board according to an embodiment, FIG. 8 is a drawing of a third example of a 1-1 wiring portion in a circuit board according to an embodiment, and FIGS. 9 and 10 are photographs of a 1-1 wiring portion in a circuit board according to an embodiment.

[0064] Referring to FIG. 1, a circuit board (100) according to an embodiment may include an insulating layer (110) and an electrode portion (120). In an embodiment, the insulating layer (110) may be provided in a structure in which a plurality of insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the plurality of insulating layers (110), thereby performing a function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0065] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (111), a build-up insulating portion (112, 113), a core electrode portion (121), and a build-up electrode portion (122, 123). In addition, in the following embodiments of the present invention, the build-up insulating portion (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated.

[0066] The build-up electrode portions (122, 123) are disposed and embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby transmitting signals and / or power from the main board (not shown) to the semiconductor elements. In addition, when the circuit board includes a core layer, it may include a core layer disposed within the insulating layer (110).

[0067] As an example, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0068] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0069] First, the insulation layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion. The following description will be based on this.

[0070] As another example, the insulating layer (110) is described as including a core layer, but the circuit board may be formed without a core.

[0071] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). For example, the core layer (111) may be disposed at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be positioned at the center of the insulating layer (110). That is, the upper build-up layer (112) may be disposed on the core layer (111), and the lower build-up layer (113) may be positioned below the core layer (111).

[0072] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0073] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0074] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and may have a thickness in the vertical direction (Y-axis direction or lamination direction) of several tens of micrometers to several hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (Y-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0075] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0076] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0077] Furthermore, the upper build-up layer (112) may include a first build-up layer (112a) in contact with the core layer (111) and a second build-up layer (112b) disposed on top of the first build-up layer (112a). In the stacking direction (Y-axis direction) or vertical direction, the first build-up layer (112a) may be positioned between the second build-up layer (112b) and the core layer (111).

[0078] As another example, the first build-up layer (112a) and the second build-up layer (112b) may be formed of fillers having different sizes. For example, the second build-up layer (112b) may have a filler smaller in size than the first build-up layer (112a). For example, the second build-up layer (112b) may include a nano-filler. In addition, the second build-up layer (112b) may be a layer on which an upper electrode portion having a smaller width or pitch than the first build-up layer (112a) is disposed.

[0079] In addition, in the circuit board (100) according to the embodiment, the electrode portion (120) is arranged for electrical connection between the main board, etc. and the chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0080] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0081] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0082] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0083] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0084] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0085] The upper electrode portion (122) may include a first wiring portion (122a) which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112) and a first via electrode (122b) which is a via electrode. The first via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0086] Furthermore, the lower electrode portion (123) may include a second wiring portion (123a) which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113) and a second via electrode (123b) which is a via electrode. In addition, the second via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0087] And in the embodiment, the first wiring portion (122a) of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion having a fine pitch (the first-first wiring portion (122aa)) and a wiring portion having a pitch larger than the first wiring portion (the first-second wiring portion (122ab)).

[0088] The first-second wiring section may refer to wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first-first wiring section may refer to fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width and spacing of the first-first wiring section may be several micrometers (㎛) or less. A detailed description thereof will be provided later.

[0089] Additionally, the circuit board (100) according to the embodiment may further include a protective layer (SR) and a bump portion (not shown).

[0090] In addition, a protective layer (SR) may be disposed on the outer side of the insulating layer (110). Specifically, the protective layer (SR) may have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between a semiconductor element and / or a main board and a circuit board, the protective layer (SR) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (SR) may be formed of a material having insulating properties for electrical connection. The protective layer (SR) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0091] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0092] The bump portion may be disposed on the protective layer (SR). For example, the bump portion may be disposed on the upper surface of the protective layer (SR). The bump portion may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bump portion may be located on the upper portion of the build-up electrode portions (122, 123). In addition, the bump portion may include a protrusion (not shown) disposed on the upper surface of the protective layer (SR) and a via portion (not shown) penetrating the protective layer (SR). In an embodiment, the via portion (not shown) and the protrusion (not shown) may each include a plurality of protrusions or convex portions protruding toward an adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (not shown) and the protrusion (not shown) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0093] Furthermore, a metal layer may be additionally disposed on the bump portion and electrically connected. Accordingly, the durability and reliability of the bump portion may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bump portion may be improved, the corrosion resistance and durability of the bump portion may be improved, and the loss of electrical signals may be minimized. The metal layer may be formed on the bump portion by deposition, electroplating, or the like of various metals.

[0094] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the aforementioned micro-pattern, such as the first-first wiring portion. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first-first wiring portion, which is a micro-pattern, may provide a function of a line for signal connection between semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0095] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0096] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0097] Referring further to FIGS. 2 to 4, in the embodiment, a first-first wiring portion (122aa) and a first-second wiring portion (122ab) may be arranged on the first build-up layer (112a). As described, the first-second wiring portion (122ab) may have a larger line / space than the first-first wiring portion (122aa).

[0098] Prior to this, the first-first wiring portion (122aa) and the first-second wiring portion (122aa) may have an inwardly concave groove at the bottom. For example, the first-first wiring portion (122aa) may have a first groove (G1), and the first-second wiring portion (122ab) may have a second groove (G2). The first groove (G1) and the second groove (G2) may be adjacent to the upper surface of the first build-up layer (112a). Accordingly, the width (W3) (maximum width) of the first-first wiring portion (122aa) may be greater than the minimum width (W4). In particular, the minimum width (W4) may be the width in an area adjacent to the lower surface rather than the upper surface of the first-first wiring portion (122aa). In addition, the width (W1) (maximum width) of the first-second wiring portion (122ab) may be greater than the minimum width (W2). And the minimum width (W4) of the 1-2 wiring section (122ab) may be the width in the area adjacent to the lower surface rather than the upper surface of the 1-2 wiring section (122ab).

[0099] Furthermore, the spacing (SW2) between adjacent 1-1 wiring portions (122aa) may be smaller than the spacing (SW1) between adjacent 1-2 wiring portions (122ab).

[0100] In an embodiment, the width (W1) of the 1-2 wiring portion (122ab) on the upper surface of the 1st build-up layer (112a) may be greater than the width (W3) of the 1-1 wiring portion (122aa). By this configuration, electrical connection between the via land and the via electrode can be easily achieved. In other words, a decrease in electrical reliability due to electrical disconnection can be prevented. In addition, the input / output count (I / O count) can be improved through the 1-1 wiring portion (122aa) which is a fine pattern. This configuration can be equally applied to the 1-2 wiring portion (122ab) of each electrode layer.

[0101] Post-exposure plating post-line / spacing (L / S, ㎛) Dry film adhesion (single line) Total Dry film edge sharp Unplated 1.5 33% 5% 96% 5% 18% 1.6 100% 22% 100% 22% 50% 1.7 100% 46% 100% 45% 75% 1.8 100% 74% 100% 74% 90% 1.9 100% 74% 100% 74% 90% 2.0 100% 83% 100% 83% 94% 2.1 100% 89% 100% 89% 98% 2.2 100% 96% 100% 96% 98% 2. 3100%98%100%98%99%2.4100%98%100%98%99%2.5100%99%100%99%99%2.6100%99%100%99%99%2.7100%99%100%99%100%2.8100%100%100%100%100%2.9100%100%100%100%3.0100%100%100%100%100%

[0102] Table 1 shows the results of defect inspection for multiple 1-1 wiring portions having different lines / spacings (e.g., 108 samples confirmed 'after plating') and dry films corresponding to the 1-1 wiring portions (e.g., 30 samples confirmed 'after exposure'). As shown in the table, when the lines / spacings of the 1-1 wiring portions are smaller than 1.7 μm, it can be seen that the dry films stick to each other, causing a disconnection between adjacent 1-1 wiring portions during plating, or the ends of the 1-1 wiring portions become sharp. More specifically, in the embodiment, the 1-1 wiring portions (122aa) may have lines / spacings of 1.7 μm to 3 μm. That is, the 1-1 wiring portions (122aa) may have a fine pattern. As a result, signal transmission efficiency can be improved. Furthermore, as described above in Table 1, since the line / spacing of the 1-1 wiring portion in the circuit board according to the embodiment is 1.7 μm to 3 μm, the problem of the dry films sticking to each other or the ends of the 1-1 wiring portions becoming sharp can be prevented. For example, when the line / spacing is smaller than 1.7 μm, when the dry film, which is a mask, is formed on the seed layer in forming the 1-1 wiring portion, there is a problem of adjacent dry films being connected to each other (see FIGS. 5(a) and 5(b)). For example, it can be seen that a short circuit occurs between adjacent 1-1 wiring portions (122aa) due to the connection of adjacent dry films in 'A1' of (a) in FIG. 5 and 'A2' of (b) in FIG. 5. In addition, as in (c) and (d) in FIGS. 5, the width (Wb) at the ends of the 1-1 wiring portions (122aa) may be smaller than the width (Wa) at the center in the extension direction. Furthermore, the spacing (SWa) at the ends between adjacent 1-1 wiring sections (122aa) may be greater than the spacing (SWb) at the center. In this way, since the 1-1 wiring sections (122aa) do not have uniform lines (widths) / spacing, both electrical characteristics and electrical reliability may deteriorate.Furthermore, when the line / spacing is greater than 3 μm, the wiring density per unit area decreases, which reduces the multi-channel I / O (input / output) capacity, which is a key requirement for a high-density interposer. In addition, the ratio of the insulating material of the first and second build-up layers to the volume on top of the core layer increases, which amplifies the mechanical stress due to the difference in thermal expansion coefficient, making electrical connection with the upper element difficult, and causing signal loss.

[0103] In summary, if the line / spacing of the 1-1 wiring section is less than 1.7 μm, the dry films may stick to each other, causing a short circuit, or the wiring ends may become sharp, preventing a uniform width from being maintained. This may result in a decrease in electrical reliability (e.g., signal loss, disconnection) and an increase in manufacturing defects. Furthermore, if the line / spacing of the 1-1 wiring section exceeds 3 μm, the wiring density per unit area may decrease, which may lower the multi-channel I / O capacity of the high-density interposer. In addition, the mechanical stress due to the difference in the thermal expansion coefficient of the insulating layer may increase, and the electrical connectivity with the upper element may be weakened, resulting in signal loss.

[0104] In contrast, the first-second wiring section (122ab) may have a larger line / spacing (e.g., 7 μm to 15 μm) than the first-first wiring section (122aa). For example, the first-second wiring section (122ab) may be connected to a lower substrate or a power supply or ground path.

[0105] In addition, if the line / spacing of the 1-2 wiring portion (122ab) is less than 7 μm, it becomes closer to a fine pattern and precision is required in the manufacturing process (e.g., exposure, plating), which may increase the defect rate. In addition, there may be a problem of reduced stability due to increased resistance when used as a power supply or ground path. In addition, if the line / spacing of the 1-2 wiring portion (122ab) exceeds 15 μm, if the wiring width becomes excessive, space utilization decreases, making high-density design difficult, and there is a possibility that the electrical connectivity with the fine pattern (1-1 wiring portion) on the upper side may be weakened. In addition, there is a problem of increased cost due to increased material usage.

[0106] Additionally, in the embodiment, the first-second wiring portion (122ab) may have the same thickness as the first-first wiring portion (122aa). The thickness (TT) of the first-first wiring portion (122aa) and the first-second wiring portion (122ab) may be about 6 μm to 15 μm (see FIG. 10).

[0107] Furthermore, if the thickness is less than 6 μm, the wiring cross-sectional area is reduced, increasing electrical resistance and degrading signal integrity. Furthermore, mechanical strength may be weakened, increasing the risk of damage during processing. Furthermore, if the thickness exceeds 15 μm, excessive thickness may result in interlayer height imbalances in the laminated structure and weakened connectivity with via electrodes. Furthermore, this may increase material costs and fail to meet thinning requirements.

[0108] Furthermore, the Aspect Ratio (thickness / width ratio) of the first-first wiring portion (122aa) may be 2.3 to 8.9. The Aspect Ratio (thickness / width ratio) of the first-first wiring portion (122aa) may be greater than the Aspect Ratio (thickness / width ratio) of the first-second wiring portion (122ab). That is, the first-first wiring portion (122aa) may have a large thickness relative to its width.

[0109] By this configuration, the first-first wiring section (122aa) can secure the cross-sectional area of ​​the wiring with a micro-pattern, thereby reducing electrical resistance and simultaneously improving signal integrity. Furthermore, by having the above-described aspect ratio, the first-first wiring section (122aa) can easily satisfy the electrical characteristics required for a high-density interposer.

[0110] Furthermore, since the 1-2 wiring section (122ab) has the aforementioned aspect ratio, low resistance and stability of the power line can be guaranteed.

[0111] Specifically, when the aspect ratio is less than 2.3, the small thickness-to-width ratio leads to insufficient wiring cross-sectional area, which increases electrical resistance and deteriorates signal integrity. Furthermore, when the aspect ratio exceeds 8.9, the excessive thickness-to-width ratio makes uniform formation difficult during manufacturing processes (e.g., plating, etching), increasing the risk of short circuits between wiring. Furthermore, mechanical stress can increase the likelihood of wiring peeling from the insulating layer.

[0112] Referring further to FIG. 6, the 1-1 wiring portion (122aa) may include a lower region (BA), a middle region (MA), and an upper region (UA) that are sequentially arranged in the stacking direction (Y-axis direction). The lower region (BA), the middle region (MA), and the upper region (UA) may have the same height in the stacking direction (Y-axis direction). That is, the lower region (BA), the middle region (MA), and the upper region (UA) may be regions divided into three equal parts in the stacking direction of the 1-1 wiring portion (122aa). The structure of this 1-1 wiring portion (122aa) is also shown in FIG. 9.

[0113] At this time, the lengths (Ta, Tb, Tc) of the lower region (BA), the middle region (MA), and the upper region (UA) may be greater than 0.5 times the line / spacing of the first-first wiring section (122aa). By this configuration, the mechanical strength of the wiring can be increased, and undercutting or over-etching that may occur during the manufacturing process can be easily prevented.

[0114] And the first-first wiring section (122aa) may have a first surface (S1) having the smallest width or diameter. The first surface (S1) may be located in the lower area (BA). And the lower area (BA) may include a first sub-area (SA1) between the first surface (S1) and the upper surface (US) and a second sub-area (SA2) between the first surface (S1) and the lower surface (BS).

[0115] At this time, the outer surface (ES1) of the first sub-area (SA1) and the first surface (S1) can form a first angle (θ). And the outer surface (ES2) of the second sub-area (SA2) and the first surface (S1) can form a second angle (θ). The first angle (θ) may be different from the second angle (θ). For example, the first angle (θ) may be smaller than the second angle (θ).

[0116] Furthermore, the height in the stacking direction (Y-axis direction) of the first sub-area (SA1) may be greater than the height in the stacking direction (Y-axis direction) of the second sub-area (SA2).

[0117] In the first sub-area (SA1), the width (or diameter) can increase in the stacking direction (Y-axis direction). And in the second sub-area (SA2), the width (or diameter) can decrease in the stacking direction (Y-axis direction).

[0118] Additionally, in the lower region (BA), the upper surface (US) may have a larger area or width than the lower surface (BS).

[0119] By this configuration, the bonding area between the build-up layer and the 1-1 wiring portion can be increased. Accordingly, the mechanical adhesive strength between the build-up layer and the 1-1 wiring portion can be improved, thereby improving the reliability of the circuit board. Furthermore, the lower gap between adjacent 1-1 wiring portions can be increased, thereby reducing the capacitance between adjacent wiring portions, thereby improving specific electrical characteristics and preventing short circuits between adjacent wiring portions. Furthermore, the mask design can be simplified when forming the 1-1 wiring portion.

[0120] Furthermore, in the first sub-area (SA1), the length in the lamination direction of the outer surface perpendicular to the first surface (S1) other than the first angle (θ) may be greater than the length of the outer surface (ES1) having the first angle (θ). This is also illustrated in detail in FIG. 9.

[0121] Referring to Fig. 7, as a second example, the first-first wiring section (122aa) may include a lower area (BA), a middle area (MA), and an upper area (UA) that are sequentially arranged in the stacking direction (Y-axis direction). In addition, the lower area (BA) may include a first sub-area (SA1) between the first surface (S1) and the upper surface (US), and a second sub-area (SA2) between the first surface (S1) and the lower surface (BS). Furthermore, the above-described contents may be applied except for the contents described below.

[0122] Furthermore, the length (Tk) of the outer surface perpendicular to the first surface (S1) in the lower region (BA) may be greater than the length (TL) of the region (outer surface, ES1) whose width decreases from the lower region (BA) to the first surface (S1). And the length (TL) of the region (outer surface, ES1) whose width decreases from the lower region (BA) to the first surface (S1) may be greater than the length (Tm) from the first surface (S1) to the lower surface (BS). The length (Tk) of the outer surface perpendicular to the first surface (S1) in the lower region (BA) may be greater than the length (Tm) from the first surface (S1) to the lower surface (BS).

[0123] Additionally, the lower region (BA) may have a convex surface (CS) that is convex upward from the lower surface (BS). The convex surface (CS) may be located below the first surface (S1). That is, the convex surface (CS) may be located in the second sub-region (SA2). In addition, the convex surface (CS) may not horizontally overlap with the first sub-region (SA1).

[0124] By this configuration, the contact area between the first-first wiring portion (122aa) and the lower build-up layer can be increased. By this configuration, the bonding strength between the lower build-up layer and the first-first wiring portion is improved, so that the circuit board according to the embodiment can provide improved mechanical reliability.

[0125] Additionally, a gap may exist between the lower surface of the first-first wiring section (122aa) and the lower build-up layer due to the convex surface (CS).

[0126] Referring to FIG. 8, in the third example, the first-first wiring section (122aa) may include a lower region (BA), a middle region (MA), and an upper region (UA) sequentially arranged in the stacking direction (Y-axis direction). In addition, the width (or diameter, WL) of the lower region (BA) may increase along the stacking direction (Y-axis direction). Alternatively, the width (or diameter) of the lower region (BA) may decrease from the upper surface (US) toward the lower surface (BS).

[0127] In addition, the third angle (θ) formed by the cross-sectional side (ES3a) and the lower surface (BS) in the lower area (BA) may be different from the fourth angle (θ) formed by the cross-sectional side (ES3b) and the lower surface (BS).

[0128] With this configuration, the adhesive strength between the first-first wiring portion and the build-up layer can be maintained uniformly. Consequently, the bonding area between the first wiring portion and the build-up layer increases, thereby improving peel strength. In other words, the mechanical reliability of the circuit board can be improved.

[0129] Additionally, the line / spacing of the second wiring section (123a) may be larger than the line / spacing of the first-first wiring section (122aa). In particular, the line / spacing of the wiring section in the lower build-up layer (113) may be larger than the line / spacing of the first-first wiring section (122aa).

[0130] Figures 11 to 16 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0131] Referring to Fig. 11, a carrier substrate can be prepared. For example, CCL (Copper Clad Laminate) can be used as the carrier board.

[0132] The carrier board may include a carrier insulating layer and a carrier metal layer disposed on at least one surface of the carrier insulating layer. In this case, as illustrated in the drawing, the carrier metal layer may be disposed on both surfaces of the carrier insulating layer. However, the present invention is not limited to this manufacturing method.

[0133] The manufacturing processes for the insulating layer, electrode layer, and via electrode of the circuit board described below can be performed on both sides of the carrier board. For example, in the embodiment, the processes described below can be performed on the upper and lower sides of the carrier board, respectively, to form multiple substrate layers at once. This can improve the mass productivity of the circuit board. The following description will focus on one side.

[0134] Referring to Fig. 12, the core electrode portion (121) can be formed by performing electrolytic plating, etc. on a carrier metal layer. At this time, the carrier metal layer can serve as a seed layer. To form the core electrode portion (121), dry film lamination, exposure and development, plating, dry film peeling, etching, etc. can be performed. For example, a dry film as a mask can be arranged to correspond to a via land and a pattern portion. Then, an opening can be formed in the dry film through an exposure and development process. Then, an electrode layer can be formed in the opening of the dry film. In other words, a via land and a pattern portion can be formed in the opening of the dry film. At this time, the first electrode layer can be formed by electrolytic plating, etc. And the dry film as a mask can be removed by peeling, etc. Then, an area excluding an area corresponding to the first electrode layer can be removed by etching, etc.

[0135] Referring to FIG. 13, a first build-up layer (112a) can be formed on the first electrode layer. The first build-up layer (112a) can be formed in various ways. The first build-up layer (112a) can be formed by performing thermal curing (e.g., lamination) on ABF.

[0136] And, a plating layer that functions as a seed layer can be formed on the first build-up layer (112a) by plating or the like. Furthermore, a via hole can be formed on the first build-up layer (112a), and a plating layer that functions as a seed layer can be additionally formed by plating or the like. Thereafter, a second via electrode can be formed by plating.

[0137] In addition, as described above, dry film lamination, exposure and development, plating, dry film peeling, etching, etc. may be performed to form the upper electrode portion (122) on the first build-up layer (112a). As a result, the upper electrode portion may be formed on the upper surface of the first build-up layer (112a).

[0138] Furthermore, FIGS. 14a to 14j illustrate the lines / spacing of the first-first wiring section at different position offsets (0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 (㎛)) when forming a pattern according to exposure on a dry film.

[0139] Table 2 shows the contents between the line / spacing of the 1-1 wiring section and the drawing for each position offset (0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 (㎛)) when forming a pattern according to exposure on a dry film.

[0140] Offset(㎛)0.0 (2.0 / 2.0)0.1 (1.9 / 2.1)0.2 (1.8 / 2.2)0.3 (1.7 / 2.3)0.4 (1.6 / 2.4)Based L / S=2 / 2(㎛ / ㎛)Fig. 14a 14b 14c 14d 14eOffset(㎛)0.5 (1.5 / 2.5)0.6 (1.4 / 2.6)0.7 (1.3 / 2.7)0.8 (1.2 / 2.8)0.9 (1.1 / 2.9)Based L / S=2 / 2(㎛ / ㎛)Fig. 14f 14g 14h 14i 14j

[0141] As shown in FIGS. 14a to 14j and Table 2, it can be seen that the change in line / spacing compared to the offset during exposure is small. That is, the formation of the 1-1 wiring portion in the circuit board according to the embodiment can be implemented more easily. Referring to FIG. 15, a second build-up layer (112b) can be formed on a first build-up layer (112a). The second build-up layer (112b) can be formed through thermal curing for ABF, etc. In addition, dry film lamination, exposure and development, plating, dry film peeling, etching, etc. can be performed to form the upper electrode portion (122). As a result, the upper electrode portion (122) can also be formed on the second build-up layer (112b).

[0142] Referring to Fig. 16, a protective layer (SR) may be formed on the upper build-up layer (112) and the lower build-up layer (113). To form the protective layer (SR), dry film lamination, exposure and development, plating, dry film peeling, etching, etc. may be performed.

[0143] FIG. 17 is a drawing of a circuit board and a laminated semiconductor element according to an embodiment of the present invention, and FIG. 18 is a drawing illustrating the arrangement of semiconductor elements on a circuit board according to an embodiment.

[0144] Referring to FIGS. 17 and 18, a package substrate including a circuit substrate according to an embodiment may include a main substrate in addition to a semiconductor element and a circuit substrate (100).

[0145] In such a package substrate, the circuit board (100) according to the embodiment may be an interposer placed between the main substrate and the semiconductor element. Furthermore, the circuit board (100) may be a substrate that performs a bridge function for the semiconductor element. Thus, the circuit board can improve yield and serve as a buffer with a fine pattern size.

[0146] Specifically, a plurality of semiconductor elements (SD1, SD1', SD2) may be mounted on the upper electrode portion, which is the outer side of the circuit board (100). The circuit board (100) may be any of the various circuit board examples described above. In addition, the circuit board (100) may have a connection region (R) connecting the plurality of semiconductor elements (DI1, DI1', DI2) to each other in adjacent portions. The connection region (R) may be formed of a wiring portion of a micro-pattern of the electrode layer as described above. In other words, a plurality of semiconductor elements may be connected to each other through the wiring portion (e.g., the 1-1 wiring portion) of the circuit board.

[0147] Furthermore, a bridge is formed within the circuit board, a first-first wiring portion is formed on the bridge, and the first-first wiring portion can connect the bridge and the semiconductor element.

[0148] Here, the plurality of semiconductor devices may include logic chips or memory chips as described above. In addition, the first semiconductor device (DI1, DI1') and the second semiconductor device (DI2) may be heterogeneous semiconductor devices as described above.

[0149] Furthermore, a pattern for connection with the main substrate under the circuit board (100) may be formed on the lower portion of the lower build-up layer. That is, the pattern portion, which is a fine pattern, may not be exposed on the lower portion of the circuit board (100). Furthermore, a protective layer may be additionally disposed on the upper surface of the uppermost insulating layer or the lower surface of the lowermost insulating layer.

[0150] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying power to semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0151] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0152] In addition, a circuit board according to an embodiment of the present invention may include a first build-up layer and a second build-up layer disposed on the first build-up layer. In addition, the first build-up layer and the second build-up layer may each include a plurality of laminated insulating layers. That is, the circuit board may be formed of insulating layers of the first build-up layer and the second build-up layer (or the first build-up layer and / or the second build-up layer). In addition, the upper build-up layer and the lower build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole may increase (increase) toward the upper side of the upper build-up layer. In addition, the width or area of ​​the via hole may decrease (increase) toward the upper side of the lower build-up layer. In addition, each build-up layer may correspond to an insulating layer other than the core layer. In addition, the circuit board may include a build-up structure, and when a core layer exists, the build-up structure may include an upper build-up layer, a core layer, and a lower build-up layer. Additionally, in the absence of a core layer, the build-up structure may include an upper build-up layer and a lower build-up layer, depending on the aforementioned expansion direction, etc. In an embodiment of the present invention, the build-up structure may include an upper build-up layer and a lower build-up layer. Furthermore, the build-up layer may be a different layer from the protective layer.

[0153] In addition, as described above, each build-up layer includes an insulating layer. For example, if a core layer exists in a circuit board, an upper build-up layer may be arranged on top of the core layer, and a lower build-up layer may be arranged under the core layer. In this case, the upper build-up layer and the lower build-up layer each include multiple insulating layers. In addition, if there is no core layer, the direction in which the width of the via increases may be different from each other. Accordingly, the circuit board can be divided into an upper build-up layer and a lower build-up layer.

[0154] In addition, as described above, the build-up layer is a different layer from the above-described protective layer, and the uppermost / lowest surface of the build-up layer (or insulating layer) corresponds to the uppermost / lowest surface of the build-up layer (insulating layer) placed on the top, and does not mean the uppermost / lowest surface of the protective layer. In other words, the uppermost surface of the insulating layer of the circuit board means the uppermost / lowest surface of the build-up layer, not the protective layer.

[0155] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0156] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First build-up layer; and It includes a 1-1 wiring section arranged on the first build-up layer and a 1-2 wiring section having a larger line / spacing than the 1-1 wiring section; A circuit board having a line / spacing of the above-mentioned 1-1 wiring section of 1.7 μm to 3 μm.

2. In paragraph 1, A circuit board including the first-first wiring section in the stacking direction, a lower region, a middle region on the lower region, and an upper region on the middle region.

3. In paragraph 2, A circuit board in which the lower region, the middle region, and the upper region each have a length in the stacking direction greater than 0.5 times the line / spacing of the first-first wiring section.

4. In paragraph 2, A circuit board including a first sub-region from the upper surface to the first surface having the smallest width or diameter, and a second sub-region from the first surface to the lower surface.

5. In paragraph 4, A circuit board in which the angle formed by the outer surface of the first sub-region with the first surface is different from the angle formed by the outer surface of the second sub-region with the first surface.

6. In paragraph 4, The above lower region is a circuit board having a convex surface convex upward on the lower surface.

7. In paragraph 6, The circuit board having the convex surface positioned below the first surface.

8. In paragraph 2, The above lower region is a circuit board whose width or diameter decreases from the upper surface to the lower surface.

9. In paragraph 2, A circuit board having a width or area on the upper surface of the lower region greater than a width or area on the lower surface of the lower region.

10. In paragraph 1, A circuit board having a thickness of the first-first wiring portion and the first-second wiring portion of 6 μm to 15 μm.

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