Circuit board, and semiconductor package including same

Abstract

An embodiment of the present invention provides a circuit board comprising: a core layer including a cavity; a connection member disposed in the cavity; and a dummy electrode disposed on the lower surface of the core layer and overlapping the cavity in the vertical direction, wherein the thickness of the dummy electrode is different from the thickness of a core wiring portion below the core layer.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to mount more semiconductor chips on a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices such as mobile devices, servers, and PCs, along with the adoption of High Bandwidth Memory (HBM), have led to larger semiconductor chip areas and the attachment of multiple semiconductor chips to a single package substrate to shorten the electrical connection distance between them, thereby increasing the size of the package. Furthermore, as the functions required for application processors increase, there is a growing need for separate processor chips for each function, and circuit boards capable of mounting these processor chips are required.

[0005] At this time, for the above application processor, even when it is separated into two processor chips by function, the number of terminals (Input / Output) provided in each processor chip is increasing.

[0006] Furthermore, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and faster communication speeds, the number of terminals on processor chips is steadily increasing due to the increase in power and signal capacity. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. Furthermore, increased circuit board area and thickness can make product miniaturization difficult, leading to reliability issues such as board warping and increased product price.

[0007] Furthermore, there is a recent trend to prevent problems such as warpage of circuit boards by making the core layer of the circuit board thicker. However, when using a thick core layer, there may be difficulties in yield, density of the spacing between via electrodes, and productivity in forming via electrodes in the core layer. In addition, in order to benefit from the process, components such as bridges are mounted in the build-up layer rather than the core layer to reduce manufacturing difficulty. In addition, in the case of interposers, components such as bridges are embedded in the core layer rather than the build-up layer to prevent degradation of signal integrity by ensuring that signal paths such as wiring paths and wiring structures are regularly formed. However, there is a problem that accuracy is significantly reduced when embedding components such as bridges in the core layer.

[0008] Additionally, there is a problem of reduced flatness of the build-up layer when embedding elements such as bridges within the core layer.

[0009] Additionally, the number (or count) of terminals (input / output, IO) provided on each processor chip is increasing, and the number of chips mounted on a circuit board is also increasing. Consequently, there is a need to increase the I / O count of circuit boards to correspond to this increase in terminals and the number of chips.

[0010] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which signal integrity is easily secured when electrically connecting an upper element and a connecting member by arranging a connecting member within a core layer as an interposer, mechanical strength is improved through a core layer having glass fiber, and in particular, alignment of the connecting member within a cavity is more accurately implemented by arranging a dummy electrode having a large thickness and spaced apart from the core wiring portion at the lower portion of the core layer.

[0011] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved thermal stability by suppressing cracks or peeling due to differences in thermal expansion by placing a connecting member in a cavity rather than a build-up layer, and by more easily dissipating heat generated from the connecting member through a dummy electrode at the bottom of the cavity.

[0012] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved electrical reliability by easily forming a build-up electrode portion in an upper build-up layer as a micro pattern or electrode pattern by arranging a connecting member in a core layer, thereby reducing an alignment error with an electrode of an upper element.

[0013] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved electrical characteristics by improving the flatness of the upper surface of the build-up layer on the upper surface of the cavity through the height and formation of the upper surface of the underfill within the cavity, thereby improving the quality of the electrode portion or the build-up layer.

[0014] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved bonding strength and improved thermal stability by controlling the height of the connecting member, the height of the underfill, and the thickness of the build-up layer on the cavity.

[0015] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which eliminate dimple and overfit issues by adjusting the height of the via electrode and the height of the connecting member even with a difference in the width (or diameter) of the via electrode, thereby achieving uniform plating.

[0016] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which a dimple or groove is formed in a build-up layer covering a connecting member to serve as an anchor during lamination of the build-up layers, thereby improving adhesive strength between the build-up layers and easily controlling warpage.

[0017] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0018] A circuit board according to an embodiment of the present invention comprises a core layer including a cavity; a connecting member disposed in the cavity; and a dummy electrode disposed on a lower surface of the core layer and vertically overlapping the cavity; wherein a thickness of the dummy electrode is different from a thickness of a core wiring portion under the core layer.

[0019] The thickness of the above dummy electrode may be greater than the thickness of the core wiring portion under the core layer.

[0020] The horizontal length of the dummy electrode may be greater than the horizontal length of the cavity.

[0021] It may include a bonding member disposed between the dummy electrode and the connecting member.

[0022] The above-mentioned bonding member may be placed within the cavity and may overlap the core layer in a horizontal direction.

[0023] The above dummy electrode may not overlap horizontally with the core layer.

[0024] The upper surface of the above dummy electrode can be in contact with the lower surface of the core layer.

[0025] The lower surface of the above connecting member may be horizontally misaligned with the lower surface of the core layer.

[0026] The lower surface of the above connecting member may be spaced apart from the lower surface of the core layer in the vertical direction.

[0027] It may include an upper build-up layer disposed on top of the core layer and within the cavity.

[0028] The cavity may include a first region that is misaligned in a vertical direction with respect to the connecting member and a second region that overlaps the connecting member in the vertical direction, and the upper surface of the upper build-up layer may include a groove protruding downward on the first region.

[0029] The dummy electrode may be vertically overlapped with the connecting member, the bonding member, the cavity, and a portion of the core layer.

[0030] The above dummy electrode can be electrically separated from the via electrode of the core layer.

[0031] The dummy electrode may have a length in the first horizontal direction greater than the length of the cavity in the first horizontal direction or the length of the connecting member in the first horizontal direction.

[0032] The length of the dummy electrode in the second horizontal direction perpendicular to the first horizontal direction may be less than the length of the cavity in the second horizontal direction.

[0033] The above bonding member may be placed on the upper surface of the lower surface of the core layer.

[0034] The above-mentioned bonding member may include an upper region in contact with the connecting member and a lower region in contact with the dummy electrode.

[0035] A portion of the upper region may extend to the outer surface of the profit connecting member.

[0036] A portion of the lower region may extend from the upper surface of the dummy electrode to the outside of the connecting member.

[0037] The lower surface of the above bonding member may extend from the dummy electrode toward the inner wall of the cavity.

[0038] A circuit board according to an embodiment comprises a core layer including a cavity; a connecting member disposed in the cavity; an underfill disposed in the cavity and surrounding the connecting member; and an upper build-up layer disposed on top of the core layer and within the cavity, wherein the underfill is positioned between the connecting member and an inner wall of the cavity and includes a concave surface recessed toward a lower surface of the core layer.

[0039] The upper surface of the above underfill may be located below the upper surface of the core layer.

[0040] The lower surface of the above underfill may be the same surface as the lower surface of the above core layer.

[0041] The cavity may include a first region that is an area between the connecting member and the inner wall, and a second region that overlaps the connecting member in a vertical direction.

[0042] The upper build-up layer may have a thickness greater than that of the upper surface of the connecting member or the upper surface of the core layer on the first region.

[0043] The thickness of the upper build-up layer may be greatest on the first region.

[0044] The thickness of the upper build-up layer may increase toward the center on the first region.

[0045] The thickness of the underfill in the first region may be greater than the thickness of the upper build-up layer in the first region of the cavity.

[0046] The upper surface of the above underfill may be positioned lower than the upper surface of the above connecting member.

[0047] The upper surface of the above underfill may be located above the vertical bisector of the above connecting member.

[0048] A circuit board according to an embodiment comprises a core layer including a cavity; a connecting member disposed in the cavity; and a first build-up layer disposed on an upper portion of the core layer and within the cavity, wherein the cavity includes a first region vertically misaligned with the connecting member and a second region vertically overlapping with the connecting member, and an upper surface of the first build-up layer includes a groove protruding downward on the first region.

[0049] A first via electrode disposed between an upper surface of the core layer and an upper surface of the first build-up layer; and a second via electrode disposed between an upper surface of the connecting member and an upper surface of the first build-up layer; wherein the height of the first via electrode may be greater than the height of the second via electrode.

[0050] The maximum width of the first via electrode may be greater than the maximum width of the second via electrode.

[0051] The upper surface of the core layer may be positioned lower than the upper surface of the connecting member.

[0052] The first region may include a first region and a second region having a width smaller in the horizontal direction than the first region.

[0053] The above groove includes a first groove on the 1-1 region and a second groove on the 1-2 region, and a length in the vertical direction of the first groove may be greater than a length in the vertical direction of the second groove.

[0054] The first groove may overlap horizontally with at least one of the connecting member and the core layer.

[0055] The first groove may have a bottom surface disposed between the upper surface of the connecting member and the upper surface of the core layer.

[0056] The first groove may be horizontally misaligned with the connecting member and the core layer.

[0057] The above home may overlap at least partly with the connecting member in a horizontal direction.

[0058] The above home may overlap at least partly with the core layer in a horizontal direction.

[0059] The upper surface of the above connecting member may be disposed between the upper surface of the first build-up layer and the upper surface of the core layer.

[0060] The vertical thickness of the above connecting member may be greater than the vertical thickness of the core layer.

[0061] It may include a third build-up layer disposed on the first build-up layer; and a third via electrode and a fourth via electrode disposed on the third build-up layer and spaced apart from each other.

[0062] At least one of the third via electrode and the fourth via electrode can penetrate the third build-up layer and the first build-up layer.

[0063] The first build-up layer may include a first recess corresponding to the third via electrode or a second recess corresponding to the fourth via electrode, and an inner surface of the first recess may be spaced apart from a side surface of the third via electrode, and an inner surface of the second recess may be spaced apart from a side surface of the fourth via electrode.

[0064] The first via electrode and the second via electrode may have a width that decreases from the upper surface of the first build-up layer toward the lower surface of the first build-up layer.

[0065] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which signal integrity is easily secured, mechanical strength is improved, and alignment of a connecting member within a cavity is more accurately implemented.

[0066] In addition, the embodiment suppresses cracks or peeling due to differences in thermal expansion by placing a connecting member in a cavity rather than a build-up layer, and heat generated from the connecting member, etc. is more easily dissipated through a dummy electrode at the bottom of the cavity, thereby enabling implementation of a circuit board and a semiconductor package including the same with improved thermal stability.

[0067] In addition, the embodiment can easily form a build-up electrode portion in an upper build-up layer into a micro pattern or electrode pattern by arranging a connecting member in a core layer, thereby reducing an alignment error with an electrode of an upper element and thereby implementing a circuit board and a semiconductor package including the same with improved electrical reliability.

[0068] In addition, the embodiment improves the flatness of the upper surface of the build-up layer on the upper part of the cavity through the height and formation of the upper surface of the underfill within the cavity, thereby improving the quality of the electrode part or the build-up layer, thereby implementing a circuit board and a semiconductor package including the same with improved electrical characteristics.

[0069] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved bonding strength and improved thermal stability by controlling the height of the connecting member, the height of the underfill, and the thickness of the build-up layer on the cavity.

[0070] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which eliminate dimple and overfit issues by adjusting the height of the via electrode and the height of the connecting member even with a difference in the width (or diameter) of the via electrode, thereby achieving uniform plating.

[0071] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which a dimple or groove is formed in a build-up layer covering a connecting member to serve as an anchor during lamination of the build-up layers, thereby improving adhesion between the build-up layers and easily controlling warpage.

[0072] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0073] Figure 1 is a plan view of a package substrate according to an embodiment of the present invention.

[0074] Figure 2 is a perspective view of a package substrate according to an embodiment of the present invention;

[0075] Figure 3 is a drawing taken along line II' in Figure 1,

[0076] Figure 4 is a cross-sectional view of a circuit board according to the first embodiment of the present invention.

[0077] Figure 5 is an enlarged view of K1 in Figure 4,

[0078] Figure 6 is a plan view of a core layer, a cavity, a dummy electrode, and a connecting member in a circuit board according to an embodiment;

[0079] Figure 7 is an enlarged view of K2 in Figure 4,

[0080] FIGS. 8 to 14 are drawings explaining a method for manufacturing a circuit board according to an embodiment of the present invention.

[0081] Fig. 15 is a plan view of a core layer, a cavity, a dummy electrode, and a connecting member in a circuit board according to the second embodiment.

[0082] Figure 16 is a drawing taken along line II' in Figure 15.

[0083] Figure 17 is a drawing taken along PP' in Figure 15,

[0084] Fig. 18 is a plan view of a core layer, a cavity, a dummy electrode, and a connecting member in a circuit board according to the third embodiment.

[0085] Fig. 19 is a cross-sectional view of a circuit board according to the third embodiment;

[0086] Fig. 20 is a cross-sectional view of a circuit board according to the fourth embodiment of the present invention.

[0087] Figure 21 is an enlarged view of K3 in Figure 20,

[0088] Figure 22 is a plan view of a core layer, a cavity, an underfill, and a connecting member in a circuit board according to an embodiment;

[0089] Fig. 23 is an enlarged view of a portion of a circuit board according to the fourth embodiment.

[0090] Figure 24 is an enlarged view of a portion of a circuit board according to a modified example.

[0091] Figure 25 is a plan view of a core layer, cavity, underfill, and connecting member in a circuit board according to a modified example.

[0092] Figures 26 to 33 are drawings explaining a method for manufacturing a circuit board according to an embodiment of the present invention.

[0093] Figure 34 is a drawing explaining the effect of a circuit board according to an embodiment.

[0094] Fig. 35 is a cross-sectional view of a circuit board according to the fifth embodiment.

[0095] Figure 36 is an enlarged view of the K4 portion in Figure 35,

[0096] Fig. 37 is a cross-sectional view of a circuit board according to the sixth embodiment.

[0097] Figure 38 is an enlarged view of part K5 in Figure 37,

[0098] Figure 39 is a cross-sectional view of a circuit board according to the seventh embodiment of the present invention.

[0099] Figure 40 is an enlarged view of K6 in Figure 39,

[0100] Figure 41 is an enlarged view of K7 in Figure 39,

[0101] Figure 42 is an enlarged view of K8 in Figure 39,

[0102] Fig. 43 is a cross-sectional view of a circuit board according to the eighth embodiment.

[0103] Fig. 44 is a modified example of Fig. 43,

[0104] Fig. 45 is another modified example of Fig. 43,

[0105] Figures 46a to 46h are drawings explaining a method for manufacturing a circuit board according to the seventh embodiment of the present invention.

[0106] Fig. 47 is a cross-sectional view of a circuit board according to the 9th embodiment.

[0107] Figure 48 is an enlarged view of K9 in Figure 47,

[0108] Fig. 49 is a modified example of Fig. 48.

[0109] Fig. 50 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0110] Fig. 51 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0111] Fig. 52 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0112] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0113] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0114] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0115] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0116] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0117] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0118] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0119] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0120] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0121] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0122] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0123] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0124] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0125] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0126] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0127] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0128] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0129] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0130] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0131] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0132] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0133] FIG. 1 is a plan view of a package substrate according to an embodiment of the present invention, FIG. 2 is a perspective view of a package substrate according to an embodiment of the present invention, and FIG. 3 is a view taken along line II' in FIG. 1.

[0134] Referring to FIGS. 1 to 3, a package substrate according to an embodiment may include a main substrate in addition to semiconductor elements (DI1, DI2) and a circuit substrate (100). For example, the main substrate may be an FPGA substrate. In particular, the circuit substrate according to the embodiment may be a substrate having a built-in connecting member.

[0135] The circuit board of the embodiment may include a first semiconductor element (DI1), a second semiconductor element (DI2), and a connecting member (BR). The first semiconductor element (DI1) and the second semiconductor element (DI2) may include a logic chip or a memory chip as described above. In addition, the first semiconductor element (DI1) and the second semiconductor element (DI2) may be different types of semiconductor elements as described above. In addition, the connecting member (BR) may be embedded in the circuit board (100). In particular, the connecting member (BR) may be embedded in a cavity of the circuit board (100). Various examples of circuit boards described below may be applied to the circuit board (100).

[0136] Additionally, the connecting member (BR) may include an upper wiring (BE) that is in contact with a third electrode portion (Fig. 5, 123) at the upper portion. The upper wiring (BE) may be electrically connected to the third electrode portion. In addition, the upper wiring (BE) may be electrically connected to the first semiconductor element and the second semiconductor element at the upper portion through the third electrode portion, thereby functioning as a bridge.

[0137] In addition, the circuit board may include a conductive member (SB) for connection between the first and second semiconductor elements and the electrode portions disposed on the upper portion of the circuit board (100), particularly on the upper build-up layer, which is the upper build-up layer. In addition, the circuit board may further include a conductive member (SB) disposed between a connection member (BR) other than the build-up layer and the first and second semiconductor elements. In addition, the connection member (BR) may electrically connect between at least two semiconductor elements. However, the following description will be given as performing an electrical connection between two semiconductor elements.

[0138] Additionally, an underfill (UF) may be positioned between the circuit board (100) and the first and second semiconductor elements (DI1, DI2). The underfill (UF) may cover the conductive member (SB).

[0139] And when the connecting member (BR) does not include a via electrode, the via electrode of the core layer of the circuit board (100) may not vertically overlap with the connecting member (BR). However, when the connecting member (BR) includes a via electrode, it may vertically overlap with the via electrode of the core layer of the circuit board (100) and be electrically connected. The via electrode of the build-up layer may vertically overlap with the connecting member (BR). Furthermore, the connecting member (BR) and the via electrode of the build-up layer may be electrically connected. In addition, the connecting member (BR) may at least partially vertically overlap with the first and second semiconductor elements (DI1, DI2).

[0140] In addition, as described above, the connecting member (BR) may be an organic or inorganic connecting member. For example, the connecting member (BR) may be an inorganic connecting member, and when the connecting member (BR) includes a via electrode, it may be advantageous in transmitting power from the circuit board (100) to the first and second semiconductor elements (DI1, DI2).

[0141] FIG. 4 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 5 is an enlarged view of K1 in FIG. 4, FIG. 6 is a plan view of a core layer, a cavity, a dummy electrode, and a connecting member in a circuit board according to an embodiment, and FIG. 7 is an enlarged view of K2 in FIG. 4.

[0142] Referring to FIG. 4, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), a dummy electrode (ST), and a connecting member (BR).

[0143] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0144] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (111), build-up insulating portions (112, 113), a core electrode portion (121), and build-up electrode portions (122, 123). Furthermore, the circuit board (100) may further include a protective layer (SR) and a bonding portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portions (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The build-up electrode portions (122, 123) may be disposed by being embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby performing a function of transmitting signals and / or power from a main board (not illustrated) to a semiconductor element.

[0145] And when the circuit board includes a core layer, it may include a core layer disposed within an insulating layer (110). Accordingly, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0146] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0147] As an example, the insulation layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion, etc. The following description will be made based on this.

[0148] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0149] And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In the present embodiment, the core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (113) may be located below the core layer (111).

[0150] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0151] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0152] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and have a thickness in a vertical direction (Y-axis direction or lamination direction) of tens to hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0153] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0154] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0155] Furthermore, the upper build-up layer (112) may be formed of a plurality of insulating layers that contact the core layer (111). The plurality of insulating layers may be formed of fillers of different sizes. For example, the filler size may decrease toward the top of the plurality of insulating layers. In addition, an upper electrode portion having a smaller width or pitch toward the upper insulating layer may be arranged among the plurality of insulating layers.

[0156] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0157] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0158] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0159] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0160] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0161] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0162] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0163] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0164] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion (first wiring portion) having a fine pitch and a wiring portion (second wiring portion) having a pitch larger than the first wiring portion.

[0165] The second wiring portion may refer to a wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first wiring portion may refer to a fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the first wiring portion may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the first wiring portion may be 30 ㎛ or less. For example, the pitch of the first wiring portion may be 55 ㎛ or less. A detailed description thereof will be provided later.

[0166] Additionally, the circuit board (100) according to the first embodiment may further include a protective layer (SR) and a bonding portion (BP).

[0167] Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material having insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0168] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0169] The bonding portion (BP) may be disposed on the protective layer (SR). For example, the bonding portion (BP) may be disposed on the upper surface of the protective layer (SR). The bonding portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bonding portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bonding portion (BP) may include a protrusion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0170] Furthermore, a metal layer may be additionally disposed on the bonding portion (BP) and electrically connected. Accordingly, the durability and reliability of the bonding portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bonding portion (BP) is improved, the corrosion resistance and durability of the bonding portion (BP) are improved, and the loss of electrical signals may also be minimized. The metal layer may be formed on the bonding portion (BP) by deposition, electroplating, or the like of various metals.

[0171] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the first wiring portion, which is the aforementioned micro-pattern. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0172] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0173] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0174] In addition, in the embodiment, the core layer (111) in the circuit board (100) may include a cavity (CV). That is, the circuit board (100) may include a core layer (111) including a cavity (CV). In the embodiments, the cavity (CV) may be expressed in various ways, such as a 'groove', a 'recess', a hole, a 'via', etc. Furthermore, the cavity (CV) may have various shapes, such as a flat surface, a circle, a square shape, etc. Furthermore, the inner wall of the cavity (CV) or the inner side of the core layer (111) may have a structure in which the width or diameter increases from the center or the central portion toward the upper surface of the core layer (111), and the width or diameter increases toward the lower surface of the core layer (111). Alternatively, the inner wall of the cavity (CV) or the inner side of the core layer (111) may only have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the core layer (111), or the width or diameter increases toward the lower surface of the core layer (111).

[0175] The cavity (CV) may have various shapes depending on the shape of the component (e.g., connecting member) mounted therein. For example, the shape of the connecting member may generally be rectangular with respect to a plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) may also have a rectangular shape with respect to a plane perpendicular to the stacking direction. However, for easy mounting of the connecting member (BR), it may have various shapes.

[0176] The circuit board (100) may include a connecting member (BR). The connecting member (BR) may be positioned within a cavity (CV). That is, a mounting space for the connecting member (BR) and the like can be easily secured in the upper build-up layer (112) through the cavity (CV). In addition, a lower electrode portion (123) having a smaller line width than the upper electrode portion (122) outside the cavity (CV) can be easily arranged on the upper portion of the cavity (CV). Accordingly, the circuit board according to the embodiment can provide easy connection between semiconductor elements and an improved input / output (I / O) count.

[0177] According to an embodiment, the connecting member (BR) may be embedded in the cavity (CV) of the core layer (111). That is, according to an embodiment, the core layer (111) may be provided to prevent warpage while the circuit board (100) is made thinner, and at this time, the connecting member (BR) may be embedded in the core layer (111). In addition, as described above, since the connecting member (BR) is arranged in the core layer (111), the reliability of the circuit board is maintained by mounting the connecting member, and mounting of various connecting members (BR) can be performed.

[0178] Additionally, the connecting member (BR) may be positioned within the core layer (111) of the circuit board (100) and may overlap with the core layer (111) in the horizontal direction (X-axis direction). For example, the connecting member (BR) may not be positioned in the upper build-up layer (112) or the lower build-up layer (113) of the circuit board (100).

[0179] For example, if a connecting member (BR) in a circuit board (100) is positioned within a lower build-up layer (113), the signal path between the connecting member (BR) and the upper element may become longer. In addition, as this signal path becomes longer, parasitic elements may increase. For example, parasitic capacitance, parasitic inductance, resistance, etc. may increase, resulting in a charge that degrades signal quality.

[0180] In addition, when forming a cavity through etching in the lower build-up layer (113), a problem occurs in which peeling occurs at the boundary of multiple insulating layers. Accordingly, by arranging a connecting member (BR) within the cavity (CV) of the circuit board (100) as in the embodiment, the reliability of the circuit board can be greatly improved.

[0181] In addition, if the connecting member (BR) in the circuit board (100) is not placed in the core layer (111) but in the build-up layer, the mechanical strength of the circuit board may be reduced. That is, if the connecting member (BR) is placed in the core layer (111) of the circuit board (100), damage to the connecting member (BR) can be suppressed even when the circuit board is subjected to external stress or expansion by the core layer (111) which has relatively strong rigidity.

[0182] In addition, when the connecting member (BR) is embedded in the upper build-up layer (112), a dummy electrode may be placed on the upper surface of the upper build-up layer. Accordingly, the connecting member (BR) may be mounted within a limited height within the upper build-up layer (112). Furthermore, when the length (thickness) of the connecting member (BR) increases in the stacking direction, problems such as peeling and cracking occurring at the boundary between the plurality of insulating layers may exist as cavities are formed in the upper build-up layer (112), which is a plurality of insulating layers. Therefore, by mounting the connecting member (BR) in the core layer (111) as in the embodiment, the connecting member (BR) can be easily mounted regardless of whether the size of the connecting member (BR) is large or small, and since a via penetrating the boundary between the plurality of insulating layers for mounting the connecting member is not formed, the reliability of the circuit board can be improved.

[0183] Since the circuit board (100) according to the embodiment can be used as an interposer, thinning is required, so that a connecting member (BR) can be embedded in the core layer (111).

[0184] In addition, the upper build-up layer (112) may be disposed on the core layer (111), and a portion thereof may be disposed within the cavity (CV) of the core layer (111). Accordingly, a portion of the lower surface of the upper build-up layer (112) may be in contact with the upper surface of the lower build-up layer (113), and may form the same surface. This may be implemented within the cavity (CV).

[0185] Furthermore, a dummy electrode (ST) may be further arranged on the lower surface of the core layer (111). However, a connecting member may be mounted in the cavity described below through various members (e.g., a film) without the dummy electrode (ST). In addition, the dummy electrode (ST) may be a dummy electrode. Hereinafter, the dummy electrode (ST) is described interchangeably with the dummy electrode (ST).

[0186] Referring further to FIGS. 5 to 7, in a circuit board (100) according to an embodiment, a dummy electrode (ST) may overlap a connecting member (BR), a bonding member (BM), a cavity (CV), and a portion of a core layer (111) in a vertical direction (Y-axis direction).

[0187] The dummy electrode (ST) may overlap with the cavity (CV) in a vertical direction. At least a portion of the cavity (CV) may overlap with the dummy electrode (ST) in a vertical direction or a stacking direction (Y-axis direction). In addition, at least a portion of the dummy electrode (ST) may overlap with the cavity (CV) in a stacking direction (Y-axis direction). A portion of the dummy electrode (ST) may not overlap with the cavity (CV) in the stacking direction (Y-axis direction) but may be misaligned.

[0188] The dummy electrode (ST) may be positioned at the bottom of the cavity (CV). Additionally, the dummy electrode (ST) may be positioned on the lower surface (BS) of the core layer (111). For example, at least a portion of the dummy electrode (ST) may be in contact with the lower surface (BS) of the core layer (111).

[0189] And the connecting member (BR) can be positioned on the dummy electrode (ST). Since the connecting member (BR) is placed within the cavity (CV), the connecting member (BR) can overlap with the dummy electrode (ST) in the lamination direction (Y-axis direction). In addition, the dummy electrode (ST) can overlap with the connecting member (BR) in the lamination direction (Y-axis direction). In addition, at least a part of the dummy electrode (ST) can be misaligned and not overlap with the connecting member (BR) in the lamination direction (Y-axis direction).

[0190] In addition, the lower surface of the connecting member (BR) may be misaligned with the lower surface (BS) of the core layer (111). In addition, the upper surface of the dummy electrode (ST) may be spaced apart from the lower surface of the connecting member (BR) in the lamination direction and may be misaligned in the horizontal direction. In addition, the lower surface of the dummy electrode (ST) may be misaligned without horizontally overlapping with the lower surface (BS) of the core layer (111).

[0191] In addition, the circuit board (100) may further include a bonding member (BM) disposed between the dummy electrode (ST) and the connecting member (BR). The bonding member (BM) may be in contact with the dummy electrode (ST) and the connecting member (BR). The bonding member (BM) may be disposed on the dummy electrode (ST). In addition, the bonding member (BM) may be disposed within the cavity (CV). Accordingly, the bonding member (BM) may overlap the cavity (CV) in a horizontal direction (X-axis direction). In addition, the bonding member (BM) may be positioned on the lower surface (BS) of the core layer (111).

[0192] Furthermore, the bonding member (BM) may overlap with the dummy electrode (ST) and the connecting member (BR) in the lamination direction (Y-axis direction). A portion of the dummy electrode (ST) may not overlap with the bonding member (BM) in the lamination direction (Y-axis direction) and may be misaligned.

[0193] By means of such a bonding member (BM), the position of the connecting member (BR) on the dummy electrode (ST) can be more precisely adjusted. That is, the alignment error of the connecting member (BR) is reduced, and thus the deterioration of electrical reliability and structural reliability due to alignment error can be prevented.

[0194] In addition, the bonding member (BM) may include an upper region (UA) and a lower region (BA). The upper region (UA) may be in contact with the connecting member (BR). And the lower region (BA) may be in contact with the dummy electrode (ST). A portion of the upper region (UA) may extend to the outer surface (ESI) of the connecting member (BR). Accordingly, the upper surface of the bonding member (BM) may extend to the outer surface (ESI) of the connecting member (BR). And a portion of the lower region (BA) may extend from the upper surface (USS) of the dummy electrode (ST) to the outer side of the connecting member (BR). That is, the lower surface of the bonding member (BM) may extend toward the inner wall (IS) of the cavity (CV) on the dummy electrode (ST). Accordingly, the length of the upper surface of the bonding member (BM) in the horizontal direction may be less than the length of the lower surface of the bonding member (BM) in the horizontal direction. By this configuration, the connecting member (BR) can be more firmly fixed within the cavity by the joining member (BM).

[0195] Additionally, the gap distance (gap1) between the lower area (BA) of the joint member (BM) and the inner wall (IS) of the cavity (CV) may be smaller than the gap distance (gap2) between the upper area (UA) of the joint member (BM) and the inner wall (IS) of the cavity (CV).

[0196] Additionally, in the embodiment, the thickness (Tb) of the dummy electrode (ST) may be different from the thickness (Ta) of the core wiring portion (121a) that overlaps in the horizontal direction (X-axis direction).

[0197] For example, the thickness (Tb) of the dummy electrode (ST) may be greater than the thickness (Ta) of the core wiring portion (121a) that overlaps in the horizontal direction (X-axis direction).

[0198] By this configuration, heat generated within the circuit board, such as the connecting member (BR), can be more easily dissipated through the dummy electrode (ST). Accordingly, the thermal and mechanical stability of the circuit board can be improved.

[0199] Furthermore, the dummy electrode (ST) may be electrically separated from the electrode portion. For example, the dummy electrode (ST) may be positioned adjacent to the core wiring portion (121a). In addition, as described above, the dummy electrode (ST) may overlap the core wiring portion (121a) in the horizontal direction (X-axis direction), but may be spaced apart from the core wiring portion (121a) in the horizontal direction. Accordingly, the dummy electrode (ST) may be electrically separated from the core wiring portion (121a).

[0200] Furthermore, at least a portion of the dummy electrode (ST) may be in contact with the upper build-up layer (112) accommodated in the cavity (CV). For example, a portion of the upper surface of the dummy electrode (ST) may be in contact with the upper build-up layer (112) within the cavity (CV).

[0201] Additionally, the dummy electrode (ST) may be positioned on the lower build-up layer (113). Accordingly, a portion (e.g., the lower surface) of the dummy electrode (ST) may be in contact with the lower build-up layer (113).

[0202] Furthermore, since the dummy electrode (ST) has a greater thickness than the core wiring portion (121a), it can overlap at least partially with the lower via electrode (123b) in the horizontal direction (X-axis direction). However, the thickness of the dummy electrode (ST) may be smaller than the thickness of the lower via electrode (123b). Accordingly, at least a portion of the lower via electrode (123b) may not overlap with the dummy electrode (ST) in the horizontal direction (X-axis direction) but may be spaced apart from it.

[0203] In addition, a connecting member (BR) may be arranged within the cavity (CV) of the core layer (111). In particular, as illustrated in FIG. 6, the horizontal direction may include a first horizontal direction (X1-axis direction) and a second horizontal direction (X2-axis direction). And the dummy electrode (ST) may have a length (Wa) in the horizontal direction that is greater than a length (Wb) in the horizontal direction of the cavity (CV) or a length (Wc) in the horizontal direction of the connecting member (BR).

[0204] Although the length is shown based on the second horizontal direction (X2 axis direction) in the drawing, the length can also be applied equally to the first horizontal direction (X axis direction).

[0205] That is, the dummy electrode (ST) may have a length (Wa) in the first horizontal direction (or the second horizontal direction) greater than the length (Wb) in the first horizontal direction (or the second horizontal direction) of the cavity (CV) or the length (Wc) in the horizontal direction of the connecting member (BR).

[0206] Additionally, the area of ​​the dummy electrode (ST) (in a plane perpendicular to the stacking direction) may be larger than the area of ​​the cavity (CV) or the area of ​​the connecting member (BR).

[0207] By this configuration, the support force for the connecting member (BR) is improved due to the dummy electrode (ST) placed at the bottom of the cavity (CV), and the movement of the connecting member (BR) within the cavity (CV) can be easily achieved during manufacturing.

[0208] Additionally, the length (Wb) of the cavity (CV) in the horizontal direction may be greater than the length (Wc) of the connecting member (BR) in the horizontal direction. Furthermore, the area of ​​the cavity (CV) may be greater than the area of ​​the connecting member (BR).

[0209] And the area of ​​the bonding member (BM) may be smaller than the area of ​​the dummy electrode (ST). And the area of ​​the bonding member (BM) may be smaller than the area of ​​the cavity (CV). The area of ​​the bonding member (BM) may be larger or smaller than the area of ​​the lower surface of the connecting member (BR). By this configuration, the bonding force between the connecting member (BR) and the dummy electrode (ST) may be improved.

[0210] Additionally, the cavity (CV) may include a first region (AR1) that is misaligned in the vertical direction (Y-axis direction) with respect to the connecting member (BR) and a second region (AR2) that overlaps in the vertical direction (Y-axis direction) with respect to the connecting member (BR).

[0211] The upper build-up layer (112) may be arranged in the first region (AR1) and may be in contact with the dummy electrode (ST) below. Furthermore, the upper surface of the upper build-up layer (112) may include a groove (GV) extending downward on the first region (AR1). By this configuration, the surface area of ​​the upper build-up layer (112) and the first protective layer that is arranged on the upper build-up layer (112) and is in contact with the upper build-up layer (112) may be further increased. In other words, the bonding strength between the build-up layer and the protective layer may be improved. Furthermore, the warpage phenomenon due to the difference in thermal expansion coefficient may be easily suppressed through the groove (GV).

[0212] Furthermore, since the connecting member (BR) can be easily moved within the cavity (CV) as described above, the electrical connection between the upper wiring (BE) and the upper electrode portion (122) disposed on the upper build-up layer (112) can be implemented more accurately. In addition, the formation of the upper electrode portion (122) disposed on the upper build-up layer (112) can be performed corresponding to the pattern of the semiconductor element mounted on the upper part of the circuit board. In other words, the electrical path toward the upper part can be formed in a variety of ways compared to the case where the connecting member (BR) is disposed on the build-up layer. In addition, since the cavity penetrating the upper build-up layer (112), which is a plurality of insulating layers, is not formed, and an insulating layer covers the cavity of the core layer, the occurrence of peeling or voiding phenomena at the interface of the insulating layers can be suppressed.

[0213] FIGS. 8 to 14 are drawings explaining a method for manufacturing a circuit board according to an embodiment of the present invention.

[0214] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0215] Referring to FIG. 8, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or greater, as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0216] Referring to FIG. 9, a via hole or a through hole (111h) can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0217] Referring to Fig. 10, a core electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0218] For example, a plating process may be performed on a via hole formed in a core layer (111) to form a through electrode. In addition, a core wiring portion may be formed on the upper and lower surfaces of the core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions.

[0219] Furthermore, a dummy electrode (ST), which is a dummy electrode, may be placed on the lower surface of the core layer (111).

[0220] Referring to Fig. 11, a cavity (CV) can be formed in a region of the core layer (111) by various methods such as a laser method, a punching method, and an etching method. The cavity (CV) can be easily formed by a dummy electrode (ST). The cavity (CV) can penetrate the core layer (111). However, the present invention is not limited thereto, and the cavity (CV) can penetrate up to a part of the core layer (111). That is, the cavity (CV) can be a hole or a groove.

[0221] A dummy electrode (ST) may be exposed by the cavity (CV). The dummy electrode (ST) may have an area or width larger than the cavity (CV). Accordingly, the dummy electrode (ST) may be in contact with the lower surface of the core layer (111).

[0222] Referring to Fig. 12, a connecting member (BR) may be mounted in a cavity (CV) of a core layer (111). The connecting member (BR) may be positioned on a dummy electrode (ST). In addition, a bonding member (BM) may be further disposed on the dummy electrode (ST). The dummy electrode (ST) and the connecting member (BR) may be easily joined by the bonding member (BM).

[0223] And the position of the connecting member (BR) on the dummy electrode (ST) can be easily adjusted by the bonding member (BM). For example, a mark (e.g., an alignment mark) for aligning the connecting member (BR) can be formed on the dummy electrode (ST). By this configuration, the connecting member (BR) can be positioned at a more accurate position according to the design within the cavity (CV). For example, the position of the connecting member (BR) can be adjusted so that the center of the connecting member (BR) is in the center of the cavity (CV).

[0224] Referring to Fig. 13, an upper build-up layer (112) can be formed above the core layer (111) and within the cavity (CV). Additionally, a lower build-up layer (113) can be formed below the core layer (111).

[0225] In addition, before forming the upper build-up layer (112), underfilling may be performed to fix the position of the connecting member (BR) in the cavity (CV). For example, a filling member (F1) may be further applied within the cavity (CV). Accordingly, the filling member (F1) may improve the bonding strength between the core layer (111) and the connecting member (BR). Accordingly, the circuit board may be protected from impact, dropping, and vibration. In addition, deformation due to differences in thermal expansion between other components, such as the connecting member (BR) and the core layer (111), may be reduced. The filling member (F1) may include epoxy, etc. Accordingly, at least a portion of the filling member (F1) may be in contact with the dummy electrode (ST). Furthermore, in some cases, the upper build-up layer (112) may not be in contact with the dummy electrode (ST). However, if the filling material (F1) is placed only in a portion of the cavity (CV), the upper build-up layer (112) and the dummy electrode (ST) may come into contact with each other.

[0226] However, as described above, the upper build-up layer (112) can be applied within the cavity (CV), and this is illustrated as a reference.

[0227] Referring to FIG. 14, a via hole or through hole may be formed in the upper build-up layer (112) and / or the lower build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0228] Additionally, an upper electrode portion (122) may be formed on the upper build-up layer (112). And a lower electrode portion (123) may be formed on the lower build-up layer (113). The upper electrode portion (122) and the lower electrode portion (123) may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0229] And the upper wiring part of the upper electrode part (122) may be formed on the upper surface of the upper build-up layer (112), and the lower wiring part of the lower electrode part (123) may be formed on the lower surface of the lower build-up layer (113). Each wiring part may have a pattern by a mask or the like. Furthermore, the wiring part may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes of a printed circuit board.

[0230] Thereafter, a first protective layer (SR1) may be formed on the upper build-up layer (112). A second protective layer (SR2) may be formed under the lower build-up layer (113). Furthermore, a via (TP) penetrating the protective layer (SR) may be formed.

[0231] Fig. 15 is a plan view of a core layer, a cavity, a dummy electrode, and a connecting member in a circuit board according to a second embodiment, Fig. 16 is a view taken along line II' in Fig. 15, and Fig. 17 is a view taken along line PP' in Fig. 15.

[0232] Referring to FIGS. 15 to 17, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), a dummy electrode (ST), and a connecting member (BR). Furthermore, the circuit board (100A) may further include a protective layer (SR) and a bonding portion (BP). As described above, the build-up electrode portions (122, 123) may be disposed to be embedded in each layer (e.g., an insulating layer) of the build-up insulating portions (112, 113), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. In addition, the connecting member (BR) may be positioned within a cavity (CV) formed in a core layer (111) of the insulating layer (110). Except for the contents described below with respect to the circuit board, the above-described contents may be equally applied.

[0233] In this example, the connecting member (BR) may be positioned within the cavity CV of the core layer (111). And the dummy electrode (ST) may be positioned at the bottom of the cavity CV and may be in contact with the lower surface of the core layer (111).

[0234] Additionally, in this example, some areas of the cavity (CV) may not overlap with the dummy electrode (ST) in the vertical direction (Y-axis direction).

[0235] Additionally, the length in one horizontal direction of the dummy electrode (ST) may be less than the length in one horizontal direction of the cavity (CV).

[0236] For example, the length (W1) of the dummy electrode (ST) in the first horizontal direction (X1-axis direction) may be greater than the length (W2) of the cavity (CV) in the first horizontal direction (X1-axis direction). In addition, the length (W2) of the cavity (CV) in the first horizontal direction (X1-axis direction) may be greater than the length (W3) of the connecting member (BR) in the first horizontal direction (X1-axis direction).

[0237] However, the length (W5) of the dummy electrode (ST) in the second horizontal direction (X2-axis direction) may be smaller than the length (W4) of the cavity (CV) in the second horizontal direction (X2-axis direction). In addition, the length of the dummy electrode (ST) in the second horizontal direction (X2-axis direction) may be equal to or different from the length (W6) of the connecting member (BR) in the second horizontal direction (X2-axis direction). For example, the length of the dummy electrode (ST) in the second horizontal direction (X2-axis direction) may be equal to the length (W6) of the connecting member (BR) in the second horizontal direction (X2-axis direction).

[0238] By this configuration, the dummy electrode (ST) can be in contact with the lower surface of the core layer (111), and while supporting the connecting member (BR), connection between the dummy electrode (ST) and the adjacent core wiring section can be prevented. Accordingly, the electrical reliability of the circuit board can be improved.

[0239] Additionally, only a portion of the first region (AR1) may vertically overlap with the dummy electrode (ST). This allows the lower build-up layer (113) and the upper build-up layer (or filling member) positioned in the first region (AR1) to come into contact with each other. Accordingly, the upper build-up layer (112) and the lower build-up layer (113) may be connected to each other, thereby improving the structural reliability of the circuit board.

[0240] Furthermore, as described above, since the dummy electrode (ST) has the longest length in one direction compared to the cavity (CV) and the connecting member (BR), the supporting force for the connecting member (BR) is improved due to the dummy electrode (ST) placed at the bottom of the cavity (CV), and the movement of the connecting member (BR) within the cavity (CV) can be easily achieved during manufacturing.

[0241] Fig. 18 is a plan view of a core layer, a cavity, a dummy electrode, and a connecting member in a circuit board according to a third embodiment, and Fig. 19 is a cross-sectional view of a circuit board according to the third embodiment.

[0242] Referring to FIGS. 18 and 19, a circuit board (100B) according to the third embodiment may include an insulating layer (110), an electrode portion (120), a dummy electrode (ST), and a connecting member (BR). Furthermore, the circuit board (100B) may further include a protective layer (SR) and a bonding portion (BP). As described above, the build-up electrode portions (122, 123) may be disposed to be embedded in each layer (e.g., an insulating layer) of the build-up insulating portions (112, 113), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. In addition, the connecting member (BR) may be positioned within a cavity (CV) formed in a core layer (111) of the insulating layer (110). Except for the contents described below with respect to the circuit board, the above-described contents may be equally applied.

[0243] In this example, the connecting member (BR) may be positioned within the cavity CV of the core layer (111). And the dummy electrode (ST) may be positioned at the bottom of the cavity CV and may be in contact with the lower surface of the core layer (111).

[0244] Additionally, in this example, some areas of the cavity (CV) may not overlap with the dummy electrode (ST) in the vertical direction (Y-axis direction).

[0245] Additionally, the length of the dummy electrode (ST) in one horizontal direction may be less than the length of the cavity (CV) in one horizontal direction. Furthermore, the length of the dummy electrode (ST) in one horizontal direction may be less than the length of the connecting member (BR) in one horizontal direction.

[0246] For example, the length (W7) of the dummy electrode (ST) in the first horizontal direction (X1-axis direction) may be greater than the length (W8) of the cavity (CV) in the first horizontal direction (X1-axis direction). In addition, the length (W8) of the cavity (CV) in the first horizontal direction (X1-axis direction) may be greater than the length (W9) of the connecting member (BR) in the first horizontal direction (X1-axis direction).

[0247] However, the length (W10) of the dummy electrode (ST) in the second horizontal direction (X2-axis direction) may be smaller than the length (W11) of the cavity (CV) in the second horizontal direction (X2-axis direction). In addition, the length of the dummy electrode (ST) in the second horizontal direction (X2-axis direction) may be smaller than the length (W12) of the connecting member (BR) in the second horizontal direction (X2-axis direction).

[0248] By this configuration, the dummy electrode (ST) can be in contact with the lower surface of the core layer (111), and while supporting the connecting member (BR), connection between the dummy electrode (ST) and the adjacent core wiring section can be prevented. Accordingly, the electrical reliability of the circuit board can be improved.

[0249] Furthermore, a portion of the connecting member (BR) may be exposed downward. Accordingly, a portion of the connecting member (BR) may be in contact with the lower build-up layer (113). Alternatively, a bonding member in contact with the lower surface of the connecting member (BR) may be in contact with the lower build-up layer (113).

[0250] Furthermore, as described above, since the dummy electrode (ST) has the longest length in one direction compared to the cavity (CV) and the connecting member (BR), the supporting force for the connecting member (BR) is improved due to the dummy electrode (ST) placed at the bottom of the cavity (CV), and the movement of the connecting member (BR) within the cavity (CV) can be easily achieved during manufacturing.

[0251] FIG. 20 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, FIG. 21 is an enlarged view of K3 in FIG. 20, FIG. 22 is a plan view of a core layer, a cavity, an underfill, and a connecting member in a circuit board according to an embodiment, and FIG. 23 is an enlarged view of a portion of a circuit board according to the fourth embodiment.

[0252] Referring to FIG. 20, a circuit board (100C) according to an embodiment may include an insulating layer (110), an electrode portion (120), an underfill (FI), and a connecting member (BR).

[0253] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0254] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100C) may include a core layer (111), build-up insulating portions (112, 113), a core electrode portion (121), and build-up electrode portions (122, 123). Furthermore, the circuit board (100C) may further include a protective layer (SR) and a bonding portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portions (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The build-up electrode portions (122, 123) may be disposed by being embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby performing a function of transmitting signals and / or power from a main board (not illustrated) to semiconductor devices.

[0255] And when the circuit board includes a core layer, it may include a core layer disposed within an insulating layer (110). Accordingly, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0256] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0257] As an example, the insulation layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion, etc. The following description will be made based on this.

[0258] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0259] And the upper build-up layer (112) may be an 'upper build-up structure' or a 'first build-up layer'. The lower build-up layer (113) may be a 'lower build-up structure' or a 'second build-up layer'. In the present embodiment, the core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (113) may be located below the core layer (111).

[0260] And the insulating layer (110) of the circuit board (100C) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100C) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer forming the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0261] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0262] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and have a thickness in a vertical direction (Y-axis direction or lamination direction) of tens to hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0263] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0264] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100C) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0265] Furthermore, the upper build-up layer (112) may be formed of a plurality of insulating layers that contact the core layer (111). The plurality of insulating layers may be formed of fillers of different sizes. For example, the filler size may decrease toward the top of the plurality of insulating layers. In addition, an upper electrode portion having a smaller width or pitch toward the upper insulating layer may be arranged among the plurality of insulating layers.

[0266] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0267] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0268] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0269] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0270] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0271] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0272] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0273] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0274] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion (first wiring portion) having a fine pitch and a wiring portion (second wiring portion) having a pitch larger than the first wiring portion.

[0275] The second wiring portion may refer to a wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first wiring portion may refer to a fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the first wiring portion may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the first wiring portion may be 30 ㎛ or less. For example, the pitch of the first wiring portion may be 55 ㎛ or less. A detailed description thereof will be provided later.

[0276] Additionally, the circuit board (100C) according to the fourth embodiment may further include a protective layer (SR) and a bonding portion (BP).

[0277] Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material having insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0278] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0279] The bonding portion (BP) may be disposed on the protective layer (SR). The bonding portion (BP) may be a bump portion. For example, the bonding portion (BP) may be disposed on the upper surface of the protective layer (SR). The bonding portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bonding portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bonding portion (BP) may include a protrusion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0280] Furthermore, a metal layer may be additionally disposed on the bonding portion (BP). And the bonding portion (BP) and the metal layer may be electrically connected. Accordingly, the durability and reliability of the bonding portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bonding portion (BP) is improved, and the corrosion resistance and durability of the bonding portion (BP) are improved, and the loss of electrical signals may also be minimized. The metal layer may be formed on the bonding portion (BP) by deposition, electroplating, or the like of various metals.

[0281] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the first wiring portion, which is the aforementioned micro-pattern. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0282] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0283] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0284] In addition, in the embodiment, the core layer (111) in the circuit board (100C) may include a cavity (CV). That is, the circuit board (100C) may include a core layer (111) including a cavity (CV). In the embodiments, the cavity (CV) may be expressed in various ways, such as a 'groove', a 'recess', a hole, a 'via', etc. Furthermore, the cavity (CV) may have various shapes, such as a flat surface, a circle, a square shape, etc. Furthermore, the inner wall of the cavity (CV) or the inner side of the core layer (111) may have a structure in which the width or diameter increases from the center or the central portion toward the upper surface of the core layer (111), and the width or diameter increases toward the lower surface of the core layer (111). Alternatively, the inner wall of the cavity (CV) or the inner side of the core layer (111) may only have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the core layer (111), or the width or diameter increases toward the lower surface of the core layer (111).

[0285] The cavity (CV) may have various shapes depending on the shape of the component (e.g., connecting member) mounted therein. For example, the shape of the connecting member (BR) may generally be rectangular with respect to a plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) may also have a rectangular shape with respect to a plane perpendicular to the stacking direction. However, for easy mounting of the connecting member (BR), it may have various shapes.

[0286] The circuit board (100C) may include a connecting member (BR). The connecting member (BR) may be positioned within a cavity (CV). That is, a mounting space for the connecting member (BR) and the like can be easily secured in the upper build-up layer (112) through the cavity (CV). In addition, a lower electrode portion (123) having a smaller line width than the upper electrode portion (122) outside the cavity (CV) can be easily arranged on the upper portion of the cavity (CV). Accordingly, the circuit board according to the embodiment can provide easy connection between semiconductor elements and an improved input / output (I / O) count.

[0287] According to an embodiment, the connecting member (BR) is located within the cavity (CV) of the core layer (111), but may be embedded within the upper build-up layer disposed on the core layer (111). That is, according to an embodiment, the core layer (111) may be provided to prevent warpage as the circuit board (100C) is made thinner, and at this time, the connecting member (BR) may be embedded within the core layer (111). However, when the circuit board (100C) is designed to be multi-layered for signal integrity and power integrity, the connecting member (BR) may be embedded within the upper build-up layer to shorten the electrical length between the first and second semiconductor elements (DI1, DI2) and the connecting member (BR). However, since the circuit board (100C) according to the embodiment can be used as an interposer, thinning is required, and thus the connecting member (BR) may be embedded within the core layer (111). Accordingly, mounting within the circuit board can be possible even when the size of the connecting member (BR) changes. Furthermore, mechanical deformation due to mounting of the connecting member relative to the build-up layer can also be suppressed. The connecting member (BR) can be embedded within the upper build-up layer by being provided with a circuit board (100C) rather than an interposer. In addition, the upper build-up layer (112) can be disposed on the core layer (111), and a portion thereof can be disposed within the cavity (CV) of the core layer (111). Accordingly, a portion of the lower surface of the upper build-up layer (112) can be in contact with the upper surface of the lower build-up layer (113), and can form the same plane with each other. This can be implemented within the cavity (CV).

[0288] Furthermore, a dummy electrode (ST) may be further arranged on the lower surface of the core layer (111). However, a connecting member may be mounted in the cavity described below through various members (e.g., a film) without the dummy electrode (ST). In addition, the dummy electrode (ST) may be a dummy electrode. The dummy electrode (ST) may also be a 'stopper portion'.

[0289] The underfill (FI) may be positioned within the cavity (CV) of the core layer (111). Accordingly, the underfill (FI) may overlap the core layer (111) in a horizontal direction (X-axis direction). In addition, the underfill (FI) may be in contact with the connecting member (BR) within the cavity (CV). For example, the underfill (FI) may be in contact with the lower surface and the side surface of the connecting member (BR) within the cavity (CV). The underfill (FI) may be positioned between the connecting member (BR) and the inner wall (IS) of the cavity (CV). In addition, the underfill (FI) may be positioned between the lower build-up layer (113) (or dummy electrode) and the lower surface of the connecting member (BR). By this underfill, alignment of the connecting member (BR) within the cavity (CV) is easily implemented, and the inflow of the upper build-up layer between the connecting member (BR) and the inner wall (IS) of the cavity (CV) is reduced, so that the flatness of the upper surface of the upper build-up layer can be improved.

[0290] Referring further to FIGS. 21 to 23, in a circuit board (100C) according to an embodiment, an underfill (FI) may be positioned between a connecting member (BR) and an inner wall (IS) of a core layer (111) within a cavity (CV) and between the connecting member (BR) and a lower build-up layer (113) (or a dummy electrode).

[0291] The underfill (FI) can surround the connecting member (BR) at the bottom of the cavity (CV). Thus, the underfill (FI) can easily protect the connecting member (BR).

[0292] Additionally, the upper build-up layer (112) may be positioned between the inner wall (IS) of the cavity (CV) and the connecting member (BR). Accordingly, the upper build-up layer (112) may be in contact with the upper surface (US1) of the underfill (FI).

[0293] At this time, the upper surface (US1) of the underfill (FI) may be formed convexly toward the lower surface (BS) from the upper surface (US) of the core layer (111). For example, the underfill (FI) may have a concave surface having a concave structure toward the lower surface of the core layer (1110). In addition, the upper surface (US) of the underfill (FI) may be such a concave surface. Accordingly, while the alignment of the connecting member (BR) is accurately achieved, overflow to the upper surface (US) of the core layer (111) can be easily suppressed. Furthermore, the bonding strength between the underfill (FI) and the connecting member (BR) (or core layer) is improved, and the bonding strength between the underfill (FI) and the upper build-up layer (112) can also be improved.

[0294] In addition, the upper surface (US) of the core layer (111) may be flush with the upper surface (US2) of the connection member (BR) or may be offset from each other in the horizontal direction (X-axis direction). For example, the upper surface (US) of the core layer (111) and the upper surface (US2) of the connection member (BR) may have the same vertical distance (Y-axis direction) from the lower surface (BS) of the core layer (111). In this way, when the upper surface (US) of the core layer (111) and the upper surface (US2) of the connection member (BR) are flush with each other, the formation of the upper electrode portion (122) in the upper build-up layer (112) can be more easily performed. For example, the formation of the upper via electrode (122b) in contact with the wiring (BE) of the connection member (BR) and the core wiring portion (121a) can be implemented in a single process. In other words, process simplification can be implemented.

[0295] In addition, the upper surface (US) of the core layer (111) and the upper surface (US2) of the connecting member (BR) can form a predetermined separation distance in the vertical direction (Y-axis direction).

[0296] Furthermore, the upper surface (US2) of the connecting member (BR) may be positioned below the upper surface (US) of the core layer (111). This will be described later.

[0297] And the upper surface (US2) of the connecting member (BR) may be positioned above the upper surface (US) of the core layer (111). Accordingly, at least a part of the connecting member (BR) may not overlap with the core layer (111) in the horizontal direction (X-axis direction) but may be misaligned.

[0298] In addition, the upper surface (US1) of the underfill (FI) may be positioned lower than the upper surface (US) of the core layer (111) and the upper surface (US2) of the connecting member (BR). For example, the vertical distance (Y-axis direction) between the upper surface (US1) of the underfill (FI) and the lower surface (BS) of the core layer (111) may be smaller than the vertical distance (Y-axis direction) between the upper surface (US) of the core layer (111) and the lower surface (BS) of the core layer (111). In addition, the vertical distance (Y-axis direction) between the upper surface (US1) of the underfill (FI) and the lower surface (BS) of the core layer (111) may be smaller than the vertical distance (Y-axis direction) between the upper surface (US2) of the connecting member (BR) and the lower surface (BS) of the core layer (111). By this configuration, the underfill may not be placed on the upper surface of the core layer (111), and the upper build-up layer (112) may not be filled to the lower portion of the cavity (CV). Therefore, the flatness of the upper surface of the upper build-up layer (112) is improved, so that the quality is improved when forming an electrode portion or via, and the electrical quality can be greatly improved.

[0299] The underfill (FI) can overlap the connecting member (BR) and the core layer (111) in the horizontal direction (X-axis direction). And the underfill (FI) can be positioned on the upper surface or the stopper portion of the lower build-up layer (113) within the cavity (CV). Accordingly, the underfill (FI) is in contact with the lower build-up layer (113), but can be positioned offset from the underfill (FI) without overlapping it in the horizontal direction (X-axis direction). In addition, the lower surface (BS1) of the underfill (FI) can be flush with the lower surface (BS) of the core layer (111). Furthermore, the lower surface (BS1) of the underfill (FI) can be in contact with the upper surface of the lower build-up layer (113) and form the same surface as the upper surface of the lower build-up layer (113).

[0300] The inner wall (IS) of the cavity (CV) in the core layer (111) on a plane (a plane perpendicular to the Y-axis direction) may be formed of a plurality of walls (or surfaces). For example, the cavity (CV) may have a rectangular shape on a plane.

[0301] Additionally, in the embodiment, the gap distance (gap1, gap2) between the connecting member (BR) and the inner wall (IS) of the cavity (CV) may be the same or different depending on the location. For example, the gap distance (gap1) between one outer surface of the connecting member (BR) and the adjacent inner wall (IS) may be the same or different from the gap distance (gap2) between the other outer surface of the connecting member (BR) and the adjacent inner wall (IS).

[0302] Additionally, an upper build-up layer or underfill (FI) may be positioned between the outer surface of the connecting member (BR) and the adjacent inner wall (IS).

[0303] And the cavity (CV) may include a first region (AR1) and a second region (AR2). The first region (AR1) may be a region that is misaligned with the connecting member (BR) in the vertical direction (Y-axis direction). And the second region (AR2) may be a region that overlaps with the connecting member (BR) in the vertical direction (Y-axis direction). Therefore, the first region (AR1) may be a region between the connecting member (BR) and the inner wall (IS) of the core layer (111).

[0304] An underfill (FI) may be placed in the first region (AR1). An underfill (FI) and a connecting member (BR) may be placed in the second region (AR2).

[0305] In an embodiment, the upper build-up layer (112) may have a thickness (T2) greater than a thickness on the upper surface (US2) of the connecting member (BR) or the upper surface (US) of the core layer (111) on the first region (AR1). For example, the thickness (T2) of the upper build-up layer (112) on the first region (AR1) may be greater than a thickness (T3) of the upper build-up layer (112) on the upper surface (US2) of the connecting member (BR). In addition, the thickness (T2) of the upper build-up layer (112) on the first region (AR1) may be greater than a thickness (T1) of the upper build-up layer (112) on the upper surface (US) of the core layer (111). In addition, the thickness of the upper build-up layer (112) may be greatest on the first region (AR1). By this configuration, the heat dissipation effect emitted from the connecting member (BR) is improved, and the upper build-up layer is introduced into the cavity, so that mechanical strength can be maintained.

[0306] And the thickness (T2) of the upper build-up layer (112) on the first region (AR1) may be smaller than the length in the vertical direction (Y-axis direction) of the first region (AR). In addition, the thickness (T2) of the upper build-up layer (112) on the first region (AR1) may be smaller than the thickness of the core layer (111) (or the thickness of the cavity (CV)). In addition, the thickness (T2) of the upper build-up layer (112) on the first region (AR1) may be smaller than the thickness of the connecting member (BR). In addition, the thickness (T2) of the upper build-up layer (112) on the first region (AR1) may be smaller than the thickness (T4) of the underfill (FI) in the first region (AR1). By this configuration, even when the cavity (CV) and the connecting member (BR) are mounted within the circuit board, the thickness change of the upper build-up layer (112) can be controlled to a minimum, so that the flatness of the upper surface of the upper build-up layer (112) can be maintained. As a result, component mounting and formation of each component of the circuit board can be facilitated, and the electrical characteristics of the circuit board can also be improved.

[0307] In addition, the thickness of the upper build-up layer (112) may increase toward the center (CP) on the first region (AR1). That is, the height (T4) from the lower surface (BS1) on the upper surface (US1) of the underfill (FI) may increase as it approaches the inner wall (IS) of the connecting member (BR) or the cavity (CV). In addition, the upper surface (US1) of the underfill (FI) may be adjacent to the lower side as it approaches the center (CP) between the inner wall (IS) and the connecting member (BR). Furthermore, the upper build-up layer (112) may have a maximum thickness (T22) at the center (CP) on the upper surface (US1) of the underfill (FI). By this configuration, the bonding between the upper build-up layer and the underfill may be easily achieved.

[0308] Additionally, the thickness (T4) of the underfill (FI) in the first region (AR1) may be greater than the thickness (T2) of the upper build-up layer (112) in the first region (AR1).

[0309] Additionally, the upper surface (US1) of the underfill (FI) may be positioned above the vertical bisector (Y-axis direction) of the connecting member (BR). In other words, the upper surface (US1) of the underfill (FI) may be positioned closer to the upper surface (US2) than to the lower surface (BS2) of the connecting member (BR).

[0310] By this configuration, the amount of the upper build-up layer (112) flowing into the first region (or between the inner wall (IS) and the bridge circuit) can be reduced. Accordingly, the flatness of the upper insulating layer can be maintained at a high level.

[0311] Fig. 24 is an enlarged view of a portion of a circuit board according to a modified example, and Fig. 25 is a plan view of a core layer, a cavity, an underfill, and a connecting member in a circuit board according to a modified example.

[0312] Referring to FIGS. 24 and 25, in a modified example, the distance between the connecting member (BR) and the inner wall (IS) of the cavity (CV) may vary depending on the location within the cavity (CV).

[0313] For example, the gap distance (gap1) between one outer surface of the connecting member (BR) and the adjacent inner wall (IS) may be different from the gap distance (gap2) between the other outer surface of the connecting member (BR) and the adjacent inner wall (IS).

[0314] Additionally, the upper surface (US1) of the underfill (FI) may be different or the same depending on the location in the first region (AR1). For example, in the present example, the upper surface (US1) of the underfill (FI) may be the same even at different locations in the first region (AR1).

[0315] As another example, the upper surface (US1) of the underfill (FI) may vary depending on the position in the first region (AR1). For example, the upper surface of the underfill (FI) between one outer surface of the connecting member (BR) and the adjacent inner wall (IS) may not horizontally overlap with the upper surface of the underfill (FI) between the other outer surface of the connecting member (BR) and the adjacent inner wall (IS). In addition, the thickness of the underfill (FI) may vary depending on the position in the first region (AR1). For example, the thickness of the underfill (FI) between one outer surface of the connecting member (BR) and the adjacent inner wall (IS) may differ from the thickness of the underfill (FI) between the other outer surface of the connecting member (BR) and the adjacent inner wall (IS). Furthermore, the upper build-up layer (112) may also have a thickness (T2) varying depending on the position in the first region (AR1).

[0316] Figures 26 to 33 are drawings explaining a method for manufacturing a circuit board according to an embodiment of the present invention.

[0317] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0318] Referring to Fig. 26, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or more as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0319] Referring to FIG. 27, a via hole or a through hole (111h) can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0320] Referring to Fig. 28, a core electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0321] For example, a plating process may be performed on a via hole formed in the core layer (111) to form a through electrode. In addition, a core wiring portion may be formed on the upper and lower surfaces of the core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions. Furthermore, a dummy electrode (ST) or a film, etc., which are dummy electrodes, may be disposed on the lower surface of the core layer (111).

[0322] Referring to Fig. 29, a cavity (CV) can be formed in a region of the core layer (111) by various methods such as a laser method, a punching method, and an etching method. The cavity (CV) can be easily formed by a dummy electrode (ST). The cavity (CV) can penetrate the core layer (111). However, the present invention is not limited thereto, and the cavity (CV) can penetrate up to a part of the core layer (111). That is, the cavity (CV) can be a hole or a groove.

[0323] In addition, a dummy electrode (ST) is disposed at the bottom, and when the cavity (CV) is a hole, the dummy electrode (ST) may be exposed by the cavity (CV). In addition, the dummy electrode (ST) may be larger than the area or width of the cavity (CV). Accordingly, the dummy electrode (ST) may be in contact with the lower surface of the core layer (111).

[0324] Referring to FIG. 30, an underfill (FI) may be placed in the cavity (CV) of the core layer (111). To form the underfill (FI) within the cavity (CV), a lower build-up layer may be formed beneath the core layer (111). In addition, the aforementioned film or dummy electrode may be placed beneath the core layer (111). The underfill (FI) may be settled on the upper build-up layer or the dummy electrode. In addition, the underfill (FI) may be applied within the cavity (CV).

[0325] Referring to FIG. 31, a connecting member (BR) may be mounted in a cavity (CV). The connecting member (BR) may be seated on an underfill (FI) within the cavity (CV). Additionally, the connecting member (BR) may be surrounded by the underfill (FI).

[0326] As described above, the underfill (FI) may be positioned in the area between the inner wall of the cavity (CV) and the connecting member (BR) and in the lower area of ​​the connecting member (BR). As the connecting member (BR) is mounted within the cavity (CV), the upper surface of the underfill (FI) may have a convex shape from the center toward the lower surface of the core layer.

[0327] Through this underfill (FI), the underfill can be filled between the inner wall and the connecting member. This can protect the circuit board from impact, dropping, and vibration. Furthermore, deformation due to thermal expansion differences between other components, such as the connecting member (BR) and the core layer (111), can be reduced. Furthermore, the position of the connecting member (BR) within the cavity (CV) can be positioned more precisely according to the design, and the upper build-up layer described below can be prevented from flowing between the inner wall and the connecting member (BR).

[0328] Referring to FIG. 32, as described above, the upper build-up layer (112) may be formed on top of the core layer (111) and within the cavity (CV). Additionally, the lower build-up layer (113) may be formed under the core layer (111). However, as before, the lower build-up layer (113) may be formed in advance under the core layer (111) before forming the underfill (FI).

[0329] For example, underfill (FI) may be further applied within the cavity (CV). Accordingly, the underfill (FI) may improve the bonding strength between the core layer (111) and the connecting member (BR).

[0330] Referring to FIG. 33, a via hole or through hole may be formed in the upper build-up layer (112) and / or the lower build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0331] Additionally, an upper electrode portion (122) may be formed on the upper build-up layer (112). And a lower electrode portion (123) may be formed on the lower build-up layer (113). The upper electrode portion (122) and the lower electrode portion (123) may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0332] And the upper wiring part of the upper electrode part (122) may be formed on the upper surface of the upper build-up layer (112), and the lower wiring part of the lower electrode part (123) may be formed on the lower surface of the lower build-up layer (113). Each wiring part may have a pattern by a mask or the like. Furthermore, the wiring part may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes of a printed circuit board.

[0333] Afterwards, a first protective layer (SR1) may be formed on the upper build-up layer (112). And a second protective layer (SR2) may be formed under the lower build-up layer (113). Furthermore, a via portion (TP) penetrating the protective layer (SR) may be formed. In addition, a protrusion portion (PP) connected to the via portion (TP) may be formed in the protective layer (SR). In other words, a bump portion or a bonding portion (BP) may be formed in the protective layer (SR).

[0334] Figure 34 is a drawing explaining the effect of a circuit board according to an embodiment.

[0335] Referring to FIGS. 34(a) and 34(b), FIG. 34(a) is a profile showing the thickness (flatness of the surface (top surface)) of the upper build-up layer in the horizontal direction in the absence of underfill. And FIG. 34(b) is a cross-sectional view of a circuit board (e.g., before dicing) in a panel unit composed of multiple circuit boards in the absence of underfill. Flatness can be measured by various methods, such as a 3D profiler, a laser interferometer, a 3D measuring instrument, or ultrasonic waves.

[0336] Referring to FIGS. 34(a) and 34(b), it can be seen that when no underfill is applied between the connecting member and the inner wall of the cavity, the upper build-up layer has a large thickness change in the first region (AR1).

[0337] In this way, it can be sufficiently seen that the flatness of the upper surface of the build-up layer does not change significantly on the first region (AR1) where the thickness change is large compared to the second region (AR2) in the circuit board according to the embodiment. Accordingly, when manufacturing a circuit board, the pattern defect rate in the exposure and development processes is reduced, the defect rate for electrical connections such as soldering is reduced, and the impedance change as a signal transmission path is reduced, so that the electrical characteristics can be maintained even when the position changes.

[0338] Fig. 35 is a cross-sectional view of a circuit board according to the fifth embodiment, and Fig. 36 is an enlarged view of part K4 in Fig. 35.

[0339] Referring to FIGS. 35 and 36, a circuit board (100D) according to the fifth embodiment may include an insulating layer (110), an electrode portion (120), an underfill (FI), and a connecting member (BR). Furthermore, the circuit board (100D) may further include a protective layer (SR) and a bonding portion (BP). As described above, the build-up electrode portions (122, 123) may be disposed to be embedded in each layer (e.g., an insulating layer) of the build-up insulating portions (112, 113), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. In addition, the connecting member (BR) may be positioned within a cavity (CV) formed in a core layer (111) of the insulating layer (110). Except for the contents described below with respect to the circuit board, the above-described contents may be equally applied.

[0340] In this example, the connecting member (BR) may be positioned within the cavity CV of the core layer (111). And the dummy electrode (ST) or the lower build-up layer (113) may be positioned at the bottom of the cavity CV and may be in contact with the lower surface of the core layer (111).

[0341] And the thickness of the upper build-up layer (112) may be the largest on the first region (AR1). In this example, the thickness (T2') of the upper build-up layer (112) on the first region (AR1) may be greater than the thickness (T1) of the upper build-up layer (112) on the upper surface (US) of the core layer (111). The thickness (T2') of the upper build-up layer (112) on the first region (AR1) may be greater than the thickness (T3) on the upper surface (US2) of the connecting member (BR).

[0342] In addition, the thickness (T2') of the upper build-up layer (112) on the first region (AR1) may be greater than the thickness (T4) of the underfill (FI) on the first region (AR1). In addition, the upper surface (US1) of the underfill (FI) may be located below the vertical bisector (Y-axis direction) of the connecting member (BR). In other words, the upper surface (US1) of the underfill (FI) may be located closer to the lower surface (BS2) of the connecting member (BR) than the upper surface (US2).

[0343] By this configuration, the bonding strength between the connecting member (BR) and the upper build-up layer (112) within the cavity (CV) can be improved.

[0344] Additionally, in this example, the upper surface of the upper build-up layer (112) may include a groove formed in an area that overlaps the first area (AR1) in the vertical direction (Y-axis direction). That is, the upper surface of the upper build-up layer (112) includes a groove, and the groove of the upper build-up layer (112) may be positioned on the first area (AR1).

[0345] Fig. 37 is a cross-sectional view of a circuit board according to the sixth embodiment, and Fig. 38 is an enlarged view of part K5 in Fig. 37.

[0346] Referring to FIGS. 34 and 35, a circuit board (100E) according to the sixth embodiment may include an insulating layer (110), an electrode portion (120), an underfill (FI), and a connecting member (BR). Furthermore, the circuit board (100E) may further include a protective layer (SR) and a bonding portion (BP). As described above, the build-up electrode portions (122, 123) may be disposed to be embedded in each layer (e.g., an insulating layer) of the build-up insulating portions (112, 113), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. In addition, the connecting member (BR) may be positioned within a cavity (CV) formed in a core layer (111) of the insulating layer (110). Except for the contents described below with respect to the circuit board, the above-described contents may be equally applied.

[0347] In this example, the connecting member (BR) may be positioned within the cavity CV of the core layer (111). And the dummy electrode (ST) or the lower build-up layer (113) may be positioned at the bottom of the cavity CV and may be in contact with the lower surface of the core layer (111).

[0348] In this example, the underfill (FI) may also be positioned on the upper surface of the connecting member (BR). That is, the underfill (FI) may be in contact with the lower surface, side surface, and upper surface of the connecting member (BR). Furthermore, the underfill (FI) may also be in contact with the upper wiring (BE) of the connecting member (BR).

[0349] Additionally, the connecting member (BR) may be shorter than the length between the lower surface (BS) and the upper surface (US) of the cavity (CV). Additionally, the distance (T5) from the upper surface (US2) of the connecting member (BR) to the lower surface (BS) of the core layer (111) may be greater than the thickness of the cavity (CV).

[0350] Furthermore, the thickness (T22') of the upper build-up layer (112) may be greatest at the center of the upper surface of the underfill (FI). At this time, the center of the upper surface of the underfill (FI) may be closer to the connecting member (BR) than the bisector between the inner surface of the cavity (CV) and the outer surface of the connecting member (BR). Alternatively, the center of the upper surface of the underfill (FI) may overlap the connecting member (BR) in the vertical direction.

[0351] The thickness (T2'') of the upper build-up layer (112) on the first region (AR1) may be equal to or greater than the thickness (T1) of the upper build-up layer (112) on the upper surface (US) of the core layer (111). In addition, the thickness (T2'') of the upper build-up layer (112) on the first region (AR1) may be equal to the thickness (T3) on the upper surface (US2) of the connecting member (BR).

[0352] In addition, the thickness (T2'') of the upper build-up layer (112) on the first region (AR1) may be smaller than the thickness (T4') of the underfill (FI) on the first region (AR1). In addition, the upper surface (US1) of the underfill (FI) may be located above the bisector in the vertical direction (Y-axis direction) of the connecting member (BR). In other words, the upper surface (US1) of the underfill (FI) may be located closer to the upper surface (US2) than to the lower surface (BS2) of the connecting member (BR).

[0353] FIG. 39 is a cross-sectional view of a circuit board according to the seventh embodiment of the present invention, FIG. 40 is an enlarged view of K6 in FIG. 39, FIG. 41 is an enlarged view of K7 in FIG. 39, and FIG. 42 is an enlarged view of K8 in FIG. 39.

[0354] Referring to FIG. 4, a circuit board (100F) according to the seventh embodiment may include a core layer (111), a build-up insulation portion (112, 113), an electrode portion (120), and a connecting member (BR).

[0355] As described above, the build-up insulation portion (112, 113) may include an insulating layer. Accordingly, the circuit board (100F) may include an insulating region (110) composed of a core layer (111) and the build-up insulation portion (112, 113).

[0356] Furthermore, the circuit board (100F) may include a protective layer (not shown) disposed on the electrode portion (120). In addition, a semiconductor element connected to a via electrode may be further disposed on the upper portion of the circuit board (100F).

[0357] First, the core layer (111) may mean an insulating layer including a reinforcing member and having a thickness in the stacking direction or vertical direction (X-axis direction) exceeding a predetermined size (e.g., 30 μm). In addition, the interface between each build-up insulating portion (112, 113) and the core layer (111) may or may not be distinguished depending on the analysis method.

[0358] The core layer (111) may include a cavity (CV). That is, the circuit board (100F) may include a core layer (111) including a cavity (CV). In embodiments, the cavity (CV) may be expressed in various ways, such as a 'groove', a 'recess', a hole, a 'via', etc. Furthermore, the cavity (CV) may have various shapes, such as a flat surface, a circle, a square shape, etc. Furthermore, the inner wall of the cavity (CV) or the inner side of the core layer (111) may have a structure in which the width or diameter increases from the center or the central portion toward the upper surface of the core layer (111), and the width or diameter increases toward the lower surface of the core layer (111). Alternatively, the inner wall of the cavity (CV) or the inner side of the core layer (111) may only have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the core layer (111), or the width or diameter increases toward the lower surface of the core layer (111).

[0359] The cavity (CV) may have various shapes depending on the shape of the component (e.g., connecting member) mounted therein. For example, the shape of the connecting member may generally be rectangular with respect to a plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) may also have a rectangular shape with respect to a plane perpendicular to the stacking direction. However, for easy mounting of the connecting member (BR), it may have various shapes.

[0360] Additionally, the cavity (CV) may include a first region (AR1) that is misaligned in the vertical direction (X-axis direction) with respect to the connecting member (BR) and a second region (AR2) that overlaps in the vertical direction (X-axis direction) with respect to the connecting member (BR).

[0361] The connecting member (BR) can be positioned within the cavity (CV). That is, through the cavity (CV), a mounting space for the connecting member (BR) and the like can be easily secured in the first build-up layer (112). In addition, a third electrode portion (123) having a smaller line width than the second electrode portion (122) outside the cavity (CV) can be easily placed on the upper portion of the cavity (CV). Accordingly, the circuit board according to the embodiment can provide easy connection between semiconductor elements and an improved input / output (I / O) count.

[0362] According to an embodiment, the connecting member (BR) is located within the cavity (CV) of the core layer (111), but may be embedded within the first build-up layer disposed on the core layer (111). That is, according to an embodiment, the core layer (111) may be provided to prevent warpage as the circuit board (100F) becomes thinner, and at this time, the connecting member (BR) may be embedded within the core layer (111). However, when the circuit board (100F) is designed to be multi-layered for signal integrity and power integrity, the connecting member (BR) may be embedded within the first build-up layer to shorten the electrical length between the first and second semiconductor elements (DI1, DI2) and the connecting member (BR). Since the circuit board (100F) according to the embodiment can be used as an interposer, thinning is required, and thus the connecting member (BR) is embedded within the core layer (111), but is not limited thereto. That is, the connection member (BR) can be embedded in the first build-up layer by being equipped with a circuit board (100F) rather than an interposer.

[0363] Additionally, the build-up insulation (112, 113) may include multiple build-up layers. As an example, the multiple build-up insulation (112, 113) may include a first build-up layer (112) and a second build-up layer (113).

[0364] The first build-up layer (112) may be placed on top of the second build-up layer (113). In addition, the first build-up layer (112) may be placed on the core layer (111), and a portion of the first build-up layer (112) may be placed within the cavity (CV) of the core layer (111).

[0365] As an example, the second build-up layer (113), the core layer (111), and the first build-up layer (112) can be sequentially arranged in the vertical direction (X-axis direction).

[0366] In addition, the lower surface (BS2) of the first build-up layer (112) may be in contact with the upper surface (US1) of the core layer (111) and form the same plane. In addition, the lower surface (BS1) of the core layer (111) may be in contact with the upper surface of the second build-up layer (113) and form the same plane. Furthermore, the first build-up layer (112) may be positioned within the cavity (CV). Accordingly, a portion of the lower surface (BS) of the first build-up layer (112) may be in contact with the upper surface of the second build-up layer (113) and form the same plane with each other. This may be implemented within the cavity (CV).

[0367] Additionally, as described above, the upper build-up layer positioned above the core layer (111) may include a first build-up layer (112). And the lower build-up layer positioned below the core layer (111) may include a second build-up layer (113). Additionally, each of the upper build-up layer and the lower build-up layer may include a plurality of insulating layers.

[0368] In addition, as described above, the build-up layer is a different layer from the above-described protective layer (not shown), and the top / bottom surface of the build-up layer (or build-up layer) corresponds to the top / bottom surface of the build-up layer (build-up layer) placed at the top, and does not mean the top / bottom surface of the protective layer (not shown). In other words, the top surface of the build-up layer of the circuit board means the top / bottom surface of the build-up layer, not the protective layer.

[0369] And the build-up insulation (112, 113) may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a photocurable resin (PID, Photo Imageable Dielectric). In addition, the build-up insulation (112, 113) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0370] For example, the build-up insulation portion (112, 113) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. The thermosetting resin may be a resin containing inorganic and / or organic fillers, for example, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., or a material such as prepreg (PPG) containing glass fibers. The photocurable resin may be any insulating resin, such as PID (Photo Imageable Dielectric) resin. The aforementioned insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, or the like, and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material made of glass fibers or aramid fibers. For example, the build-up insulation (112, 113) may be formed of a resin containing inorganic and / or organic fillers, for example, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the build-up insulation (112, 113) may include a plurality of layers composed of ABF.

[0371] Each build-up layer may be composed of the same or different material. For example, a second build-up layer may be composed of the same or different material as the other build-up layers.

[0372] In addition, in the embodiment, the first build-up layer (112) may include a groove (G) located on the upper surface (US2). The groove (G) may be located on the first region (AR1). That is, the groove (G) may not overlap at least a portion of the connecting member (BR) in the vertical direction (X-axis direction). Furthermore, the groove (G) may overlap at least a portion of the cavity (CV) in the vertical direction (X-axis direction). The groove (G) may be provided convexly toward the core layer (111) on the upper surface of the insulating layer that is arranged most adjacent to the core layer (111) among the insulating layers of the first build-up layer (112) located on the first region (AR1). For example, the groove (G) may correspond to a concave region in the vertical direction (X-axis direction) on the upper surface (US2) of the insulating layer that is arranged most adjacent to the core layer (111) among the insulating layers of the first build-up layer (112).

[0373] And the electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0374] As an example, the electrode portion (120) may include a wiring electrode and a via electrode. The wiring electrode may include a wiring (or circuit pattern, pattern) and a pad arranged on a build-up layer. The via electrode may be positioned within a through hole or a via (Vertical Interconnect Access) hole formed on the build-up layer. Through the via electrode, the wirings arranged on each build-up layer may be electrically connected in a vertical direction.

[0375] In addition, the pads arranged on the outermost side along the vertical direction of the electrode portion (120) can be bonded to semiconductor elements, substrates, boards, etc. with solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern in order to solve current technical barriers or yield securing problems. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. In addition, the pads arranged on the inner side function to connect the via electrodes and the circuit pattern. When the via electrodes are arranged with a width wider than the circuit pattern, pads having a width wider than the circuit pattern are provided in order to ensure alignment of the positions of the via electrodes during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad directly in contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad directly in contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, but should also be understood as a concave or convex surface that may appear depending on various processes.

[0376] As an example, the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123) depending on the location. Hereinafter, the electrode portion may include a wiring portion corresponding to the wiring electrode and a via electrode.

[0377] The first electrode portion (121) may include a first wiring portion (121a) and a through electrode (121b). In addition, the second electrode portion (122) may include a second wiring portion (122a) and a first via electrode (122b). The third electrode portion (123) may include a third wiring portion (123a) and a second via electrode (123b).

[0378] The first electrode portion (121) may be positioned on the core layer (111). The through electrode (121b) may penetrate the core layer (111). The through electrode (121b) may have a structure in which the width (or diameter) decreases and then increases along the vertical direction. In addition, the first wiring portion (121a) may be arranged on both sides (upper and lower surfaces) of the core layer (111).

[0379] In the second electrode portion (122), the first via electrode (122b) can penetrate the first build-up layer (112). The second wiring portion (122a) can be located in the first build-up layer (112). For example, the second wiring portion (122a) can be located on the upper surface (US2) of the first build-up layer (112). The width (or diameter) of the first via electrode (122b) can increase in the vertical direction (X-axis direction). Alternatively, the width (or diameter) of the first via electrode (122b) can increase from the lower surface (BS1) of the core layer (111) toward the upper surface (US1).

[0380] The third electrode portion (123) may be positioned in an area vertically overlapping with the connecting member (BR) of the first build-up layer (112). The second via electrode (123b) of the third electrode portion (123) may penetrate the first build-up layer (112). The third wiring portion (123a) of the third electrode portion (123) may be positioned in the first build-up layer (112). For example, the third wiring portion (123a) may be positioned on the upper surface (US2) of the first build-up layer (112). And the second via electrode (123b) may have a width (or diameter) that increases in the vertical direction (X-axis direction). Alternatively, the width (or diameter) of the second via electrode (123b) may increase from the lower surface (BS1) of the core layer (111) toward the upper surface (US1).

[0381] Additionally, the electrode portion (120) may further include an electrode portion (not shown) penetrating the second build-up layer (113).

[0382] Furthermore, the through-hole electrode (121b) may be positioned between the upper surface (US1) and the lower surface (BS1) of the core layer (111). The through-hole electrode (121b) may penetrate the upper surface (US1) and the lower surface (BS1) of the core layer (111). In addition, the first via electrode (122b) may be positioned between the upper surface (US2) and the lower surface (BS2) of the first build-up layer (112). Alternatively, the first via electrode (122b) may be disposed between the upper surface (US) of the core layer (111) and the upper surface (US2) of the first build-up layer (112). The first via electrode (122b) may penetrate the upper surface (US2) and the lower surface (BS2) of the first build-up layer (112). In addition, the second via electrode (123b) may be positioned between the upper surface (US2) and the lower surface (BS2) of the first build-up layer (112). Alternatively, the second via electrode (123b) may be disposed between the upper surface (US3) of the connecting member (BR) (or the upper surface (US) of the core layer (111)) and the upper surface (US2) of the first build-up layer (112). The second via electrode (123b) may penetrate the upper surface (US2) and the lower surface (BS2) of the first build-up layer (112). That is, the penetration electrode (121b), the first via electrode (122b), and the second via electrode (123b) may penetrate the build-up layer adjacent to the core layer. In the embodiment, the upper surface (US3) of the connecting member (BR) may be located between the upper surface (US2) of the first build-up layer (112) and the upper surface (US1) of the core layer (111).

[0383] Furthermore, the third electrode part (123) may be positioned above the cavity (CV) of the core layer (111). Accordingly, the third electrode part (123) may overlap with the cavity (CV) (or connecting member) in the vertical direction (X-axis direction). And the second electrode part (122) may be positioned above an area other than the cavity (CV) in the core layer (111). Accordingly, the second electrode part (122) may overlap with an area other than the cavity (CV) in the core layer (111) in the vertical direction (X-axis direction).

[0384] Additionally, in this specification, the through-hole electrode and the via electrode may be positioned within a via hole formed in the core layer and each build-up layer, etc. This corresponds to the via electrode penetrating at least a portion of each build-up layer, etc. This is described as a reference in this specification.

[0385] And, among the plurality of via electrodes in the circuit board (100F), the through electrode (121b) may be positioned in a different region in the vertical direction with respect to the first via electrode (122b) and the second via electrode (123b). For example, the through electrode (121b) may not overlap with the first via electrode (122b) and the second via electrode (123b) in the horizontal direction (Y-axis direction).

[0386] Additionally, the first via electrode (122b) may overlap with the second via electrode (123b) in the horizontal direction (Y-axis direction). Additionally, at least a portion of the first via electrode (122b) may not overlap with the second via electrode (123b) in the horizontal direction (Y-axis direction).

[0387] A protective layer (not shown) may be further disposed on the top or bottom of the build-up insulation (112, 113). The protective layer (not shown) may include a first protective layer and a second protective layer. The first protective layer may be positioned below the second build-up layer (113). And the second protective layer may be positioned above the first build-up layer (112).

[0388] A protective layer (not shown) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining a semiconductor element and / or a main board and a circuit board, the protective layer (not shown) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material that has insulating properties for electrical connection. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third build-up layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. Furthermore, the build-up layer or protective layer (not shown) located in the outer laminated region of the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor devices, circuit boards, etc.

[0389] Additionally, the protective layer (not shown) may include a connection groove for electrical connection with each electrode portion and semiconductor elements, etc.

[0390] Referring to FIG. 40, the upper surface (US1) of the core layer (111) may be positioned lower than the upper surface (US3) of the connecting member (BR). In addition, the upper surface (US3) of the connecting member (BR) may be positioned between the upper surface (US1) of the core layer (111) and the upper surface (US2) of the first build-up layer (112). Accordingly, a predetermined vertical distance (gap1) may exist between the upper surface (US1) of the core layer (1112) and the upper surface (US3) of the connecting member (BR). In addition, the vertical length (thickness) of the connecting member (BR) may be greater than the vertical length (thickness) of the core layer (111). Accordingly, even if the widths (or diameters) between the first via electrode (122b) and the second via electrode (123b) are different from each other, uniform plating properties for the via electrodes can be secured along the vertical length of the first via electrode (122b) and the second via electrode (123b). In other words, the first via electrode (122b) and the second via electrode (123b) may not have a vertically convex or concave shape on their upper surfaces. In addition, in the process of arranging the connecting member (BR) in the cavity (CV) and then filling it with an insulating layer, the height difference between the area where the upper surface of the insulating layer filling the connecting member (BR) vertically overlaps the connecting member (BR) and the area where it does not vertically overlap the cavity (CV) is made uniform, thereby securing the yield of the plating and lamination processes in the subsequent processes.

[0391] In this way, if the width (or diameter) of a via electrode of the same length is varied, a conductive layer such as copper may be filled into the via in response to the width (or diameter), which may cause different lengths of the via electrode, for example, uneven filling. This may result in a decrease in the reliability of the via electrode or difficulty in electrical connection with other elements. In the embodiment, the uneven via electrode structure described above can be solved by arranging the upper surface (US3) of the connecting member (BR) above the lower surface (BS2) of the first build-up layer (112) in response to the fact that the width of the third electrode portion on the cavity (CV) is smaller than the width of the second electrode portion.

[0392] Additionally, the length in the horizontal direction of the first region (AR1) can correspond to the gap distance (gap2, gap3) between the connecting member (BR) and the inner surface of the cavity (CV).

[0393] Referring to FIG. 40, the first region (AR1) between the connecting member (BR) and the wall surface of the cavity (CV) may be a spaced region surrounding the connecting member and may have a closed loop shape surrounding the connecting member (BR). In addition, the horizontal length of the first region (AR1) may not be uniform along the perimeter of the connecting member (BR). That is, the position of the connecting member (BR) may be misaligned during the process of arranging the connecting member (BR) and / or the process of curing the adhesive film (not shown) arranged between the connecting member (BR) and the core layer (111). Accordingly, the vertical depth of the groove (G) may also not be uniform along the perimeter of the first region (AR1). If the connecting member (BR) is not located at the center of the circuit board (100F), the horizontal width and vertical depth of the groove (G) may not be uniform along the perimeter of the connecting member (BR), and if a plurality of connecting members (BR) are arranged, the unevenness of the grooves (G) can evenly distribute the stress applied to the circuit board (100F), thereby alleviating the overall warpage of the circuit board (100F). However, in the embodiment, for the convenience of explanation, an example in which one connecting member (BR) is arranged at the center of the circuit board (100F), and the horizontal length of the first region (AR1) is uniform along the perimeter of the connecting member (BR) is described. Accordingly, the groove (G) on the first region (AR1) may also have the same length in the vertical direction. For example, the groove (G) may overlap the third electrode portion (123) in the horizontal direction (Y-axis direction). The groove (G) may overlap horizontally with the second via electrode (123b) of the third electrode portion (123). In addition, the groove (G) may not overlap horizontally with the connecting member (BR). This groove (G) may perform an anchor function. That is, when an additional insulating layer is disposed on the insulating layer that embeds the connecting member (BR), the bonding strength between the added insulating layer and the existing first build-up layer (112) may be improved by the groove (G).Furthermore, the warpage phenomenon of various components, such as the build-up layer and core layer, can be controlled through the home (G). In other words, the reliability of the circuit board can be improved.

[0394] Referring to FIG. 41, specifically, the through electrode (121b), the first via electrode (122b), and the second via electrode (123b) penetrating the first build-up layer (112) may have different lengths in the vertical direction (X-axis direction). For example, the first via electrode (122b) and the second via electrode (123b) may penetrate at least a portion of the insulating layer of the first build-up layer (112). Accordingly, the first via electrode (122b) and the second via electrode (123b) may be electrodes penetrating one insulating layer or a plurality of insulating layers. However, in the embodiment, it is described that the first via electrode (122b) and the second via electrode (123b) penetrating the first build-up layer (112), which is one insulating layer. That is, the height or length (H1) in the vertical direction of the first via electrode (122b) may be different from the height or length (H2) in the vertical direction of the second via electrode (123b). For example, the height or length (H1) in the vertical direction of the first via electrode (122b) may be greater than the height or length (H2) in the vertical direction of the second via electrode (123b).

[0395] In addition, the maximum width (or diameter) of the first via electrode (122b) may be different from the maximum width (or diameter) of the second via electrode (123ㅠ). The following description will be based on the width. In addition, as described above, the width (W1) of the first via electrode (122b) may increase in the vertical direction or toward the upper surface of the first build-up layer (112). In addition, the width (W2) of the second via electrode (122b) may increase in the vertical direction or toward the upper surface of the first build-up layer. Conversely, the width (W1) of the first via electrode (122b) may decrease toward the lower surface of the first build-up layer (112). In addition, the width (W2) of the second via electrode (122b) may decrease toward the lower surface of the first build-up layer.

[0396] Accordingly, the first via electrode (122b) can have a maximum width (W1a) on the upper surface. Similarly, the second via electrode (123b) can have a maximum width (W2a) on the upper surface. At this time, the maximum width (W1a) of the first via electrode (122b) can be larger than the maximum width (W2a) of the second via electrode (123b). Accordingly, the upper surfaces of the first via electrode (122b) and the second via electrode (123b) described above can be formed flat through uniform plating.

[0397] Additionally, the first via electrode (122b) and the second via electrode (123b) may be spaced apart from each other in the horizontal direction. Furthermore, the groove (G) may also be located in the area between the first via electrode (122b) and the second via electrode (123b) in the first area.

[0398] Referring further to Fig. 42, the groove (G) may include a first groove (G1) and a second groove (G2) spaced apart from each other in cross section. However, since the groove (G) is positioned in a cavity (CV) that does not vertically overlap with the connecting member (BR), it may be positioned to surround the connecting member (BR) along the outer side of the connecting member (BR). The groove (G) may be positioned continuously or discontinuously along the outer side of the connecting member (BR). This means that, as described above, the groove (G) may have a uniform depth in some areas and an uneven depth in other areas.

[0399] For example, if the grooves (G) are arranged discontinuously, the grooves (G) may include a first groove (G1) and a second groove (G2). If the grooves (G) are continuous, they may include a first groove (G1) and a second groove (G2) that are separated from each other.

[0400] Furthermore, the length (H3) in the vertical direction of the partitioned area or the spaced first groove (G1) and the length (H4) in the vertical direction of the second groove (G2) may be the same or different. The length (H3) in the vertical direction of the partitioned area or the spaced first groove (G1) and the length (H4) in the vertical direction of the second groove (G2) may correspond to the gap distance (gap2, gap3) between the connecting member (BR) and the inner surface of the cavity (CV).

[0401] In an embodiment, the distance (gap2, gap3) between the inner surface of the connecting member (BR) and the cavity (CV) (or the distance in the horizontal direction of the first region) may be the same. Accordingly, the vertical length (H3) of the partitioned region or the spaced first groove (G1) and the vertical length (H4) of the second groove (G2) may be the same. Accordingly, the bonding force between the first build-up layer (112) and the additional build-up layer on top may be formed uniformly without being concentrated on one side.

[0402] Fig. 43 is a cross-sectional view of a circuit board according to the eighth embodiment, Fig. 44 is a modified example of Fig. 43, and Fig. 45 is another modified example of Fig. 43.

[0403] Referring to Fig. 43, a circuit board (100G) according to the eighth embodiment may include a core layer (111), a build-up insulation portion (112, 113), an electrode portion (120), and a connecting member (BR). In addition, the above-described contents may be equally applied, except for the contents described below.

[0404] In the circuit board (100F) according to the eighth embodiment, the first region (AR1) may include a first-first region (AR11) and a first-second region (AR12). The first-first region (AR11) and the first-second region (AR12) may have different lengths in the horizontal direction. That is, the distance between the connection member (BR) and the inner surface of the cavity (CV) in the first-first region (AR11) and the first-second region (AR12) may be different from each other. For example, the distance (gap2) between the connection member (BR) and the inner surface of the cavity (CV) in the first-first region (AR11) may be greater than the distance (gap3) between the connection member (BR) and the inner surface of the cavity (CV) in the first-first region (AR11).

[0405] Furthermore, the groove (G) may include a first groove (G1) on the first-first region (AR11) and a second groove (G2) on the first-second region (AR12). The first groove (G1) may overlap vertically with the first-first region (AR11). The second groove (G2) may overlap vertically with the first-second region (AR12).

[0406] Furthermore, the length (H3) in the vertical direction of the partitioned area or the spaced first groove (G1) and the length (H4) in the vertical direction of the second groove (G2) may be different from each other. The length (H3) in the vertical direction of the partitioned area or the spaced first groove (G1) may be greater than the length (H4) in the vertical direction of the second groove (G2). Accordingly, the first groove (G1) may have a height difference (gap4) with the second groove (G2). That is, a height difference (gap4) may exist between the first groove (G1) and the second groove (G2).

[0407] Accordingly, the bottom surface of the first groove (G1) may be located between the upper surface (US3) of the connecting member (BR) and the upper surface (US1) of the core layer (111). In an embodiment, the groove (G) may at least partially overlap with the connecting member (BR) in the horizontal direction. That is, the first groove (G1) may overlap with the connecting member (BR) in the horizontal direction. However, the first groove (G1) may not overlap with the core layer (111) in the horizontal direction. In other words, the first groove (G1) may be misaligned with the core layer (111) in the horizontal direction.

[0408] Furthermore, the second groove (G2) may not overlap horizontally with the core layer (111). In addition, the second groove (G2) may or may not overlap horizontally with a portion of the connecting member (BR).

[0409] The length (H3) in the vertical direction of the spaced first groove (G1) and the length (H4) in the vertical direction of the second groove (G2) may be the same or different. The length (H3) in the vertical direction of the partitioned area or the length (H4) in the vertical direction of the second groove (G2) may correspond to the gap distance (gap2, gap3) between the connecting member (BR) and the inner surface of the cavity (CV).

[0410] Referring to Fig. 44, the first groove (G1) and the second groove (G2) may have a height difference therebetween. In particular, the bottom surface of the first groove (G1) may be positioned below the upper surface (US1) of the core layer (111). Accordingly, the first groove (G1) may overlap with the core layer (111) in the horizontal direction. However, the bottom surface of the first groove (G1) may be vertically spaced apart from the lower surface of the core layer (111) by a predetermined distance. In addition, the first groove (G1) may overlap with the connecting member (BR) in the horizontal direction. The second groove (G2) may not overlap with the core layer (111) and the connecting member (BR) in the horizontal direction.

[0411] Referring to Fig. 45, there may be a height difference between the first groove (G1) and the second groove (G2). However, the height difference between the first groove (G1) and the second groove (G2) may be smaller than the distance between the upper surface of the connecting member (BR) and the upper surface of the first build-up layer (112).

[0412] Accordingly, the first groove (G1) may have its bottom surface positioned above the upper surface (US1) of the core layer (111). In addition, the first groove (G1) may have its bottom surface positioned above the upper surface (US3) of the connecting member (BR). Accordingly, the first groove (G1) may not horizontally overlap with the core layer (111) and the connecting member (BR). In addition, the second groove (G2) may not horizontally overlap with the core layer (111) and the connecting member (BR).

[0413] As in the examples described above, the vertical length of the groove (G) can be adjusted in various ways depending on the position. Accordingly, the warpage of the circuit board can be easily controlled by adjusting the length of the groove (G) and the distance between the connecting member and the inner surface of the cavity.

[0414] Figures 46a to 46h are drawings explaining a method for manufacturing a circuit board according to the seventh embodiment of the present invention.

[0415] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0416] Referring to Fig. 46a, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or more, as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0417] Referring to FIG. 46b, a via hole or a through hole can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0418] Referring to Fig. 46(c), a first electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0419] For example, a plating process may be performed on a via hole formed in a core layer (111) to form a through electrode. Then, a first wiring portion may be formed on the upper and lower surfaces of the core layer (111). The first wiring portion may have a pattern using a mask or the like. Furthermore, the first wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions.

[0420] Furthermore, a stopper portion (ST) may be arranged on the lower surface of the core layer (111). However, a connecting member may be mounted in the cavity described below through various members (e.g., a film) without the stopper portion (ST). In addition, the stopper portion (ST) may be a dummy electrode.

[0421] Referring to Fig. 46(d), a cavity (CV) can be formed in a region of the core layer (111) by a laser method, a punching method, an etching method, or the like. The cavity (CV) can be easily formed by a stopper portion (ST). The cavity (CV) can penetrate the core layer (111). However, the present invention is not limited thereto, and the cavity (CV) can penetrate a portion of the core layer (111). That is, the cavity (CV) can be a hole or a groove.

[0422] Referring to Fig. 46(e), a connecting member (BR) can be mounted in the cavity (CV) of the core layer (111). The connecting member (BR) can be mounted on the stopper portion (ST). Alternatively, if the stopper portion (ST) does not exist, a member (e.g., a film) can be placed on the lower surface of the core layer (111) after the cavity (CV) is formed. The above-described member (e.g., a film) can overlap the cavity (CV) in a vertical direction. And the connecting member (BR) can be mounted on the member (e.g., a film).

[0423] Referring to FIG. 46(f), a first build-up layer (112) may be formed on top of the core layer (111) and within the cavity (CV). Additionally, a second build-up layer (113) may be formed on the bottom of the core layer (111). At this time, the upper surface of the first build-up layer (112) may have a groove (G) formed on the first region described above.

[0424] In addition, before forming the first build-up layer (112), underfilling may be performed to fix the position of the connecting member (BR) in the cavity (CV). For example, a filling member (F1) may be applied within the cavity (CV). Accordingly, the filling member (F1) may improve the bonding strength between the core layer (111) and the connecting member (BR). As a result, the circuit board may be protected from impact, dropping, and vibration. In addition, deformation due to differences in thermal expansion between other components, such as the connecting member (BR) and the core layer (111), may be reduced. The filling member (F1) may include epoxy, etc.

[0425] Referring to FIG. 46(g), a via hole or through hole may be formed in the first build-up layer (112) and / or the second build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0426] Referring to Fig. 46(h), a second electrode portion (122) and a third electrode portion (123) may be formed on the first build-up layer (112). In addition, an electrode portion may also be formed on the second build-up layer (113). Such an electrode portion may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0427] And, a second wiring section, a third wiring section, etc. can be formed on the upper and lower surfaces of the first build-up layer (112). Each wiring section can have a pattern using a mask, etc. Furthermore, the wiring section can be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards.

[0428] Fig. 47 is a cross-sectional view of a circuit board according to the ninth embodiment, Fig. 48 is an enlarged view of K9 in Fig. 47, and Fig. 49 is a modified example of Fig. 48.

[0429] Referring to FIGS. 47 and 48, a circuit board (100H) according to the ninth embodiment may include a core layer (111), build-up layers (112, 113, 114, 115), an electrode portion (120), and a connecting member (BR). In addition, the above-described contents may be equally applied, except for the contents described below.

[0430] There may be multiple build-up layers. For example, the build-up layers may include a first build-up layer (112), a second build-up layer (113), a third build-up layer (114), and a fourth build-up layer (115). The first build-up layer (112) may be disposed on top of the core layer (111) and in the cavity (CV). And the second build-up layer (113) may be positioned on top of the first build-up layer (112). The upper surface of the first build-up layer (112) may be in contact with the lower surface of the second build-up layer (113).

[0431] Furthermore, a second build-up layer (113) may be positioned in a groove located on the upper surface of the first build-up layer (112). Accordingly, as described above, the bonding area between the first build-up layer (112) and the second build-up layer (113) increases, and the bonding strength therebetween may be improved.

[0432] The third build-up layer (114) may be located below the core layer (111). And the fourth build-up layer (115) may be located below the third build-up layer (114).

[0433] Here, the third build-up layer (114) may correspond to the second build-up layer in a circuit board other than the seventh embodiment.

[0434] Additionally, the fourth build-up layer (115), the third build-up layer (114), the core layer (111), the first build-up layer (112), and the second build-up layer (113) can be sequentially stacked in the vertical direction.

[0435] In addition, the electrode portion (120) may include a fourth electrode portion (124) and a fifth electrode portion (125). The fourth electrode portion (124) may include a fourth wiring portion (124a) and a third via electrode (124b). The fifth wiring portion (125a) may include a fifth wiring portion (125a) and a fourth via electrode (125b). The third via electrode (124b) may overlap with the first via electrode in a vertical direction. The third via electrode (124b) may be in contact with the first via electrode and may be electrically connected. The fourth via electrode (125b) may overlap with the second via electrode in a vertical direction. The fourth via electrode (125b) may be in contact with the second via electrode and may be electrically connected. Furthermore, the third via electrode (124b) and the fifth via electrode (125b) can be spaced apart from each other in the horizontal direction.

[0436] The third via electrode (124b) and the fourth via electrode (125b) can penetrate the second build-up layer (113). In addition, at least one of the third via electrode (124b) and the fourth via electrode (125b) can penetrate the first build-up layer (112) and the second build-up layer (113).

[0437] For example, the third via electrode (124b) and the fourth via electrode (125b) can penetrate the first build-up layer (112) and the second build-up layer (113). At this time, the third via electrode (124b) and the fourth via electrode (125b) can have an extension portion that extends in the horizontal direction (Y-axis direction) from the interface between the first build-up layer (112) and the second build-up layer (113). The third via electrode (124b) can have a first extension portion (EP1) that extends in the horizontal direction (Y-axis direction) from the interface between the first build-up layer (112) and the second build-up layer (113). The fourth via electrode (125b) may have a second extension portion (EP2) extending in a horizontal direction (Y-axis direction) at the interface between the first build-up layer (112) and the second build-up layer (113). This may improve the bonding strength between the via electrode and the build-up layer. The groove (G) may be positioned between the first extension portion (EP1) and the second extension portion (EP2). Furthermore, at least a portion of the groove (G) may overlap the first extension portion (EP1) and / or the second extension portion (EP2) in the horizontal direction.

[0438] However, it should be understood that the third via electrode (124b) and the fourth via electrode (125b) may penetrate only the second build-up layer (113), or may penetrate the first build-up layer (112) and the second build-up layer (113) as described above.

[0439] Referring to FIG. 49, in a modified example, the first build-up layer (112) may further include recesses corresponding to the third via electrode (124b) and the fourth via electrode (125b). For example, the first build-up layer (112) may include a first recess (GR1) corresponding to the third via electrode (124b) on the upper surface. The first build-up layer (112) may include a second recess (GR2) corresponding to the fourth via electrode (125b) on the upper surface.

[0440] A second build-up layer (113) may be positioned in the first recess (GR1). And, a third via electrode (124b) may penetrate the first recess (GR1) and the second build-up layer (113) within the first recess (GR1). Accordingly, an inner surface (IS1) of the first recess (GR1) and a side surface (S1) of the third via electrode (124b) may be spaced apart from each other by a predetermined distance (gap5) in the horizontal direction. Accordingly, issues of peeling or overhang occurring at the interface between the first build-up layer (112) and the second build-up layer (113) may be resolved.

[0441] In addition, the inner surface (IS1) of the first recess (GR1) and the side surface (S1) of the third via electrode (124b) may overlap in the horizontal direction. In addition, the inner surface (IS1) of the first recess (GR1) and the side surface (S1) of the third via electrode (124b) may overlap in the horizontal direction with the groove (G).

[0442] In addition, a second build-up layer (113) may be positioned in the second recess (GR2). And, the fourth via electrode (125b) may penetrate the second recess (GR2) and the second build-up layer (113) within the second recess (GR2). Accordingly, the inner surface (IS2) of the second recess (GR2) and the side surface (S2) of the fourth via electrode (125b) may be spaced apart from each other by a predetermined distance (gap6) in the horizontal direction. Accordingly, issues of peeling or overhang occurring at the interface between the first build-up layer (112) and the second build-up layer (113) may be resolved.

[0443] In addition, the inner side surface (IS2) of the second recess (GR2) and the side surface (S2) of the fourth via electrode (125b) may overlap in the horizontal direction. In addition, the inner side surface (IS1) of the second recess (GR2) and the side surface (S1) of the fourth via electrode (125b) may overlap with the groove (G) in the horizontal direction. In addition, the inner side surface (IS1) of the second recess (GR2) and the side surface (S1) of the fourth via electrode (125b) may overlap with the inner side surface (IS1) of the first recess (GR1) and the third via electrode (124b) in the horizontal direction.

[0444] FIG. 50 is a cross-sectional view showing a semiconductor package according to the first embodiment, FIG. 51 is a cross-sectional view showing a semiconductor package according to the second embodiment, and FIG. 52 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0445] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0446] Referring to FIG. 50, the semiconductor package of the first embodiment may include a second substrate (1200) and a semiconductor element (1300).

[0447] Furthermore, the semiconductor package may further include a first substrate and a connecting member (1210) described below.

[0448] The first substrate may mean or include a 'package substrate' or a 'circuit substrate'. The first substrate may be omitted. For example, the first substrate may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate. In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate.

[0449] Additionally, although not shown in the drawing, the first substrate may provide a space in which at least one semiconductor element is mounted.

[0450] The first substrate may include at least one build-up insulating portion and an electrode portion disposed on the at least one build-up insulating portion.

[0451] A second substrate (1200) can be placed on the first substrate.

[0452] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate. That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0453] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0454] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate.

[0455] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate.

[0456] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor element (1300) and the first substrate, and may have passive element functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor element (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor element (1300) is increasing, and accordingly, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided in the first substrate to have a width and spacing for being connected to the semiconductor element (1300) and the main board, there is a problem that the thickness of the first substrate increases or the layer structure of the first substrate becomes complicated. Accordingly, the first embodiment can place a second substrate (1200) on the first substrate and the semiconductor element (1300). And the second substrate (1200) can include an electrode having a microscopic width and spacing corresponding to the terminal of the semiconductor element (1300).

[0457] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0458] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0459] For example, a semiconductor package may include a first connector (1410) positioned between a first substrate and a second substrate (1200). The first connector (1410) may electrically connect the second substrate (1200) to the first substrate while bonding them therebetween.

[0460] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0461] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate. The third connector (1430) may electrically connect the first substrate to the main board while connecting them therebetween.

[0462] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0463] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a solder layer formed between the plurality of components by recrystallization.

[0464] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0465] At this time, in at least one of the first substrate and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the build-up insulation portion of the corresponding substrate. The protrusion may protrude outward from the first substrate or the second substrate (1200).

[0466] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0467] Furthermore, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0468] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0469] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0470] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0471] The semiconductor package of the first embodiment may include a second substrate (1200) and a semiconductor element (1300). In this case, the semiconductor package of the first embodiment may have a structure in which the first substrate is omitted compared to the semiconductor package of the first embodiment.

[0472] That is, the second substrate (1200) of the first embodiment can function as a package substrate while also functioning as an interposer.

[0473] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0474] Referring to FIG. 51, the semiconductor package of the second embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0475] At this time, the semiconductor package of the second embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0476] That is, the first substrate (1100) of the second embodiment can function as a package substrate while also connecting the semiconductor elements (1300) and the main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting between a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting between a plurality of semiconductor elements.

[0477] Referring to FIG. 52, the semiconductor package of the third embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the third embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0478] In this way, the semiconductor package of the third embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0479] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0480] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0481] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0482] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0483] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0484] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0485] The semiconductor package of the third embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive joint (1450).

[0486] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0487] Meanwhile, the third semiconductor element (1330) in the third embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0488] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0489] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0490] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0491] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0492] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Core layer containing a cavity; a connecting member disposed in the cavity; and A dummy electrode disposed on the lower surface of the core layer and vertically overlapping the cavity; A circuit board in which the thickness of the above dummy electrode is different from the thickness of the core wiring portion under the core layer.

2. In paragraph 1, A circuit board in which the thickness of the above dummy electrode is greater than the thickness of the core wiring portion under the above core layer.

3. In paragraph 1, A circuit board in which the horizontal length of the dummy electrode is greater than the horizontal length of the cavity.

4. In paragraph 1, A circuit board comprising a bonding member disposed between the dummy electrode and the connecting member.

5. In paragraph 4, A circuit board in which the above bonding member is placed within the cavity and overlaps the core layer in a horizontal direction.

6. In paragraph 1, A circuit board in which the above dummy electrode does not overlap horizontally with the above core layer.

7. In paragraph 1, A circuit board in which the upper surface of the above dummy electrode is in contact with the lower surface of the above core layer.

8. In paragraph 1, A circuit board in which the lower surface of the above connecting member is horizontally misaligned with the lower surface of the above core layer.

9. In paragraph 1, A circuit board in which the lower surface of the above connecting member is vertically spaced from the lower surface of the above core layer.

10. In paragraph 1, A circuit board comprising an upper build-up layer disposed on top of the core layer and within the cavity.

11. In paragraph 10, The cavity includes a first region that is misaligned in the vertical direction with the connecting member and a second region that overlaps the connecting member in the vertical direction, A circuit board in which the upper surface of the upper build-up layer includes a groove protruding downward on the first region.

12. In paragraph 4, A circuit board in which the dummy electrode vertically overlaps the connecting member, the bonding member, the cavity, and a portion of the core layer.

13. In paragraph 1, The above dummy electrode is a circuit board electrically separated from the via electrode of the core layer.

14. In paragraph 1, The circuit board wherein the dummy electrode has a length in the first horizontal direction greater than the length of the cavity in the first horizontal direction or the length of the connecting member in the first horizontal direction.

15. In paragraph 14, A circuit board having a length in a second horizontal direction perpendicular to the first horizontal direction of the dummy electrode, the length of which is less than the length in the second horizontal direction of the cavity.

16. In paragraph 4, A circuit board in which the above bonding member is placed on the upper surface of the lower surface of the core layer.

17. In paragraph 4, A circuit board wherein the above bonding member includes an upper region in contact with the connecting member and a lower region in contact with the dummy electrode.

18. In paragraph 17, A circuit board in which a portion of the upper region extends to the outer surface of the profit connecting member.

19. In paragraph 17, A circuit board in which a portion of the lower region extends from the upper surface of the dummy electrode to the outside of the connecting member.

20. In paragraph 17, A circuit board in which the lower surface of the above bonding member extends from the dummy electrode toward the inner wall of the cavity.

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