Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment includes: a build-up structure including a build-up insulating part and a build-up wiring part; and a protective layer arranged on the build-up structure and having a plurality of through-holes. The build-up wiring part includes a plurality of pad parts exposed to the plurality of through-holes and a connection wire selectively connecting the plurality of pad parts. The connection wire includes a first connection part which is arranged to overlap the protective layer in the vertical direction and a second connection part is connected to the pad parts. The second connection part includes a stepped part connected to the first connection part and formed to be stepped, and a wire width of the stepped part may be 30 % to 85 % of the width of the first connection part.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of electronic components on a limited-size circuit board. However, conventional semiconductor packages typically accommodate a single electronic component, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple electronic components across multiple substrates have recently been developed. These semiconductor packages feature a structure in which multiple electronic components are interconnected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​the electronic components and enabling high-speed signal transmission through short signal transmission paths between the components.

[0004] Meanwhile, a circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, a circuit board may mean that a mounting position of each electronic component is predetermined for mounting at least one electronic component, and a build-up wiring body connected to the electronic component is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The electronic component is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005] Traditionally, efforts have been made to design certain areas of wiring wider to reduce stress due to increased wiring density and integration. However, this increased width can lead to increased parasitic capacitance and inductance, degrading the quality of high-frequency signals.

[0006] One of the technical challenges of the present invention is to provide a circuit board with easy inductance control and improved electrical / mechanical reliability.

[0007] A circuit board according to an embodiment comprises a build-up structure including a build-up insulator and a build-up wiring body, and a protective layer disposed on the build-up structure and having a plurality of through holes; wherein the build-up wiring body includes a plurality of pad portions exposed to the plurality of through holes and a connecting wire selectively connecting the plurality of pad portions, wherein the connecting wire includes a first connecting portion disposed to vertically overlap the protective layer and a second connecting portion connected to the pad portion, wherein the second connecting portion is connected to the first connecting portion and includes a step portion formed in a stepwise manner, and a wiring width of the step portion may be 30% to 85% of a width of the first connecting portion.

[0008] According to an embodiment of the invention, the size of the through hole is formed larger than the size of the pad portion, and the upper surface and the side surface of the pad portion can be exposed by the through hole. The second connecting portion can be exposed by the through hole. The thickness of the step portion can be 30% to 85% of the thickness of the first connecting portion. The length of the step portion can be 60% to 135% of the wiring width of the step portion. The thickness of the first connecting portion and the thickness of the second connecting portion can be the same. The wiring width of the first connecting portion and the wiring width of the second connecting portion can be the same. The wiring width of the second connecting portion can be smaller than the wiring width of the first connecting portion. The thickness of the second connecting portion can be smaller than the thickness of the first connecting portion.

[0009] A semiconductor package according to an embodiment may include any one of the circuit boards disclosed above and include a semiconductor element disposed on the pad portion.

[0010] According to the circuit board of the present invention, since the connecting wires have stepped portions, inductance control can be facilitated. Furthermore, since the width of the stepped portions is 30% to 85% of the width of the connecting wires, signal control can be facilitated. Furthermore, the contact area is increased by the stepped portions, thereby improving mechanical / electrical reliability.

[0011] Figure 1 is a cross-sectional view showing a circuit board according to the first embodiment.

[0012] Figure 2 is a plan view showing a state in which a second protective member is placed within a through hole of a first protective member.

[0013] Figure 3 is an enlarged view of area A of Figure 2.

[0014] Figure 4 is an enlarged plan view of area B of Figure 3.

[0015] Figure 5 is an enlarged cross-sectional view of area B of Figure 3.

[0016] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0017] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0018] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0019] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0020] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0021] These terms are only intended to distinguish the component from other components and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0022] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0023] Additionally, when it is described that a component A is in 'contact' with a component B, it may include not only cases where that component is in 'contact' with the other component directly, but also cases where that component is 'in contact' with another component between that component and the other component. Thus, if a component A is to be understood to be in 'direct contact' with a component B, it is described as being in 'direct contact'.

[0024] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0025] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0026] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0027]

[0028] -Electronic devices-

[0029] Before describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various chips may be mounted on the semiconductor package. Broadly speaking, the semiconductor package may include various components or chips. The components or chips may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc.; logic chips such as an analog-to-digital converter, an ASIC (application-specific IC), etc.

[0030] Additionally, the device or chip may include active devices and passive devices.

[0031] The above active element refers to an element that actively utilizes the nonlinear portion of the signal characteristics. In addition, a passive element refers to an element that does not utilize the nonlinear signal characteristics even though both linear and nonlinear signal characteristics exist. For example, the active element may include a transistor, an IC semiconductor element, etc., and the passive element may include a capacitor, a resistor, an inductor, etc. The passive element may increase the signal processing speed of the semiconductor chip, which is the active element, or perform a filtering function, etc. In addition, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communication, etc.

[0032] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0033] At this time, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the present invention is not limited thereto, and it is obvious that the electronic device may be any other electronic device that processes data.

[0034]

[0035] Figure 1 is a cross-sectional view showing a circuit board according to the first embodiment.

[0036] Referring to FIG. 1, a circuit board (10) according to the first embodiment may include a build-up structure (100), a protective layer (140, 150) disposed on the upper surface and / or lower surface of the build-up structure (100), and a bonding portion (160) penetrating at least a portion of the protective layer (140).

[0037] Here, the meaning of being arranged on one side and the other side should not be understood only as a configuration that is in direct contact with the one side and the other side, but should also be understood as having another configuration between one side of the build-up structure (100) and the first protective layer (140), and between the other side of the build-up structure (100) and the second protective layer (150).

[0038] The build-up structure (100) includes a build-up wiring body including a build-up insulator (110) and a wiring layer (120) and a through electrode (130).

[0039] The build-up insulator (110) may have a structure in which a plurality of insulating layers are laminated along a vertical direction. The build-up insulator (110) may include a core insulating layer (110a), an upper insulating layer (110f), and a lower insulating layer (110g). The upper insulating layer (110f) and the lower insulating layer (110g) may be formed of a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Image-able Dielectric, PID) for forming a fine pattern may be used.

[0040]

[0041] A build-up structure (100) may include a core layer (CS) including a core insulating layer (110a), a first build-up layer (UB) disposed on the upper surface of the core layer (CS), and a second build-up layer (LB) disposed on the lower surface of the core layer (CS).

[0042] The core layer (CS) may include a core insulating layer (110a), an upper core wiring layer (110b), a lower core wiring layer (110c), a core through-electrode (110d), and an insulating member (110e).

[0043] The core insulating layer (110a) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing member (110aR) such as glass fiber, and has the function of improving the rigidity of the circuit board. That is, as the number of terminals of semiconductor devices arranged on the circuit board increases, the wiring becomes more complex, and accordingly, the thickness of the first and second build-up insulating layers (110b, 110c) tends to increase. Accordingly, the core insulating layer (110a) of the present embodiment may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board and prevent excessive signal loss. A via hole penetrating one surface and the other surface may be formed in the core insulating layer (110a). The via hole of the core insulating layer (110a) may be formed using a mechanical drilling process or a CO2 laser, etc. When a via hole of the core insulating layer (110a) is formed using a mechanical drill, the inclination of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core insulating layer (110a), and when a via hole of the core insulating layer (110a) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the core insulating layer (110a), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the core insulating layer (110a). In addition, the concave portions and the convex portions may be alternately provided on the inner wall forming the via hole of the core insulating layer (110a) along the vertical direction. Here, "alternately provided" may mean that a convex portion is provided between multiple concave portions, or that a concave portion is provided between multiple convex portions. In the case of via holes formed using a mechanical drilling process, the path for transmitting electrical signals may be shortened, which may be advantageous for electrical properties, but may also increase the process cost.In addition, when forming concave and convex portions on the inner wall of a via hole using a CO2 laser, the thickness of the core penetration electrode (110d) provided on the inner wall of the via hole can be increased in a subsequent process, which has the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the core insulating layer (110a) can be freely and selectively used depending on the application field of the semiconductor package.

[0044] A core through electrode (110d) may be placed within the through hole of the core insulating layer (110a). The core through electrode (110d) functions to electrically connect the first build-up layer (UB) and the second build-up layer (LB). Therefore, it is desirable for the core through electrode (110d) to densely fill the via hole for resistance or heat dissipation. However, when the thickness of the core insulating layer (110a) becomes thick as described above, it may become difficult for the core through electrode (110d) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core insulating layer (110a) as described above according to the plating process, a void may occur within the core through electrode (110d). The void expands due to heat generated during the operation of the semiconductor package, which may deteriorate the mechanical reliability of the circuit board. Accordingly, a core through-electrode (110d) having a predetermined thickness is arranged on the inner wall of the via hole of the core insulating layer (110a). The thickness of the core through-electrode (110d) refers to the thickness in the horizontal direction perpendicular thereto, not the thickness in the vertical direction in which the first build-up layer (UB), the core insulating layer (110a), and the second build-up layer (LB) are laminated. The thickness of the core through-electrode (110d) may be arranged to have a thickness of 5 μm to 20 μm in order to prevent a voltage drop that occurs as the thickness of the core insulating layer (110a) increases and to prevent the occurrence of voids. It is difficult to densely fill the inner side of the core through-electrode (110d) with metal through a process such as plating, resulting in the creation of empty spaces. The empty spaces may cause problems in that it is difficult to evenly arrange the upper core wiring layer (110b) and the lower core wiring layer (110c).

[0045] Accordingly, the insulating member (110e) can be placed on the inner side of the core through-hole electrode (110d), thereby ensuring the flatness of the core layer (CS). For example, the insulating member (110e) can be placed in the via hole of the core insulating layer (110a), and the core through-hole electrode (110d) can surround the side of the insulating member (110e) and be placed between the inner wall of the via hole and the outer surface of the insulating member (110e).

[0046] The upper surface of the insulating member (110e) may be on the same plane as the upper surface of the core insulating layer (110a), or may be disposed closer to the first build-up layer (UB) in the vertical direction than the upper surface of the core insulating layer (110a). The lower surface of the insulating member (110e) may be on the same plane as the lower surface of the core insulating layer (110a), or may be disposed closer to the second build-up layer (LB) in the vertical direction than the lower surface of the core insulating layer (110a). This can be freely designed to address flatness during lamination of the first build-up layer (UB) and the second build-up layer (LB).

[0047] An upper core wiring layer (110b) is arranged on the upper surface of the core insulation layer (110a), and a lower core wiring layer (110c) is arranged on the lower surface of the core insulation layer (110a). In addition, the upper core wiring layer (110b) and the lower core wiring layer (110c) are electrically connected to each other through a core penetration electrode (100d).

[0048] A first build-up layer (UB) is disposed on one surface of the core layer (CS). The first build-up layer (UB) includes a plurality of upper insulating layers (110f), a plurality of upper wiring layers (121), a plurality of upper through-hole electrodes (130-2), a first protective layer (140), and a bonding portion (160). A second build-up layer (LB) is disposed on the other surface of the core layer (CS). The second build-up layer (LB) includes a plurality of lower insulating layers (110g), a plurality of lower wiring layers (122), a plurality of lower through-hole electrodes (130-3), and a second protective layer (150).

[0049] The wiring layer (120) includes an upper wiring layer (121) and a lower wiring layer (122). The upper wiring layer (121) includes a first upper wiring layer (121a), a second upper wiring layer (121b), and a third upper wiring layer (121c) arranged on the uppermost side of the upper insulating layer (110f), and includes a fourth upper wiring layer (121d) integrated between the upper insulating layers (110f). The first upper wiring layer (121a), the second upper wiring layer (121b), and the third upper wiring layer (121c) may be referred to as a first pad portion (121a), a second pad portion (121b), and a third pad portion (121c). The first upper wiring layer (121a), the second upper wiring layer (121b), and the third upper wiring layer (121c) may refer to electrodes connected to semiconductor elements mounted on the circuit board (10) and / or terminals of an external substrate. The first upper wiring layer (121a), the second upper wiring layer (121b), and the third upper wiring layer (121c) may refer to portions that overlap vertically with a plurality of through holes of the first protective layer (140). The upper wiring layer (121) may further include a connection wiring (121T) that selectively connects the first upper wiring layer (121a), the second upper wiring layer (121b), and the third upper wiring layer (121c).

[0050] The lower wiring layer (122) includes a first lower wiring layer (122a) positioned at the lowermost side of the lower insulating layer (110g) and a second lower wiring layer (122b) directly between the lower insulating layer (110g). The first lower wiring layer (122a) may overlap with a plurality of through holes of the second protective layer (150) in a vertical direction.

[0051] The through-electrode (130) includes a core through-electrode (110d) penetrating the core layer (CS), an upper through-electrode (130-2) penetrating the upper insulating layer (100f), and a lower through-electrode (130-3) penetrating the lower insulating layer (110g). The upper through-electrode (130-2) can connect at least one of the first to third upper wiring layers (121a, 121b, 121c) arranged on the upper insulating layer (100f) and the fourth upper wiring layer (121d). The lower through-electrode (130-3) can electrically connect the first lower wiring layer (122a) and the second lower wiring layer (122b).

[0052]

[0053] The protective layer (140, 150) may include a first protective layer (140) disposed on the upper surface of the build-up structure (100) and / or a second protective layer (150) disposed on the lower surface of the build-up structure (100). The first protective layer (140) may protect the upper surface of the upper wiring layer (121) and / or the upper insulating layer (110f) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (10) using a material such as solder, the first protective layer (140) functions to prevent short circuits between solders due to low wettability with the solder. The first protective layer (140) may use a photocurable insulating material, and for example, a solder resist may be used. However, the embodiment is not limited thereto, and the first protective layer (140) may include a thermocurable insulating material that is the same insulating material as the build-up insulating layer (110). The first protective layer (140) may have the same insulating material as the first insulating layer (111), and may be provided as, for example, ABF (Ajinomoto Build-up Film) from Ajinomoto Corporation.

[0054] A bonding portion (160) may be arranged on the build-up structure (100). The bonding portion (160) may penetrate at least a portion of the first protective layer (140) along the vertical direction on the build-up structure (100).

[0055] The bonding portion (160) may penetrate at least a portion of the first protective layer (140). The bonding portion (160) may overlap the first protective layer (140) in a vertical direction. The embodiment may enable the bonding portion (160) to be stably positioned on the build-up structure (100), thereby improving the mechanical reliability and / or electrical reliability of the circuit board.

[0056]

[0057] Fig. 2 is an enlarged view of area A of Fig. 1, Fig. 3 is a plan view of a circuit board according to an embodiment, and Fig. 4 is an enlarged view of area B of Fig. 3.

[0058] Referring to FIGS. 1 and 2, the first protective layer (140) may have a plurality of through holes (141, 142). The provision of a plurality of through holes (141, 142) may mean that a plurality of through holes that are not connected to each other are provided horizontally and spaced apart from each other. The through holes (141, 142) of the first protective layer (140) may penetrate the upper and lower surfaces of the first protective layer (140). The through holes (141, 142) of the first protective layer (140) may be provided to vertically overlap with an electrode portion provided in a circuit board.

[0059] The first through hole (141) is formed so that the first protective layer (140) is spaced apart from the first upper wiring layer (121a), and may expose a portion of the upper surface and side surface of the first upper wiring layer (121a). For example, the first through hole (141) may have an SRO (Solder resist opening) region. That is, the first upper wiring layer (121a) exposed by the first through hole (141) may be a NSMD (Non-Solder Mask Defined) pad.

[0060] The second through hole (142) may be formed so that the first protective layer (140) covers a portion of the upper surface of the second upper wiring layer (121b), and may expose a portion of the upper surface of the second upper wiring layer (121b). For example, the second upper wiring layer (121b) may be a SMD (Solder Mask Defined) pad.

[0061] The circuit board may further include a first surface layer (171) disposed on the first upper wiring layer (121a) and a second surface layer (172) disposed on the second upper wiring layer (121b). The first surface layer (171) and the second surface layer (172) may include a metal material. The first surface layer (171) and the second surface layer (172) may be an Electroless Nickel Immersion Gold (ENIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer.

[0062] The first surface layer (171) and the second surface layer (172) may have different shapes. The first surface layer (171) may be positioned within the first through hole (141) of the first protective layer (140). At this time, the first through hole (141) does not contact the upper and lower surfaces of the first upper wiring layer (121a). Therefore, the first surface layer (171) may be provided to entirely cover the upper and side surfaces of the first upper wiring layer (141a).

[0063] In contrast, the second surface layer (172) is disposed within the second through hole (142) provided in the first protective layer (140). The upper surface of the second upper wiring layer (121b) partially overlaps with the second through hole (142) in the vertical direction. Therefore, the second surface layer (172) may be provided to cover a portion of the upper surface of the second upper wiring layer (121b) that overlaps with the second through hole (142) in the vertical direction.

[0064]

[0065] Referring back to FIG. 1, the semiconductor package of the embodiment includes a connection portion (210). For example, the connection portion (210) may be disposed on the first upper wiring layer (121a) and the second upper wiring layer (121b). The connection portion (210) may be formed using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. The wire bonding method refers to electrically connecting an electrode portion of a circuit board to a terminal of a semiconductor element using a conductive wire such as gold (Au). The solder bonding method electrically connects an electrode portion of a circuit board to a terminal of a semiconductor element using a material including at least one of Sn, Ag, and Cu. The direct metal-to-metal bonding method refers to directly bonding the electrode portion to the terminal of a semiconductor element by applying heat and pressure between the electrode portion and the terminal of the semiconductor element to recrystallize the electrode portion and the terminal of the semiconductor element without using a solder, wire, conductive adhesive, or the like. At this time, the connection portion (210) may mean a metal layer between the electrode portion and the terminal of the semiconductor element provided by recrystallization.

[0066] For example, the connection portion (210) can electrically connect the electrode portion and the terminal of the semiconductor element by a thermal compression bonding method. The thermal compression bonding method can reduce the volume of the connection portion (210) and prevent short circuits between multiple adjacent connection portions. Therefore, when the terminal and / or electrode portion of the semiconductor element has a fine pitch, the thermal compression bonding method may be advantageous.

[0067] Additionally, the semiconductor package may include a semiconductor element disposed on the connection portion (210).

[0068] By way of example, the semiconductor package includes a first semiconductor element (220) coupled to a connection portion (210). The first semiconductor element (220) may include a terminal (221). The terminal (221) of the first semiconductor element (220) may be electrically connected to a first upper wiring layer (121a) and a second upper wiring layer (121b) of a circuit board through the connection portion (210). According to an embodiment, the first semiconductor element (220) may include a conductive pillar (222) disposed on the terminal (221), but is not limited thereto. The conductive pillar (222) may be provided to space the terminal (221) of the first semiconductor element (220) and the first upper wiring layer (121a) and the second upper wiring layer (121b) apart from each other by a predetermined distance in the vertical direction, thereby improving the alignment between the terminal (221) of the first semiconductor element (220) and the first upper wiring layer (121a) and the second upper wiring layer (121b).

[0069]

[0070] Referring to FIGS. 3 and 4, any one of the first upper wiring layers (121a) can be electrically connected to the first upper wiring layer (121a) and / or the second upper wiring layer (121b) by a connection wiring (121T).

[0071] The first upper wiring layer (121a) is exposed by the first through hole (141), and the first upper wiring layer (121a) may have a horizontal separation space (SA) with the first protective layer (141). A portion of the connection wiring (121T) connected to the first upper wiring layer (121a) may be exposed by the separation space (SA). The connection wiring (121T) may include a first connection portion (121T1) sealed by the first protective layer (140) and a second connection portion (121T2) exposed by the separation space (SA).

[0072] The connecting wire (121T) may further include a step portion (121T-1) formed at a portion where the first connecting portion (121T1) and the second connecting portion (121T2) are connected. The step portion (121T-1) may be a configuration included in the second connecting portion (121T2). That is, the step portion (121T-1) may be exposed by the separation space (SA). The step portion (121T-1) may have a width / thickness smaller than the first connecting portion (121T1) and the second connecting portion (121T2).

[0073]

[0074] The wiring width (W1) of the first connecting portion (121T1) may be the same as the wiring width (W2) of the second connecting portion (121T2). However, the present invention is not limited thereto, and the wiring width (W1) of the first connecting portion (121T1) may be larger than the wiring width (W2) of the second connecting portion (121T2). In addition, the wiring width (W1) of the first connecting portion (121T1) may be smaller than the wiring width (W2) of the second connecting portion (121T2). The wiring width (W3) of the step portion (121T-1) may be the same as or smaller than the wiring width (W1) of the first connecting portion (121T1). The wiring width (W3) of the step portion (121T-1) may be the same as or smaller than the wiring width (W2) of the second connecting portion (121T2). Preferably, the wiring width (W1) of the first connection portion (121T1) is equal to the wiring width (W2) of the second connection portion (121T2), and the wiring width (W3) of the step portion (121T-1) is smaller than the wiring widths (W1, W2) of the first and second connection wires (121T1, 121T2). For example, the wiring width (W3) of the step portion (121T-1) may have a range of 30% to 85% of the wiring widths (W1, W2) of the first and second connection wires (121T1, 121T2). As a result, parasitic capacitance and inductance may be reduced, thereby improving signal quality. If the wiring width (W3) of the step portion (121T-1) is less than 30% of the wiring widths (W1, W2) of the first and second connecting wires (121T1, 121T2), problems such as circuit opening may occur due to process errors, and signal transmission characteristics may be degraded due to the width (W3) of the step portion (121T-1) being too thin or having an excessive difference from the wiring widths (W1, W2) of the first and second connecting wires (121T1, 121T2). On the other hand, if the wiring width (W3) of the step portion (121T-1) exceeds 85% of the wiring widths (W1, W2) of the first and second connecting wires (121T1, 121T2), the effect of the change in width may be minimal.

[0075]

[0076] Referring to FIGS. 4 and 5, the length (L1) of the step portion (121T-1) may be smaller than the wiring widths (W1, W2) of the first and second connecting wires (121T1, 121T2). In addition, the length (L1) of the step portion (121T-1) may have a range of 60% to 135% of the width (W3) of the step portion (121T-1). If the length (L1) of the step portion (121T-1) is less than 60% of the width (W3) of the step portion (121T-1), the effect due to the change in width may be minimal. Conversely, if the length (L1) of the step portion (121T-1) exceeds 135% of the width (W3) of the step portion (121T-1), the resistance in the connecting wire (121T) increases, and power loss and signal loss may occur.

[0077] The side of the first connecting portion (121T1) overlapping the first protective layer (140) may be arranged on the same plane as the side of the first protective layer (140). However, this is not limited thereto.

[0078] The thickness (T3) of the step portion (121T-1) may be smaller than the thickness (T1) of the first connecting portion (121T1) and the thickness (T2) of the second connecting portion (121T2). The thickness (T1) of the first connecting portion (121T1) and the thickness (T2) of the second connecting portion (121T2) may be the same. However, the present invention is not limited thereto, and the thickness (T1) of the first connecting portion (121T1) may be larger than the thickness (T2) of the second connecting portion (121T2). The thickness (T2) of the second connecting portion (121T2) may be equal to or smaller than the thickness (D) of the first upper wiring layer (121a).

[0079] The thickness (T3) of the step portion (121T-1) may range from 30% to 85% of the thickness (T1) of the first connecting portion (121T1) or / and the thickness (T2) of the second connecting portion (121T2). If the thickness (T3) of the step portion (121T-1) is less than 30% of the thickness (T1) of the first connecting portion (121T1) or / and the thickness (T2) of the second connecting portion (121T2), a problem of the circuit being opened due to a slight process error may occur. On the other hand, if the thickness (T3) of the step portion (121T-1) exceeds 85% of the thickness (T1) of the first connecting portion (121T1) or / and the thickness (T2) of the second connecting portion (121T2), the effect of the change in width at the step portion (121T-1) may be small.

[0080] The step portion (121T-1) can increase the contact area with the molding layer during the assembly stage, thereby improving the mechanical reliability and / or electrical reliability of the semiconductor package.

[0081]

[0082] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up structure including a build-up insulator and a build-up wiring body; and A protective layer disposed on the above build-up structure and having a plurality of through holes; The above build-up wiring body includes a plurality of pad portions exposed to the plurality of through holes and a connecting wiring that selectively connects the plurality of pad portions, The above connecting wire includes a first connecting portion arranged to overlap vertically with the protective layer and a second connecting portion connected to the pad portion, The second connecting portion is connected to the first connecting portion and includes a step portion formed in a stepwise manner, A circuit board in which the wiring width of the above-mentioned step portion is 30% to 85% of the width of the above-mentioned first connecting portion.

2. In paragraph 1, The size of the above through hole is formed to be larger than the size of the above pad portion, The above pad portion is a circuit board whose upper surface and side surfaces are exposed by the above through hole.

3. In paragraph 2, The second connecting portion is a circuit board exposed by the through hole.

4. In paragraph 3, A circuit board wherein the thickness of the step portion is 30% to 85% of the thickness of the first connecting portion.

5. In paragraph 4, A circuit board in which the length of the step portion is 60% to 135% of the wiring width of the step portion.

6. In paragraph 5, A circuit board in which the thickness of the first connecting portion and the thickness of the second connecting portion are the same.

7. In paragraph 5, A circuit board in which the wiring width of the first connecting portion and the wiring width of the second connecting portion are the same.

8. In paragraph 5, A circuit board in which the wiring width of the second connecting portion is smaller than the wiring width of the first connecting portion.

9. In paragraph 5, A circuit board wherein the thickness of the second connecting portion is smaller than the thickness of the first connecting portion.

10. In a circuit board according to any one of clauses 1 to 9, A semiconductor package comprising a semiconductor element arranged on a pad portion of the circuit board.

Images