Circuit board and semiconductor package comprising same

Abstract

A circuit board according to the present invention is disclosed, the circuit board comprising: a build-up insulating part including a plurality of build-up layers which are stacked in a vertical direction; and an electrode part including a wiring part arranged on the build-up insulating part and a via electrode penetrating the plurality of build-up layers, wherein the via electrode includes a first sub-via electrode and a second sub-via electrode spaced apart from each other in a horizontal direction, and the wiring part being in contact with the first sub-via electrode and the second sub-via electrode includes an extension part which protrudes upwards.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to mount more semiconductor chips on a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package containing a processor chip and a memory package containing memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing chip mounting area and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices such as mobile devices, servers, and PCs, along with the adoption of High Bandwidth Memory (HBM), have led to larger semiconductor chip areas and the attachment of multiple semiconductor chips to a single package substrate to shorten the electrical connection distance between them, thereby increasing the size of the package. Furthermore, as the functions required for application processors increase, there is a growing need for separate processor chips for each function, and circuit boards capable of mounting these processor chips are required.

[0005] At this time, for the above application processor, even when it is separated into two processor chips by function, the number of terminals (Input / Output) provided in each processor chip is increasing.

[0006] Furthermore, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and faster communication speeds, the number of terminals on processor chips is steadily increasing due to the increase in power and signal capacity. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. Furthermore, increased circuit board area and thickness can make product miniaturization difficult, leading to reliability issues such as board warping and increased product price.

[0007] Furthermore, recent circuit boards are stacking multiple build-up layers for complex connections. At this time, stress between electrodes within multiple build-up layers can be concentrated in a single area, leading to problems such as cracks.

[0008] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, which have sub-via electrodes spaced apart from each other in a horizontal direction between via electrodes spaced apart from each other in a stacking direction and a wiring portion connected to the sub-via electrodes having an extension portion extending upward, thereby relieving stress applied to the via electrodes and suppressing cracks.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which improve signal integrity through the shape of the upper surface in the extension of the wiring portion and have improved mechanical stability through stress distribution.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention includes a build-up insulating portion including a plurality of build-up layers stacked in a vertical direction; and an electrode portion including a wiring portion disposed in the build-up insulating portion and a via electrode penetrating the plurality of build-up layers; wherein the via electrode includes a first sub-via electrode and a second sub-via electrode spaced apart in a horizontal direction, and the wiring portion in contact with the first sub-via electrode and the second sub-via electrode includes an extension portion protruding upward.

[0012] The plurality of build-up layers may include a first build-up layer, a second build-up layer, and a third build-up layer that are sequentially arranged in a vertical direction; the wiring portion may include a first wiring portion arranged in the first build-up layer, a second wiring portion arranged in the second build-up layer, and a third wiring portion arranged in the third build-up layer; and the via electrode may include a first via electrode penetrating the first build-up layer, a second via electrode penetrating the second build-up layer, and a third via electrode penetrating the third build-up layer.

[0013] The first via electrode and the third via electrode may be overlapped and connected to each other in the vertical direction.

[0014] The above second via electrode may include a second-first via electrode and a second-second via electrode that are electrically separated.

[0015] The second-first via electrode can be placed between the first via electrode and the third via electrode.

[0016] The above 2-1 via electrode may include the first sub-via electrode and the second sub-via electrode.

[0017] The thickness of the first sub-via electrode and the second sub-via electrode may be smaller than the thickness of the second build-up layer.

[0018] The thickness of the above-mentioned 2-1 via electrode may be smaller than the thickness of the above-mentioned 2-2 via electrode.

[0019] The second wiring section may include a second-1 wiring section and a second-2 wiring section that are electrically separated.

[0020] The above 2-1 wiring section can be in contact with the first sub-via electrode and the second sub-via electrode.

[0021] The thickness of the above-mentioned 2-1 wiring portion may be greater than the thickness of the above-mentioned 2-2 wiring portion.

[0022] The above extension portion may be located in the above 2-1 wiring portion.

[0023] The above extension portion may not overlap at least partially in the horizontal direction with the above 2-2 wiring portion.

[0024] The upper surface of the above extension can be in contact with the third via electrode.

[0025] The above 2-1 wiring section includes a support section arranged below the extension section, and the widths of the support section and the extension section in the horizontal direction may be different.

[0026] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which have sub-via electrodes spaced apart from each other in a horizontal direction between via electrodes spaced apart from each other in a stacking direction and a wiring portion connected to the sub-via electrodes having an extension portion extending upward, thereby relieving stress applied to the via electrodes and suppressing cracks.

[0027] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which improve signal integrity through the shape of the upper surface in the extension of the wiring portion and improve mechanical stability through stress distribution.

[0028] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0029] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0030] Figure 2 is an enlarged view of K1 in Figure 1,

[0031] Figure 3 is a plan view of a via electrode and a wiring portion in a circuit board according to the first embodiment of the present invention.

[0032] Figure 4 is an enlarged view of K2 in Figure 1,

[0033] Figure 5 is another example of Figure 2,

[0034] Figure 6 is another example of Figure 2,

[0035] Figures 7 to 11 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0036] Fig. 12 is a cross-sectional view of a circuit board according to the second embodiment;

[0037] Figure 13 is an enlarged view of K3 in Figure 12,

[0038] Fig. 14 is a modified example of Fig. 13,

[0039] Fig. 15 is a cross-sectional view of a circuit board according to the third embodiment;

[0040] Figure 16 is an enlarged view of K4 of Figure 15,

[0041] Fig. 17 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0042] Fig. 18 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0043] Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0044] Fig. 20 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0045] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0046] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0047] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0048] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0049] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0050] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0051] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0052] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0053] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0054] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0055] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0056] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0057] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0058] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0059] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0060] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0061] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0062] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0063] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0064] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0065] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0066] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of K1 in FIG. 1, FIG. 3 is a plan view of a via electrode and a wiring portion in a circuit board according to the first embodiment of the present invention, FIG. 4 is an enlarged view of K2 in FIG. 1, FIG. 5 is another example of FIG. 2, and FIG. 6 is another example of FIG. 2.

[0067] Referring to FIG. 1, a circuit board (100) according to the first embodiment may include an insulating layer (110) and an electrode portion (120).

[0068] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0069] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (111), build-up insulating portions (112, 113), a core electrode portion (121), and build-up electrode portions (122, 123). Furthermore, the circuit board (100) may further include a protective layer (SR) and a bump portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portions (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The build-up electrode portions (122, 123) may be disposed by being embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby performing a function of transmitting signals and / or power from a main board (not illustrated) to semiconductor devices.

[0070] And when the circuit board includes a core layer, it may include a core layer disposed within an insulating layer (110). Accordingly, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0071] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0072] As an example, the insulation layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion, etc. The following description will be made based on this.

[0073] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0074] And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In the present embodiment, the core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (113) may be located below the core layer (111).

[0075] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0076] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0077] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and may have a thickness in a vertical direction (Y-axis direction or lamination direction) of several tens of micrometers to several hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0078] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0079] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0080] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0081] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0082] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0083] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0084] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0085] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111). The core via electrode (121b) of the core layer may have an inner surface that is inclined, or its width (or diameter) may decrease and then increase. In addition, the core via electrode (121b) may have an inner surface that is perpendicular to the lower surface.

[0086] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0087] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0088] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion (first wiring portion) having a fine pitch and a wiring portion (second wiring portion) having a pitch larger than the first wiring portion.

[0089] The second wiring portion may refer to a wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first wiring portion may refer to a fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the first wiring portion may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the first wiring portion may be 30 ㎛ or less. For example, the pitch of the first wiring portion may be 55 ㎛ or less. A detailed description thereof will be provided later.

[0090] Additionally, the circuit board (100) according to the first embodiment may further include a protective layer (SR) and a bump portion (BP).

[0091] Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material that has insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0092] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0093] The bump portion (BP) may be disposed on the protective layer (SR). For example, the bump portion (BP) may be disposed on the upper surface of the protective layer (SR). The bump portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bump portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bump portion (BP) may include a protrusion portion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion portion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0094] Furthermore, a metal layer may be additionally disposed on the bump portion (BP) and electrically connected. Accordingly, the durability and reliability of the bump portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bump portion (BP) is improved, the corrosion resistance and durability of the bump portion (BP) are improved, and the loss of electrical signals may be minimized. The metal layer may be formed on the bump portion (BP) by deposition, electroplating, or the like of various metals.

[0095] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the first wiring portion, which is the aforementioned micro-pattern. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0096] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0097] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0098] And the following description is based on the upper build-up layer (112) and the upper electrode portion (122). Furthermore, the structure of the via electrode and the wiring portion can be equally applied to the lower build-up layer and the lower electrode portion in addition to the upper build-up layer and the upper electrode portion.

[0099] Referring further to FIG. 2, in the embodiment, the upper electrode portion (122) may be located in the upper build-up layer (112).

[0100] And the upper build-up layer (112) may include a plurality of build-up layers that are sequentially positioned in the vertical direction (Y-axis direction). For example, the upper build-up layer (112) may include a first build-up layer (112a), a second build-up layer (112b), and a third build-up layer (112c). The second build-up layer (112b) may be positioned between the first build-up layer (112a) and the third build-up layer (113c). In addition, the second build-up layer (112b) may be positioned on the first build-up layer (112a), and the third build-up layer (112c) may be positioned on the second build-up layer (112b).

[0101] Additionally, the upper electrode portion (122) may include an upper wiring portion (122a) and an upper via electrode (122b) arranged in multiple build-up layers of the upper build-up layer (112).

[0102] The upper wiring portion (122a) may include a first wiring portion (122a1), a second wiring portion (122a2), and a third wiring portion (112a3). The first wiring portion (122a1) may be located in the first build-up layer (112a). For example, the first wiring portion (122a1) may be located on the upper surface of the first build-up layer (112a). The second wiring portion (122a2) may be located in the second build-up layer (112b). For example, the second wiring portion (122a2) may be located on the upper surface of the second build-up layer (112b). The third wiring portion (112a3) may be located in the third build-up layer (112c). For example, the third wiring portion (112a3) may be located on the upper surface of the third build-up layer (112c).

[0103] The upper via electrode (122b) may include a first via electrode (122b1), a second via electrode (122b2), and a third via electrode (122b3). The first via electrode (122b1) may penetrate the first build-up layer (112a). The second via electrode (122b2) may penetrate the second build-up layer (112b). The third via electrode (122b3) may penetrate the third build-up layer (112c). In addition, the first via electrode (122b1) may be in contact with the first wiring portion (122a) at the upper portion. The second via electrode (122b2) may be in contact with the first wiring portion (122a) at the lower portion and may be in contact with the second wiring portion (122b) at the upper portion. The third via electrode (122b3) can be in contact with the second wiring portion (122b) at the bottom and the third wiring portion (122c) at the top.

[0104] And in the circuit board according to the embodiment, the thicknesses of the plurality of via electrodes (or wiring portions) penetrating each build-up layer may be different from each other or may not overlap at least partially in the horizontal direction.

[0105] Specifically, the first via electrode (122b1) and the third via electrode (122b3) may overlap in the vertical direction (Y-axis direction). However, as described above, a plurality of wiring portions and via electrodes may be arranged in each build-up layer and may or may not overlap each other in the vertical direction (Y-axis direction). In addition, a plurality of wiring portions and via electrodes located in each build-up layer may or may not overlap each other in the horizontal direction (X-axis direction). Hereinafter, the first via electrode (122b1) and the third via electrode (122b3) will be described based on the case where they overlap each other in the vertical direction (Y-axis direction) and are electrically connected.

[0106] A second via electrode (122b2) may be positioned between the first via electrode (122b1) and the third via electrode (122b3). The second via electrode (122b2) may be connected to the first via electrode (122b1) and the third via electrode (122b3). The first via electrode (122b1) and the third via electrode (122b3) may be connected to each other through the second via electrode (122b2).

[0107] However, in the second build-up layer (122b), the second via electrode (122b2) may include a second-first via electrode (122b2a) and a second-second via electrode (122b2b) that are electrically separated. The second-first via electrode (122b2a) is positioned between the first via electrode (122b1) and the third via electrode (122b3), and may be electrically connected to the first via electrode (122b1) and the third via electrode (122b3). In addition, the second-second via electrode (122b2b) may be electrically separated from the second-first via electrode (122b2a), and may also be electrically separated from the first via electrode (122b1) and the third via electrode (122b3). The 2-2 via electrode (122b2b) can be spaced apart from the 2-1 via electrode (122b2a) while overlapping in the horizontal direction (X-axis direction). That is, the 2-2 via electrode (122b2b) can be spaced apart from the 2-1 via electrode (122b2a) in the horizontal direction, thereby being physically separated.

[0108] In addition, the second wiring portion (122a2) may be positioned on the second build-up layer (112b) and may include a second-first wiring portion (122a2a) and a second-second wiring portion (122a2b) that are electrically separated from each other. The second-first wiring portion (122a2a) and the second-second wiring portion (122a2b) may be positioned on the same second build-up layer (112b). Accordingly, the second-first wiring portion (122a2a) and the second-second wiring portion (122a2b) may overlap at least partially in the horizontal direction (X-axis direction). In addition, the second-first wiring portion (122a2a) and the second-second wiring portion (122a2b) may be spaced apart from each other in the horizontal direction (X-axis direction).

[0109] The 2-1 wiring portion (122a2a) can be in contact with the 2-1 via electrode (122b2a). The 2-1 wiring portion (122a2a) can be electrically connected to the 2-1 via electrode (122b2a). In addition, the 2-1 wiring portion (122a2a) can overlap the 2-1 via electrode (122b2a) in the vertical direction (Y-axis direction). In addition, the lower surface of the 2-1 wiring portion (122a2a) can have a larger area than the upper surface of the 2-1 via electrode (122b2a).

[0110] In addition, as an embodiment, the 2-1 via electrode (122b2a) may include a first sub-via electrode (122b2aa) and a second sub-via electrode (122b2ab). The first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be spaced apart from each other in the horizontal direction (X-axis direction). However, the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may equally penetrate the second build-up layer (122b). In addition, the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may overlap in the horizontal direction (X-axis direction). And the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) can be in contact with the 2-1 wiring portion (122a2a). Accordingly, the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) can be electrically connected to each other. In other words, the 2-1 wiring portion (122a2a) is in contact with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) below, and can have a lower surface area larger than the total area of ​​the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab).

[0111] And in the embodiment, the wiring portion (e.g., the 2-1 wiring portion (122a2a)) that comes into contact with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may include an extension portion (L2) that protrudes upward. The following description will be made based on the 2-1 wiring portion.

[0112] Specifically, the 2-1 wiring portion (122a2a) may include a support portion (L1) and an extension portion (L2). That is, the extension portion (L2) may be located in the 2-1 wiring portion (122a2a) or may be an area of ​​the 2-1 wiring portion.

[0113] The support portion (L1) may be located on the second build-up layer (112b). The support portion (L1) may be located on the upper surface of the second build-up layer (112b). The support portion (L1) may be in contact with the second via electrode. In particular, the support portion (L1) may be in contact with the 2-1 via electrode (122b2a). In addition, the support portion (L1) may be in contact with the 1st sub-via electrode (122b2aa) and the 2nd sub-via electrode (122b2ab). The support portion (L1) may be located below the 2-1 wiring portion (122a2a).

[0114] The extension portion (L2) may be positioned on the support portion (L1). The extension portion (L2) may not overlap with the second-second wiring portion (122a2b) in the horizontal direction (X-axis direction). For example, the extension portion (L2) may not overlap with the second-second wiring portion (122a2b) at least partially in the horizontal direction (X-axis direction). Alternatively, the support portion (L1) may overlap with the second-second wiring portion (122a2b) in the horizontal direction (X-axis direction).

[0115] For example, the thickness of the 2-1 wiring portion (122a2a) may be greater than the thickness of the 2-2 wiring portion (122a2b). For example, the difference in thickness between the 2-1 wiring portion (122a2a) and the 2-2 wiring portion (122a2b) may correspond to the thickness of the extension portion (L2).

[0116] By means of such extensions, the stress applied to the via electrodes stacked and overlapped in the vertical direction (Y-axis direction) can be alleviated. For example, the stress (FF) applied from the lower 2-1 wiring section to the extension through the third via electrode can be widely spread. Accordingly, the stress can be prevented from being concentrated at one point, etc. Furthermore, the stress alleviation through multiple sub-via electrodes can be further improved, and the area consumed when alleviating the stress of the via can be minimized.

[0117] The extension (L2) is positioned on the support (L1) and can be in contact with the third via electrode (122b3) on the upper side. That is, the upper surface (US) of the extension (L2) can be in contact with the third via electrode (122b3). In particular, the upper surface (US) of the extension (L2) can be in contact with the lower surface of the third via electrode (122b3).

[0118] And the upper surface (US) of the extension portion (L2) may have an extended convex shape that is convex upwards. That is, the upper surface (US) of the extension portion (L2) or the upper surface of the wiring portion (e.g., the 2-1 wiring portion (122a2a)) that is in contact with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be a convex surface that is convex upwards.

[0119] In addition, in the embodiment, the width (W2) of the extension (L2) (or the width of the upper surface of the extension) may be different from the width (W1) of the lower surface of the third via electrode (122b3). The width (W2) of the extension (L2) (or the width of the upper surface of the extension) may be greater than the width (W1) of the lower surface of the third via electrode (122b3). Accordingly, the stress coming down from the upper side may spread to a wider area in the second-first wiring section. Accordingly, the stress applied to the via electrode may be reduced, thereby preventing damage to the via electrode.

[0120] Additionally, in the embodiment, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W2) of the extension portion (L2). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be smaller than the width (W2) of the extension portion (L2).

[0121] And the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W1) of the lower surface of the third via electrode (122b3). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be greater than the width (W1) of the lower surface of the third via electrode (122b3).

[0122] By this configuration, the stress spread through the third via electrode (122b3) and the second-first wiring portion (122a2a) can easily spread to the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab).

[0123] In this way, damage to the via electrode can be prevented more effectively.

[0124] Furthermore, the thickness of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be smaller than the thickness of the second build-up layer (112b). For example, the thickness of the first sub-via electrode (122b2aa) may be smaller than the thickness of the second build-up layer (112b). The thickness of the second sub-via electrode (122b2ab) may be smaller than the thickness of the second build-up layer (112b).

[0125] In addition, the thickness of the 2-1 via electrode (122b2a) may be smaller than the thickness of the 2-2 via electrode (122b2b). The thicknesses of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be smaller than the thickness of the 2-2 via electrode (122b2b). For example, the thickness of the first sub-via electrode (122b2aa) may be smaller than the thickness of the 2-2 via electrode (122b2b). The thickness of the second sub-via electrode (122b2ab) may be smaller than the thickness of the 2-2 via electrode (122b2b).

[0126] Referring further to FIG. 3, the third via electrode (122b3) (or the first via electrode, 122b1) may be positioned at the center of the second-first wiring portion (122a2a) (illustrated as the second wiring portion (122a2) in the drawing). And the third via electrode (122b3) may overlap the second-first wiring portion (122a2a) in the vertical direction (Y-axis direction).

[0127] And the third via electrode (122b3) (or the first via electrode) may overlap at least partially with the second-first via electrode (122b2a) and the second-second via electrode (122b2b).

[0128] In addition, the 2-1 wiring portion (122a2a) may at least partially overlap with the 2-1 via electrode (122b2a) and the 2-2 via electrode (122b2b) in the vertical direction (Y-axis direction). The 2-1 wiring portion (122a2a) may overlap with the 3rd via electrode (122b3) (or the 1st via electrode) in the vertical direction (Y-axis direction).

[0129] In particular, the extension portion (L2) of the 2-1 wiring portion (122a2a) may at least partially overlap with the 2-1 via electrode (122b2a) and the 2-2 via electrode (122b2b) in the vertical direction (Y-axis direction). In addition, the extension portion (L2) of the 2-1 wiring portion (122a2a) may overlap with the 3rd via electrode (122b3) (or the 1st via electrode) in the vertical direction (Y-axis direction).

[0130] Accordingly, the stress applied from the lower 2-1 wiring portion to the extension portion through the third via electrode can be widely spread to the 2-1 via electrode and the 2-2 via electrode. Accordingly, the stress can be uniformly spread along the extension portion, the support portion, and the 2-1 via electrode, etc., without being concentrated at one point.

[0131] As a variation, a third via electrode (122b3) (or first via electrode) may be positioned in a region between the second-first via electrode (122b2a) and the second-second via electrode (122b2b). Accordingly, the third via electrode (122b3) (or first via electrode) may not overlap with the second-first via electrode (122b2a) and the second-second via electrode (122b2b) in the vertical direction (Y-axis direction).

[0132] In addition, referring further to FIG. 4, the stress relief structure for the above-described via electrode can be applied not only to the build-up electrode portion but also to the core electrode portion (121).

[0133] As described above, the core electrode portion (121) may include a core wiring portion (121a) disposed on the core layer (111) and a core via electrode (121b) penetrating the core layer (111). The core wiring portion (121a) may be located on the upper and lower surfaces of the core layer (111). In addition, the core wiring portion (121a) may be in contact with the core via electrode (121b).

[0134] As an example, there may be a plurality of core wiring portions (121a) and core via electrodes (121b). The following description describes the structure of a portion of a plurality of core wiring portions (121a) and a plurality of core via electrodes (121b).

[0135] A plurality of core wiring portions (121a) may be spaced apart horizontally (X-axis direction). In addition, a plurality of core via electrodes (121b) may be spaced apart horizontally (X-axis direction). At this time, adjacent core via electrodes (121b) may be in contact with the same core wiring portion (121a) (hereinafter, first core wiring portion). That is, adjacent core via electrodes (121b) may overlap with the first core wiring portion (121a) in the vertical direction (Y-axis direction) and may be in contact with each other.

[0136] The first core wiring portion (121a) may include a core support portion (L3) and a core extension portion (L4). The core extension portion (L4) may be connected to the upper electrode portion (122) at the top. For example, the core extension portion (L4) may be in contact with the first via electrode. Accordingly, stress applied downward through the first via electrode may spread along the core extension portion (L4) and the core support portion (L3) (FF1).

[0137] By this configuration, multiple build-up layers (e.g., high-layers) are stacked on the core layer (111), and the stress applied to the via electrode of the build-up layer can be accumulated downward. At this time, the accumulated stress can be relieved by the above-described structure (core extension) of the core layer (111).

[0138] Additionally, the core extension (L4) may not overlap at least partially in the horizontal direction (X-axis direction) with core wiring portions other than the first core wiring portion. And the thickness of the first core wiring portion may be greater than the thickness of core wiring portions other than the first core wiring portion.

[0139] Additionally, this structure can be equally applied to the lower part of the core layer (111).

[0140] Referring to FIG. 5, as described above, the third via electrode (122b3) may overlap the second-first wiring portion (122a2a) in the vertical direction (Y-axis direction). In addition, the third via electrode (122b3) may be electrically connected to the second-first wiring portion (122a2a). The same may be true for the first via electrode.

[0141] The second via electrode (122b2) may include the second-first via electrode (122b2a) and the second-second via electrode (122b2b). And the third via electrode (122b3) (or the first via electrode) may at least partially overlap the second-first via electrode (122b2a) and the second-second via electrode (122b2b).

[0142] In addition, the 2-1 wiring portion (122a2a) may at least partially overlap with the 2-1 via electrode (122b2a) and the 2-2 via electrode (122b2b) in the vertical direction (Y-axis direction). The 2-1 wiring portion (122a2a) may overlap with the 3rd via electrode (122b3) (or the 1st via electrode) in the vertical direction (Y-axis direction).

[0143] In particular, the extension portion (L2) of the 2-1 wiring portion (122a2a) may at least partially overlap with the 2-1 via electrode (122b2a) and the 2-2 via electrode (122b2b) in the vertical direction (Y-axis direction). In addition, the extension portion (L2) of the 2-1 wiring portion (122a2a) may overlap with the 3rd via electrode (122b3) (or the 1st via electrode) in the vertical direction (Y-axis direction).

[0144] In this way, stress can be spread evenly along the extension, support, and 2-1 via electrodes, etc., without being concentrated at one point.

[0145] In particular, in the present example, a part of the upper surface (US2) of the extension (L2) may be concave. For example, the upper surface (US2) of the extension (L2) may be concave in a region in contact with the third via electrode (122b3). Alternatively, the upper surface (US2) of the extension (L2) may be concave. Accordingly, at least a part of the extension (L2) may overlap the third via electrode (122b3) in the horizontal direction (X-axis direction). In addition, the edge of the extension (L2) may be positioned lower than the center.

[0146] Accordingly, the extension portion (L2) in contact with the third via electrode (122b3) can propagate the stress transmitted from the third via electrode (122b3) to a larger area. In other words, the stress is structurally distributed, so cracks and the like can be easily prevented. In addition, a material on the extension portion (L2) can be easily formed during a process such as plating.

[0147] Referring to FIG. 6, as described above, the third via electrode (122b3) may overlap with the second-first wiring portion (122a2a) in the vertical direction (Y-axis direction). In addition, the third via electrode (122b3) may be electrically connected to the second-first wiring portion (122a2a). The same may be true for the first via electrode.

[0148] The second via electrode (122b2) may include the second-first via electrode (122b2a) and the second-second via electrode (122b2b). And the third via electrode (122b3) (or the first via electrode) may at least partially overlap the second-first via electrode (122b2a) and the second-second via electrode (122b2b).

[0149] In addition, the 2-1 wiring portion (122a2a) may at least partially overlap with the 2-1 via electrode (122b2a) and the 2-2 via electrode (122b2b) in the vertical direction (Y-axis direction). The 2-1 wiring portion (122a2a) may overlap with the 3rd via electrode (122b3) (or the 1st via electrode) in the vertical direction (Y-axis direction).

[0150] Furthermore, the 2-1 wiring portion (122a2a) may include a support portion (L1) and an extension portion (L2). The extension portion (L2) is positioned on the support portion (L1) and may be in contact with the third via electrode (122b3). At this time, at least a portion of the extension portion (L2) may be horizontally misaligned with the 2-2 wiring portion (122a2b) as described above. In addition, the extension portion (L2) may at least partially overlap the third via electrode, which is electrically separated from the 2-1 wiring portion, in the horizontal direction (X-axis direction).

[0151] And the upper surface (US) of the extension (L2) is in contact with the third via electrode (122b3), and a part of the upper surface (US) may be a flat surface. For example, a part of the upper surface (US) may be parallel to the upper surface of the build-up layer. In addition, the upper surface (US) may be parallel to the upper surface of the build-up layer.

[0152] This configuration can improve the signal integrity of the circuit board through uniform electrical contact. Furthermore, uniform plating can be achieved on the circuit board, and mechanical stability can also be improved through stress distribution.

[0153] Figures 7 to 11 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0154] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0155] Referring to FIG. 7, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or greater, as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0156] Referring to FIG. 8, a via hole or a through hole (111h) can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0157] Referring to Fig. 9, a core electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0158] For example, a plating process may be performed on a via hole formed in a core layer (111) to form a through electrode. In addition, a core wiring portion may be formed on the upper and lower surfaces of the core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions.

[0159] Referring to Fig. 10, a build-up insulation portion (112, 113) can be formed on the core layer (111). For example, the upper build-up layer (112) can be formed on top of the core layer (111). Additionally, the lower build-up layer (113) can be formed on the lower side of the core layer (111).

[0160] And a via hole or through hole may be formed in the upper build-up layer (112) and / or the lower build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0161] Additionally, an upper electrode portion (122) may be formed on the upper build-up layer (112). And a lower electrode portion (123) may be formed on the lower build-up layer (113). The upper electrode portion (122) and the lower electrode portion (123) may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0162] And the upper wiring part of the upper electrode part (122) may be formed on the upper surface of the upper build-up layer (112), and the lower wiring part of the lower electrode part (123) may be formed on the lower surface of the lower build-up layer (113). Each wiring part may have a pattern by a mask or the like. Furthermore, the wiring part may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes of a printed circuit board.

[0163] Referring to FIG. 11, a protective layer (SR) may be formed. For example, a first protective layer (SR1) may be formed on an upper build-up layer (112). And a second protective layer (SR2) may be formed under a lower build-up layer (113).

[0164] Furthermore, a bump portion (BP) may be formed in the protective layer (SR). For example, a via portion (TP) penetrating the protective layer (SR) may be formed. In addition, a protrusion portion (PP) connected to the via portion (TP) may be formed in the protective layer (SR).

[0165] Fig. 12 is a cross-sectional view of a circuit board according to the second embodiment, Fig. 13 is an enlarged view of K3 in Fig. 12, and Fig. 14 is a modified example of Fig. 13.

[0166] Referring to FIGS. 12 and 13, a circuit board (100A) according to the second embodiment may include an insulating layer (110) and an electrode portion (120). In addition, the circuit board (100A) according to the second embodiment may further include a protective layer (SR) and a bump portion (BP). In addition, the contents described in other embodiments may be equally applied to this example, except for the contents described below.

[0167] In this example, the second wiring portion (122a2) may include a second-first wiring portion (122a2a) and a second-second wiring portion (122a2b) that are electrically separated. In addition, the second via electrode (122b2) may include a second-first via electrode (122b2a) and a second-second via electrode (122b2b) that are electrically separated.

[0168] The 2-1 via electrode (122b2a) is in contact with the 2-1 wiring portion (122a2a) and can be electrically connected to each other. The 2-2 via electrode (122b2a) is in contact with the 2-2 wiring portion (122a2b) and can be electrically connected to each other.

[0169] In addition, the first via electrode (122b1) and the third via electrode (122b3) may overlap in the vertical direction, and the second-first via electrode (122b2a) may be positioned between the first via electrode (122b1) and the third via electrode (122b3). The second-first via electrode (122b2a) may be in contact with the first via electrode (122b1) and the third via electrode (122b3) and may be electrically connected to each other.

[0170] And the 2-1 via electrode (122b2a) may include a first sub-via electrode (122b2aa) and a second sub-via electrode (122b2ab). In addition, the 2-1 wiring portion (122a2a) may include a support portion (L1) and an extension portion (L2).

[0171] In this example, the support portion (L1) and the extension portion (L2) may have different widths. That is, the width of the support portion (L1) may be different from the width of the extension portion (L2).

[0172] The width (W5) of the extension (L2) (or the width of the upper surface of the extension) may be different from the width (W4) of the lower surface of the third via electrode (122b3). The width (W5) of the extension (L2) (or the width of the upper surface of the extension) may be greater than the width (W4) of the lower surface of the third via electrode (122b3).

[0173] Accordingly, the stress coming from above can spread over a wider area in the second-first wiring section. Accordingly, the stress applied to the via electrode is reduced, thereby preventing damage to the via electrode.

[0174] Additionally, in the embodiment, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W5) of the extension portion (L2). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be greater than the width (W5) of the extension portion (L2).

[0175] Furthermore, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W4) of the lower surface of the third via electrode (122b3). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be greater than the width (W4) of the lower surface of the third via electrode (122b3).

[0176] By this configuration, the stress spread through the third via electrode and the second-first wiring portion can easily spread to the first sub-via electrode and the second sub-via electrode.

[0177] Additionally, the extension portion (L2) may overlap at least partially with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) in the stacking direction (Y-axis direction). And at least partially with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may not overlap with the extension portion (L2) in the stacking direction (Y-axis direction).

[0178] Referring to Fig. 14, as a variation, the support portion (L1) and the extension portion (L2) may have different widths. For example, the width (W7) of the support portion (L1) may be different from the width (W6) of the extension portion (L2). In addition, the width (W7) of the support portion (L1) may be greater than the width (W6) of the extension portion (L2).

[0179] Furthermore, in this example, the width (W6) of the extension (L2) (or the width of the upper surface of the extension) may be different from the width (W4) of the lower surface of the third via electrode (122b3). The width (W6) of the extension (L2) (or the width of the upper surface of the extension) may be greater than the width (W4) of the lower surface of the third via electrode (122b3).

[0180] Accordingly, the stress coming from above can spread over a wider area in the second-first wiring section. Accordingly, the stress applied to the via electrode is reduced, thereby preventing damage to the via electrode.

[0181] Additionally, in the embodiment, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W6) of the extension portion (L2). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be smaller than the width (W6) of the extension portion (L2).

[0182] Furthermore, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W4) of the lower surface of the third via electrode (122b3). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be greater than the width (W4) of the lower surface of the third via electrode (122b3).

[0183] By this configuration, the stress spread through the third via electrode and the second-first wiring portion can easily spread to the first sub-via electrode and the second sub-via electrode below.

[0184] Additionally, the extension portion (L2) may overlap at least partially with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) in the stacking direction (Y-axis direction). And at least partially with the extension portion (L2) may not overlap with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) in the stacking direction (Y-axis direction).

[0185] Fig. 15 is a cross-sectional view of a circuit board according to the third embodiment, and Fig. 16 is an enlarged view of K4 of Fig. 15.

[0186] The circuit board (100B) according to the third embodiment may include an insulating layer (110) and an electrode portion (120). In addition, the circuit board (100B) according to the third embodiment may further include a protective layer (SR) and a bump portion (BP). Except for the contents described below, the contents described in other embodiments may be equally applied to this example.

[0187] In this example, the second wiring portion (122a2) may include a second-first wiring portion (122a2a) and a second-second wiring portion (122a2b) that are electrically separated. In addition, the second via electrode (122b2) may include a second-first via electrode (122b2a) and a second-second via electrode (122b2b) that are electrically separated.

[0188] The 2-1 via electrode (122b2a) is in contact with the 2-1 wiring portion (122a2a) and can be electrically connected to each other. The 2-2 via electrode (122b2a) is in contact with the 2-2 wiring portion (122a2b) and can be electrically connected to each other.

[0189] In addition, the first via electrode (122b1) and the third via electrode (122b3) may overlap in the vertical direction, and the second-first via electrode (122b2a) may be positioned between the first via electrode (122b1) and the third via electrode (122b3). The second-first via electrode (122b2a) may be in contact with the first via electrode (122b1) and the third via electrode (122b3) and may be electrically connected to each other.

[0190] And the 2-1 via electrode (122b2a) may include a first sub-via electrode (122b2aa) and a second sub-via electrode (122b2ab). In addition, the 2-1 wiring portion (122a2a) may include a support portion (L1) and an extension portion (L2).

[0191] The support portion (L1) and the extension portion (L2) may have different widths. For example, the width (W9) of the support portion (L1) may be different from the width (W10) of the extension portion (L2). In addition, the width (W9) of the support portion (L1) may be smaller than the width (W10) of the extension portion (L2). That is, at least a portion of the extension portion (L2) may not overlap the support portion (L1) in the vertical direction (Y-axis direction).

[0192] In particular, in this example, the width (W10) of the extension (L2) (or the width of the upper surface of the extension) may be different from the width (W8) of the lower surface of the third via electrode (122b3). The width (W10) of the extension (L2) (or the width of the upper surface of the extension) may be greater than the width (W8) of the lower surface of the third via electrode (122b3).

[0193] Accordingly, the stress coming from above can spread over a wider area in the second-first wiring section. Accordingly, the stress applied to the via electrode is reduced, thereby preventing damage to the via electrode.

[0194] Additionally, in the embodiment, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W10) of the extension portion (L2). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be smaller than the width (W10) of the extension portion (L2).

[0195] Additionally, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W9) of the support portion (L1). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be smaller than the width (W9) of the support portion (L1).

[0196] Furthermore, the maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be different from the width (W8) of the lower surface of the third via electrode (122b3). The maximum width (W3) of the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) may be greater than the width (W8) of the lower surface of the third via electrode (122b3).

[0197] By this configuration, the stress spread through the third via electrode and the second-first wiring portion can easily spread to the first sub-via electrode and the second sub-via electrode below.

[0198] Additionally, the extension portion (L2) may overlap at least partially with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) in the stacking direction (Y-axis direction). And at least partially with the extension portion (L2) may not overlap with the first sub-via electrode (122b2aa) and the second sub-via electrode (122b2ab) in the stacking direction (Y-axis direction).

[0199] Fig. 17 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 18 is a cross-sectional view showing a semiconductor package according to the second embodiment, Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 20 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0200] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0201] Referring to FIG. 17, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0202] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0203] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0204] The first substrate (1100) may include at least one insulating layer and a build-up electrode portion disposed on the at least one insulating layer.

[0205] A second substrate (1200) may be placed on the first substrate (1100).

[0206] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0207] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0208] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0209] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0210] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0211] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0212] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0213] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0214] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0215] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0216] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0217] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0218] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0219] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0220] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0221] Additionally, looking further into FIG. 17, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0222] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0223] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0224] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0225] Referring to FIG. 18, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0226] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0227] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0228] Referring to FIG. 19, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0229] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0230] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0231] Referring to FIG. 20, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0232] In this way, the semiconductor package of the fourth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0233] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0234] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0235] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0236] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0237] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0238] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0239] The semiconductor package of the fourth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0240] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0241] Meanwhile, the third semiconductor element (1330) in the fourth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0242] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0243] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0244] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0245] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0246] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0247] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up insulation comprising a plurality of build-up layers stacked in a vertical direction; and It includes an electrode part including a wiring part arranged in the above build-up insulation part and a via electrode penetrating the plurality of build-up layers; The above via electrode includes a first sub-via electrode and a second sub-via electrode spaced horizontally apart, A circuit board in which the wiring portion in contact with the first sub-via electrode and the second sub-via electrode has a convex surface with an upper surface convex upward.

2. In paragraph 1, The above plurality of build-up layers include a first build-up layer, a second build-up layer, and a third build-up layer sequentially arranged in a vertical direction; The wiring section includes a first wiring section arranged in the first build-up layer, a second wiring section arranged in the second build-up layer, and a third wiring section arranged in the third build-up layer; A circuit board including a first via electrode penetrating the first build-up layer, a second via electrode penetrating the second build-up layer, and a third via electrode penetrating the third build-up layer.

3. In paragraph 2, A circuit board in which the first via electrode and the third via electrode are overlapped and connected to each other in the vertical direction.

4. In paragraph 2, The second via electrode is a circuit board including a second-1 via electrode and a second-2 via electrode that are electrically separated.

5. In paragraph 4, A circuit board in which a second via electrode is positioned between the first via electrode and the third via electrode.

6. In paragraph 4, The above 2-1 via electrode is a circuit board including the first sub-via electrode and the second sub-via electrode.

7. In paragraph 6, A circuit board wherein the thickness of the first sub-via electrode and the second sub-via electrode is smaller than the thickness of the second build-up layer.

8. In paragraph 4, A circuit board in which the thickness of the above-mentioned 2-1 via electrode is smaller than the thickness of the above-mentioned 2-2 via electrode.

9. In paragraph 6, The above wiring portion includes an extension portion extending upward, A circuit board including a second wiring section and a second wiring section, wherein the second wiring section is electrically separated from the first wiring section.

10. In paragraph 9, The above 2-1 wiring section is a circuit board in contact with the first sub-via electrode and the second sub-via electrode.

11. In paragraph 9, A circuit board in which the thickness of the above-mentioned 2-1 wiring portion is greater than the thickness of the above-mentioned 2-2 wiring portion.

12. In paragraph 9, The above extension part is a circuit board located in the above 2-1 wiring part.

13. In paragraph 9, A circuit board in which the extension portion does not overlap at least partially in the horizontal direction with the second-second wiring portion.

14. In paragraph 9, The upper surface of the above extension portion is a circuit board in contact with the third via electrode.

15. In paragraph 9, The above 2-1 wiring section includes a support section arranged below the extension section; A circuit board having different widths in the horizontal direction of the support portion and the extension portion.

Images