Semiconductor power device and manufacturing method therefor

Abstract

Provided in the present invention are a semiconductor power device and a manufacturing method therefor. The semiconductor power device comprises a protection unit located in a drift layer. The protection unit comprises: a first epitaxial protection layer, which surrounds the side wall and the bottom surface of a gate structure; and a second doped protection layer, which is located on the side of the first epitaxial protection layer facing a semiconductor substrate layer and which is in contact with the first epitaxial protection layer, the conductivity type of the second doped protection layer being opposite to that of the first epitaxial protection layer, and the second doped protection layer and the first epitaxial protection layer constituting a PN junction. The semiconductor power device further comprises a channel region, which is located in the first epitaxial protection layer of the sidewall of the gate structure. The present invention relieves electric field concentration of the bottom region of the gate structure of the semiconductor power device in a reverse blocking state, and independently regulates and controls the doping concentration and length of the channel region, such that during forward conduction, the first epitaxial protection layer on the side wall of a trench can have a current spreading function.

Description

Semiconductor power device and preparation method thereof

[0001] This application claims priority to Chinese patent application CN202410406036.3, entitled “Semiconductor power device and its preparation method,” filed on April 3, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a preparation method thereof. Background Art

[0003] Power semiconductor devices are core components for power conversion and circuit control in power electronics. With the recent development of industries such as new energy vehicles, photovoltaics, rail transit, and smart grids, market demand for power devices has rapidly increased. Third-generation semiconductor SiC materials offer significant advantages in bandgap, thermal conductivity, critical breakdown field strength, and electron saturation drift velocity, aligning with the future trend of power electronics systems toward miniaturization, lightweighting, efficient integration, safety, and reliability.

[0004] With the continuous iteration of planar SiC MOSFET technology, its ability to reduce cell size is gradually approaching its limit. In comparison, trench SiC MOSFET, with its inherent advantages such as smaller cell size and higher channel density, is destined to be the development trend of the next generation of SiC power devices. For trench SiC MOSFETs, the electric field concentration of the bottom gate oxide in the reverse blocking state is a key issue that restricts its performance and reliability. Secondly, as part of the well region, it is difficult to independently control the doping concentration and length of the channel region. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to improve the electric field concentration in the bottom area of ​​the gate structure of a semiconductor power device in a reverse blocking state and how to independently regulate the doping concentration and length of the channel region.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; and a protection unit located in the drift layer. The protection unit comprises: a first epitaxial protection layer surrounding the sidewalls and bottom surface of the gate structure, the first epitaxial protection layer having the same conductivity type as the drift layer and having a doping concentration greater than that of the drift layer; and a second doped protection layer located on the side of the first epitaxial protection layer facing the semiconductor substrate layer and in contact with the first epitaxial protection layer, the second doped protection layer having a conductivity type opposite to that of the first epitaxial protection layer, and the second doped protection layer and the first epitaxial protection layer forming a PN junction. The semiconductor power device also comprises a channel region located in the first epitaxial protection layer on the sidewalls of the gate structure.

[0007] Optionally, the doping concentration of the second doped protection layer is greater than the doping concentration of the first epitaxial protection layer.

[0008] Optionally, a surface of the channel region facing away from the semiconductor substrate layer is spaced from a surface of the drift layer facing away from the semiconductor substrate layer, and a surface of the channel region facing the semiconductor substrate layer is spaced from a surface of the gate structure facing the semiconductor substrate layer.

[0009] Optionally, a dimension of the second doping protection layer along the width direction of the gate structure is smaller than, equal to, or larger than the width of the bottom surface of the gate structure.

[0010] Optionally, the semiconductor power device also includes: a first source region, located in the drift layer on both sides of the gate structure in the width direction, and the conductivity type of the first source region is opposite to the conductivity type of the drift layer; and a second source region, located in a partial area of ​​the first source region, and the conductivity type of the second source region is opposite to the conductivity type of the first source region.

[0011] Optionally, the doping concentration of the first source region is 5 to 500 times the doping concentration of the channel region.

[0012] Optionally, the doping concentration of the channel region is lower than the doping concentration of the first source region.

[0013] Optionally, the second source region contacts a sidewall of the first epitaxial protection layer on a side laterally away from the gate structure, or the second source region further extends into the first epitaxial protection layer on a side of the channel region away from the semiconductor substrate layer.

[0014] Optionally, a surface of the first source region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than a surface of the second doping protection layer facing away from the semiconductor substrate layer.

[0015] Optionally, a longitudinal distance from a surface of the first source region facing the semiconductor substrate layer to a surface of the second doping protection layer facing away from the semiconductor substrate layer is 1 micrometer to 1.5 micrometers.

[0016] Optionally, the semiconductor power device also includes: a current spreading layer, located in the drift layer on the side of the first source region facing the semiconductor substrate layer and on the side of the gate structure, the current spreading layer is in contact with the first source region and the first epitaxial protection layer on the side wall of the gate structure respectively, the conductivity type of the current spreading layer is opposite to the conductivity type of the first source region, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer.

[0017] Optionally, the current spreading layer and the second doped protective layer are spaced apart, or the current spreading layer and the second doped protective layer are spaced apart and in contact with each other.

[0018] Optionally, the second doping protection layer includes a first sub-doping region and a second sub-doping region arranged at intervals, the first sub-doping region surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on one side along the width direction, and the second sub-doping region surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on the other side along the width direction.

[0019] Optionally, the semiconductor power device further includes: a third doped protection layer located in the first epitaxial protection layer at the bottom of the gate structure, and the conductivity type of the third doped protection layer is the same as the conductivity type of the second doped protection layer.

[0020] Optionally, the doping concentration of the third doping protection layer is the same as the doping concentration of the second doping protection layer, or the doping concentration of the third doping protection layer is less than the doping concentration of the second doping protection layer, or the doping concentration of the third doping protection layer is greater than the doping concentration of the second doping protection layer.

[0021] Optionally, the second doping protection layer includes a first sub-doping region and a second sub-doping region arranged at intervals, the first sub-doping region surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on one side along the width direction, and the second sub-doping region surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on the other side along the width direction.

[0022] Optionally, the third doping protection layer is laterally spaced apart from the first sub-doping region and the second sub-doping region respectively in a width direction of the gate structure.

[0023] Optionally, the thickness of the first epitaxial protection layer is 10 nanometers to 1 micron.

[0024] Optionally, a plurality of the second doped protection layers are arranged at intervals along the length direction of the gate structure, or the second doped protection layer is continuous along the length direction of the gate structure.

[0025] Optionally, the semiconductor power device is a SiC-based semiconductor power device.

[0026] The present invention also provides a method for fabricating a semiconductor power device, comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a trench extending from a surface of the drift layer facing away from the semiconductor substrate to a portion of the thickness of the drift layer; and forming a protection unit. Forming the protection unit comprises: forming a second doped protection layer in the drift layer at the bottom of the trench; after forming the second doped protection layer, epitaxially forming a first epitaxial protection layer on the inner wall surface of the trench, wherein the first epitaxial protection layer has the same conductivity type as the drift layer and an opposite conductivity type as the second doped protection layer, the doping concentration of the first epitaxial protection layer being greater than the doping concentration of the drift layer, and the second doped protection layer and the first epitaxial protection layer forming a PN junction. The fabrication method further comprises: forming a channel region in the first epitaxial protection layer on the sidewall surface of the trench; and after forming the protection unit, forming a gate structure in the trench.

[0027] Optionally, the channel region is formed before forming the gate structure.

[0028] Optionally, the preparation method also includes: before forming the trench, forming a first initial source region in the drift layer of partial thickness, the conductivity type of the first initial source region and the conductivity type of the drift layer are opposite, and the process of forming a trench extending from the surface of the side of the drift layer away from the semiconductor substrate to the drift layer of partial thickness is: forming a trench in the first initial source region and a portion of the drift layer at the bottom of the first initial source region, and forming the first source region on both sides of the trench.

[0029] Optionally, the preparation method further includes: before forming the first initial source region in the drift layer with partial thickness, forming an initial current spreading layer in the drift layer with partial thickness, the step of forming the first initial source region in the drift layer with partial thickness is: forming the first initial source region in the initial current spreading layer, the surface of the first initial source region facing the semiconductor substrate layer is away from the semiconductor substrate layer relative to the surface of the initial current spreading layer facing the semiconductor substrate layer, in the process of forming the trench, the trench also penetrates the initial current spreading layer, and the initial current spreading layer on the side of the trench forms a current spreading layer.

[0030] Optionally, the preparation method also includes: before forming the trench, forming a second initial source region in the first initial source region, the conductivity type of the second initial source region is opposite to the conductivity type of the first initial source region, the lateral size of the second initial source region is smaller than the lateral size of the first initial source region, the surface of the second initial source region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than the surface of the first initial source region facing the semiconductor substrate layer, and the process of forming a trench extending from the surface of the drift layer away from the semiconductor substrate to the drift layer of partial thickness is: forming a trench in the second initial source region, the first initial source region and a part of the drift layer at the bottom of the first initial source region, and the second initial source regions on both sides of the trench form a second source region; after forming the first epitaxial protection layer, the second source region contacts the side wall of the first epitaxial protection layer laterally away from the trench.

[0031] Optionally, the ion implantation process used to form the channel region has an implantation direction perpendicular to the upper surface of the semiconductor substrate layer.

[0032] Optionally, the preparation method further comprises: after forming the channel region, forming a second source region in a portion of the first source region and in the first epitaxial protection layer on a side of the channel region away from the semiconductor substrate layer.

[0033] Optionally, an angle between an implantation direction of an ion implantation process used to form the channel region and a sidewall surface of the trench is greater than zero.

[0034] Optionally, during the process of forming the channel region, a third doped protection layer is formed in the first epitaxial protection layer at the bottom of the trench, and the conductivity type of the third doped protection layer is opposite to that of the first epitaxial protection layer.

[0035] The technical solution of the present invention has the following technical effects:

[0036] The present invention provides a method for fabricating a semiconductor power device, which forms a protection unit. The method comprises: forming a second doped protection layer in the drift layer at the bottom of the trench; after forming the second doped protection layer, epitaxially forming a first epitaxial protection layer on the inner wall surface of the trench. The first epitaxial protection layer has the same conductivity type as the drift layer and an opposite conductivity type to the second doped protection layer. The first epitaxial protection layer has a greater doping concentration than the drift layer, and the second doped protection layer and the first epitaxial protection layer form a PN junction. This allows the PN junction formed by the second doped protection layer and the first epitaxial protection layer to be depleted during reverse withstand voltage, shifting part of the electric field peak to the junction of the PN junction. The PN junction protects the gate dielectric layer at the bottom of the gate structure, thereby alleviating the problem of electric field concentration at the bottom of the gate structure during reverse withstand voltage. A channel region is formed in the first epitaxial protection layer on the trench sidewall surface, so that the doping concentration and length of the channel region can be well controlled, allowing the threshold voltage and channel resistance to be independently adjusted. The process of epitaxially forming the first epitaxial protection layer on the inner wall surface of the trench includes an epitaxial process, which enables the morphology of the first epitaxial protection layer to be more precisely controlled. The first epitaxial protection layer is formed within the trench and does not increase the lateral dimensions of the cell. Furthermore, when the semiconductor power device is forward-conducting, the first epitaxial protection layer on the trench sidewall acts as an accumulation layer under the action of the gate structure, thereby promoting current expansion.

[0037] Furthermore, before forming the trench, a first initial source region is formed in a portion of the drift layer. After the trench is formed, the first initial source regions on both sides of the trench form first source regions. The doping concentration of the first source region is higher than the doping concentration of the well region in the prior art. The first source region and the drift layer at the bottom of the first source region are depleted, and part of the electric field peak is transferred to the junction of the first source region and the drift layer, thereby protecting the gate dielectric layer in the sidewall region of the gate structure. Secondly, the first epitaxial protection layer on the sidewalls of the first source region and the gate structure can be depleted, so that the first epitaxial protection layer can be fully depleted to protect the gate dielectric layer.

[0038] Furthermore, after forming the channel region, a second source region is formed in a portion of the first source region and in the first epitaxial protection layer on a side of the channel region facing away from the semiconductor substrate layer. The second source region can control the length and doping concentration of the channel region.

[0039] Furthermore, when the dimension of the second doped protection layer along the width direction of the gate structure is smaller than the width of the bottom surface of the gate structure, the first epitaxial protection layer at the bottom of the trench can function as an accumulation layer under the action of the gate structure to expand the current.

[0040] Furthermore, when a plurality of the second doped protection layers are arranged at intervals along the length direction of the gate structure, the first epitaxial protection layer at the bottom of the trench can function as an accumulation layer under the action of the gate structure to play a role in current expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] 1 to 9 are schematic structural diagrams of a process for preparing a semiconductor power device according to an embodiment of the present invention;

[0043] FIG10 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0044] FIG11 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0045] 12 to 15 are schematic structural diagrams of a process for preparing a semiconductor power device according to an embodiment of the present invention;

[0046] FIG16 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0047] 17 to 24 are schematic structural diagrams of a process for preparing a semiconductor power device according to an embodiment of the present invention;

[0048] FIG25 is a schematic structural diagram of a semiconductor power device provided by another embodiment of the present invention;

[0049] 26 to 31 are schematic structural diagrams of a process for preparing a semiconductor power device according to an embodiment of the present invention;

[0050] FIG32 is a schematic structural diagram of a semiconductor power device provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0051] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0052] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0053] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0054] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0055] Example 1

[0056] One embodiment of the present invention provides a method for fabricating a semiconductor power device, the method comprising: forming a drift layer on one side of a semiconductor substrate layer; forming a trench extending from a surface of the drift layer facing away from the semiconductor substrate to a portion of the thickness of the drift layer; and forming a protection unit. Forming the protection unit comprises: forming a second doped protection layer in the drift layer at the bottom of the trench; after forming the second doped protection layer, epitaxially forming a first epitaxial protection layer on the inner wall surface of the trench, wherein the first epitaxial protection layer has the same conductivity type as the drift layer and an opposite conductivity type to the second doped protection layer, the doping concentration of the first epitaxial protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first epitaxial protection layer form a PN junction. The fabrication method further comprises: forming a channel region in the first epitaxial protection layer on the sidewall surface of the trench; and after forming the protection unit, forming a gate structure in the trench.

[0057] The preparation method of the semiconductor power device provided in this embodiment forms a protection unit, and the second doped protection layer and the first epitaxial protection layer constitute a PN junction. In this way, during the reverse withstand voltage process, the PN junction formed by the second doped protection layer and the first epitaxial protection layer is depleted, and part of the electric field peak is transferred to the junction of the PN junction, and the PN junction protects the gate dielectric layer at the bottom of the gate structure. The problem of electric field concentration at the bottom of the gate structure during the reverse withstand voltage state is alleviated. A channel region is formed in the first epitaxial protection layer on the surface of the trench sidewall, so the doping concentration of the channel region and the length of the channel region can be well controlled, so that the threshold voltage and the channel resistance can be independently regulated. Secondly, the existence of the first epitaxial protection layer on the trench sidewall as an accumulation layer under the action of the gate structure can play a role in current expansion.

[0058] The following describes in detail the process of manufacturing the semiconductor power device of this embodiment with reference to FIG. 1 to FIG. 9 .

[0059] 1 , a drift layer 110 is formed on one side of a semiconductor substrate layer 100 .

[0060] In this embodiment, the new generation of SiC-based semiconductor power devices represented by SiC have higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered to be a new hope in the field of power conversion. It should be noted that in this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0061] In one embodiment, the conductivity type of the drift layer 110 is the same as that of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is lower than that of the semiconductor substrate layer 100. In one embodiment, the drift layer is made of silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions. The formation process of the drift layer 110 includes an epitaxial process.

[0062] 2 , a first initial source region 1200 is formed in a partial thickness of the drift layer 110 . The conductivity type of the first initial source region 1200 is opposite to that of the drift layer 110 .

[0063] The process of forming the first initial source region 1200 includes an ion implantation process. The doping concentration of the first initial source region 1200 is greater than the doping concentration of the drift layer 110 .

[0064] It should be noted that the doping concentration of the first initial source region 1200 is greater than the doping concentration of a conventional well region in the prior art.

[0065] In this embodiment, the preparation method of the semiconductor power device also includes: forming a second initial source region 1300 in the first initial source region 1200, the conductivity type of the second initial source region 1300 is opposite to the conductivity type of the first initial source region 1200, the lateral size of the second initial source region 1300 is smaller than the lateral size of the first initial source region 1200, and the surface of the second initial source region 1300 facing the semiconductor substrate layer 100 is away from the semiconductor substrate layer 100 relative to the surface of the first initial source region 1200 facing the semiconductor substrate layer 100.

[0066] The process of forming the second initial source region 1300 includes an ion implantation process. The doping concentration of the second initial source region 1300 is greater than the doping concentration of the drift layer 110 .

[0067] 3 , a trench 140 is formed in the drift layer 110 , extending from a surface of the drift layer 110 facing away from the semiconductor substrate 100 to a portion of the thickness of the drift layer 110 .

[0068] The process of forming the trench 140 extending from the surface of the drift layer 110 on the side facing away from the semiconductor substrate 100 to a portion of the drift layer 110 is as follows: the trench 140 is formed in the first initial source region 1200 and the portion of the drift layer 110 at the bottom of the first initial source region 1200, and the first initial source region 1200 on both sides of the trench 140 forms the first source region 120. Furthermore, the trench 140 is formed in the second initial source region 1300, the first initial source region 1200, and the portion of the drift layer 110 at the bottom of the first initial source region 1200, and the second initial source region 1300 on both sides of the trench 140 forms the second source region 130.

[0069] The doping concentration of the first source region 120 is higher than the doping concentration of the well region in the prior art. The first source region 120 and the drift layer 110 at the bottom of the first source region 120 are depleted, and part of the electric field peak is transferred to the junction of the first source region 120 and the drift layer 110, thereby protecting the gate dielectric layer in the sidewall area of ​​the gate structure.

[0070] The process for forming the trench 140 includes an etching process. It should be noted that before forming the trench 140, a mask layer can be formed to cover a portion of the second initial source region 1300 and the first initial source region 1200. The mask layer exposes a portion of the second initial source region 1300. The second initial source region 1300, the first initial source region 1200, and a portion of the drift layer 110 at the bottom of the first initial source region 1200 are then etched using the mask layer as a mask to form the trench 140. After forming the trench 140, the mask layer is removed.

[0071] 4 , a second doping protection layer 150 is formed in the drift layer 110 at the bottom of the trench 140 .

[0072] The process for forming the second doped protective layer 150 includes an ion implantation process. In one embodiment, ions are implanted into the drift layer 110 at the bottom of the trench 140 using a mask layer as a mask to form the second doped protective layer 150. The mask layer is then removed. The conductivity type of the second doped protective layer 150 is opposite to that of the drift layer 110.

[0073] In one embodiment, the lateral width of the second doped protective layer 150 is equal to the lateral width of the trench 140. After the gate structure is subsequently formed, the lateral width of the second doped protective layer 150 is equal to the width of the gate structure. The first epitaxial protective layer at the bottom of the trench acts as an accumulation layer under the action of the gate structure and can play a role in current expansion. In other embodiments, the lateral width of the second doped protective layer is less than the lateral width of the trench 140. After the gate structure is subsequently formed, the lateral width of the second doped protective layer 150 is less than the width of the gate structure. In other embodiments, the lateral width of the second doped protective layer is greater than the lateral width of the trench 140. After the gate structure is subsequently formed, the lateral width of the second doped protective layer 150 is greater than the width of the gate structure.

[0074] Multiple second doped protective layers 150 are spaced apart along the length of the trench 140, and multiple subsequent second doped protective layers 150 are spaced apart along the length of the gate structure. The first epitaxial protective layer at the bottom of the trench acts as an accumulation layer under the action of the gate structure to spread the current. Alternatively, the second doped protective layer 150 is continuous along the length of the trench 140, and subsequent second doped protective layers 150 are continuous along the length of the gate structure.

[0075] The length direction of the gate structure is perpendicular to the width direction of the gate structure and both are parallel to the surface of the semiconductor substrate layer 100 .

[0076] 5 , after the second doping protection layer 150 is formed, a first epitaxial protection layer 160 is epitaxially formed on the inner wall surface of the trench 140 .

[0077] A first epitaxial protection layer 160 is epitaxially formed on the sidewall surfaces and bottom surface of the trench 140. The first epitaxial protection layer 160 is also formed on the surface of the first source region 120 and the second source region 130 facing away from the semiconductor substrate layer 100. After the gate structure is subsequently formed, the first epitaxial protection layer 160 on the surface of the first source region 120 and the second source region 130 facing away from the semiconductor substrate layer 100 is removed.

[0078] The process of forming the first epitaxial protection layer 160 includes an epitaxial process, so that the morphology of the first epitaxial protection layer 160 can be more accurately controlled, and the first epitaxial protection layer 160 is formed inside the trench without increasing the lateral size of the cell.

[0079] After forming the first epitaxial protection layer 160 , the second source region 130 contacts the sidewall of the first epitaxial protection layer 160 laterally away from the trench 140 , and the first source region 120 contacts the sidewall of the first epitaxial protection layer 160 laterally away from the trench 140 .

[0080] The first source region 120 and the first epitaxial protection layer 160 on the sidewall of the gate structure can be depleted, so that the first epitaxial protection layer 160 can be fully depleted to protect the gate dielectric layer.

[0081] In one embodiment, the thickness of the first epitaxial protection layer is 10 nm to 1 μm, for example, 10 nm, 20 nm, 50 nm, 100 nm, 200 nm, 500 nm, 800 nm or 1 μm.

[0082] 6 , a channel region 170 is formed in the first epitaxial protection layer 160 on the sidewall surface of the trench 140. The channel region 170 is formed by an ion implantation process.

[0083] In one embodiment, the ion implantation process used to form the channel region 170 has an implantation direction perpendicular to the upper surface of the semiconductor substrate layer 100 .

[0084] The doping concentration of the channel region 170 is lower than the doping concentration of the second source region 130 and lower than the doping concentration of the first source region 120. Since the doping concentration of the channel region 170 is relatively low, the conductivity type of the second source region 130 is not changed. Since the conductivity type of the ions implanted in the channel region 170 is the same as the conductivity type of the ions in the first source region 120, the conductivity type of the first source region 120 is not changed.

[0085] In one embodiment, the doping concentration of the first source region 120 is 5 to 500 times the doping concentration of the channel region 170 , for example, 5, 10, 20, 30, 50, 100, 150, 200, 300, or 500 times.

[0086] In one embodiment, the ion implantation process used to form the channel region 170 has an implantation direction perpendicular to the upper surface of the semiconductor substrate layer 100. During the ion implantation process to form the channel region 170, ions are also implanted into the second doped protective layer 150, without changing the conductivity type of the second doped protective layer 150. In FIG6 , during the ion implantation process to form the channel region 170, ions are not implanted into the first epitaxial protective layer 160 at the bottom of the trench 140.

[0087] When the semiconductor power device is forward-conducting, electrons pass from the second source region 130 through the channel region 170 and the first epitaxial protection layer 160 at the bottom of the channel region 170. Because the doping concentration of the first epitaxial protection layer 160 is greater than the doping concentration of the drift layer 110, the forward on-resistance is reduced.

[0088] 7 and 8 , after forming the protection unit, a gate structure is formed in the trench 140 .

[0089] 7 , a gate dielectric layer 181 is formed on the inner wall surface of the trench 140. Referring to FIG8 , after the gate dielectric layer 181 is formed, a gate electrode layer 182 is formed in the trench 140. The gate dielectric layer 181 is made of silicon oxide, and the gate electrode layer 182 is made of polysilicon.

[0090] In this embodiment, after the channel region 170 is formed, a gate structure is formed in the trench 140 .

[0091] 8 , an isolation layer 190 is formed on a surface of the gate structure facing away from the semiconductor substrate layer 100 . The isolation layer 190 also covers the first epitaxial protection layer 160 on the side of the gate structure.

[0092] The material of the isolation layer 190 includes silicon oxide.

[0093] 9 , after forming the isolation layer 190 , the first epitaxial protection layer 160 on the side of the isolation layer 190 is removed; a front electrode layer 191 is formed on the surfaces of the first source region 120 and the second source region 130 ; and a drain metal layer (not shown) is formed on the surface of the semiconductor substrate layer 100 facing away from the drift layer 110 .

[0094] Example 2

[0095] The difference between this embodiment and Embodiment 1 is that, referring to FIG11 , a third doped protective layer 192 is formed in the first epitaxial protective layer 160 at the bottom of the trench during the formation of the channel region 170. The conductivity type of the third doped protective layer 192 is opposite to that of the first epitaxial protective layer 160. The conductivity type of the third doped protective layer 192 is the same as that of the second doped protective layer 150.

[0096] The PN junction formed by the third doped protection layer 192 and the first epitaxial protection layer 160 can also protect the gate dielectric layer 181 in the bottom area of ​​the gate structure, alleviating the phenomenon of electric field concentration in the gate dielectric layer 181 in the bottom area of ​​the gate structure.

[0097] In one embodiment, the lateral width of the third doped protection layer 192 is less than the lateral width of the second doped protection layer 150. In other embodiments, the lateral width of the third doped protection layer is equal to the lateral width of the second doped protection layer 150. In other embodiments, the lateral width of the third doped protection layer is greater than the lateral width of the second doped protection layer.

[0098] The lateral width of the third doping protection layer 192 is parallel to the width of the gate structure. The lateral width of the second doping protection layer 150 is parallel to the width of the gate structure.

[0099] The other steps after forming the channel region 170 are the same as those in Example 1 and will not be described in detail.

[0100] Example 3

[0101] The difference between the preparation method of the semiconductor power device of this embodiment and the preparation method of the semiconductor power device of Examples 1 and 2 is that: before forming the first initial source region in the partial thickness of the drift layer 110, an initial current spreading layer is formed in the partial thickness of the drift layer 110; the step of forming the first initial source region in the partial thickness of the drift layer 110 is: forming the first initial source region in the initial current spreading layer, and the surface of the first initial source region facing the semiconductor substrate layer 100 is farther away from the semiconductor substrate layer 100 than the surface of the initial current spreading layer facing the semiconductor substrate layer 100.

[0102] In the process of forming a trench extending from the surface of the drift layer 110 on the side facing away from the semiconductor substrate 100 to a partial thickness of the drift layer 110, the trench also penetrates the initial current spreading layer, and the initial current spreading layer on the side of the trench forms a current spreading layer. The current spreading layer is located in the drift layer 110 on the side of the first source region 120 facing the semiconductor substrate layer 100 and is in contact with the first source region 120. The conductivity type of the current spreading layer 112 is opposite to the conductivity type of the first source region 120, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer 110.

[0103] Taking the current spreading layer 112 in FIG. 10 as an example, the current spreading layer 112 is located in the drift layer 110 on the side of the first source region 120 facing the semiconductor substrate layer 100 and is in contact with the first source region 120. The conductivity type of the current spreading layer 112 is opposite to that of the first source region 120, and the doping concentration of the current spreading layer 112 is greater than the doping concentration of the drift layer 110. It should be noted that the step of forming an initial current spreading layer can also be provided based on Example 2.

[0104] The other steps after forming the channel region 170 are the same as those in Example 3 and will not be described in detail.

[0105] After the second doping protection layer 150 and the first epitaxial protection layer 160 are formed, the current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the trench.

[0106] In one embodiment, the current spreading layer 112 is spaced apart from the second doped protection layer 150, which has the advantage of reducing the forward on-resistance. In other embodiments, the current spreading layer and the second doped protection layer may also be in contact.

[0107] Regarding the steps after the grooves are formed, refer to Examples 1 and 2 and will not be described in detail.

[0108] Example 4

[0109] The difference between this embodiment and embodiment 1 is that after the trench is formed, a second doping protection layer is formed in the drift layer, and the second doping protection layer includes a first sub-doping region and a second sub-doping region arranged at intervals, the first sub-doping region surrounds a portion of the bottom surface of the trench and a portion of the side wall of the trench on one side along the width direction, and the second sub-doping region surrounds a portion of the bottom surface of the trench and a portion of the side wall of the trench on the other side along the width direction.

[0110] The method for manufacturing the semiconductor power device of this embodiment will be described in detail below with reference to FIG. 12 to FIG. 15 .

[0111] Referring to Figure 12, Figure 12 is a schematic diagram based on Figure 3. After the trench 140 is formed, a second doping protection layer is formed in the drift layer 110. The second doping protection layer includes a first sub-doping region 1501 and a second sub-doping region 1502 spaced apart. The first sub-doping region 1501 surrounds a portion of the bottom surface of the trench 140 and a portion of the side wall of the trench 140 on one side along the width direction, and the second sub-doping region 1502 surrounds a portion of the bottom surface of the trench 140 and a portion of the side wall of the trench 140 on the other side along the width direction.

[0112] The ion implantation process for forming the first sub-doping region 1501 is a tilted ion implantation process, and the ion implantation process for forming the second sub-doping region 1502 is a tilted ion implantation process.

[0113] The second sub-doping region 1502 is formed after the first sub-doping region 1501 is formed, or the first sub-doping region 1501 is formed after the second sub-doping region 1502 is formed.

[0114] 13 , after forming the second doping protection layer, a first epitaxial protection layer 160 is epitaxially formed on the inner wall surface of the trench 140. The description of this step is similar to that of embodiment 1 and will not be described in detail.

[0115] 14 , a channel region 170 is formed in the first epitaxial protection layer 160 on the sidewall surface of the trench 140. This step is described with reference to Embodiment 1 and will not be described in detail.

[0116] Referring to FIG15 , after forming the protection unit, a gate structure is formed in the trench 140 . An isolation layer 190 is formed on the surface of the gate structure facing away from the semiconductor substrate layer 100 . The isolation layer 190 also covers the first epitaxial protection layer 160 on the side of the gate structure. After forming the isolation layer 190 , the first epitaxial protection layer 160 on the side of the isolation layer 190 is removed. A front electrode layer 191 is formed on the surfaces of the first source region 120 and the second source region 130 . A drain metal layer (not shown) is formed on the surface of the semiconductor substrate layer 100 facing away from the drift layer 110 . The description of this step is similar to that of Example 1 and will not be repeated in detail.

[0117] The first sub-doping region 1501 surrounds part of the bottom surface of the gate structure and part of the side wall of the gate structure along one side of the width direction, and the second sub-doping region 1502 surrounds part of the bottom surface of the gate structure and part of the side wall of the gate structure along the other side of the width direction.

[0118] Example 5

[0119] The difference between this embodiment and Embodiment 4 is that, referring to FIG16 , a third doped protective layer 192 is formed in the first epitaxial protective layer 160 at the bottom of the trench during the formation of the channel region 170. The conductivity type of the third doped protective layer 192 is opposite to that of the first epitaxial protective layer 160. The conductivity type of the third doped protective layer 192 is the same as that of the second doped protective layer.

[0120] The PN junction formed by the third doped protection layer 192 and the first epitaxial protection layer 160 can also protect the gate dielectric layer 181 in the bottom area of ​​the gate structure, alleviating the phenomenon of electric field concentration in the gate dielectric layer 181 in the bottom area of ​​the gate structure.

[0121] In one embodiment, the lateral width of the third doped protective layer 192 is less than the lateral width of the second doped protective layer 150. In other embodiments, the lateral width of the third doped protective layer is equal to the lateral width of the second doped protective layer 150. In other embodiments, the lateral width of the third doped protective layer is greater than the lateral width of the second doped protective layer. The lateral width of the third doped protective layer 192 is parallel to the width direction of the gate structure. The lateral width of the second doped protective layer 150 is parallel to the width direction of the gate structure.

[0122] In one embodiment, the third doping protection layer 192 is laterally spaced from the first sub-doping region 1501 in the width direction of the trench, and the third doping protection layer 192 is laterally spaced from the second sub-doping region 1502 in the width direction of the trench. In other embodiments, the orthographic projections of the third doping protection layer 192 and the first sub-doping region 1501 on the surface of the semiconductor substrate layer have an overlapping area, and / or the orthographic projections of the third doping protection layer 192 and the second sub-doping region 1502 on the surface of the semiconductor substrate layer have an overlapping area.

[0123] When the orthographic projections of the third doping protection layer 192 and the first sub-doping region 1501 on the surface of the semiconductor substrate layer have an overlapping area, and / or the orthographic projections of the third doping protection layer 192 and the second sub-doping region 1502 on the surface of the semiconductor substrate layer have an overlapping area, preferably, a plurality of first sub-doping regions 1501 are arranged at intervals along the length direction of the groove, and a plurality of second sub-doping regions 1502 are arranged at intervals along the length direction of the groove.

[0124] The other steps after forming the channel region 170 are the same as those in the fourth embodiment and will not be described in detail.

[0125] Example 6

[0126] This embodiment differs from Embodiment 4 and Embodiment 5 in that an initial current spreading layer is formed in the partial-thickness drift layer 110 before forming the first initial source region in the partial-thickness drift layer 110. The step of forming the first initial source region in the partial-thickness drift layer 110 includes forming the first initial source region in the initial current spreading layer, with the surface of the first initial source region facing the semiconductor substrate layer 100 being farther away from the semiconductor substrate layer 100 than the surface of the initial current spreading layer facing the semiconductor substrate layer 100.

[0127] In the process of forming a trench extending from the surface of the drift layer 110 on the side facing away from the semiconductor substrate 100 to a partial thickness of the drift layer 110, the trench also penetrates the initial current spreading layer, and the initial current spreading layer on the side of the trench forms a current spreading layer. The current spreading layer is located in the drift layer 110 on the side of the first source region 120 facing the semiconductor substrate layer 100 and is in contact with the first source region 120. The conductivity type of the current spreading layer 112 is opposite to the conductivity type of the first source region 120, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer 110.

[0128] After the second doped protection layer and the first epitaxial protection layer 160 are formed, the current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the trench.

[0129] The current spreading layer and the second doped protective layer are spaced apart from each other, or the current spreading layer is in contact with the second doped protective layer.

[0130] The other steps after forming the channel region 170 are similar to those in Embodiment 4 and Embodiment 5 and will not be described in detail.

[0131] Example 7

[0132] The following describes in detail the method for manufacturing the semiconductor power device of this embodiment with reference to FIG. 17 to FIG. 25 .

[0133] 17 , a drift layer 110 is formed on one side of a semiconductor substrate layer 100 ; a first initial source region 1200 is formed in a partial thickness of the drift layer 110 , wherein the conductivity type of the first initial source region 1200 is opposite to that of the drift layer 110 .

[0134] The description of the drift layer 110 and the first initial source region 1200 refers to that of the first embodiment.

[0135] 18 , a trench 140 is formed in the drift layer 110 , extending from a surface of the drift layer 110 facing away from the semiconductor substrate 100 to a portion of the thickness of the drift layer 110 .

[0136] The process of forming the trench 140 is as follows: the trench 140 is formed in the first initial source region 1200 and a portion of the drift layer 110 at the bottom of the first initial source region 1200, and the first initial source regions 1200 on both sides of the trench 140 form the first source region 120. The description of the first source region 120 is as described in Example 1.

[0137] The process of forming the trench 140 includes an etching process. The process of forming the trench 140 is similar to that of the first embodiment.

[0138] 19 , a second doped protection layer 150 is formed in the drift layer 110 at the bottom of the trench 140. The process of forming the second doped protection layer 150 includes an ion implantation process.

[0139] The conductivity type of the second doped protective layer 150 is opposite to the conductivity type of the drift layer 110. In one embodiment, the lateral width of the second doped protective layer 150 is equal to the lateral width of the trench 140. After the gate structure is subsequently formed, the lateral width of the second doped protective layer 150 is equal to the width of the gate structure. In other embodiments, the lateral width of the second doped protective layer is less than the lateral width of the trench 140. After the gate structure is subsequently formed, the lateral width of the second doped protective layer 150 is less than the width of the gate structure. In other embodiments, the lateral width of the second doped protective layer is greater than the lateral width of the trench 140. After the gate structure is subsequently formed, the lateral width of the second doped protective layer 150 is greater than the width of the gate structure.

[0140] 20 , after the second doping protection layer 150 is formed, a first epitaxial protection layer 160 is epitaxially formed on the inner wall surface of the trench 140 .

[0141] Specifically, a first epitaxial protection layer 160 is epitaxially formed on the sidewall surfaces and bottom surface of the trench 140. The first epitaxial protection layer 160 is also formed on the surface of the first source region 120 facing away from the semiconductor substrate layer 100. After the gate structure is subsequently formed, the first epitaxial protection layer 160 on the surface of the first source region 120 facing away from the semiconductor substrate layer 100 is removed.

[0142] After the first epitaxial protection layer 160 is formed, the first source region 120 contacts the sidewall of the first epitaxial protection layer 160 that is laterally away from the trench 140 .

[0143] The description of the first epitaxial protection layer 160 refers to the description of the first embodiment.

[0144] 21 , a channel region 170a is formed in the first epitaxial protection layer 160 on the sidewall surface of the trench 140. The channel region 170a is formed by an ion implantation process.

[0145] Specifically, before the gate structure is subsequently formed, the channel region 170 a is formed.

[0146] In one embodiment, the ion implantation process used to form the channel region 170a has an angle greater than zero relative to the sidewall surface of the trench 140, i.e., an angled ion implantation process is used. During the implantation of the channel region 170a, ions are implanted into the first epitaxial protection layer 160 above the channel region 170a and the first epitaxial protection layer 160 on the surface of the first source region 120, thereby forming a dummy channel region in the first epitaxial protection layer 160 above the channel region 170a and the first epitaxial protection layer 160 on the surface of the first source region 120. Because the channel region 170a is formed using an angled ion implantation process, the channel region 170a is formed at a lower implantation energy. By adjusting the implantation angle, the lower surface of the channel region 170a is brought closer to the bottom surface of the trench 140. This prevents the length of the channel region 170a from being excessively shortened, even if the depth of the second source region is subsequently increased. The length of the channel region 170a is perpendicular to the upper surface of the semiconductor substrate layer 100. In addition, the bottom of the trench 140 is not affected by the tilted ion implantation process, and the position of the channel region 170 a does not need to be affected by controlling the implantation depth at the bottom of the trench.

[0147] In another embodiment, the ion implantation process used to form the channel region 170a has an implantation direction perpendicular to the upper surface of the semiconductor substrate layer 100. During the ion implantation process to form the channel region 170a, ions are also implanted into the second doped protective layer 150, without changing the conductivity type of the second doped protective layer 150. In FIG. 21 , during the ion implantation process to form the channel region 170a, ions are not implanted into the first epitaxial protective layer 160 at the bottom of the trench 140.

[0148] The doping concentration of the channel region 170a is lower than the doping concentration of the second source region 130 and lower than the doping concentration of the first source region 120. Since the conductivity type of the ions implanted in the channel region 170a is the same as that of the ions in the first source region 120, the conductivity type of the first source region 120 is not changed.

[0149] 22, after forming the channel region 170a, a second source region 130a is formed in a portion of the first source region 120 and in the first epitaxial protection layer 160 on the side of the channel region 170a facing away from the semiconductor substrate layer 100. The second source region 130a is formed by ion implantation.

[0150] It should be noted that the method for manufacturing a semiconductor power device further includes: forming a sacrificial layer 200 in the trench 140 before forming the second source region 130a, and forming the second source region 130a after forming the sacrificial layer 200. The material of the sacrificial layer 200 includes silicon oxide.

[0151] In this embodiment, the second source region 130a can control the length and doping concentration of the channel region. By controlling the implantation depth during the ion implantation process used to form the second source region 130a, the position of the upper surface of the channel region 170a is determined. During the ion implantation process of the second source region 130a, regions located near the channel region 170a can neutralize some of the ions in the channel region 170a, thereby adjusting the doping concentration of the channel region 170a.

[0152] It should be noted that the dummy channel region in the first epitaxial protection layer 160 above the channel region 170 a and part of the dummy channel region in the first epitaxial protection layer 160 on the surface of the first source region 120 are neutralized by the ions implanted by the second source region 130 a .

[0153] Referring to FIG. 23 , after forming the protection unit, a gate structure is formed in the trench 140. The gate structure formation process includes: forming a gate dielectric layer 181 on the inner wall surface of the trench 140; after forming the gate dielectric layer 181, forming a gate electrode layer 182 in the trench 140. The material of the gate dielectric layer 181 includes silicon oxide. The material of the gate electrode layer 182 includes polycrystalline silicon.

[0154] After removing the sacrificial layer 200 , a gate structure is formed in the trench 140 .

[0155] In this embodiment, the method for manufacturing a semiconductor power device further includes forming an isolation layer 190 on a surface of the gate structure facing away from the semiconductor substrate layer 100. The isolation layer 190 also covers a portion of the second source region 130a on the side of the gate structure. The isolation layer 190 is made of silicon oxide.

[0156] Referring to Figure 24, after the isolation layer 190 is formed, part of the second source region 130a and the pseudo channel region on the side of the isolation layer 190 are removed; a front electrode layer 191 is formed on the surface of the first source region 120 and the second source region 130; and a drain metal layer (not shown) is formed on the surface of the side of the semiconductor substrate layer 100 away from the drift layer 110.

[0157] Example 8

[0158] The difference between this embodiment and Embodiment 7 is that, referring to FIG25 , during the formation of the channel region 170 a, a third doped protective layer 192 is formed in the first epitaxial protective layer 160 at the bottom of the trench. The conductivity type of the third doped protective layer 192 is opposite to that of the first epitaxial protective layer 160. The conductivity type of the third doped protective layer 192 is the same as that of the second doped protective layer 150.

[0159] In one embodiment, the third doping protection layer 192 is described with reference to Embodiment 2.

[0160] The other steps after forming the channel region 170a are the same as those in Example 7 and will not be described in detail.

[0161] Example 9

[0162] The method for fabricating a semiconductor power device in this embodiment differs from the methods for fabricating semiconductor power devices in Embodiments 7 and 8 in that, before forming the first initial source region in the partial-thickness drift layer 110, an initial current spreading layer is formed in the partial-thickness drift layer 110. The step of forming the first initial source region in the partial-thickness drift layer 110 comprises forming the first initial source region in the initial current spreading layer, with the surface of the first initial source region facing the semiconductor substrate layer 100 being farther away from the semiconductor substrate layer 100 than the surface of the initial current spreading layer facing the semiconductor substrate layer 100.

[0163] In the process of forming a trench extending from the surface of the drift layer 110 on the side facing away from the semiconductor substrate 100 to a partial thickness of the drift layer 110, the trench also penetrates the initial current spreading layer, and the initial current spreading layer on the side of the trench forms a current spreading layer. The current spreading layer is located in the drift layer 110 on the side of the first source region 120 facing the semiconductor substrate layer 100 and is in contact with the first source region 120. The conductivity type of the current spreading layer is opposite to the conductivity type of the first source region 120, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer 110.

[0164] The steps after forming the grooves are the same as those in Example 7 and Example 8 and will not be described in detail.

[0165] After the second doping protection layer 150 and the first epitaxial protection layer 160 are formed, the current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the trench.

[0166] The current spreading layer is spaced apart from the second doped protection layer 150. In other embodiments, the current spreading layer and the second doped protection layer may also be in contact with each other.

[0167] Example 10

[0168] The difference between this embodiment and embodiment 7 is that after the trench is formed, a second doping protection layer is formed in the drift layer, and the second doping protection layer includes a first sub-doping region and a second sub-doping region that are spaced apart, the first sub-doping region surrounds a portion of the bottom surface of the trench and a portion of the side wall of the trench on one side along the width direction, and the second sub-doping region surrounds a portion of the bottom surface of the trench and a portion of the side wall of the trench on the other side along the width direction.

[0169] The following describes in detail the method for manufacturing the semiconductor power device of this embodiment in conjunction with Figures 26 to 31.

[0170] Referring to Figure 26, Figure 26 is a schematic diagram based on Figure 18. After the groove 140 is formed, a second doping protection layer is formed in the drift layer 110. The second doping protection layer includes a first sub-doping region 1501 and a second sub-doping region 1502 arranged at intervals. The first sub-doping region 1501 surrounds a portion of the bottom surface of the groove 140 and a portion of the side wall of the groove 140 on one side along the width direction, and the second sub-doping region 1502 surrounds a portion of the bottom surface of the groove 140 and a portion of the side wall of the other side of the groove 140 along the width direction.

[0171] The ion implantation process for forming the first sub-doping region 1501 is a tilted ion implantation process, and the ion implantation process for forming the second sub-doping region 1502 is a tilted ion implantation process. The second sub-doping region 1502 is formed after the first sub-doping region 1501 is formed, or the first sub-doping region 1501 is formed after the second sub-doping region 1502 is formed.

[0172] For the description of the first sub-doping region 1501 and the second sub-doping region 1502 , refer to Example 4.

[0173] 27 , after forming the second doping protection layer, a first epitaxial protection layer 160 is epitaxially formed on the inner wall surface of the trench 140. The description of this step is similar to that of Embodiment 7 and will not be described in detail.

[0174] 28 , a channel region 170 a is formed in the first epitaxial protection layer 160 on the sidewall surface of the trench 140. This step is described with reference to Embodiment 7 and will not be described in detail.

[0175] 29 , after forming the channel region 170a, a second source region 130a is formed in a portion of the first source region 120 and in the first epitaxial protection layer 160 on the side of the channel region 170a facing away from the semiconductor substrate layer 100. This step is described with reference to Example 7 and will not be described in detail.

[0176] It should be noted that the method for manufacturing a semiconductor power device further includes: forming a sacrificial layer 200 in the trench 140 before forming the second source region 130 a , and forming the second source region 130 a after forming the sacrificial layer 200 .

[0177] 30 , after forming the protection unit, a gate structure is formed in the trench 140 . The process of forming the gate structure includes: forming a gate dielectric layer 181 on the inner wall surface of the trench 140 ; ​​and forming a gate electrode layer 182 in the trench 140 after forming the gate dielectric layer 181 .

[0178] After removing the sacrificial layer 200 , a gate structure is formed in the trench 140 .

[0179] The first sub-doping region 1501 surrounds part of the bottom surface of the gate structure and part of the side wall of the gate structure on one side along the width direction, and the second sub-doping region 1502 surrounds part of the bottom surface of the gate structure and part of the side wall of the gate structure on the other side along the width direction.

[0180] In this embodiment, the method for fabricating a semiconductor power device further includes forming an isolation layer 190 on a surface of the gate structure facing away from the semiconductor substrate layer 100. The isolation layer 190 also covers a portion of the second source region 130a on the side of the gate structure. The formation of the isolation layer 190 is described in Example 7 and will not be further elaborated.

[0181] Referring to Figure 31, after the isolation layer 190 is formed, part of the second source region 130a and the pseudo channel region on the side of the isolation layer 190 are removed; a front electrode layer 191 is formed on the surface of the first source region 120 and the second source region 130; and a drain metal layer (not shown) is formed on the surface of the side of the semiconductor substrate layer 100 away from the drift layer 110.

[0182] Example 11

[0183] The difference between this embodiment and embodiment 10 is that, referring to FIG32 , during the process of forming the channel region 170 a, a third doped protective layer 192 is formed in the first epitaxial protective layer 160 at the bottom of the trench. The conductivity type of the third doped protective layer 192 is opposite to that of the first epitaxial protective layer 160. The conductivity type of the third doped protective layer 192 is the same as that of the second doped protective layer.

[0184] The description of the third doping protection layer 192 refers to the aforementioned embodiment.

[0185] Regarding the positional relationship between the third doping protection layer 192 and the first sub-doping region 1501 , and the positional relationship between the third doping protection layer 192 and the second sub-doping region 1502 , refer to Example 5.

[0186] The other steps after forming the channel region 170a are the same as those in Example 10 and will not be described in detail.

[0187] Example 12

[0188] This embodiment differs from Embodiment 10 and Embodiment 11 in that an initial current spreading layer is formed in the partial-thickness drift layer 110 before forming the first initial source region in the partial-thickness drift layer 110. The step of forming the first initial source region in the partial-thickness drift layer 110 includes forming the first initial source region in the initial current spreading layer, with the surface of the first initial source region facing the semiconductor substrate layer 100 being farther away from the semiconductor substrate layer 100 than the surface of the initial current spreading layer facing the semiconductor substrate layer 100. In the process of forming a trench extending from the surface of the drift layer 110 on the side facing away from the semiconductor substrate 100 to a partial thickness of the drift layer 110, the trench also penetrates the initial current spreading layer, and the initial current spreading layer on the side of the trench forms a current spreading layer. The current spreading layer is located in the drift layer 110 on the side of the first source region 120 facing the semiconductor substrate layer 100 and is in contact with the first source region 120. The conductivity type of the current spreading layer 112 is opposite to the conductivity type of the first source region 120, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer 110.

[0189] The other steps after forming the channel region 170a refer to Embodiment 10 and Embodiment 11 and are not described in detail.

[0190] After the second doped protection layer and the first epitaxial protection layer 160 are formed, the current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the trench.

[0191] The current spreading layer and the second doped protective layer are spaced apart. The current spreading layer and the second doped protective layer can also be spaced apart.

[0192] Example 13

[0193] This embodiment provides a semiconductor power device. Referring to FIG9 , the semiconductor power device includes: a semiconductor substrate layer 100; a drift layer 110 located on one side of the semiconductor substrate layer 100; a gate structure located in the drift layer 110; and a protection unit located in the drift layer 110. The protection unit includes: a first epitaxial protection layer 160 surrounding the sidewalls and bottom surface of the gate structure. The conductivity type of the first epitaxial protection layer 160 is the same as that of the drift layer 110, and the doping concentration of the first epitaxial protection layer 160 is greater than that of the drift layer 110; and a second doped protection layer 150 located on the side of the first epitaxial protection layer 160 facing the semiconductor substrate layer 100 and in contact with the first epitaxial protection layer 160. The conductivity type of the second doped protection layer 150 is opposite to that of the first epitaxial protection layer 160, and the second doped protection layer 150 and the first epitaxial protection layer 160 form a PN junction. The semiconductor power device also includes: a channel region 170 located in the first epitaxial protection layer 160 on the sidewalls of the gate structure.

[0194] In this embodiment, the second doped protective layer 150 and the first epitaxial protective layer 160 form a PN junction. In this way, during the reverse withstand voltage process, the PN junction formed by the second doped protective layer 150 and the first epitaxial protective layer 160 is depleted, and part of the electric field peak is transferred to the junction of the PN junction, and the PN junction protects the gate dielectric layer at the bottom of the gate structure. The problem of electric field concentration at the bottom of the gate structure during the reverse withstand voltage state is alleviated. The channel region is arranged in the first epitaxial protective layer 160 on the side wall of the gate structure, so the doping concentration of the channel region and the length of the channel region can be well controlled, so that the threshold voltage and the channel resistance can be independently regulated. Secondly, the doping concentration of the first epitaxial protective layer 160 is greater than the doping concentration of the drift layer 110, so the resistance of the first epitaxial protective layer 160 is small when the semiconductor power device is forward-conducted, which reduces the forward conduction resistance.

[0195] In this embodiment, the new generation of SiC-based semiconductor power devices represented by SiC have higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance compared to Si-based semiconductor power devices, and are therefore considered to be a new hope in the field of power conversion. It should be noted that the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, there is no restriction on the conductivity type of the semiconductor substrate layer 100.

[0196] In one embodiment, the conductivity type of the drift layer 110 is the same as that of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is lower than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the drift layer is made of silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions.

[0197] In this embodiment, the semiconductor power device further includes: first source regions 120, located in the drift layer 110 on both sides of the gate structure in the width direction. The conductivity type of the first source regions 120 is opposite to the conductivity type of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the first source regions 120 is P-type.

[0198] In one embodiment, the doping concentration of the first source region 120 is 5 to 500 times the doping concentration of the channel region 170 .

[0199] The doping concentration of the first source region 120 is higher than that of the well region in the prior art. This causes depletion in the first source region 120 and the drift layer 110 at its base. Part of the electric field peak is transferred to the interface between the first source region 120 and the drift layer 110, protecting the gate dielectric layer in the sidewall region of the gate structure. Furthermore, depletion of the first epitaxial protection layer 160 in the first source region 120 and on the sidewalls of the gate structure allows for sufficient depletion of the first epitaxial protection layer 160 to protect the gate dielectric layer.

[0200] The implantation of the first source region 120 and the implantation of the channel region 170 are performed in separate steps. The implantation of the first source region 120 does not affect the doping concentration of the channel region 170. The ion implantation dose in the channel region 170 affects the doping concentration of the channel region 170 and controls the threshold voltage of the device. The implantation energy in the channel region 170 controls the length of the channel region 170 and thus the channel resistance.

[0201] Even if the doping concentration of the first source region 120 is relatively high, it will not affect the doping concentration of the channel region 170 and will not affect the threshold voltage of the device.

[0202] In this embodiment, the semiconductor power device further includes a second source region 130 located in a portion of the first source region 120. The conductivity type of the second source region 130 is opposite to that of the first source region 120. The surface of the second source region 130 facing the semiconductor substrate layer 100 is further away from the semiconductor substrate layer 100 than the surface of the first source region 120 facing the semiconductor substrate layer 100.

[0203] In one embodiment, the second source region 130 contacts a sidewall of the first epitaxial protection layer 160 that is laterally away from the gate structure. That is, the first epitaxial protection layer 160 separates the second source region 130 from the gate structure.

[0204] In this embodiment, the semiconductor power device further includes a drain metal layer located on a surface of the semiconductor substrate layer 100 facing away from the drift layer 110 .

[0205] The surface of the first source region 120 facing the semiconductor substrate layer 100 is farther away from the semiconductor substrate layer 100 than the surface of the second doped protection layer 150 facing away from the semiconductor substrate layer 100. During forward conduction, electrons travel from the second source region 130 through the channel region 170, and then from the first epitaxial protection layer 160 at the bottom of the channel region 170 through the drift layer 110 at the bottom of the first source region 120, until they reach the drain metal layer.

[0206] In one embodiment, the longitudinal distance from the surface of the first source region 120 facing the semiconductor substrate layer 100 to the surface of the second doping protection layer 150 facing away from the semiconductor substrate layer 100 is 0.1 micron to 1.5 microns, for example 0.1 micron, 0.5 micron, 1 micron or 1.5 microns.

[0207] Furthermore, the doping concentration of the channel region 170 is lower than the doping concentration of the first source region 120 , so that the channel region 170 is more easily inverted and the channel resistance is smaller.

[0208] The surface of the channel region 170 facing away from the semiconductor substrate layer 100 is spaced from the surface of the drift layer 110 facing away from the semiconductor substrate layer 100, and the surface of the channel region 170 facing the semiconductor substrate layer 100 is spaced from the surface of the gate structure facing the semiconductor substrate layer 100. The surface of the channel region 170 facing away from the semiconductor substrate layer 100 is closer to the semiconductor substrate layer 100 than the surface of the second source region 130 facing away from the semiconductor substrate layer 100.

[0209] In one embodiment, the channel region 170, which faces away from the surface of the semiconductor substrate layer 100, is closer to the semiconductor substrate layer 100 than the surface of the second source region 130 facing the semiconductor substrate layer 100. In other embodiments, the channel region 170, which faces away from the surface of the semiconductor substrate layer 100, is flush with the surface of the second source region 130 facing the semiconductor substrate layer 100. In other embodiments, the channel region 170, which faces away from the surface of the semiconductor substrate layer 100, is farther away from the semiconductor substrate layer 100 than the surface of the second source region 130 facing the semiconductor substrate layer 100.

[0210] In one embodiment, a dimension of the second doping protection layer 150 along the width direction of the gate structure is smaller than, equal to, or larger than the width of the bottom surface of the gate structure.

[0211] In one embodiment, a plurality of second doping protection layers 150 are spaced apart along the length direction of the gate structure. Alternatively, the second doping protection layer 150 is continuous along the length direction of the gate structure.

[0212] In this embodiment, the gate structure includes a gate dielectric layer 181 and a gate electrode layer 182. The gate dielectric layer 181 is located on the surface of the gate electrode layer 182 facing the semiconductor substrate layer 100 (that is, the bottom surface of the gate electrode layer 182) and the sidewalls of the gate electrode layer 182. The material of the gate dielectric layer 181 includes silicon oxide, and the material of the gate electrode layer 182 includes polycrystalline silicon.

[0213] In one embodiment, the doping concentration of the first epitaxial protection layer 160 is 2 to 10 times the doping concentration of the drift layer 110, for example, 2 times, 5 times, or 10 times. In one embodiment, the doping concentration of the first epitaxial protection layer 160 is 1E16 atom / cm 3 ~2E17atom / cm 3 .

[0214] In one embodiment, the doping concentration of the second epitaxial protective layer 150 is greater than the doping concentration of the first epitaxial protective layer 160. Since the area of ​​the first epitaxial protective layer 160 is larger than that of the second epitaxial protective layer 150, the doping concentration of the second epitaxial protective layer 150 needs to be greater than the doping concentration of the first epitaxial protective layer 160 to achieve charge balance between the first epitaxial protective layer 160 and the second doped protective layer 150, thereby ensuring more complete depletion between the first epitaxial protective layer 160 and the second doped protective layer 150. In one embodiment, the thickness of the first epitaxial protective layer is 10 nanometers to 1 micron.

[0215] In one embodiment, the thickness of the second doping protection layer 150 is 10 nanometers to 1 micrometer. In one embodiment, the thickness of the first epitaxial protection layer 160 is 10 nanometers to 1 micrometer.

[0216] Example 14

[0217] This embodiment provides a semiconductor power device. Referring to Figure 11, the difference between this embodiment and embodiment 13 corresponding to Figure 9 is that the semiconductor power device also includes: a third doped protective layer 192, located in the first epitaxial protective layer 160 at the bottom of the gate structure, and the conductivity type of the third doped protective layer 192 is the same as the conductivity type of the second doped protective layer 150.

[0218] The doping concentration of the third doping protection layer 192 is the same as the doping concentration of the second doping protection layer 150 , or the doping concentration of the third doping protection layer 192 is less than the doping concentration of the second doping protection layer 150 , or the doping concentration of the third doping protection layer 192 is greater than the doping concentration of the second doping protection layer 150 .

[0219] The third doping protection layer 192 contacts the second doping protection layer 150. In other embodiments, the third doping protection layer 192 is spaced apart from the second doping protection layer 150.

[0220] In one embodiment, the lateral width of the third doped protection layer 192 is less than the lateral width of the second doped protection layer 150. In other embodiments, the lateral width of the third doped protection layer is equal to the lateral width of the second doped protection layer 150. In other embodiments, the lateral width of the third doped protection layer is greater than the lateral width of the second doped protection layer.

[0221] The doping concentration of the third doping protection layer 192 is greater than the doping concentration of the drift layer 110 .

[0222] In one embodiment, the lateral widths of the third doping protection layer 192 and the second doping protection layer 150 are both smaller than the width of the gate structure.

[0223] The lateral width of the third doping protection layer 192 is parallel to the width of the gate structure. The lateral width of the second doping protection layer 150 is parallel to the width of the gate structure.

[0224] The rest of the contents of this embodiment are the same as those of Embodiment 13 and will not be described in detail.

[0225] Example 15

[0226] This embodiment provides a semiconductor power device. The semiconductor power device of this embodiment differs from the semiconductor power devices of Embodiments 13 and 14 in that the semiconductor power device further includes a current spreading layer located in the drift layer 110 on the side of the first source region 120 facing the semiconductor substrate layer 100 and on the side of the gate structure. The current spreading layer contacts the first source region 120 and the first epitaxial protection layer 160 on the sidewalls of the gate structure, respectively. The conductivity type of the current spreading layer is opposite to that of the first source region 120, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer 110.

[0227] The current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the gate structure.

[0228] The current spreading layer is spaced apart from the second doping protection layer 150 . The current spreading layer may also be in contact with the second doping protection layer 150 .

[0229] For example, a current spreading layer 112 is provided in reference to Figure 10. It should be noted that a current spreading layer can also be provided on the basis of the fourteenth embodiment.

[0230] For other contents of this embodiment, please refer to Examples 13 and 14 and will not be described in detail.

[0231] Example 16

[0232] This embodiment provides a semiconductor power device. Referring to Figure 15, the difference between this embodiment and embodiment 13 corresponding to Figure 9 is that the second doping protection layer includes a first sub-doping region 1501 and a second sub-doping region 1502 arranged at intervals, and the first sub-doping region 1501 surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on one side along the width direction, and the second sub-doping region 1502 surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the other side of the gate structure along the width direction.

[0233] The other contents of this embodiment that are the same as those of Example 13 will not be described in detail.

[0234] Example 17

[0235] This embodiment provides a semiconductor power device. The difference between the semiconductor power device of this embodiment and the semiconductor power device of Example 16 is that: referring to Figure 16, the semiconductor power device also includes: a third doped protective layer 192, located in the first epitaxial protective layer 160 at the bottom of the gate structure, and the conductivity type of the third doped protective layer 192 is the same as the conductivity type of the second doped protective layer 150.

[0236] The description of the third doping protection layer 192 refers to the contents of the aforementioned embodiment and will not be described in detail again.

[0237] In one embodiment, the third doping protection layer 192 is laterally spaced from the first sub-doping region 1501 in the width direction of the gate structure, and the third doping protection layer 192 is laterally spaced from the second sub-doping region 1502 in the width direction of the gate structure. In other embodiments, the orthographic projections of the third doping protection layer 192 and the first sub-doping region 1501 on the surface of the semiconductor substrate layer have an overlapping area, and / or the orthographic projections of the third doping protection layer 192 and the second sub-doping region 1502 on the surface of the semiconductor substrate layer have an overlapping area.

[0238] When the orthographic projections of the third doping protection layer 192 and the first sub-doping region 1501 on the surface of the semiconductor substrate layer have an overlapping area, and / or the orthographic projections of the third doping protection layer 192 and the second sub-doping region 1502 on the surface of the semiconductor substrate layer have an overlapping area, preferably, a plurality of first sub-doping regions 1501 are arranged at intervals along the length direction of the gate structure, and a plurality of second sub-doping regions 1502 are arranged at intervals along the length direction of the gate structure.

[0239] The other contents of this embodiment that are the same as those of Example 16 will not be described in detail.

[0240] Example 18

[0241] This embodiment provides a semiconductor power device. The semiconductor power device of this embodiment differs from the semiconductor power devices of Embodiments 16 and 17 in that the semiconductor power device further includes a current spreading layer located on the side of the drift layer 110 facing the semiconductor substrate layer 100 from the first source region 120 and lateral to the gate structure. The current spreading layer contacts the first source region 120 and the first epitaxial protection layer 160 on the sidewalls of the gate structure, respectively. The conductivity type of the current spreading layer is opposite to that of the first source region 120, and the doping concentration of the current spreading layer is greater than the doping concentration of the drift layer 110.

[0242] The current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the gate structure.

[0243] The current spreading layer is spaced apart from the second doping protection layer 150 . The current spreading layer may also be in contact with the second doping protection layer 150 .

[0244] For other contents of this embodiment, please refer to Example 16 and Example 17 and will not be described in detail.

[0245] Example 19

[0246] This embodiment provides a semiconductor power device. Referring to FIG. 24 , the semiconductor power device of this embodiment differs from that of Example 13 in that a second source region 130a is located in a portion of the first source region 120 and further extends into the first epitaxial protection layer 160 on the side of the channel region 170a facing away from the semiconductor substrate layer 100. The conductivity type of the second source region 130a is opposite to that of the first source region 120.

[0247] The second source region 130a is in contact with the channel region 170a. Specifically, the side surface of the second source region 130a facing the semiconductor substrate layer 100 is in contact with the side surface of the channel region 170a facing away from the semiconductor substrate layer 100. In this way, when forward conduction occurs, electrons directly enter the channel region 170a from the second source region 130a, thereby reducing the forward conduction resistance.

[0248] The rest of the contents of this embodiment are the same as those of Example 13 and will not be described in detail.

[0249] Example 20

[0250] This embodiment provides a semiconductor power device. Referring to Figure 25, the difference between the semiconductor power device of this embodiment and Example 19 is that the semiconductor power device also includes: a third doped protective layer 192, located in the first epitaxial protective layer 160 at the bottom of the gate structure, and the conductivity type of the third doped protective layer 192 is the same as the conductivity type of the second doped protective layer 150.

[0251] The description of the third doping protection layer 192 refers to the contents of the aforementioned embodiment.

[0252] The rest of the contents of this embodiment are the same as those of Embodiment 19 and will not be described in detail.

[0253] Example 21

[0254] This embodiment provides a semiconductor power device. The semiconductor power device of this embodiment differs from the semiconductor power devices of Embodiments 19 and 20 in that the semiconductor power device further includes a current spreading layer located on the side of the first source region 120 facing the semiconductor substrate layer 100 and on the side of the gate structure. The current spreading layer contacts the first source region 120, has a conductivity type opposite to that of the first source region 120, and has a doping concentration greater than that of the drift layer 110.

[0255] The current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the gate structure.

[0256] The current spreading layer is spaced apart from the second doping protection layer 150 . The current spreading layer may also be in contact with the second doping protection layer 150 .

[0257] For other contents of this embodiment, please refer to Example 19 and Example 20 and will not be described in detail.

[0258] Example 22

[0259] This embodiment provides a semiconductor power device. Referring to Figure 31, the difference between the semiconductor power device of this embodiment and the semiconductor power device of Example 19 is that the second doping protection layer includes a first sub-doping region 1501 and a second sub-doping region 1502 arranged at intervals, the first sub-doping region 1501 surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on one side along the width direction, and the second sub-doping region 1502 surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the other side of the gate structure along the width direction.

[0260] The other contents of this embodiment that are the same as those of Example 19 will not be described in detail.

[0261] Example 23

[0262] This embodiment provides a semiconductor power device. Referring to Figure 32, the difference between the semiconductor power device of this embodiment and the semiconductor power device of Example 22 is that the semiconductor power device also includes: a third doped protective layer 192, located in the first epitaxial protective layer 160 at the bottom of the gate structure, and the conductivity type of the third doped protective layer 192 is the same as the conductivity type of the second doped protective layer.

[0263] In one embodiment, the positional relationship between the third doping protection layer 192 and the first sub-doping region 1501 and the positional relationship between the third doping protection layer 192 and the first sub-doping region 1501 refer to Example 17. The description of the third doping protection layer 192 refers to the above embodiment and is not described in detail.

[0264] The rest of the contents of this embodiment are the same as those of Embodiment 22 and will not be described in detail.

[0265] Example 24

[0266] This embodiment provides a semiconductor power device. The semiconductor power device of this embodiment differs from the semiconductor power devices of Embodiments 22 and 23 in that the semiconductor power device further includes a current spreading layer located on the side of the first source region 120 facing the semiconductor substrate layer 100 and on the side of the gate structure. The current spreading layer contacts the first source region 120, has a conductivity type opposite to that of the first source region 120, and has a doping concentration greater than that of the drift layer 110.

[0267] The current spreading layer contacts the first epitaxial protection layer 160 on the sidewall of the gate structure.

[0268] The current spreading layer is spaced apart from the second doping protection layer 150 . The current spreading layer may also be in contact with the second doping protection layer 150 .

[0269] For other contents of this embodiment, please refer to Example 22 and Example 23 and will not be described in detail.

[0270] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A semiconductor power device, characterized in that: The semiconductor power device comprises: semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer; a gate structure located in the drift layer; a protection unit located in the drift layer, the protection unit comprising: a first epitaxial protection layer, surrounding the sidewalls and bottom surface of the gate structure, the first epitaxial protection layer having the same conductivity type as the drift layer, and a doping concentration of the first epitaxial protection layer greater than the doping concentration of the drift layer; and a second doped protection layer, located on a side of the first epitaxial protection layer facing the semiconductor substrate layer and in contact with the first epitaxial protection layer, the second doped protection layer having an opposite conductivity type to the first epitaxial protection layer, and the second doped protection layer and the first epitaxial protection layer forming a PN junction; and A channel region is located in the first epitaxial protection layer on the sidewall of the gate structure.

2. The semiconductor power device according to claim 1, wherein: The doping concentration of the second doping protection layer is greater than the doping concentration of the first epitaxial protection layer.

3. The semiconductor power device according to claim 1, wherein: A surface of the channel region facing away from the semiconductor substrate layer is spaced from a surface of the drift layer facing away from the semiconductor substrate layer, and a surface of the channel region facing the semiconductor substrate layer is spaced from a surface of the gate structure facing the semiconductor substrate layer.

4. The semiconductor power device according to claim 1, wherein: A dimension of the second doping protection layer along a width direction of the gate structure is smaller than, equal to, or larger than a width of a bottom surface of the gate structure.

5. The semiconductor power device according to claim 1, wherein: The semiconductor power device further includes: first source regions, each located in the drift layer on both sides of the gate structure in a width direction, the first source region having a conductivity type opposite to that of the drift layer; and a second source region, located in a portion of the first source region, the second source region having a conductivity type opposite to that of the first source region. Preferably, the doping concentration of the first source region is 5 to 500 times the doping concentration of the channel region; Preferably, the doping concentration of the channel region is lower than the doping concentration of the first source region.

6. The semiconductor power device according to claim 5, characterized in that The second source region contacts a sidewall of the first epitaxial protection layer on a side laterally away from the gate structure, or the second source region further extends into the first epitaxial protection layer on a side of the channel region away from the semiconductor substrate layer.

7. The semiconductor power device according to claim 5, characterized in that The surface of the first source region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than the surface of the second doping protection layer facing away from the semiconductor substrate layer; Preferably, a longitudinal distance from a surface of the first source region facing the semiconductor substrate layer to a surface of the second doping protection layer facing away from the semiconductor substrate layer is 0.1 micrometers to 1.5 micrometers.

8. The semiconductor power device according to claim 5, characterized in that The semiconductor power device further includes: a current spreading layer located in the drift layer on the side of the first source region facing the semiconductor substrate layer and on the side of the gate structure, the current spreading layer being in contact with the first source region and the first epitaxial protection layer on the sidewall of the gate structure, the conductivity type of the current spreading layer being opposite to the conductivity type of the first source region, and the doping concentration of the current spreading layer being greater than the doping concentration of the drift layer, Preferably, the current spreading layer and the second doped protective layer are spaced apart from each other, or the current spreading layer and the second doped protective layer are spaced apart from each other and in contact with each other.

9. The semiconductor power device according to any one of claims 1 to 8, characterized in that: The second doping protection layer includes a first sub-doping region and a second sub-doping region arranged at intervals, the first sub-doping region surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on one side along the width direction, and the second sub-doping region surrounds a portion of the bottom surface of the gate structure and a portion of the side wall of the gate structure on the other side along the width direction.

10. The semiconductor power device according to any one of claims 1 to 8, characterized in that: The semiconductor power device further includes: a third doped protection layer located in the first epitaxial protection layer at the bottom of the gate structure, wherein the conductivity type of the third doped protection layer is the same as the conductivity type of the second doped protection layer. Preferably, the doping concentration of the third doping protection layer is the same as the doping concentration of the second doping protection layer; or the doping concentration of the third doping protection layer is less than the doping concentration of the second doping protection layer; or the doping concentration of the third doping protection layer is greater than the doping concentration of the second doping protection layer. Preferably, the second doped protection layer includes a first sub-doped region and a second sub-doped region spaced apart from each other, the first sub-doped region surrounding a portion of the bottom surface of the gate structure and a portion of the sidewall of the gate structure on one side along the width direction, and the second sub-doped region surrounding a portion of the bottom surface of the gate structure and a portion of the sidewall of the gate structure on the other side along the width direction. Preferably, the third doping protection layer is laterally spaced from the first sub-doping region and the second sub-doping region respectively in a width direction of the gate structure.

11. The semiconductor power device according to claim 1, wherein: The thickness of the first epitaxial protection layer is 10 nanometers to 1 micron.

12. The semiconductor power device according to claim 1, wherein: A plurality of the second doped protection layers are arranged at intervals along the length direction of the gate structure, or the second doped protection layers are continuous along the length direction of the gate structure.

13. The semiconductor power device according to claim 1, wherein: The semiconductor power device is a SiC-based semiconductor power device.

14. A method for preparing a semiconductor power device, characterized in that: The preparation method comprises: forming a drift layer on one side of the semiconductor substrate layer; forming a trench extending from a surface of the drift layer facing away from the semiconductor substrate to a portion of the thickness of the drift layer; forming a protection unit, the forming of the protection unit comprising: forming a second doped protection layer in the drift layer at the bottom of the trench; after forming the second doped protection layer, epitaxially forming a first epitaxial protection layer on the inner wall surface of the trench, wherein the conductivity type of the first epitaxial protection layer is the same as the conductivity type of the drift layer and is opposite to the conductivity type of the second doped protection layer, the doping concentration of the first epitaxial protection layer is greater than the doping concentration of the drift layer, and the second doped protection layer and the first epitaxial protection layer form a PN junction; forming a channel region in the first epitaxial protection layer on the sidewall surface of the trench; and After forming the protection unit, a gate structure is formed in the trench.

15. The method for preparing a semiconductor power device according to claim 14, wherein: The channel region is formed before forming the gate structure.

16. The method for preparing a semiconductor power device according to claim 14, wherein: The preparation method further comprises: before forming the trench, forming a first initial source region in a portion of the thickness of the drift layer, wherein the conductivity type of the first initial source region is opposite to the conductivity type of the drift layer, The process of forming a trench extending from a surface of the drift layer on a side facing away from the semiconductor substrate to a portion of the drift layer thickness is as follows: forming a trench in the first initial source region and a portion of the drift layer at the bottom of the first initial source region, and forming the first source region on both sides of the trench. Preferably, the preparation method further includes: before forming the first initial source region in the drift layer with partial thickness, forming an initial current spreading layer in the drift layer with partial thickness, the step of forming the first initial source region in the drift layer with partial thickness is: forming the first initial source region in the initial current spreading layer, wherein a surface of the first initial source region facing the semiconductor substrate layer is away from the semiconductor substrate layer relative to a surface of the initial current spreading layer facing the semiconductor substrate layer; in the process of forming the trench, the trench also penetrates the initial current spreading layer, and the initial current spreading layer on the side of the trench forms a current spreading layer.

17. The method for preparing a semiconductor power device according to claim 16, wherein: The preparation method further includes: before forming the trench, forming a second initial source region in the first initial source region, wherein the conductivity type of the second initial source region is opposite to that of the first initial source region, the lateral size of the second initial source region is smaller than the lateral size of the first initial source region, and the surface of the second initial source region facing the semiconductor substrate layer is farther away from the semiconductor substrate layer than the surface of the first initial source region facing the semiconductor substrate layer. The process of forming a trench extending from a surface of the drift layer on a side facing away from the semiconductor substrate to a portion of the thickness of the drift layer comprises: forming a trench in the second initial source region, the first initial source region, and a portion of the drift layer at the bottom of the first initial source region, with the second initial source regions on both sides of the trench forming a second source region; After the first epitaxial protection layer is formed, the second source region contacts the sidewall of the first epitaxial protection layer that is laterally away from the trench. Preferably, the ion implantation process used to form the channel region has an implantation direction perpendicular to the upper surface of the semiconductor substrate layer.

18. The method for preparing a semiconductor power device according to claim 16, wherein: The preparation method further includes: after forming the channel region, forming a second source region in a portion of the first source region and in the first epitaxial protection layer on a side of the channel region away from the semiconductor substrate layer, Preferably, the angle between the implantation direction of the ion implantation process used to form the channel region and the sidewall surface of the trench is greater than zero.

19. The method for preparing a semiconductor power device according to any one of claims 14 to 18, wherein: The preparation method further includes: forming a third doped protection layer in the first epitaxial protection layer at the bottom of the trench during the process of forming the channel region, wherein the conductivity type of the third doped protection layer is opposite to that of the first epitaxial protection layer.

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