Method for self-calibration of comparators

Abstract

Provided is a method for self-calibration of comparators. The comparator may be a threshold inverter quantization (TIQ) comparator. The method provides for simultaneous self-calibration of both the PVT corner dependent threshold voltage and the PVT corner dependent reaction time of a TIQ comparator. The method includes pre-charging a capacitor of the comparator by a first current, and then discharging the capacitor such that the capacitor voltage drops to a trip voltage equal to a delay dependent voltage below the threshold voltage. The capacitor is then charged by a signal current to capture a signal on the capacitor and then discharged until the capacitor voltage equals the trip voltage thereby tripping the capacitor to generate an output time pulse from the comparator, where the output time pulse is equal to a signal width of the signal.

Description

Method for Self-Calibration of ComparatorsTechnical Field

[0001] The embodiments disclosed herein relate to comparators, and, in particular to a method for self-calibration of comparators and more specifically TIQ comparators in analog systems and applications.Introduction

[0002] Comparators generally and threshold inverter quantization (TIQ) comparators more specifically have been used almost exclusively in flash analog to digital converters (Tangel, A., VLSI Implementation of the Threshold Inverter Quantization (TIQ) Technique for CMOS Flash ADC Applications, 1999, Penn. State University, PhD. thesis; Yoo, J., A TIQ Based CMOS Flash ADC for SOC Applications, 2003, Penn. State University, PhD. thesis).

[0003] The traditional method for TIQ comparator self-calibration is to quantify and capture the comparator threshold voltage by an auto zero cycle. FIG. 1 A is an example of an autozero cycle 100 that can be implemented. FIG. 1 B is a diagram of a comparator circuit 120 implementing a version of the auto zero cycle 100. Here, the comparator circuit 120 initially closes switch 122 for a period of time which charges the capacitor, CCOM, to the threshold voltage of inverter 128. Following this initial phase, the signal current is integrated onto CCOM for a set period of time. Then the discharge current, IDISC, discharges the capacitor, CCOM, until the voltage on the capacitor returns to the threshold of the inverter 128 at which point in time the output of the inverter will flip state. The result is a comparator output pulse width which is proportional to the ratio of IINT and IDISC. FIG. 1 C shows voltage timing diagrams 150, 152, 154, and comparator output 156 for the auto zero initial phase 102 and the subsequent integration 104 and discharge 106 phases in the comparator circuit 120.

[0004] Referring to FIGS. 1A, 1 B and 1 C, at step 102, auto-zero calibration commences when an auto-zero switch 122 is turned on to capture the threshold voltage, VTH, of the inverter on the comparator capacitor, CCOM. After the threshold voltage is captured on CCOM, switch 122 is turned off and signal capture occurs at step 104, whenan input switch 124 is turned on and the signal current, IINT, charges CCOM. At step 106, a discharge switch 126 is turned on and a fixed current, IDISC, discharges CCOM. When the voltage on CCOM, VCAP, reaches VTH, the comparator trips and provides the output signal time pulse.

[0005] A limitation of the auto zero cycle 100 is that when an amplifier 128 is in zero gain mode / mid voltage mode, maximum current flows through the comparator circuit 120 resulting in a large amount of wasted energy. A further limitation is, when CCOM is discharged, there is actually some extra discharge below VTH, due to a reaction time delay of the comparator which may introduce significant errors in certain applications (see FIG. 3). For example, the delay may be for a considerable time (for example, several nanoseconds).

[0006] The extra discharge and resulting reaction time delay is dependent on the process, voltage and temperature (i.e., PVT corner dependent) of the circuit / comparator. Consider a TIQ comparator 200 shown in FIG. 2. The threshold voltage of the comparator 200 is calculated as:

[0007] where, pP, pn, WP, Wn, VDD, VTP, VTn are MOS (metal-oxide semiconductor) device parameters that vary with process, voltage, temperature, and due to fabrication mismatch errors. pPand pnrefer to the mobility of holes and electrons. WPand Wnrefer to the width of PMOS (p-channel metal-oxide semiconductor) devices 204 and NMOS (N- type metal-oxide-sem iconductor) devices 202, respectively. For this example, lengths of these devices 202, 204 have been assumed to be equal. VDD refers to the supply voltage. VTPand VTn refer to the threshold voltage of the PMOS and NMOS devices 202, 204, respectively.

[0008] The threshold temperature sensitivity of the comparator 200 is:

[0009] The threshold power supply sensitivity of the comparator 200 is:

[0010] A timing diagram of the comparator 200 discharge during an auto-zero cycle is shown in FIG. 3. Vsignai represents the sampled voltage during the auto-zero cycle and is calculated as:

[0011] where \Signai is the input signal current applied to the capacitor (IINT in FIG. 1 B), tsignai is the input signal pulse width and CINT is the value of the capacitance.

[0012] The comparator 200 output pulse width during discharge is calculated as:Comparator Output width = Ideal signal width + Reaction timePVT

[0013] As noted above, the reaction time delay (Reaction timepvr in equation (5)) of the comparator 200 is dependent on the process, voltage and temperature of the comparator 200. Thus, the voltage when the capacitor trips, VTRIP, is not equal to the threshold voltage (VTRIP + VTH).

[0014] Given that the output of the comparator is a time pulse, the reaction time delay is part of the time pulse and introduces inherent error to the output signal. Also, complete settling to VTH may take several microseconds. Using low-power circuits further compounds the reaction time delay problem. When an amplifier 128 is in zero gain mode / mid voltage mode, maximum current flows through the comparator circuit 120 resulting in a large amount of wasted energy. Accordingly, there is a need for a new selfcalibrating comparator that overcomes the inherent limitations of the traditional auto-zero cycle calibration.Summary

[0015] According to some embodiments, there is device and a method for selfcalibrating comparators. The comparator may be a threshold inverter quantizer (TIQ) comparator. The method provides for simultaneous self-calibration of both the PVT corner dependent threshold voltage and the PVT corner dependent reaction time of a TIQ comparator. The method includes pre-charging a capacitor of the comparator by a first current, and then discharging the capacitor such that the capacitor voltage drops to a trip voltage equal to a delay dependent voltage below the threshold voltage. At this point, the capacitor is charged to a trip voltage which captures both the effect of the PVT cornerdependent threshold voltage and the PVT corner-dependent reaction time of a TIQ comparator.

[0016] The capacitor is then charged by a signal current to capture a signal on the capacitor and then discharged until the capacitor voltage equals the trip voltage thereby tripping the comparator to generate an output time pulse from the comparator, wherein the output time pulse is equal to a signal width of the signal.

[0017] The method may further include integration of the signal current on the capacitor and a capacitor voltage at the beginning of integration may be the same as at the end of discharging the signal charge from the capacitor.

[0018] According to other embodiments, there is a comparator configured to selfcalibrate. The comparator is configured to pre-charge a capacitor of the comparator by a first current, wherein the capacitor has a PVT dependent threshold voltage. The comparator is further configured to discharge the capacitor such that the capacitor voltage drops to a trip voltage equal to a delay dependent voltage below the threshold voltage. The comparator is further configured to charge the capacitor by a signal current to capture a signal on the capacitor and discharge the capacitor until the voltage on the capacitor equals the trip voltage, thereby causing the capacitor to trip and generate an output time pulse from the comparator, wherein the output time pulse is equal to a signal width of the signal.

[0019] According to various embodiments, the comparator may be a threshold inverter quantizer (TIQ) comparator or a general-purpose comparator.

[0020] Other aspects and features will become apparent, to those ordinarily skilled in the art, upon review of the following description of some exemplary embodiments.Brief Description of the Drawings

[0021] The drawings included herewith are for illustrating various examples of articles, methods, and apparatuses of the present specification. In the drawings:

[0022] FIG. 1 A is a flow chart of a traditional auto-zero cycle calibration;

[0023] FIG. 1 B is a diagram of a comparator circuit implementing the auto zero cycle in FIG. 1A;

[0024] FIG. 1 C is timing diagrams for the auto-zero cycle shown in FIG. 1A;

[0025] FIG. 2 is a diagram of an exemplary TIQ comparator;

[0026] FIG. 3 is a timing diagram showing discharge of a TIQ comparator during a traditional auto-zero cycle calibration;

[0027] FIG. 4 is a flow chart of a method for comparator self-calibration of PVT corner dependance, according to an embodiment;

[0028] FIG. 5A is a voltage timing diagram showing pre-charging and discharge of a comparator implementing the self-calibration method shown in FIG. 4; and

[0029] FIG. 5B is a timing diagram showing comparator output of the comparator implementing the self-calibration method of FIG. 4, in accordance with an embodiment.Detailed Description

[0030] Various apparatuses or processes will be described below to provide an example of each claimed embodiment. No embodiment described below limits any claimed embodiment and any claimed embodiment may cover processes or apparatuses that differ from those described below. The claimed embodiments are not limited to apparatuses or processes having all of the features of any one apparatus or process described below or to features common to multiple or all of the apparatuses described below.

[0031] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention.

[0032] Further, although process steps, method steps, algorithms or the like may be described (in the disclosure and I or in the claims) in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order that is practical. Further, some steps may be performed simultaneously.

[0033] When a single device or article is described herein, it will be readily apparent that more than one device I article (whether or not they cooperate) may be used in place of a single device I article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device I article may be used in place of the more than one device or article.

[0034] Referring to FIG. 4, shown therein is a flow chart of a method 300 for selfcalibration of a comparator, according to an embodiment. The comparator may be, for example, a TIQ comparator, or a general-purpose comparator according to various embodiments. The method 300 provides for simultaneous self-calibration of both the PVT corner dependent VTH and the PVT corner dependent reaction time (Reaction timepvr) of a TIQ comparator (e.g., the comparator 200 shown in FIG. 2).

[0035] Instead of sampling VTH by auto-zero sampling (FIGS. 1A-1 C), VTH and a delay-dependent voltage, VCDS, are sampled on the capacitor of the comparator by a precharging step 302 and a discharge step 304. VCDS is calculated as:

[0036] The pre-charging step 302 is commenced at a voltage that is below VTH, and the discharge step 304 ends when the capacitor voltage, VCAP, reaches VTH-VCDS (the trip voltage, VTRIP). At 306, the capacitor is charged by a signal current to capture a signal on the capacitor. At 308, the capacitor is discharged until the VCAP equals the trip voltage,VTRIP, thereby causing the capacitor to trip and generate an output time pulse from the comparator, wherein the output time pulse is equal to a signal width of the signal. Generally, a magnitude of VTRIP may be less than VTH or greater than VTH. This is explained further with reference to FIGS. 5A-5B.

[0037] Referring to FIG. 5A, shown therein is a voltage timing diagram 600, of the comparator implementing the method of FIG. 4. The timing diagram 600 shows precharging 608 during step 302 of the self-calibration method 300. The timing diagram 600 includes a first discharge 610 and comparator tripping 611 during step 304 the selfcalibration method 300, to reach VTH - VCDS. The timing diagram 600 includes an integration of the signal current, Isignai 612, at step 306 of the method 300, until VTH - VCDS + Vsignai is achieved at 614. A duration of integration of Isignai on the capacitor is the input signal pulse width, tsignai 613. A second discharge 616 occurs at step 308 of the method 300 when a discharge current, IDISC is applied and the comparator is tripped to VTRIP = VTH-VCDS at discharge stop 604. It should be noted that IDISC is constant and the rate of capacitor discharge between the time points 614, 604 is a fixed rate.

[0038] As shown in FIG. 5A, VTH-VCDS takes into account the PVT dependent VTH and the PVT dependent reaction time, thus the capacitor voltage, VCAP, at the beginning of integration of charge 602 and at the end of discharge 604 when the capacitor trips is equal, that is VTH-VCDS = VTRIP. The comparator output 620 (FIG. 5B) is independent of PVT corner and the width of the comparator output 606b will be equal to the output signal width 606a, as follows.

[0039] When the processing of an input signal begins at 602, the charge on the capacitor is:Qi=(VTH ~ CDS) * NT (a)After the input signal is acquired at time 604, the charge on the capacitor is:

[0040] Since the comparator output will trip in time when the VCAP reaches VTRIP = VTH-VCDS and the charge on the capacitor is equal to Qi. Thus, the comparator output willswitch in time once the charge on the capacitor is returned to Qi at time 604. The comparator output 620 is thus:which provides the desired result of an accurate comparator output pulse which is equal to the ratio of Isignai and IDISC multiplied by the tsignai.

[0041] Preferably, the self-calibration method 300 is used each time the comparator processes a signal. However, it should be noted that when different signals are processed, it may cause temperature change of the chip / comparator itself. Thus, practically, the self-calibration method 300 may be performed only once at device startup or at defined intervals of time.

[0042] While the above description provides examples of one or more apparatus, methods, or systems, it will be appreciated that other apparatus, methods, or systems may be within the scope of the claims as interpreted by one of skill in the art.

Claims

Claims:1 . A method for self-calibration of a comparator, the method comprising: pre-charging a capacitor of the comparator by a first current, wherein the capacitor has a process-voltage-temperature (PVT) dependent threshold voltage (VTH); discharging the capacitor such that a voltage on the capacitor (VCAP) drops to a trip voltage (VTRIP), the VTRIP equal to the VTH - a delay dependent voltage (VCDS); charging the capacitor by a signal current to capture a signal on the capacitor; and discharging the capacitor until the VCAP equals the VTRIP, thereby causing the capacitor to trip and generate an output time pulse from the comparator, wherein the output time pulse is equal to a signal width of the signal.

2. The method of claim 1 , wherein a magnitude of the VTRIP is less than VTH or greater than VTH.

3. The method of claim 1 , wherein the comparator is a threshold inverter quantizer (TIQ) comparator.

4. The method of claim 1 , wherein the comparator is a general-purpose comparator.

5. The method of claim 1 , wherein the VCAP at the beginning of charging the capacitor by the signal current is the same as the VTRIP at the time of discharging end.

6. The method of claim 1 further comprising integration of the signal current on the capacitor to capture the signal on the capacitor.

7. A comparator configured to self-calibrate, the comparator being configured to:pre-charge a capacitor of the comparator by a first current, wherein the comparator has a PVT dependent threshold voltage (VTH); discharge the capacitor such that a voltage on the capacitor (VCAP) drops to a trip voltage (VTRIP) equal to the VTH - a delay dependent voltage (VCDS); charge the capacitor by a signal current to capture a signal on the capacitor; and discharge the capacitor until the VCAP equals the VTRIP, thereby causing the capacitor to trip and generate an output time pulse from the comparator, wherein the output time pulse is equal to a signal width of the signal.

8. The comparator of claim 7, wherein a magnitude of the VTRIP is less than VTH or greater than VTH.

9. The comparator of claim 7, wherein the capacitor is a threshold inverter quantizer (TIQ) comparator.

10. The comparator of claim 7, wherein the comparator is a general-purpose comparator.11 . The comparator of claim 7, VCAP at the beginning of charging the capacitor by the signal current is the same as the VTRIP at the time of discharging end.

12. The comparator of claim 7, wherein the comparator is further configured to integrate the signal current on the capacitor to capture the signal on the capacitor.

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