Photonic-integrated SOA for varying mode profile to combine high gain and high power

Abstract

A semiconductor optical amplifier comprising: a substrate, a first region, a second region, and a top layer. The first region comprises a semiconductor material. A first width of the first region at a first end of the first region is less than a second width of the first region at a second end of the first region. The second region comprises a semiconductor material, on the substrate, and separated from the first region. The third region comprises a semiconductor material, on the substrate, and separated from the first region. The top layer is on at least a part of the first, second, and third regions. A waveguide is at least partly provided by the top layer and the first region. The waveguide is for guiding light from the first end to the second end.

Description

[0001] Photonic-integrated SOA for varying mode profile to combine high gain and high power

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to semiconductor devices. Particular embodiments relate to a semiconductor optical amplifier, SOA, a mask, a method for producing an SOA, a computer program, a computer apparatus, and a lithographic apparatus.

[0004] BACKGROUND

[0005] Semiconductor optical amplifiers (SOAs) are an integral part of communication and sensor system, either as a discrete component, or as part of a photonic integrated circuit (PIC). They are furthermore the “gain” element in a (planar) laser diode. Such SOAs, much like their electronics counterparts, come in many flavours, and can be optimized for high gain, for high (saturation) power, and of course for various wavelengths.

[0006] For a given operating bandwidth, i.e. fixed wavelength range, there might be contradicting design requirements in the epitaxial layer stack for high-gain operation and high-power operation. This is not so much of an issue for discrete components, as they can be made out of different epitaxial material. However, for a PIC, where typically an epitaxial layer stack is shared, this is an issue. Furthermore, it is also a disadvantage of using discrete components that this may give rise to undesirable mode conversions due to the transition from one discrete component to another discrete component.

[0007] Moreover, a major issue is also the fact that within a single SOA, one might want to combine the need for high-gain and high-power, for example to first boost a low input signal with high-gain, followed by a high saturation power. The reason is that ideally carriers (electrons and holes) have to be converted to photons as efficiently as possible, to make the SOA energy-efficient. A key metric here is “power added efficiency” (PAE), which is typically not used in photonics, but is a standard metric in electronic amplifiers.

[0008] So far, several approaches have been described in the literature:

[0009] • Monolithic SOAs can be tapered out to increase the mode area. This increases the output saturation power, while still keeping the single-mode operation and high gain at the input. This method, however, does not decrease the optical loss at the output side.

[0010] • A way to create different types of SOAs has been proposed in the so-called “hybrid silicon lll-V platform” (cf. infra), for different purposes, but these have not been combined for a high-PAE SOA;

[0011] • Different types of SOA can be realized by varying the position of the quantum wells, for example, and / or by changing the waveguide cross-section by epitaxial design. Although in principle this can be integrated on a PIC with regrowth techniques, this is technologically challenging, and is typically not done.

[0012] • US9910220B2 describes the “hybrid silicon platform” (cf. supra) and how different types of SOAs and lasers can be realized;

[0013] • US10847673B2 and US9772447B2 describe methods of realizing similar structures as the “hybrid silicon platform” (cf. supra) using micro-transfer printing.

[0014] An important context is that the field of photonic integration is relatively young, so detailed optimization of on-chip SOAs has not been given much attention yet. The focus in the state of the art has so far predominantly been on laser (wall-plug) efficiency.

[0015] SUMMARY

[0016] It is an aim of various embodiments according to the present disclosure to alleviate one or more of the above-mentioned problems. An SOA typically adds both gain and loss: the gain is due to carrier recombination; the loss is due to, mostly, tree-carrier absorption, such as doping. Various embodiments according to the present disclosure may help to solve the problem that SOAs typically either have too low gain at the input side, thus wasting carriers, or too high losses (low gain) at the output side due to i.a. tree-carrier absorption, such as doping, thus wasting photons. These embodiments may help to maximize gain at both input and output side of the SOA.

[0017] Accordingly, there is provided in a first aspect according to the present disclosure a semiconductor optical amplifier (100, 200), SOA, comprising:

[0018] - a substrate (101);

[0019] - a first region (111 , 211 A, 211 B) comprising a dielectric semiconductor material, disposed on the substrate and having both a length and a width (WA, WB) in parallel with the substrate, wherein the first region integrally extends lengthwise (L) from a first end (A) of the first region to a second end (B) of the first region, opposite from the first end;

[0020] - a second region (112, 212) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the second region is arranged along a first side of the first region at a distance from the first region;

[0021] - a third region (113, 213) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the third region is arranged along a second side of the first region, opposite from the first side, at a distance from the first region; and

[0022] - a top layer (104, 105, 106, 107, 108, 109) disposed on at least a part of the first, second and third regions, in order to define, in conjunction with the first region (111), a waveguide for light travelling from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region increases from the first end (A) to the second end (B), so as to define a tapered elongate ridge extending lengthwise from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region varies so gradually along the whole length (L) of the first region that a mode profile of the light travelling in said waveguide varies without mode conversions and without reflections. In other words, the width (WA, WB) of the first region varies so gradually (i.e. in a mathematically continuous manner) along the whole length (L) of the first region (i.e. from the first end to the second end) that the mode profile of the light travelling in said waveguide varies in a quantum adiabatic manner, i.e. without mode conversions and without reflections.

[0023] It is an insight of the inventor that, at the input side of an SOA, one typically has a low signal, so a high gain is required to boost this and other losses have less impact, as the signal is still low, whereas, at the output side, where the signal is high, the gain might saturate (or it is desired to avoid saturation), so the gain will be limited. However, since the losses are now affecting a large signal, these will dominate the efficiency. Therefore, as the signal power will increase along the SOA, the optimal trade-off between gain and other losses (e.g. doping, etc.) will change. There is thus a desire to provide an SOA that changes along the propagation direction.

[0024] By combining seamlessly and gradually, using tapered on-chip structures, definable by lithography only, both high-confinement (i.e. high-gain) and low-confinement (i.e. high-power and lower-loss) SOA sections, the PAE (power added efficiency) of a single SOA can then be optimized for the application.

[0025] Preferably, only the first region is shaped so as to define a tapered elongate ridge, as it is the first region which makes the mode move up or down and, thus, change confinement. This is different from the state of the art wherein “tapered SOAs” exist, where the whole ridge is tapered and the mode is widened or narrowed. This means that, in embodiments according to the present disclosure, the intensity is changed, rather than the confinement, as in prior art approaches. That is, overlap with the horizontal layerstack does not change if the mode is only widened or narrowed, but does change if the mode is moved up or down, which is desirable.

[0026] In other words, forming the ridge to have a varying width from the first end to the second end, such that the mode profile of propagated light varies in an adiabatic manner, i.e. without mode conversions and without reflections, allows to tailor the properties of an optical amplifier by (mask) design only, and change these along the light propagation direction of the amplifier. This is important as the light intensity increases due to the gain from input to output. A higher intensity requires a different amplifier design as compared to lower intensity light, to be efficient. However, many conventional amplifiers have amplifier properties that are still the same everywhere, and thus a sub-optimal trade-off is typically chosen. However, if these properties can be changed along the length, i.e. optimized for low intensity at the input and optimized for high intensity at the output, the overall performance of the optical amplifier can be improved beyond the state of the art.

[0027] It is noted that quantum adiabaticity in the context of semiconductor optical amplifiers (SOAs) refers to the property of the SOA where the optical gain follows the instantaneous changes in the input signal without any significant delay or loss of coherence. Repeating the statement hereinabove that it is possible to ascertain the fact that the mode profile has varied in such a quantum adiabatic manner by verifying that the light has propagated within the ridge without mode conversion and without reflections, it is noted that in a quantum adiabatic system, the system remains in its instantaneous eigenstate as it evolves slowly in time, such that no transitions occur between different eigenstates. In the context of SOAs, this means that the optical gain of the device follows the instantaneous changes in the input signal without any significant delay or loss of coherence. This is important for many applications where a high-fidelity signal is required, such as in quantum communication and computing.

[0028] In an SOA, the input signal is typically a weak optical signal that is amplified by the stimulated emission of photons from the active region of the device. The adiabaticity of the device is determined by the rate of change of the input signal and the relaxation time of the device. If the rate of change of the input signal is slow compared to the relaxation time of the device, the system can remain in its instantaneous eigenstate, and the optical gain follows the input signal without any significant delay or loss of coherence.

[0029] It is noted that the first width and the second width may be defined transversally to a longitudinal axis of the ridge. If a side of the first region is locally curved, an imaginary tangent may be drawn, defining the longitudinal axis. Thus, there is always a clearly defined width of the first region.

[0030] If the first region would lack a singular longitudinal axis, for example if the first region would be zigzag shaped or S-shaped, the first width and the second width may still be defined transversally to a local longitudinal axis of the first region, at the first end and at the second end, respectively.

[0031] Examples of a dielectric semiconductor material that can be used for the first and / or second and / or third regions may preferably include: silicon (Si), silicon nitride (Si N), aluminium nitride (AIN), and aluminium oxide (AIO). In a preferred embodiment, the dielectric semiconductor material is silicon. Of course, any suitable dielectric semiconductor material may be used, provided that it would function within the context of the present disclosure, to the skilled person’s knowledge.

[0032] In a particular embodiment, the entire SOA is integrated as a single semiconductor device.

[0033] An entirely integrated SOA (i.e. an SOA embodied as a Photonic Integrated Circuit or PIC) has i.a. the advantages of miniaturization, improved performance, and ease of integration. Such an integrated SOA can be applied in e.g. optical communication systems and signal processing systems, because such integrated SOAs may be well- suited for applications where size, efficiency, and integration with other photonic components are relevant.

[0034] In a particular embodiment, the width (WA, WB) of the first region varies strictly monotonously, preferably increases linearly or parabolically or exponentially, from the first end (A) to the second end (B). Additionally or alternatively, the width (WA, WB) of the first region at least doubles from the first end (A) to the second end (B).

[0035] Preferably, the strictly monotonously varying width may be optimized for expected input power and target output power; and / or for whether only a power boost is desired or whether linear amplification (i.e. no signal degradation, saturation) is desired. It is noted that a strictly monotonous function differs from functions that are monotonous (which allow sections of equal width among sections of increasing or decreasing with) or even non-monotonous shapes (for example a smooth sine wave).

[0036] It is noted that the limits of the first width and the second width would be a zero width (i.e. a single-point end) at minimum and full-width or even wider (significantly wider than the width of the optical mode) at maximum.

[0037] In mathematics, a function is said to be "smooth" if it has derivatives of all orders, meaning that the function is differentiable and the derivatives of the function are continuous. In other words, a smooth function is a function that is infinitely differentiable and has a graph that has no abrupt changes in direction or curvature. More formally, a function f(x) is said to be smooth on an interval [a, b] if it has derivatives of all orders on that interval, and each derivative is continuous on that interval. A function is said to be globally smooth if it is smooth on its entire domain.

[0038] In mathematics, a function f(x) is said to be continuous at a point x = a if the limit of f(x) as x approaches a exists and is equal to f(a). More formally, a function f(x) is continuous at x = a if and only if for every E > 0, there exists a 5 > 0 such that |f(x) - f(a) | < E whenever 0 < |x - a| < 5. This definition means that a function is continuous at a point if it can be drawn without lifting the pen from the paper at that point. It also implies that a function is continuous on an interval [a, b] if it is continuous at every point in that interval. Intuitively, a continuous function is one that does not have any sudden jumps or breaks in its graph. It can be a smooth function or a non-smooth function, but it must have a well-defined and continuous graph.

[0039] It is enough for the function to be continuous. An even more suitable type of function would be a function that is smooth. Consider an example of a strictly triangular sawtooth waveform: this is a continuous function, but not a smooth function, as the peaks and troughs of the sawtooth feature abrupt changes in direction. However, a continuous function such as the mentioned sawtooth function may ensure that there are no undesired mode conversions and may thus be useful. It is further noted that “essentially continuous” functions can also be regarded as continuous, if the discontinuity of such an essentially continuous function is small enough for the reflections and mode conversions to be negligible (i.e. less than -40 or -50 dB ), then that can also be considered sufficiently continuous. Therefore, limitations of lithographic resolution and small imperfections in atomic positioning may not necessarily detract from the requirement for continuity.

[0040] In a particular embodiment, the SOA comprises: a first channel (214A, 214B) in the distance between the first region (111 , 211A, 211 B) and the second region (112, 212); and a second channel (215A, 215B) in the distance between the first region (111 , 211 A, 211 B) and the third region (113, 213). The first channel and the second channel may contain a dielectric material, such as silicon oxide, air or a polymer, such as benzocyclobutene (BCB) or polyimide. This may help to ensure that the index of refraction in the channels (114, 115) and in the oxide layer (102) is lower than the index of refraction of the first region (111), making them transparent to the light, and thus confining the light in the directions of these elements. In contrast, confinement towards the top layer (which will be further described below) does not have to be so strict, as the mode expands from the first region (111) into the top layer.

[0041] In a particular embodiment, the SOA has been produced by heterogeneous die-to- wafer, D2W, or wafer-to-wafer bonding on silicon or by micro transfer printing. In practice, it may be preferred that the first region is sufficiently thick and close to the compound semiconductor layer (e.g. InP mesa) to significantly affect the mode shape.

[0042] This can for example be verified for a given produced SOA by checking for heterogeneous integration, as one can simply observe the presence of two different materials. The use of bonding may be verified by looking at the interface (typically by scanning electron microscope, SEM), noting of course that micro transfer printing (pTP) is also a form of bonding. The difference between pTP and die / wafer bonding is that in pTP the SOAs will be individually placed, whereas in die bonding, they will be defined all at once lithographically. So one can look at the differences in alignment between pTP and die bonding techniques: pTP will have local variations, die bonding will only have global variations. In a particular embodiment, the width (WA, WB) of the first region is constant over a height (H) of the first region defined perpendicularly to the substrate.

[0043] This improves the ease of manufacturing.

[0044] Note that the effective index of the first region can be compared to that of the top layer. The higher the first region (that is, for relatively high H), the more the mode is pulled down (due to lower confinement within the top layer). If the first region tapers to zero, i.e. if the mode is fully confined within the top layer, then a maximum difference can be obtained. For lower first regions (that is, for relatively small H), this difference is less pronounced.

[0045] Preferably, any section of the first region has a rectangular shape, said section being taken along the width (WA, WB) of the first region and having an infinitesimal dimension along the length (L) of the first region.

[0046] In a particular embodiment forming a first alternative, the distance (D1) between the first region and the second region is essentially constant along the length (L) of the first region. Additionally or alternatively, the distance (D2) between the first region and the third region is essentially constant along the length (L) of the first region.

[0047] In a particular embodiment forming a second alternative as opposed to said first alternative described above, the distance (D1) between the first region and the second region increases along the length (L) of the first region from the first end (A) to the second end (B). Additionally or alternatively, the distance (D2) between the first region and the third region increases along the length (L) of the first region from the first end (A) to the second end (B).

[0048] In a particular embodiment, the top layer comprises:

[0049] - an optional silicon oxide layer (104) disposed on the first (111), second (112) and third (113) regions; - a first compound semiconductor layer (105), preferably an n-lnP layer, disposed on the optional silicon oxide layer (104) or on the first (111), second (112) and third (113) regions;

[0050] - a separate confinement heterostructure, SCH, comprising:

[0051] - a first SCH layer (106) disposed on the first compound semiconductor layer (105);

[0052] - a quantum well layer (107) comprising an active region defined by a plurality of quantum wells, disposed on the first SCH layer (106); and

[0053] - a second SCH layer (108) disposed on the quantum well layer (107); and

[0054] - a second compound semiconductor layer (109), preferably a p-lnP layer, disposed on the SCH and forming a mesa.

[0055] In this context, it is noted that the compound semiconductor layer may be formed of a compound semiconductor material, such as any lll-V or ll-VI semiconductor material, including any one or more of, but not limited to, e.g. indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), and lattice-matched layers of indium gallium arsenide phosphide (InGaAsP), aluminium gallium indium arsenide (AIGalnAs), and / or indium gallium arsenide (InGaAs). In a preferred embodiment, the compound semiconductor layer is formed of InP. Of course, any suitable compound semiconductor material may be used, provided that it would function within the context of the present disclosure, to the skilled person’s knowledge.

[0056] Optionally, (a part of) the top layer above the quantum well layer can be formed into a ridge. The optical mode then "sees" both the first region and the (preferably InP) ridge at the top layer, and optical properties and mode profile may then come to depend on both geometries. The ridge at the top layer can in theory also be tapered to get some of the same effects as for the first region, but this appears to be impossible in practice, as it also should be able to serve as a top contact: if the top layer ridge were to become too narrow, the SOA would seem to not work properly anymore.

[0057] In various embodiments, the top layer may be formed by means of die bonding, wafer bonding, or micro-transfer printing. In various embodiments, the top layer may comprise a bulk or quantum well, dash, or dot active medium.

[0058] In various embodiments, the top layer may comprise any one or more of the following materials: GaN, InP, and GaAs.

[0059] Of course, it is noted that the layers can be optimized for the intended application, e.g. high gain, high saturation and / or similar applications.

[0060] There is provided in a second aspect according to the present disclosure a mask adapted for lithographically producing a semiconductor optical amplifier according to any one of the preceding claims.

[0061] There is provided in a third aspect according to the present disclosure a method for producing a semiconductor optical amplifier (100, 200), SOA. The method comprises:

[0062] - providing a substrate (101);

[0063] - forming a first region (111 , 211 A, 211 B) comprising a dielectric semiconductor material, disposed on the substrate and having both a length and a width (WA, WB) in parallel with the substrate, wherein the first region integrally extends lengthwise (L) from a first end (A) of the first region to a second end (B) of the first region, opposite from the first end;

[0064] - forming a second region (112, 212) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the second region is arranged along a first side of the first region at a distance from the first region;

[0065] - forming a third region (113, 213) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the third region is arranged along a second side of the first region, opposite from the first side, at a distance from the first region; and

[0066] - forming a top layer (104, 105, 106, 107, 108, 109) disposed on at least a part of the first, second and third regions, in order to define, in conjunction with the first region (111), a waveguide for light travelling from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region increases from the first end (A) to the second end (B), so as to define a tapered elongate ridge extending lengthwise from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region varies so gradually along the whole length (L) of the first region that a mode profile of the light travelling in said waveguide varies without mode conversions and without reflections.

[0067] In a particular embodiment, the entire SOA is integrated as a single semiconductor device.

[0068] In a particular embodiment, the width (WA, WB) of the first region varies strictly monotonously, preferably increases linearly or parabolically or exponentially, from the first end (A) to the second end (B); and / or wherein the width (WA, WB) of the first region at least doubles from the first end (A) to the second end (B).

[0069] In a particular embodiment, the method comprises forming:

[0070] - a first channel (214A, 214B) in the distance between the first region (111 , 211 A, 211 B) and the second region (112, 212); and

[0071] - a second channel (215A, 215B) in the distance between the first region (111 , 211A, 211 B) and the third region (113, 213); wherein the first channel and the second channel may contain a dielectric material, such as silicon oxide, air or a polymer, such as benzocyclobutene (BCB) or polyimide, as explained above.

[0072] In a particular embodiment, the SOA has been produced by heterogeneous die-to- wafer, D2W, bonding or wafer-to-wafer bonding on silicon or by micro transfer printing.

[0073] In a particular embodiment, the width (WA, WB) of the first region is constant over a height (H) of the first region defined perpendicularly to the substrate.

[0074] In a particular embodiment forming a first alternative, the distance (D1) between the first region and the second region is essentially constant along the length (L) of the first region. Additionally or alternatively, the distance (D2) between the first region and the third region is essentially constant along the length (L) of the first region.

[0075] In a particular embodiment forming a second alternative as opposed to said first alternative described above, the distance (D1) between the first region and the second region increases along the length (L) of the first region from the first end (A) to the second end (B). Additionally or alternatively, the distance (D2) between the first region and the third region increases along the length (L) of the first region from the first end (A) to the second end (B).

[0076] In a particular embodiment, the top layer comprises:

[0077] - an optional silicon oxide layer (104) disposed on the first (111), second (112) and third (113) regions;

[0078] - a first compound semiconductor layer (105), preferably an n-lnP layer, disposed on the optional silicon oxide layer (104) or on the first (111), second (112) and third (113) regions;

[0079] - a separate confinement heterostructure, SCH, comprising:

[0080] - a first SCH layer (106) disposed on the first compound semiconductor layer (105);

[0081] - a quantum well layer (107) comprising an active region defined by a plurality of quantum wells, disposed on the first SCH layer (106); and

[0082] - a second SCH layer (108) disposed on the quantum well layer (107); and

[0083] - a second compound semiconductor layer (109), preferably a p-lnP layer, disposed on the SCH and forming a mesa.

[0084] The skilled person will understand that various considerations, further developments and advantages described above with respect to embodiments of the SOA may also apply, mutatis mutandis, to corresponding embodiments of the method, and vice versa.

[0085] The embodiments described herein are provided for illustrative purposes and should not be construed as limiting the scope of the invention. It is to be understood that the invention encompasses other embodiments and variations that are within the scope of the appended claims. The invention is not restricted to the specific configurations, arrangements, and features described herein. The invention has wide applicability and should not be limited to the specific examples provided. The embodiments disclosed are merely exemplary, and the skilled person will appreciate that various modifications and alternative designs can be made without departing from the scope of the invention.

[0086] BRIEF DESCRIPTION OF THE DRAWINGS

[0087] The above embodiments are intended to illustrate the principles of the present disclosure, which will be more fully understood with the help of the appended drawings, in which:

[0088] Figure 1 schematically illustrates a first embodiment of an SOA according to the present disclosure;

[0089] Figure 2 schematically illustrates the first embodiment of Figure 1 , seen as a cross section taken along the P plane indicated in Figure 1 ;

[0090] Figure 3 schematically illustrates an example a tapered-confinement SOA, wherein the ridge is linearly tapered;

[0091] Figure 4 schematically illustrates a second embodiment of an SOA according to the present disclosure;

[0092] Figure 5 illustrates an exemplary plot of four graphs in four panes, representing examples of mode field shapes and how these can vary as a function of the ridge width;

[0093] Figure 6 illustrates a plot of taper shapes for indicated input powers, wherein the taper’s width is plotted as a function of the position along a 2-mm SOA; and

[0094] Figure 7 illustrates a plot comparing output power (in pane (a) of the plot) and PAE (in pane (b) of the plot) of various exemplary straight-waveguide SOAs (taking the SOA with the optimal width for each separate subrange of the input power) on the one hand with an exemplary embodiment of an SOA according to the present disclosure on the other hand.

[0095] LIST OF REFERENCE NUMBERS

[0096] 100, 200 embodiment

[0097] 101 substrate 102 optional oxide layer, optionally a compound semiconductor

[0098] 111 , 211 A, 211 B first region

[0099] 112, 212 second region

[0100] 113, 213 third region

[0101] 103, 203 first, second and third region A first end of first region

[0102] B second end of first region WA width of first region at first end of first region WB width of first region at second end of first region L length of first region H height of first region

[0103] 104, 105, 106, 107, 108, 109, 209 top layer 104 optional silicon oxide layer 105 first compound semiconductor layer

[0104] 106 first SCH layer 107 quantum well layer 108 second SCH layer 109, 209 second compound semiconductor layer

[0105] 114, 214A, 214B space between first and second region

[0106] 115, 215A, 215B space between first and third region D1 distance between first and second region D2 distance between first and third region

[0107] 301 light input 302 tapered confinement 303 light output

[0108] 400 embodiment 401 light waveguide 402 tapered ridge 411 metal contacts 412 lll / V diode with quantum wells 413 SOI (silicon on insulator) circuit 414 SOI waveguide

[0109] 415 tapered mode converter

[0110] 416 hybrid waveguide

[0111] 501 , 502 light confinement for a first region width of 1.0 pm: most light is confined in quantum wells 501 , very little light is confined in first region 502

[0112] 503, 504 light confinement for a first region width of 1.5 pm: most of the light is still confined in quantum wells 503, but a little more light is confined in first region 504, than at a width of 1 .0 pm

[0113] 505, 506 light confinement for a first region width of 2.5 pm: less light is still confined in quantum wells 505, and significantly more light is confined in first region

[0114] 506, than at a width of 1.5 pm

[0115] 507, 508 light confinement for a first region width of 3.0 pm: even less light is now confined in quantum wells 507, and significantly more light is confined in first region

[0116] 508, than at a width of 2.5 pm

[0117] DETAILED DESCRIPTION

[0118] Figure 1 schematically illustrates a first embodiment of an SOA according to the present disclosure. The SOA 100, 200, may comprise:

[0119] - a substrate 101 ;

[0120] - an optional oxide layer 102, configured to have a lower index of refraction than the first region 111 , 211 A, 211 B in case the substrate 101 does not have a lower index of refraction than the first region 111 , 211 A, 211 B (for example if both the substrate 101 and the first region 111 , 211 A, 211 B are formed of the same or a very similar material in terms of index of refraction) - if, however, the substrate 101 does have a lower index of refraction than the first region 111 , 211 A, 211 B (e.g. if the substrate 101 is formed of glass), then there may be no need for this optional oxide layer 102;

[0121] - a first region 111 , 211 A, 211 B comprising a dielectric semiconductor material, disposed on the substrate and having both a length and a width WA, WB in parallel with the substrate, wherein the first region integrally extends lengthwise L from a first end A of the first region to a second end B of the first region, opposite from the first end; - a second region 112, 212 comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the second region is arranged along a first side of the first region at a distance from the first region;

[0122] - a third region 113, 213 comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the third region is arranged along a second side of the first region, opposite from the first side, at a distance from the first region; and

[0123] - a top layer 104, 105, 106, 107, 108, 109 disposed on at least a part of the first, second and third regions, in order to define, in conjunction with the first region 111 , a waveguide for light travelling from the first end A to the second end B; wherein the width WA, WB of the first region increases from the first end A to the second end B, so as to define a tapered elongate ridge extending lengthwise from the first end A to the second end B; wherein the width WA, WB of the first region varies so gradually along the whole length L of the first region that a mode profile of the light travelling in said waveguide varies without mode conversions and without reflections.

[0124] Figure 2 schematically illustrates the first embodiment of Figure 1 , seen as a cross section taken along the P plane indicated in Figure 1. Note that the two figures are not to the same scale. Therefore, any remarks made with respect to Figurel may also apply to Figure 2, and vice versa.

[0125] In the first embodiment, purely as an example, the top layer is also shown in more detail, and the top layer may comprise:

[0126] - an optional silicon oxide layer 104 disposed on the first 111 , second 112 and third 113 regions;

[0127] - a first compound semiconductor layer 105, preferably an n-lnP layer, disposed on the optional silicon oxide layer 104 or on the first 111 , second 112 and third 113 regions;

[0128] - a separate confinement heterostructure, SCH, comprising:

[0129] - a first SCH layer 106 disposed on the first compound semiconductor layer

[0130] 105; - a quantum well layer 107 comprising an active region defined by a plurality of quantum wells, disposed on the first SCH layer 106; and

[0131] - a second SCH layer 108 disposed on the quantum well layer 107; and

[0132] - a second compound semiconductor layer 109, preferably a p-lnP layer, disposed on the SCH and forming a mesa.

[0133] In this context, the active region 107 is where the optical amplification occurs. It may comprise a thin layer within the surrounding first 106 and second 108 SCH layers, that is doped with specific elements to create a pin diode structure. Sending a forward current through the pin diode structure then creates a population inversion. This inversion is used for stimulated emission, in order to amplify the incoming optical signal. The active region may thus serve as the optical gain medium, where the input light signal may undergo amplification. The gain medium may have a population inversion, meaning that more electrons are in higher energy states than in lower energy states, enabling stimulated emission, wherein incoming photons may trigger the release of additional photons with the same energy and phase, resulting in amplification of the optical signal.

[0134] In this particular example embodiment 100, quantum wells 107 may be used, which are specific regions within the active layer of the SOA where charge carriers (electrons and holes) are confined in a potential well. These wells may be composed of semiconductor materials with a lower bandgap energy than the surrounding barrier layers. The confinement of carriers in quantum wells 107 may lead to quantized energy levels, enhancing the interaction between carriers and photons. This enhanced interaction may contribute to optical gain and the amplification of the incoming optical signal.

[0135] The SOA according to the present disclosure defines a waveguide (sometimes also termed a ‘waveguide structure’), in order to guide an optical signal within the active region 107. The waveguide may help in efficient interaction between the optical signal and the gain medium of the active region, increasing the overall performance of the amplifier. It is further noted that SOAs may of course have input and output ports for optical signals. The input port is where the weak optical signal to be amplified is introduced, and the output port is where the amplified signal is extracted. In the SOA according to the present invention, it is foreseen that the overall input port of the SOA is coupled with the first end A of the first region 111 , 211 , and that the overall output port of the SOA is coupled with the second end B of the first region 111 , 211.

[0136] It is further noted that SOAs may of course have a pump source, in order to achieve population inversion in the active region. This pump source may provide energy to elevate electrons to higher energy levels, creating the conditions for optical amplification.

[0137] It is further noted that SOAs may of course have control electronics to adjust and optimize the amplification process. These electronics may be used to control the pump power, manage the gain, or implement other functionalities to enhance the performance of the amplifier.

[0138] It is further noted that SOAs may of course have a cooling mechanism, to dissipate the heat generated during operation and to prevent damage to the device. Cooling may involve the use of heat sinks or other thermal management techniques.

[0139] It is further noted that SOAs may be packaged to protect them from external environmental factors and to provide mechanical stability. The packaging may also include connectors for easy integration into optical communication systems.

[0140] The term ‘mesa’ may refer to a raised area or mesa-like structure. It may be created using selective etching processes to remove material from areas surrounding the active region. The mesa can serve multiple purposes, including defining the waveguide structure, providing isolation between different regions of the device, and enhancing optical confinement. As indicated above, in some embodiments, the SOA may have been produced by heterogeneous die-to-wafer, D2W, or wafer-to-wafer bonding on silicon or by micro transfer printing.

[0141] Heterogeneous die-to-wafer bonding involves attaching individual semiconductor dies or chips, which may be made of different materials or have different functionalities, onto a silicon wafer. This process allows for the integration of diverse components onto a single substrate, enabling the creation of complex integrated circuits or systems. In this technique, individual semiconductor dies or chips are bonded onto a silicon wafer. The bonding process typically involves creating a permanent connection between the chip and the wafer, often using techniques like adhesive bonding, eutectic bonding, or direct bonding. This allows for the integration of different materials or components onto a single substrate, enabling the creation of complex integrated circuits or systems. Examples of applications include heterogeneous integration of III- V semiconductors (such as gallium arsenide) with silicon for optoelectronic devices or the integration of MEMS (Micro-Electro-Mechanical Systems) devices with CMOS (Complementary Metal-Oxide-Semiconductor) circuitry.

[0142] Micro transfer printing, on the other hand, involves transferring microscale or nanoscale structures, such as semiconductor devices or sensors, from one substrate to another. This technique enables the assembly of devices with high precision and customization, as well as the integration of materials that may not be compatible with conventional fabrication methods. Micro transfer printing involves transferring microscale or nanoscale structures, such as semiconductor devices or sensors, from one substrate to another. The transfer process allows for precise positioning and assembly of devices with high resolution and customization. This enables the integration of materials that may not be compatible with conventional fabrication methods or the creation of flexible and stretchable electronic systems.

[0143] In other words, in wafer and die bonding, the material is first bonded and then processed into a structure 105-109, whereas in pTP, the structure 105-109 is first processed, on a native substrate wafer, and then transferred component by component to the waver containing 101-102-111-104. This means that the techniques differ from each other. In heterogeneous die-to-wafer bonding, individual dies or chips are bonded onto a silicon wafer, whereas in micro transfer printing, microscale or nanoscale structures are transferred from one substrate to another.

[0144] Figure 3 schematically illustrates an example a tapered-confinement SOA, wherein the first region 303 is linearly tapered from input 301 to output 302. Mode converters to transition adiabatically between the silicon and hybrid modes are not shown. At the output 302, a wider silicon waveguide can be tapered down into a single-mode waveguide again.

[0145] In the example SOA embodiment of Figure 3, light enters the SOA through a silicon waveguide, which can be realized on a silicon-on-insulator platform. In the SOA, the light can be partially overlapping with the silicon and partially with the InP mesa, and the quantum wells (QWs) therein. The silicon waveguide within the SOA can then be varied, for example by tapering out. This will change the QW confinement along the SOA. The magnitude of this change and the actual confinement depend on the geometry and materials (refractive index) of the cross-section, such as the silicon waveguide thickness and the InP epitaxial layer stack.

[0146] Figure 4 schematically illustrates a purely exemplary second embodiment 400 of an SOA according to the present disclosure. The figure schematically illustrates a heterostructure mesa 412 comprising a lll / V diode with quantum wells, bonded to a ridge 402, thus forming a hybrid mode in light waveguide 401 , overlapping with both the heterostructure 412 and ridge 402 materials. The embodiment may be implemented as a SOI (silicon on insulator) circuit 413. The ridge 402 may preferably made of Si, but other materials are also possible, as described hereinabove. The heterostructure 412 may comprise (mostly) InP, but also lattice-matched layers of InGaAsP, AIGalnAs, and / or InGaAs, etc., or other materials, as described hereinabove. The figure further illustrates metal contacts 411 arranged to contact the n-lnP side and p-side (typically p-lnGaAs)., a SOI waveguide 414, a tapered mode converter 415, and the hybrid waveguide 416. In the rest of the present disclosure, the term ‘tapered ridge’ may also be used to refer to a first region shaped according to the definition given in the claims. In general, in a semiconductor device, a tapered ridge is a structure defining a ridge that is tapered down to a smaller width towards one end. These structures can be used to confine and guide light in a waveguide or a laser diode.

[0147] Since the ridge and the mesa form together a waveguide, the width of the ridge has impact on the mode shape (i.e. confinement in the quantum wells). Thus, tapering the ridge changes the mode, which changes the confinement in the quantum wells, which changes the gain / saturation.

[0148] By changing the width of the first region, the overlap with the quantum wells can be changed, and thus by tapering the ridge along the SOA length, the overlap can be made to vary, from input to output. This can improve SOA gain and saturation.

[0149] The effect of the tapered ridge on light propagation depends on the specific design of the device. However, in general, the tapered ridge can be designed to control the mode size, the effective refractive index, and the confinement of the light in the active area I quantum wells I gain area. The mode size and effective refractive index are important parameters that affect the interaction between the light and the SOA, and hence, the device performance.

[0150] Overall, the use of tapered ridges in semiconductor devices can help improve the device performance by enhancing the optical gain, reducing optical losses, and controlling the light propagation.

[0151] Tapered ridges can be made using a variety of materials, including silicon, lll-V semiconductors (such as GaAs, InP), and silicon-on-insulator (SOI) substrates. The choice of material depends on the specific device requirements, such as the operating wavelength, mode size, and integration with other components.

[0152] SOAs are typically made of lll-V semiconductors, such as InGaAsP or InGaAs in the gain layer or quantum wells, which have a direct bandgap and can provide high optical gain at telecom wavelengths. The SOA typically has InP around its core. The specific material used for an SOA depends on the desired operating wavelength, the device structure, and the required gain characteristics.

[0153] Several lll-V semiconductors have also been explored for use in the geometry of the lll-V layer of SOAs, with geometries including bulk layers, quantum dots, quantum dashes and quantum wells. These materials can provide unique gain characteristics and may be suitable for specific applications. Therefore, lll-V semiconductors are the most widely used material for SOAs due to their high gain and compatibility with existing fabrication processes.

[0154] Without loss of generality, in the present disclosure, reference may be made to a Si ridge, but this choice of material is to be seen as an example only, and various other materials may be substituted for the silicon instead, such as the above-recited materials, but also other materials.

[0155] The optical mode in an SOA realized by heterogeneous die / wafer bonding on silicon or by micro-transfer-printing can depend on the width of the underlying silicon waveguide or ridge, as shown in Figures 5, 6 and 7. It can be seen that the width of the underlying ridge influences the mode shape.

[0156] The light is confined (thus forming a guided mode) due to index differences (layers and ridge etching). If this index “map” or geometry changes, the mode changes. Practically, this means that one can tune the mode overlap with (or confinement in) the quantum wells (so, the gain) of the SOA and the overlap with the doped layers (so, no gain, but loss), by changing the width of the first region. Note that Si is typically not doped and is thus low loss.

[0157] When light propagates through an optical waveguide, its intensity is concentrated in the vicinity of the waveguide core. This concentration of optical power is often referred to as mode confinement, and it is influenced by the refractive indices of the waveguide material and its surroundings, as well as the dimensions of the waveguide. With respect to the SOA what counts is the confinement in I overlap with the quantum wells, as these provide gain, and - secondary - confinement in the highly-doped layers, as these lead to loss. In the case of SOAs realized by heterogeneous die / wafer bonding on silicon or by micro-transfer-printing, the active semiconductor material (typically an InP-lnGaAsP stack) is bonded to a silicon waveguide or ridge. The dimensions of the silicon waveguide or ridge can affect the mode confinement of the optical signal propagating through the SOA. In particular, the width of the silicon waveguide or ridge can impact the confinement of the optical mode. A narrower waveguide or ridge will provide stronger confinement of the optical mode, which can increase the gain of the SOA by reducing the spatial extent of the optical mode and therefore increasing the overlap with the active semiconductor material (in particular, the quantum wells, or equivalently, a similar gain layer, quantum dots, quantum dashes, a bulk gain layer, etc.). Conversely, a wider waveguide or ridge will provide higher confinement of the optical mode in the Si tapered ridge and lower confinement in the InP mesa, and thus lower confinement in the quantum wells weaker confinement of the optical mode, which can reduce the gain of the SOA by allowing the optical mode to spread out and reduce its overlap with the active semiconductor material. When the mode is pulled down, there is less overlap with the gain, but more overlap with the ridge and thus a lower gain. Therefore, the width of the underlying silicon waveguide or ridge can play a significant role in determining the performance of SOAs realized by heterogeneous die / wafer bonding on silicon, by micro-transfer-printing, or by other similar techniques. Optimization of the waveguide or ridge dimensions can be an important factor in achieving the desired performance characteristics of the device.

[0158] In other words, if a wide ridge is present, the mode is pulled down, due to the high refractive index of Si. If the ridge is narrow - or missing - the mode is pulled up, overlapping mainly with the lll-V, e.g. InP.

[0159] The existing insight is that a narrow ridge can lead to higher gain, due to higher overlap with the quantum wells. However, this can also lead to increased losses, due to increased overlap with highly doped cladding. On the other hand, a wide ridge can lead to lower overlap with the quantum wells, and thus lower gain and higher saturation power. Also, it can lead to lower losses, as the mode overlaps less with the cladding and more with the undoped (i.e. low loss) ridge. It is an insight of the inventors that features that have not previously been combined may actually be combined in a single SOA by continuously tapering (varying) the ridge, for example as shown in Figures 1 , 2, 3 and 4. A slowly-varying ridge width change helps to avoid abrupt changes in the mode profile, which might lead to reflections and mode conversion inside the SOA. Reflections may be undesired for its operation. In addition, the combination of features allows, by careful optimization, to realize an SOA which can be optimized for energy-efficiency. This may help to afford more design freedom of the confinement along the SOA length, by lithographic design only.

[0160] In summary, various embodiment of the present disclosure may be characterized by the following features or insights, in particular: 1) the insight that these features may be combined in a single SOA, 2) the insight that this transition may be continuous, e.g. tapered, and 3) the insight that this may lead to improved SOA functionality. In other words, various embodiment of the present disclosure may be characterized by the following features or insights:

[0161] - The use of an underlying ridge to tailor the mode profile (and confinement in the quantum wells) and to use this in a PIC to change the mode profile along the SOA;

[0162] - The implementation to do this in a smooth (adiabatic) way, to avoid detrimental reflections;

[0163] - The optimization of this variation of mode profiles to obtain an improved SOA, for example, with respect to PAE.

[0164] Note that the width variation may have the shape of a linear taper, but it can also be parabolic, or it can be shaped according to any other suitable function, provided that this tapering is gradual, in order to avoid abrupt steps in mode profiles, which might lead to undesired reflections or mode conversion.

[0165] It is noted that in the tapered transition sections between a purely silicon waveguide and a hybrid InP-Si waveguide the mode might also change shape, but that this is different from the mode profile in the SOA.

[0166] InP and Si are two different types of semiconductors. InP is a compound semiconductor that is commonly used in optoelectronic devices such as lasers and photodetectors, while Si is an elemental semiconductor that is widely used in electronic devices such as transistors and microprocessors.

[0167] A ridge is a structure in a semiconductor device that is formed by etching or depositing a material on a substrate to create a raised strip or ridge that serves as a waveguide for the light. This is usually done using a process called reactive ion etching, which removes the surrounding material and leaves a raised ridge. The ridge structure helps to confine and guide the light along the device.

[0168] On the other hand, a mesa is a structure in a semiconductor device that is formed by etching away the surrounding material to create a raised platform or mesa that serves as a base for the device components. The mesa structure typically has a rectangular or square shape and is used to isolate the device components from the surrounding material and to reduce the surface area of the device.

[0169] Thus, while both ridge and mesa structures involve etching or depositing materials on a substrate, the structures themselves serve different functions in a semiconductor device. The ridge is used to guide light, while the mesa is used to isolate device components and reduce the surface area of the device.

[0170] As discussed above, Figure 4 schematically illustrates a cross-section of a heterogeneously integrated SOA embodiment 400 according to the present disclosure, where the optical guiding is achieved by a silicon waveguide, i.e. a structure in which the InP mesa is bonded to the ridge. When the two materials are brought into close proximity like this, a hybrid mode is formed. This means that the electrical and optical properties of the structure are influenced by both the InP and Si materials. The hybrid mode overlaps with both the InP and Si materials, meaning that it can interact with both types of semiconductor.

[0171] In particular embodiments, the gain medium can be InP, GaAs, GaN or any lll-V or II- VI material stack that provides gain.

[0172] In particular embodiments, the Si ridge can be SiN, AIN, AIO, or any similar material. In particular embodiments, the SOA may be optimized for PAE operation. In particular embodiments, the SOA may be optimized for linear operation.

[0173] In particular embodiments, tapered mode converters may couple light in and out into the SOA from the Si waveguide.

[0174] Figure 5 illustrates an exemplary plot of four graphs in four panes, representing examples of mode field shapes and how these can vary as a function of the ridge width. In other words, the figure schematically illustrates plots of simulations of a hybrid mode, overlapping with both the silicon and the InP materials, showing the variation in confinement as a function of silicon waveguide widths of 1.0 pm, 1.5 pm, 2.5 pm and 3.0 pm.

[0175] It can be seen that, as the width of the silicon waveguide increased from a width of 1.0 pm 501 , over 1.5 pm 503, over 2.5 pm 505, up to 3.0 pm 507, there is a concomitant change in the respectively corresponding mode profile due to different confinement within the active region 501 , 503, 505, 507 on the one hand and the first region 502, 504, 506, 508 on the other hand, respectively, causing a change in gain profile along the length of the SOA.

[0176] In the top left pane, light confinement is shown for a first region width of 1.0 pm: most of the light is confined in quantum wells 501 , and very little light is confined in first region 502. Note also how the light in the first region 502 conforms substantively to the generally rectangular shape of the first region.

[0177] In the top right pane, light confinement is shown for a first region width of 1.5 pm: most of the light is still confined in quantum wells 503, but a little more light is confined in first region 504, than at a width of 1.0 pm as shown in the top left pane.

[0178] In the bottom left pane, light confinement is shown for a first region width of 2.5 pm: less light is still confined in quantum wells 505, and significantly more light is confined in first region 506, than at a width of 1.5 pm as in the top right pane. In the bottom right pane, light confinement is shown for a first region width of 3.0 pm: even less light is now confined in quantum wells 507, and significantly more light is confined in first region 508, than at a width of 2.5 pm as in the bottom left pane.

[0179] Figure 6 illustrates a plot of taper shapes for indicated input powers 602, wherein the taper’s width is plotted as a function of the position along a 2-mm SOA. The taper shape is optimized for PAE, for the optical input power levels indicated. SOA position is defined along the direction of propagation, with the input at position 0 and the output at position 2000 pm. As can be seen, for a low input power (e.g. around 0.01 mW), the waveguide width 604 does not need to vary much over the position along the SOA, whereas for a high input power (e.g. around 30 mW), the waveguide width 601 , 602 varies significantly over the position along the SOA.

[0180] Simulations of the SOA according to the present disclosure have been performed using parameters based on Davenport et al., IEEE JSTQE 22 (6) 2016, to determine the so-called 3 dB saturation, i.e. the point where the gain drops by 3 dB for increasing input power, as a function of the linear, i.e. small-signal, gain of the SOA. For a given target gain, the saturation is ideally as high as possible, to avoid signal distortion. In the simulations, a “straight” waveguide SOA 702, 712 has been compared to SOAs with different tapered waveguides 701 , 711 according to various embodiments according to the present disclosure, of different widths.

[0181] The gain of an optical input signal in the SOA can in general be simulated using rate equations for carrier density N(z,t) and optical power A logarithmic model for the gain G(z,f) is used. Note that gain compression is not taken into account. The coordinate z indicates the longitudinal position along the SOA length, with position 0 at the input. The simulation parameters and values are determined using separateconfinement heterostructure thicknesses of 125 pm at both the p and n side of the QWs, as this approach represents a comprehensive and experimentally verified approach for a typical SOA implementation. Values used are injection efficiency qi = 0.6; QW thickness tow = 7 nm and width WQW = 4 pm; number of QWs NQW = 3; carrier lifetime T = (J\I B with the bimolecular recombination B = 1O- 1O’10cm3s'1; the elementary charge q; Planck’s constant tv, the optical angular frequency co = 2TTX 193 THZ, corresponding to a wavelength of 1550 nm; the mode area o = WQWTQW- / F ; the linear gain coefficient aN = 1.65- 1 O'19m2; the transparency carrier density / Vtr= 1018cm-3. The confinement factor F(wsi) per QW and the passive loss Oj(wsi) are functions of the silicon width wsi. An SOA length of 2 mm is considered at a current injection density J = 3400 Acm-2, so the current I = 280 mA, at a voltage of 2.3 V.

[0182] The rate equations can be numerically solved for the steady-state condition and by distributing the SOA in segments of 10 pm length. Note that saturation effects can be taken into account through the interdependency of / \ / (z) and P(z). Only values of wsi between 0.5 pm and 2.0 pm may be considered.

[0183] It will thus be appreciated that varying the confinement factor of the SOA along the propagation direction can improve the SOA performance. A qualitative explanation is that at the input side of the SOA, where the optical power is relatively small, high gain is preferred over high loss, as long as the gain exceeds the loss. At the output side, where the optical power is higher, saturation needs to be avoided, so the lower confinement and lower loss are beneficial there.

[0184] It is noted that the point on the varying confinement factor will be appreciated by the skilled person, as in discrete SOAs or related components, the confinement varies from device to device, to allow for various functions. More generally, it is known from electronics that we have low-noise amplifiers and high-power amplifiers. In a link, one might use a varying sequence and the effect of their differences is known (e.g. from the Friis formula). Therefore, the skilled person will understand how varying the confinement factor of the SOA along the propagation direction can improve the SOA performance.

[0185] Figure 7 illustrates a plot comparing output power (in pane (a) of the plot) and PAE (in pane (b) of the plot) of various exemplary straight-waveguide SOAs (taking the SOA with the optimal width for each separate subrange of the input power) on the one hand with an exemplary embodiment of an SOA according to the present disclosure on the other hand.

[0186] Results from these simulations are shown in Figure 7. Figure 7 illustrates a plot comparing output power (in pane (a) of the plot) and PAE (in pane (b) of the plot) of various exemplary straight-waveguide SOAs (taking the SOA with the optimal width for each separate subrange of the input power) on the one hand with an exemplary embodiment of an SOA according to the present disclosure on the other hand.

[0187] It can be seen that for a given linear gain 704, 714, an almost 2 dB improvement 703, 713 in input saturation power, i.e. in 3 dB saturation, can be achieved. This shows that varying the confinement factor of the SOA along the propagation direction can improve the SOA performance. A qualitative explanation for this phenomenon is that at the input side of the SOA, where the optical power is relatively small, high gain is preferred over high loss, as long as the gain exceeds the loss. At the output side, where the optical power is higher, saturation is preferably avoided, so the lower confinement and lower loss are beneficial there.

[0188] An efficient SOA can be offered as a “basic building block” in the process design kits (PDKs) of foundries that run relevant processes, and / or used for internal use / production.

[0189] Further optimizations can be made, e.g. multiple segmented tapers and / or parabolic tapers.

[0190] As used in this application and in the claims, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. The systems, apparatus, and methods described herein should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and sub-combinations with one another. The disclosed systems, methods, and apparatus are not limited to any specific aspect or feature or combinations thereof, nor do the disclosed systems, methods, and apparatus require that any one or more specific advantages be present or problems be solved. Any theories of operation are to facilitate explanation, but the disclosed systems, methods, and apparatus are not limited to such theories of operation.

[0191] Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed systems, methods, and apparatus can be used in conjunction with other systems, methods, and apparatus. Additionally, the description sometimes uses terms like “obtaining” and “outputting” to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by the skilled person.

[0192] It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals may have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the examples described herein. However, it will be understood by the skilled person that the examples described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the examples described herein. Of course, the skilled person will understand that the present invention may be implemented in other ways than those specifically set forth herein without departing from the essential characteristics of the invention. The embodiments described herein are thus to be considered in all respects as illustrative and not restrictive, and all changes within the scope of the appended claims are intended to be embraced therein.

[0193] Some examples herein relate to a photonic integrated circuit (PIC) or a device comprising the semiconductor optical amplifier described herein. The PIC or device may be for at least one of: interferometry, light detection and ranging (LiDAR), frequency-modulated continuous wave light detection and ranging (FMCW LiDAR), coherent detection, telecommunications, or quantum computing. Other uses of the PIC and / or the device are envisaged.

[0194] Clause 1. A semiconductor optical amplifier (100, 200), SOA, comprising:

[0195] - a substrate (101);

[0196] - a first region (111 , 211 A, 211 B) comprising a dielectric semiconductor material, disposed on the substrate and having both a length and a width (WA, WB) in parallel with the substrate, wherein the first region integrally extends lengthwise (L) from a first end (A) of the first region to a second end (B) of the first region, opposite from the first end;

[0197] - a second region (112, 212) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the second region is arranged along a first side of the first region at a distance from the first region;

[0198] - a third region (113, 213) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the third region is arranged along a second side of the first region, opposite from the first side, at a distance from the first region; and

[0199] - a top layer (104, 105, 106, 107, 108, 109) disposed on at least a part of the first, second and third regions, in order to define, in conjunction with the first region (111), a waveguide for light travelling from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region increases from the first end (A) to the second end (B), so as to define a tapered elongate ridge extending lengthwise from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region varies so gradually along the whole length (L) of the first region that a mode profile of the light travelling in said waveguide varies without mode conversions and without reflections.

[0200] Clause 2. The SOA of clause 1 , wherein the entire SOA is integrated as a single semiconductor device.

[0201] Clause 3. The SOA of any preceding clause, wherein the width (WA, WB) of the first region varies strictly monotonously, preferably increases linearly or parabolically or exponentially, from the first end (A) to the second end (B); and / or wherein the width (WA, WB) of the first region at least doubles from the first end (A) to the second end (B).

[0202] Clause 4. The SOA of any preceding clause, comprising:

[0203] - a first channel (214A, 214B) in the distance between the first region (111 , 211 A, 211 B) and the second region (112, 212); and

[0204] - a second channel (215A, 215B) in the distance between the first region (111 , 211 A, 211 B) and the third region (113, 213); wherein the first channel and the second channel contain a dielectric material.

[0205] Clause 5. The SOA of any preceding clause, wherein the SOA has been produced by heterogeneous die-to-wafer, D2W, or wafer-to-wafer bonding on silicon or by micro transfer printing.

[0206] Clause 6. The SOA of any preceding clause, wherein the width (WA, WB) of the first region is constant over a height (H) of the first region defined perpendicularly to the substrate.

[0207] Clause 7. The SOA of any one of clauses 1-6, wherein the distance (D1) between the first region and the second region is essentially constant along the length (L) of the first region; and / or wherein the distance (D2) between the first region and the third region is essentially constant along the length (L) of the first region.

[0208] Clause 8. The SOA of any one of clause 1-6, wherein the distance (D1) between the first region and the second region increases along the length (L) of the first region from the first end (A) to the second end (B); and / or wherein the distance (D2) between the first region and the third region increases along the length (L) of the first region from the first end (A) to the second end (B).

[0209] Clause 9. The SOA of any preceding clause, wherein the top layer comprises:

[0210] - an optional silicon oxide layer (104) disposed on the first (111), second (112) and third (113) regions;

[0211] - a first compound semiconductor layer (105), preferably an n-lnP layer, disposed on the optional silicon oxide layer (104) or on the first (111), second (112) and third (113) regions;

[0212] - a separate confinement heterostructure, SCH, comprising:

[0213] - a first SCH layer (106) disposed on the first compound semiconductor layer (105);

[0214] - a quantum well layer (107) comprising an active region defined by a plurality of quantum wells, disposed on the first SCH layer (106); and

[0215] - a second SCH layer (108) disposed on the quantum well layer (107); and

[0216] - a second compound semiconductor layer (109), preferably a p-lnP layer, disposed on the SCH and forming a mesa.

[0217] Clause 10. A method for producing a semiconductor optical amplifier (100, 200), SOA; the method comprising:

[0218] - providing a substrate (101);

[0219] - forming a first region (111 , 211 A, 211 B) comprising a dielectric semiconductor material, disposed on the substrate and having both a length and a width (WA, WB) in parallel with the substrate, wherein the first region integrally extends lengthwise (L) from a first end (A) of the first region to a second end (B) of the first region, opposite from the first end;

[0220] - forming a second region (112, 212) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the second region is arranged along a first side of the first region at a distance from the first region;

[0221] - forming a third region (113, 213) comprising a dielectric semiconductor material, disposed on the substrate and extending from the first end to the second end, wherein the third region is arranged along a second side of the first region, opposite from the first side, at a distance from the first region; and - forming a top layer (104, 105, 106, 107, 108, 109) disposed on at least a part of the first, second and third regions, in order to define, in conjunction with the first region (111), a waveguide for light travelling from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region increases from the first end (A) to the second end (B), so as to define a tapered elongate ridge extending lengthwise from the first end (A) to the second end (B); wherein the width (WA, WB) of the first region varies so gradually along the whole length (L) of the first region that a mode profile of the light travelling in said waveguide varies without mode conversions and without reflections.

[0222] Clause 11. The method of clause 10, wherein the entire SOA is integrated as a single semiconductor device.

[0223] Clause 12. The method of any one of clauses 10-11 , wherein the width (WA, WB) of the first region varies strictly monotonously, preferably increases linearly or parabolically or exponentially, from the first end (A) to the second end (B); and / or wherein the width (WA, WB) of the first region at least doubles from the first end (A) to the second end (B).

[0224] Clause 13. The method of any one of clauses 10-12, comprising forming:

[0225] - a first channel (214A, 214B) in the distance between the first region (111 , 211 A, 211 B) and the second region (112, 212); and

[0226] - a second channel (215A, 215B) in the distance between the first region (111 , 211A, 211 B) and the third region (113, 213); wherein the first channel and the second channel contain a dielectric material.

[0227] Clause 14. The method of any one of clauses 10-13, wherein the SOA has been produced by heterogeneous die-to-wafer, D2W, or wafer-to-wafer bonding on silicon or by micro transfer printing.

[0228] Clause 15. The method of any one of clauses 10-14, wherein the top layer comprises:

[0229] - an optional silicon oxide layer (104) disposed on the first (111), second (112) and third (113) regions;

[0230] - a first compound semiconductor layer (105), preferably an n-lnP layer, disposed on the optional silicon oxide layer (104) or on the first (111), second (112) and third (113) regions;

[0231] - a separate confinement heterostructure, SCH, comprising: - a first SCH layer (106) disposed on the first compound semiconductor layer (105);

[0232] - a quantum well layer (107) comprising an active region defined by a plurality of quantum wells, disposed on the first SCH layer (106); and

[0233] - a second SCH layer (108) disposed on the quantum well layer (107); and

[0234] - a second compound semiconductor layer (109), preferably a p-lnP layer, disposed on the SCH and forming a mesa.

Claims

CLAIMS1. A semiconductor optical amplifier comprising: a substrate; a first region comprising a semiconductor material, a first width of the first region at a first end of the first region less than a second width of the first region at a second end of the first region; a second region comprising a semiconductor material, on the substrate, and separated from the first region; a third region comprising a semiconductor material, on the substrate, and separated from the first region; and a top layer on at least a part of the first, second, and third regions, a waveguide at least partly provided by the top layer and the first region, the waveguide for guiding light from the first end to the second end.

2. The semiconductor optical amplifier of claim 1 , wherein the width of the first region is tapered from the first end to the second end.

3. The semiconductor optical amplifier of claim 1 or 2, integrated as a single semiconductor device.

4. The semiconductor optical amplifier of any preceding claim, wherein the width of the first region at least one of: increases linearly; increases parabolically; or increases exponentially, from the first end to the second end.

5. The semiconductor optical amplifier of any preceding claim, wherein the second width is no less than double the first width.

6. The semiconductor optical amplifier of any preceding claim, comprising: a first dielectric portion between the first region and the second region; and a second dielectric portion between the first region and the third region.

7. The semiconductor optical amplifier of any preceding claim, wherein the SOA has been produced by at least one of: heterogeneous die-to-wafer; wafer-to-wafer bonding on silicon; or micro transfer printing.

8. The semiconductor optical amplifier of any preceding claim, wherein the width of the first region is constant over a height of the first region perpendicular to the substrate.

9. The semiconductor optical amplifier of any preceding claim, wherein the first width and the second width are both perpendicular a direction from the first end to the second end.

10. The semiconductor optical amplifier of any preceding claim, wherein: a side of the second region at a first distance from a first side of the first region at the first end and at a second distance from the first side at the second end a side of the second region at a third distance from a second side of the first region opposite the first side at the first end and at a fourth distance from the second side at the second end.11 . The semiconductor optical amplifier of claim 10, wherein at least one of: the first distance is equal the second distance; or the third distance is equal the fourth distance.

12. The semiconductor optical amplifier of claim 10 or 11 , wherein at least one of: the side of the second region is parallel the first side; or the side of the third region is parallel the second side.

13. The semiconductor optical amplifier of claim 10, wherein, wherein at least one of: the first distance is less than the second distance; or the third distance is less than the fourth distance.

14. The semiconductor optical amplifier of any preceding claim, wherein the top layer comprises: a first compound semiconductor layer on the first region, the second region, and the third region; a separate confinement heterostructure comprising: a first separate confinement heterostructure layer on the first compound semiconductor layer, a quantum well layer comprising a plurality of quantum wells, and on the first separate confinement heterostructure layer, and a second separate confinement heterostructure layer on the quantum well layer; and a second compound semiconductor layer on the separate confinement heterostructure.

15. The semiconductor optical amplifier of claim 14, wherein the first compound semiconductor layer comprises n-doped indium phosphide.

16. The semiconductor optical amplifier of claim 14 or 15, wherein the second compound semiconductor layer comprises n-doped indium phosphide.

17. The semiconductor optical amplifier of any of claims 14 to 16, wherein the second compound semiconductor layer is a mesa.

18. The semiconductor optical amplifier of any of claims 14 to 17, wherein the top layer comprises a silicon oxide layer, the silicon oxide layer on the first region, the second region, and the third region.

19. The semiconductor optical amplifier of claim 18, wherein the first compound semiconductor layer is on the silicon oxide layer.

20. The semiconductor optical amplifier of any preceding claim, wherein at least one of: the semiconductor material of the first region is a dielectric semiconductor; the semiconductor material of the second region is a dielectric semiconductor; or the semiconductor material of the third region is a dielectric semiconductor.

21. A method of producing the semiconductor optical amplifier of any preceding claim.

22. A method of producing a semiconductor optical amplifier, the method comprising: providing a substrate; forming a first region comprising a semiconductor material, a first width of the first region at a first end of the first region less than a second width of the first region at a second end of the first region; forming a second region comprising a semiconductor material, on the surface, and separated from the first region; forming a third region comprising a semiconductor material, on the surface, and separated from the first region; and forming a top layer on at least a part of the first, second, and third regions, a waveguide at least partly provided by the top layer and the first region, the waveguide for guiding light from the first end to the second end.

23. The method of claim 22, wherein the width of the first region is tapered from the first end to the second end.

24. The method of claim 22 or 23, comprising integrating the semiconductor optical amplifier as a single semiconductor device.

25. The method of any of claims 22 to 24, wherein the width of the first region at least one of: increases linearly; increases parabolically; or increases exponentially, from the first end to the second end.

26. The method of any of claims 22 to 25, wherein the second width is no less than double the first width.

27. The method of any of claims 22 to 26, comprising: forming a first dielectric portion between the first region and the second region; and forming a second dielectric portion between the first region and the third region.

28. The method of any of claims 22 to 27, comprising at least one of: heterogeneous die-to-wafer; wafer-to-wafer bonding on silicon; or micro transfer printing.

29. The method of any of claims 22 to 28, wherein the width of the first region is constant over a height of the first region perpendicular to the substrate.

30. The method of any of claims 22 to 25, wherein the first width and second width both perpendicular a light propagation direction of the waveguide.31 . The method of any of claims 22 to 30, wherein: a side of the second region at a first distance from a first side of the first region at the first end and at a second distance from the first side at the second end a side of the second region at a third distance from a second side of the first region opposite the first side at the first end and at a fourth distance from the second side at the second end.

32. The method of claim 31 , wherein at least one of: the first distance is equal the second distance; or the third distance is equal the fourth distance.

33. The method of claim 31 or 32, wherein at least one of: the side of the second region is parallel the first side; or the side of the third region is parallel the second side.

34. The semiconductor optical amplifier of claim 31 , wherein, wherein at least one of: the first distance is less than the second distance; or the third distance is less than the fourth distance.

35. The method of any of claims 22 to 34, wherein forming the top layer comprises: forming a first compound semiconductor layer on the first region, the second region, and the third region; forming a separate confinement heterostructure comprising: a first separate confinement heterostructure layer on the first compound semiconductor layer; a quantum well layer comprising a plurality of quantum wells, and on the first separate confinement heterostructure layer; and a second separate confinement heterostructure layer on the quantum well layer; and forming a second compound semiconductor layer on the separate confinement heterostructure.

36. The method of claim 35, wherein the first compound semiconductor layer comprises n-doped indium phosphide.

37. The method of claim 35 or 36, wherein the second compound semiconductor layer comprises n-doped indium phosphide.

38. The method of any of claims 35 to 37, wherein the second compound semiconductor layer is a mesa.

39. The method of any of claims 35 to 38, wherein forming the top layer comprises forming a silicon oxide layer, the silicon oxide layer on the first region, the second region, and the third region.

40. The method of claim 39, wherein the first compound semiconductor layer is on the silicon oxide layer.41 . The method of any of claims 22 to 40, wherein at least one of: the semiconductor material of the first region is a dielectric semiconductor; the semiconductor material of the second region is a dielectric semiconductor; or the semiconductor material of the third region is a dielectric semiconductor.

42. A semiconductor optical amplifier obtained by any of claims 22 to 41.

43. A photonic integrated circuit comprising the semiconductor optical amplifier of any of claims 1 to 20, or 42.

44. A device comprising the photonic integrated circuit of claim 43, or the semiconductor optical amplifier of any of claims 1 to 20, or 42.

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