Display panel and electronic device including same

Abstract

The present invention provides a display panel and an electrode device including same, the display panel comprising: a pixel circuit disposed in a display area; a light-emitting diode disposed in the display area; a repair circuit disposed in a peripheral area outside the display area; a repair line extending from the peripheral area to the display area in a first direction; a voltage line extending in the first direction; and a first connection line electrically connecting the repair line and the voltage line.

Description

Display panel and electronic device including same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] A display panel may include a plurality of pixels. Each pixel may include a light-emitting element including a light-emitting layer and a pixel circuit for controlling the brightness of the light-emitting element. The pixel circuit may include thin film transistors, capacitors, and wiring.

[0003] Recently, display panels have become thinner and lighter, making them suitable for use in a variety of electronic devices. As these display panels become more widely used, various display panel types and electronic devices incorporating them are being designed.

[0004] Defects in certain pixel circuits can cause bright or dark spots on a display panel. The present invention aims to address these and other issues, and provides a display device and electronic device that include a repair pixel circuit electrically connected to a light-emitting element in place of a defective pixel circuit. However, these tasks are exemplary and do not limit the scope of the present invention.

[0005] According to one aspect of the present invention, a display panel is provided, including a pixel circuit arranged in a display area, a light emitting diode arranged in the display area, a repair circuit arranged in a peripheral area outside the display area, a repair line extending from the peripheral area to the display area along a first direction, a voltage line extending in the first direction, and a first connection line electrically connecting the repair line and the voltage line.

[0006] In one embodiment, the pixel circuit may include a semiconductor layer, and a first gate electrode disposed on the semiconductor layer and electrically connected to a first node, a first transistor electrically connected between a driving voltage line and a second node, a second transistor electrically connected between the first node and a data line, a capacitor including a second electrode electrically connected between the first node and the second node, a third transistor electrically connected between the first node and the first voltage line, a fourth transistor electrically connected between the second node and a third node to which a pixel electrode of the light-emitting diode is electrically connected, and a fifth transistor electrically connected between the third node and the second voltage line.

[0007] In one embodiment, the voltage line may be one of the first voltage line and the second voltage line.

[0008] In one embodiment, the pixel circuit further includes a sixth transistor electrically connected between the second node and a third voltage line, wherein the voltage line may be any one of the first voltage line, the second voltage line, and the third voltage line.

[0009] In one embodiment, the light emitting diode includes a pixel electrode, a common electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the common electrode, and the voltage line may be a common voltage line that transmits a common voltage applied to the common electrode.

[0010] In one embodiment, the semiconductor layer includes an oxide semiconductor material, and the first connecting line may be disposed in the same layer as the semiconductor layer.

[0011] In one embodiment, the display panel further includes a first insulating layer disposed under the semiconductor layer, and the repair line may be disposed under the first insulating layer.

[0012] In one embodiment, the first connecting line may comprise a conductive oxide.

[0013] In one embodiment, the first connecting line comprises a metal, and the thickness of the first connecting line may be less than or equal to about 1,000 Å.

[0014] In one embodiment, the display panel may further include a second connection line electrically connecting the pixel circuit or the repair line to the light emitting diode.

[0015] In one embodiment, the display panel further includes a third connecting line electrically connected to the repair circuit and overlapping the repair line, wherein when the second connecting line is electrically connected to the repair line, the third connecting line can be electrically connected to the repair line.

[0016] When the second connecting line is electrically connected to the repair line, the first connecting line is cut so that the repair line and the voltage line can be electrically separated.

[0017] In one embodiment, the repair line may overlap the voltage line in a plane.

[0018] According to another aspect of the present invention, an electronic device is provided, which includes a display panel including a display area in which a plurality of pixels are arranged and a peripheral area outside the display area, wherein the display panel includes a pixel circuit arranged in the display area, a light-emitting diode arranged in the display area, a repair circuit arranged in the peripheral area outside the display area, a repair line extending from the peripheral area to the display area along a first direction, a voltage line extending in the first direction, and a first connection line electrically connecting the repair line and the voltage line.

[0019] In one embodiment, the pixel circuit may include a semiconductor layer, and a first gate electrode disposed on the semiconductor layer and electrically connected to a first node, a first transistor electrically connected between a driving voltage line and a second node, a second transistor electrically connected between the first node and a data line, a capacitor including a second electrode electrically connected between the first node and the second node, a third transistor electrically connected between the first node and the first voltage line, a fourth transistor connected between the second node and a third node to which a pixel electrode of the light-emitting diode is electrically connected, and a fifth transistor electrically connected between the third node and the second voltage line.

[0020] In one embodiment, the voltage line may be one of the first voltage line and the second voltage line.

[0021] In one embodiment, the pixel circuit further includes a sixth transistor electrically connected between the second node and a third voltage line, wherein the voltage line may be any one of the first voltage line, the second voltage line, and the third voltage line.

[0022] In one embodiment, the semiconductor layer may include an oxide semiconductor material.

[0023] In one embodiment, the display panel further includes a second connection line electrically connecting the light emitting diode and the pixel circuit or the repair line, and when the second connection line is electrically connected to the repair line, the first connection line is cut so that the repair line and the voltage line can be electrically separated.

[0024] In one embodiment, the first connecting line may comprise a conductive oxide.

[0025] In one embodiment, the first connecting line comprises a metal, and the thickness of the first connecting line may be less than or equal to about 1,000 Å.

[0026] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0027] According to one embodiment of the present invention, which is achieved as described above, a display device and an electronic device including a repair pixel circuit can be implemented. Of course, the scope of the present invention is not limited by these effects.

[0028] FIG. 1 is a perspective view schematically illustrating a display panel according to one embodiment of the present invention.

[0029] FIG. 2 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0030] FIG. 3A is a drawing schematically illustrating a portion of a display panel according to one embodiment of the present invention.

[0031] FIG. 3b is a schematic diagram for explaining a method of repairing a defective pixel in the display panel illustrated in FIG. 3a.

[0032] FIG. 4a is an equivalent circuit diagram schematically showing a repair circuit and one pixel according to one embodiment of the present invention.

[0033] FIG. 4b is a schematic diagram illustrating a method for repairing a defective pixel in a display panel according to one embodiment of the present invention.

[0034] FIG. 5a and FIG. 5b are equivalent circuit diagrams schematically showing a repair circuit and a pixel according to one embodiment of the present invention, respectively.

[0035] FIG. 6A is a cross-sectional view schematically illustrating a display panel according to one embodiment of the present invention.

[0036] FIG. 6b is a cross-sectional view illustrating a method for repairing a defective pixel in the display panel illustrated in FIG. 6a.

[0037] FIG. 7 is a schematic plan view of a portion of a display panel according to one embodiment of the present invention.

[0038] FIG. 8A is a cross-sectional view schematically illustrating a display panel according to one embodiment of the present invention.

[0039] FIG. 8b is a schematic cross-sectional view illustrating a method for repairing a defective pixel in the display panel illustrated in FIG. 8a.

[0040] FIG. 9 is a cross-sectional view schematically illustrating a display panel according to one embodiment of the present invention.

[0041] FIG. 10 is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention.

[0042] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0044] In this specification, the terms "first" and "second" are not used in a limiting sense, but rather to distinguish one component from another. For example, referring to a first component as a second component, or a second component as a first component, is understood to be within the scope disclosed herein.

[0045] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0046] In this specification, terms such as “include” or “have” mean that a feature, step, or component described in the specification exists, and do not preclude the possibility that one or more other features, steps, or components may be added.

[0047] In this specification, when it is said that a part such as a film, region, or component is on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

[0048] In this specification, the term "overlapping" between two components refers to a case where the first component is positioned above or below the second component. Furthermore, the term "overlapping" may be interpreted by those skilled in the art as other appropriate terms, such as "covering," "covering," or "partially covering."

[0049] The terms "facing" or "opposing" indicate a case where a first element directly or indirectly faces a second element. For example, a third element may intervene between the first and second elements, in which case the first and second elements may be understood to face each other but indirectly face each other. When one element is described as not overlapping or non-overlapping with another element, this may be understood by those skilled in the art to mean that the two elements are spaced apart from each other or are offset by other appropriate terms.

[0050] In this specification, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0051] In this specification, the x-axis, y-axis, and z-axis are not limited to the three axes on the orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0052] In some embodiments of this specification, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0053] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0054] As used herein, "about" or "approximately" includes the disclosed value and means within an acceptable range of deviation for the measurement value as determined by one of ordinary skill in the art, taking into account the disclosed value and the errors associated with a particular measurement (i.e., limitations of the measurement system). For example, "about" means within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0055] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0056] FIG. 1 is a perspective view schematically illustrating a display panel according to one embodiment of the present invention, and FIG. 2 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0057] Referring to FIG. 1, a display panel (1) may include a display area (DA) for displaying an image and a peripheral area (PA) outside the display area (DA). The display area (DA) may be entirely surrounded by the peripheral area (PA).

[0058] When the display area (DA) is viewed as a planar shape, the display area (DA) may have a rectangular shape. In other embodiments, the display area (DA) may have a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have rounded corners at its edges.

[0059] Referring to Fig. 2, the display panel (1) may include a plurality of pixels (P) arranged in the display area (DA). The plurality of pixels (P) may be arranged in a stripe arrangement, a pentile arrangement, TMThe pixels (P) can be arranged in various forms such as an array (diamond array), a mosaic array, etc. to implement an image. Each pixel (P) includes a light-emitting element (e.g., a light-emitting diode), and the light-emitting element can be electrically connected to a pixel circuit. In one embodiment, each pixel (P) can emit light of a different color. In one embodiment, each of the pixels (P) can emit red, green, or blue light. In another embodiment, each of the pixels (P) can emit red, green, blue, or white light. The display panel (1) can express an image using the light emitted from the pixels (P). Each pixel circuit can be electrically connected to a gate line (GL), a voltage line (VL), and a data line (DL), and can include a plurality of transistors and at least one capacitor.

[0060] Repair pixels (RP) may be arranged in the peripheral area (PA). Each of the repair pixels (RP) may include a repair circuit, but may not include a light-emitting element. Each repair circuit may be electrically connected to a gate line (GL), a voltage line (VL), and a repair data line (DLr), and may have a configuration substantially identical to or similar to the pixel circuit of the pixel (P).

[0061] The peripheral area (PA) may include a first peripheral area (PA1) and a second peripheral area (PA2) that are arranged facing each other with the display area (DA) therebetween. In one embodiment, the repair pixels (RP) may include first repair pixels (RP1) arranged in the first peripheral area (PA1) and second repair pixels (RP2) arranged in the second peripheral area (PA2). The repair data lines (DLr) may include a first repair data line (DLr1) arranged in the first peripheral area (PA1) and a second repair data line (DLr2) arranged in the second peripheral area (PA2). The first repair pixels (RP1) may be electrically connected to the first repair data line (DLr1), and the second repair pixels (RP2) may be electrically connected to the second repair data line (DLr2).

[0062] Data lines (DL) extend in a second direction (e.g., y direction) from the display area (DA) and can transmit data signals to connected pixels (P). A first repair data line (DLr1) extends in a second direction (e.g., y direction) from a first peripheral area (PA1) and can transmit a first repair data signal to the first repair pixels (RP1). A second repair data line (DLr2) extends in a second direction (e.g., y direction) from a second peripheral area (PA2) and can transmit a second repair data signal to the second repair pixels (RP2).

[0063] Gate lines (GL) and voltage lines (VL) can extend in a first direction (e.g., x direction) and be connected to pixels (P) and repair pixels (RP) located in the same row. Each of the gate lines (GL) can transmit a gate signal to the connected pixels (P) and repair pixels (RP).

[0064] Each of the voltage lines (VL) can transmit a constant voltage to the connected pixels (P) and repair pixels (RP). In one embodiment, the constant voltage transmitted by the voltage line (VL) may be an initialization voltage for initializing nodes of each of the pixel circuits and repair circuits. In another embodiment, the constant voltage transmitted by the voltage line (VL) may be a common voltage applied to the opposite electrode of the light-emitting element.

[0065] The display panel (1) may further include repair lines (RPL) extending in a first direction (e.g., x direction) from the peripheral area (PA) to the display area (DA). The repair lines (RPL) may be arranged so as to be connectable to light-emitting elements of pixels (P) arranged in the same row as any one repair pixel (RP). Here, the repair line (RPL) being 'connectable' to the light-emitting elements of the repair pixel (RP) and the pixel (P) refers to a state in which the repair line (RPL) is not connected to the repair pixel (RP) and the pixel (P), but can be connected through a repair process. When the repair line (RPL) is not connected to the light-emitting elements of the repair pixel (RP) and the pixel (P), the repair line (RPL) may be electrically connected to the voltage line (VL). In FIG. 2, the repair line (RPL) and the voltage line (VL) are arranged adjacent to each other, but the present invention is not limited thereto. In one embodiment, the repair line (RPL) may overlap the voltage line (VL) in a plane.

[0066] The peripheral area (PA) may include various conductive lines that transmit electrical signals to be applied to the display area (DA), peripheral circuits electrically connected to pixel circuits, and pads to which printed circuit boards or driver IC chips are attached. For example, the peripheral area (PA) may include a gate driving circuit, a data driving circuit, a power supply circuit, and a controller.

[0067] During the manufacturing process, some pixel circuits may be damaged, resulting in defective pixels such as bright spots that are brighter than adjacent pixels (P) on the display panel (1) or dark spots that are darker than adjacent pixels (P). In this case, the light-emitting element of the defective pixel can be electrically connected to a repair pixel (RP) through a repair line (RPL) to operate normally.

[0068] In one embodiment, the repair lines (RPL) may include left (e.g., in the -x direction) repair lines (RPLa) extending from the first peripheral area (PA1) toward an imaginary center line (CL) that bisects the display area (DA), and right (e.g., in the +x direction) repair lines (RPLb) extending from the second peripheral area (PA2) toward the imaginary center line (CL). The left (e.g., in the -x direction) repair line (RPLa) and the right repair line (RPLb) positioned in the same row may be spaced apart in the first direction (e.g., in the x direction). A light-emitting element of a defective pixel positioned to the left with respect to the imaginary center line (CL) may be electrically connected to the first repair pixel (RP1) through the corresponding left repair line (RPLa). The light emitting element of a defective pixel located to the right (+x direction) with respect to the virtual center line (CL) can be electrically connected to a second repair pixel (RP2) through a corresponding right repair line (RPLb).

[0069] In one embodiment, the first repair pixel (RP1) and the first repair data line (DLr1) may be omitted, or the second repair pixel (RP2) and the second repair data line (DLr2) may be omitted. In this case, the repair line (RPL) may be provided integrally so as to cross the display area (DA) rather than being positioned to the left and right of the imaginary center line (CL).

[0070] In FIG. 2, pixels (P) and repair pixels (RP) arranged in the same row are shown as being connected to one gate line (GL), but this is merely exemplary, and pixels (P) and repair pixels (RP) arranged in the same row are connected to two or more gate lines, and the gate driving circuit can supply two or more gate signals having different timings for applying the on voltage to the corresponding gate lines.

[0071] FIG. 3a is a drawing schematically illustrating a portion of a display panel according to one embodiment of the present invention, and FIG. 3b is a drawing for explaining a method of repairing a defective pixel in the display panel illustrated in FIG. 3a.

[0072] Referring to FIG. 3A, a display panel (1, see FIG. 1) includes a plurality of pixels arranged in a display area (DA) and a plurality of repair pixels arranged in a peripheral area (PA). For ease of understanding, only six pixels and two repair pixels are illustrated in FIGS. 3A and 3B, but the present invention is not limited thereto. In the display area (DA), m×n pixels may be arranged, for example, in a matrix, and in the peripheral area (PA), m repair pixels may be arranged along a column direction (e.g., a second direction or a y direction). In one embodiment, m repair pixels may be arranged along the column direction on each of both sides of the display area (DA).

[0073] A pixel located in the i-th row and the j-th column may include a light-emitting diode (LEDij) as a light-emitting element and a pixel circuit (PCij) connected to the light-emitting diode (LEDij). A repair pixel located in the i-th row may include a repair circuit (RPCi). Here, i is a natural number greater than or equal to 1 and less than or equal to m, and j is a natural number greater than or equal to 1 and less than or equal to n.

[0074] Each of the data lines (DL1, DL2, DL3 ... DLn) can extend in a second direction (e.g., y direction) to transmit data signals to pixel circuits (PC) located in the same column. The repair data line (DLr) can extend in a second direction (e.g., y direction) to transmit repair data signals to repair circuits (RPC). Each of the gate lines (GL1, GL2 ... GLm) can extend in a first direction (e.g., x direction) to transmit scan signals to pixel circuits (PC) and repair circuits (RPC) located in the same row. The pixel circuit (PCij) located in the i-th row and the j-th column is connected to the gate line (GLi) and the data line (DLj). The repair circuit (RPCi) located in the i-th row is connected to the gate line (GLi) and the repair data line (DLr). Each of the m voltage lines (VL) extends in a first direction (e.g., x direction) and can transmit a constant voltage to pixel circuits (PC) and repair circuits (RPC) located in the same row.

[0075] Each of the m repair lines (RPL) extends in a first direction (e.g., x direction) and can be electrically connected to a voltage line (VL) via first connection lines (CNL1). The first connection line (CNL1) can include a first-first connection line (CNL1_1) connecting the first repair line (RPL1) to the voltage line (VL) and a first-second connection line (CNL1_2) connecting the second repair line (RPL2) to the voltage line (VL).

[0076] Repair lines (RPL) may be arranged adjacent to or partially overlapping with components and signal lines of a pixel circuit (PC). As a comparative example, when the repair lines are not electrically connected to a voltage line and are in a floating state, a deterioration in image quality, such as a stain, may occur on the display panel due to parasitic capacitance generated between adjacent components and the repair lines. Embodiments of the present invention can reduce the parasitic capacitance between the repair lines (RPL) and adjacent components by electrically connecting the repair lines (RPL) that are not connected to a defective pixel to the voltage line (VL) through the first connection line (CNL1).

[0077] The pixel circuit (PCij) may be electrically connected to the light-emitting diode (LEDij) via the second connection line (CNL2). The pixel circuit (PCij) may include a driving transistor that controls the amount of current flowing to the light-emitting diode (LEDij) based on a data signal. Since the light-emitting diode (LEDij) emits light with a brightness corresponding to the amount of current received from the driving transistor, each pixel can express a grayscale corresponding to the data signal.

[0078] The third connection line (CNL3) may be arranged to be able to connect a repair circuit (RPCi) and a corresponding repair line (RPLi). For example, the third connection line (CNL3) may include a third-first connection line (CNL3_1) connecting the first repair circuit (RPC1) and the first repair line (RPL1), and a third-second connection line (CNL3_2) connecting the second repair circuit (RPC2) and the second repair line (RPL2). The third-first connection line (CNL3_1) overlaps the first repair line (RPL1) in a plane, but at least one insulating layer may be interposed between the third-first connection line (CNL3_1) and the first repair line (RPL1). Therefore, the third-first connection line (CNL3_1) and the first repair line (RPL1) may be electrically isolated. Likewise, the third-second connection line (CNL3_2) and the second repair line (RPL2) can be electrically isolated.

[0079] Referring to Fig. 3b, a defect may occur in a pixel circuit of any one of a plurality of pixels. Fig. 3b assumes that a defect has occurred in the pixel circuit (PC13, hereinafter referred to as a defective pixel circuit) of the first row and third column, and describes a method for repairing the defective pixel.

[0080] The light emitting diode (LED13) of the defective pixel can be electrically separated from the defective pixel circuit (PC13) and electrically connected to the first repair line (RPL1). For example, a part of the second connection line (CNL2) electrically connecting the light emitting diode (LED13) of the defective pixel and the defective pixel circuit (PC13) can be cut, and the second connection line (CNL2) and the first repair line (RPL1) can be connected. The cutting of the second connection line (CNL2) and the connection of the second connection line (CNL2) and the first repair line (RPL1) can be performed by irradiating a laser.

[0081] A repair circuit (RPC) of a repair pixel located in the same row as a defective pixel may be connected to a repair line (RPL). For example, a first repair circuit (RPC1) may be electrically connected to a first repair line (RPL1) via a third-first connection line (CNL3_1). At this time, a part of the first-first connection line (CNL1_1) may be cut, and the first repair line (RPL1) may be electrically separated from the voltage line (VL). The connection of the third-first connection line (CNL3_1) and the first repair line (RPL1) and the cutting of the first-first connection line (CNL1_1) may be performed by irradiating a laser. The cutting of the second connection line (CNL2), the connection of the second connection line (CNL2) and the first repair line (RPL1), the connection of the third-first connection line (CNL3_1) and the first repair line (RPL1), and the cutting of the first-first connection line (CNL1_1) may be performed simultaneously or in separate processes. Even after the repair process, the second repair line (RPL2) in which no defective pixels are located in the corresponding pixel row may be electrically connected to the voltage line (VL) via the first-second connection line (CNL1_2).

[0082] The first repair circuit (RPC1) may include a driving transistor that controls the amount of current based on a data signal, similar to the pixel circuits (PC). The repair data line (DLr) transmits a data signal corresponding to the defective pixel circuit (PC13) to the first repair circuit (RPC1), and the light-emitting diode (LED13) may emit light with a brightness corresponding to the amount of current received from the first repair circuit (RPC1) through the first repair line (RPL1).

[0083] FIG. 4a is an equivalent circuit diagram schematically showing a repair pixel and a single pixel according to one embodiment of the present invention.

[0084] Referring to FIG. 4A, a repair pixel (RP) may include a repair circuit (RPC), and a pixel (P) may include a pixel circuit (PC) and a light emitting diode (LED). The repair pixel (RP) and the pixel (P) located in the same row may be connected to the same gate lines (GWL, GRL, GIL, EML, EMBL) and voltage lines (VL1, VL2, VL3). The repair circuit (RPC) may have a configuration substantially the same as or similar to that of the pixel circuit (PC). Hereinafter, the same or similar configuration will be described with a focus on the pixel circuit (PC).

[0085] A pixel circuit (PC) can be electrically connected to a first gate line (GWL) that transmits a first gate signal (GW), a second gate line (GRL) that transmits a second gate signal (GR), a third gate line (EML) that transmits a third gate signal (EM), a fourth gate line (GIL) that transmits a fourth gate signal (GI), a fifth gate line (EMBL) that transmits a fifth gate signal (EMB), and a data line (DL) that transmits a data signal (DATA). Since the light emission of a light emitting diode (LED) is controlled by the third gate signal (EM) and the fifth gate signal (EMB), the third gate signal (EM) and the fifth gate signal (EMB) can be represented as light emission control signals, and the third gate line (EML) and the fifth gate line (EMBL) can be represented as light emission control lines. The pixel circuit (PC) can be electrically connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a first voltage line (VL1) that transmits a reference voltage (Vref), a second voltage line (VL2) that transmits a first initialization voltage (Vaint), and a third voltage line (VL3) that transmits a second initialization voltage (Vint).

[0086] In one embodiment, the plurality of transistors included in the pixel circuit (PC) may be N-type oxide transistors. An oxide transistor may be a transistor in which a semiconductor layer includes an oxide.

[0087] The pixel circuit (PC) may include first to seventh transistors (T1, T2, T3, T4, T5, T6, T7), a first capacitor (C1), and a second capacitor (C2). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal (DATA), and the second to seventh transistors (T2, T3, T4, T5, T6, T7) may be switching transistors that transmit signals. The first terminal (or first electrode) and the second terminal (or second electrode) of each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be a source (or source electrode) or a drain (or drain electrode) depending on the voltage of the first terminal and the second terminal. For example, depending on the voltages of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the first gate electrode of the first transistor (T1) is connected may be defined as a first node (N1), and the node to which the second terminal of the first transistor (T1) is connected may be defined as a second node (N2).

[0088] The first transistor (T1) may be connected to a driving voltage line (PL) and a light emitting diode (LED). The first transistor (T1) may be connected between the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) may include a gate (hereinafter, a first gate electrode) connected to a first node (N1), a first terminal, and a second terminal connected to a second node (N2). The first transistor (T1) may further include a lower gate connected to the second node (N2).

[0089] A first terminal of a first transistor (T1) may be connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal may be connected to a pixel electrode of a light-emitting diode (LED) via a sixth transistor (T6). The first transistor (T1) may receive a data signal (DATA) according to a switching operation of the second transistor (T2) and control the amount of driving current flowing to the light-emitting diode (LED).

[0090] The second transistor (T2) may be connected between the data line (DL) and the first node (N1). The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on by the first gate signal (GW) transmitted to the first gate line (GWL) and may transmit the data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0091] A third transistor (T3) may be connected between a first node (N1) and a first voltage line (VL1). The third transistor (T3) may include a gate connected to a second gate line (GRL), a first terminal connected to the first node (N1), and a second terminal connected to the first voltage line (VL1). The third transistor (T3) may be turned on by a second gate signal (GR) transmitted to the second gate line (GRL) and may transmit a reference voltage (Vref) transmitted to the first voltage line (VL1) to the first node (N1).

[0092] The fourth transistor (T4) may be connected between the third node (N3) and the second voltage line (VL2). The fourth transistor (T4) may include a gate connected to the fourth gate line (GIL), a first terminal connected to the third node (N3), and a second terminal connected to the second voltage line (VL2). The first terminal of the fourth transistor (T4) may be connected to a pixel electrode of a light-emitting diode (LED) via the third node (N3). The fourth transistor (T4) may be turned on by the fourth gate signal (GI) transmitted to the fourth gate line (GIL) and may transmit the first initialization voltage (Vaint) transmitted to the second voltage line (VL2) to the third node (N3), thereby initializing the pixel electrode (e.g., anode) of the light-emitting diode (LED).

[0093] The fifth transistor (T5) may be connected to the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the third gate line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a third gate signal (EM) transmitted to the third gate line (EML).

[0094] The sixth transistor (T6) may be connected between the second node (N2) and the third node (N3). The sixth transistor (T6) may include a gate connected to the fifth gate line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The sixth transistor (T6) may be turned on or off according to the fifth gate signal (EMB) transmitted to the fifth gate line (EMBL).

[0095] The seventh transistor (T7) may be connected between the second node (N2) and the third voltage line (VL3). The seventh transistor (T7) may include a gate connected to the fourth gate line (GIL), a first terminal connected to the second node (N2), and a second terminal connected to the third voltage line (VL3). The seventh transistor (T7) may be turned on by the fourth gate signal (GI) transmitted to the fourth gate line (GIL) and may transmit the second initialization voltage (Vint) transmitted to the third voltage line (VL3) to the second node (N2).

[0096] In one embodiment, the second initialization voltage (Vint) and the first initialization voltage (Vaint) may be the same voltage. In this case, the second terminal of the seventh transistor (T7) is connected to the second voltage line (VL2), and the third voltage line (VL3) may be omitted.

[0097] A first capacitor (C1) may be connected between a first node (N1) and a second node (N2). For example, a first electrode of the first capacitor (C1) may be connected to the first node (N1), and a second electrode may be connected to the second node (N2). The first capacitor (C1) may function as a storage capacitor and may store a voltage corresponding to a threshold voltage of the first transistor (T1) and a data signal (DATA).

[0098] When the third transistor (T3) and the fifth transistor (T5) are turned on, the first transistor (T1) can be turned on. When the voltage of the second node (N2) drops to the difference (Vref-Vth1) between the reference voltage (Vref) and the threshold voltage (Vth1) of the first transistor (T1), the first transistor (T1) is turned off, and a voltage corresponding to the threshold voltage (Vth1) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth1) of the first transistor (T1) can be compensated.

[0099] A second capacitor (C2) may be connected between a driving voltage line (PL) and a second node (N2). A first electrode of the second capacitor (C2) may be connected to the driving voltage line (PL), and a second electrode of the second capacitor (C2) may be connected to the second node (N2).

[0100] The capacitance of each of the first capacitor (C1) and the second capacitor (C2) may vary depending on the color of light emitted from the light-emitting diode (LED).

[0101] A light emitting diode (LED) may be connected to a third node (N3) via a second connection line (CNL2). The light emitting diode (LED) may include a pixel electrode (anode) connected to the second connection line (CNL2) and a counter electrode (cathode) facing the pixel electrode. The counter electrode may receive a common voltage (ELVSS) via a common voltage line (VSSL). A driving current output by a first transistor (T1) flows to the light emitting diode (LED) by a turned-on fifth transistor (T5) and a turned-on sixth transistor (T6), and the light emitting diode (LED) may emit light with a brightness corresponding to the magnitude of the driving current.

[0102] The repair pixels (RP) and pixels (P) located in the same row can be connected to the same second voltage line (VL2). The repair line (RPL) can be arranged so as to be connectable to the repair circuit (RPC) and the light-emitting diodes (LEDs) of each of the pixels (P). For example, the repair line (RPL) can overlap the second connection line (CNL2) and the third connection line (CNL3) on a plane. At least one insulating layer can be arranged between the repair line (RPL) and the second connection line (CNL2) and between the repair line (RPL) and the third connection line (CNL3). Therefore, the repair line (RPL) can be electrically isolated from the repair circuit (RPC) and the light-emitting diodes (LED) in an initial state before a repair process. At this time, the repair line (RPL) is electrically connected to the second voltage line (VL2) through the first connection line (CNL1) to receive the first initialization voltage (Vaint).

[0103] In one embodiment, the first initialization voltage (Vaint) transmitted to the pixel circuit (PC) may vary depending on the color of light emitted from the light emitting diode (LED) of the pixel (P). In this case, a plurality of second voltage lines (VL2) may be provided depending on the color of light emitted by the pixels (P), and the repair line (RPL) may be electrically connected to any one of the plurality of second voltage lines (VL2) via the first connection line (CNL1).

[0104] Although FIG. 4A illustrates that each of the pixel circuit (PC) and the repair circuit (RPC) includes seven transistors, the present invention is not limited thereto. In another embodiment, the pixel circuit (PC) and the repair circuit (RPC) may include six transistors. For example, the seventh transistor (T7) may be omitted. In another embodiment, the number of transistors in the pixel circuit (PC) and the repair circuit (RPC) may be five or less, or eight or more.

[0105] FIG. 4b is a drawing for explaining a method of repairing a defective pixel in a display panel according to one embodiment of the present invention.

[0106] Referring to FIG. 4b, a defect may occur in the pixel circuit of any one of the pixels located in the same row as the repair pixel (RP). Hereinafter, a pixel in which a defect occurs in the pixel circuit is referred to as a defective pixel (P').

[0107] A portion of the second connection line (CNL2) connecting the pixel circuit (PC) of a defective pixel (P') and the light emitting diode (LED) can be cut to electrically isolate the pixel circuit (PC) and the light emitting diode (LED). At this time, another portion of the second connection line (CNL2) can be connected to the repair line (RPL).

[0108] The repair circuit (RPC) can be electrically connected to a first gate line (GWL) that transmits a first gate signal (GW), a second gate line (GRL) that transmits a second gate signal (GR), a third gate line (EML) that transmits a third gate signal (EM), a fourth gate line (GIL) that transmits a fourth gate signal (GI), a fifth gate line (EMBL) that transmits a fifth gate signal (EMB), and a repair data line (DLr) that transmits a repair data signal (DATAr).

[0109] When the second connection line (CNL2) is connected to the repair line (RPL), the third node (N3) of the repair circuit (RPC) can be connected to the repair line (RPL) via the third connection line (CNL3). In addition, the first connection line (CNL1) connecting the repair line (RPL) and the second voltage line (VL2) can be cut, so that the driving voltage line (PL) and the second voltage line (VL2) can be electrically separated. The first transistor (T1) of the repair circuit (RPC) can receive a repair data signal (DATAr) according to the switching operation of the second transistor (T2) and control the current amount of the driving current flowing to the repair line (RPL).

[0110] Figures 5a and 5b are equivalent circuit diagrams schematically showing a repair circuit and a pixel according to an embodiment of the present invention, respectively. Figures 5a and 5b are similar to Figure 4a, but voltage lines electrically connected through the repair line (RPL) and the first connection line (CNL1) may be different. Hereinafter, redundant descriptions of identical components will be omitted, and the differences will be described.

[0111] Referring to FIGS. 5A and 5B, the repair pixels (RP) and pixels (P) located in the same row can be connected to the same gate lines (GWL, GRL, GIL, EML, EMBL) and voltage lines (VL1, VL2, VL3). For example, the repair line (RPL) can overlap the second connection line (CNL2) and the third connection line (CNL3) on a plane. At least one insulating layer can be disposed between the repair line (RPL) and the second connection line (CNL2) and between the repair line (RPL) and the third connection line (CNL3). Therefore, the repair line (RPL) can be electrically isolated from the repair circuit (RPC) and the light emitting diode (LED) in an initial state before the repair process.

[0112] The repair line (RPL) can be electrically connected to any one of the voltage lines that transmit a constant voltage to the pixel circuit (PC) and the repair circuit (RPC) via the first connection line (CNL1). Here, the constant voltage can be a voltage that is lower than the driving voltage (ELVDD) and equal to or higher than the common voltage (ELVSS). The constant voltage can be a reference voltage (Vref), a first initialization voltage (Vaint), a second initialization voltage (Vint), or a common voltage (ELVSS).

[0113] In one embodiment, as illustrated in FIG. 5A, the repair line (RPL) may be electrically connected to a third voltage line (VL3) via a first connection line (CNL1) to receive a second initialization voltage (Vint). The third voltage line (VL3) may be connected to a seventh transistor (T7) of each of the pixel circuit (PC) and the repair circuit (RPC). The second initialization voltage (Vint) may be transmitted to the second node (N2) to initialize the second node (N2) when the seventh transistor (T7) is turned on by a fourth gate signal (GI) transmitted to the fourth gate line (GIL).

[0114] Depending on the color of light emitted from the light emitting diode (LED) of the pixel (P), the second initialization voltage (Vint) transmitted to the pixel circuit (PC) may vary. In this case, a plurality of third voltage lines (VL3) may be provided depending on the color of light emitted from the pixels (P), and the repair line (RPL) may be electrically connected to any one of the plurality of third voltage lines (VL3) via the first connection line (CNL1).

[0115] In another embodiment, as illustrated in FIG. 5b, the repair line (RPL) may be electrically connected to the first voltage line (VL1) via the first connection line (CNL1) to receive a reference voltage (Vref). The first voltage line (VL1) may be connected to the third transistor (T3) of each of the pixel circuit (PC) and the repair circuit (RPC). The reference voltage (Vref) may be transmitted to the first node (N1) to initialize the first node (N1) when the third transistor (T3) is turned on by the second gate signal (GR) transmitted to the second gate line (GRL).

[0116] In another embodiment, the repair line (RPL) may be electrically connected to the common voltage line (VSSL) via the first connection line (CNL1). The common voltage line (VSSL) may be a wire that is arranged in the display area (DA) and extends in the first direction (e.g., the x direction) and transmits the common voltage (ELVSS) to the opposite electrode of the light emitting diode (LED).

[0117] FIG. 6a is a cross-sectional view schematically illustrating a display panel according to one embodiment of the present invention, and FIG. 6b is a cross-sectional view for explaining a method of repairing a defective pixel in the display panel illustrated in FIG. 6a.

[0118] Referring to FIGS. 6A and 6B, the display panel (1) includes a display area (DA) and a peripheral area (PA). Pixel circuits (PC) and light-emitting diodes (LEDs) electrically connected to the pixel circuits (PC) may be arranged in the display area (DA), and repair circuits (RPCs) may be arranged in the peripheral area (PA). The peripheral area (PA) may be a non-display area in which light-emitting diodes (LEDs) are not arranged.

[0119] The pixel circuit (PC) may include a first thin-film transistor (TFT1), and the repair circuit (RPC) may include a second thin-film transistor (TFT2). In one embodiment, each of the first thin-film transistor (TFT1) and the second thin-film transistor (TFT2) may correspond to the sixth transistor (T6) described with reference to FIG. 4A.

[0120] The substrate (100) may include a glass material or a polymer resin. As an example, the substrate (100) may have a multilayer structure in which a base layer including a polymer resin and a barrier layer including an inorganic insulating material are alternately laminated. The base layer may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or the like. The barrier layer may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0121] The first insulating layer (101) may be disposed on the substrate (100). The first insulating layer (101) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0122] The repair line (RPL) may be disposed on the first insulating layer (101). The repair line (RPL) may extend from the peripheral area (PA) to the display area (DA). The repair line (RPL) may include a conductive material such as a metal, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials. In another embodiment, the repair line (RPL) may be disposed between the substrate (100) and the first insulating layer (101).

[0123] The second insulating layer (102) may be disposed on the repair line (RPL). The second insulating layer (102) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0124] The first thin-film transistor (TFT1) and the second thin-film transistor (TFT2) may be arranged on the second insulating layer (102). The first thin-film transistor (TFT1) and the second thin-film transistor (TFT2) may have substantially the same or similar structures. Hereinafter, the first thin-film transistor (TFT1) will be described.

[0125] The semiconductor layer (Act) may be disposed on the second insulating layer (102). The semiconductor layer (Act) may include a channel region, a source region and a drain region disposed on both sides of the channel region. The semiconductor layer (Act) may include at least one oxide selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer (Act) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc.

[0126] The gate electrode (GE) may be disposed on the semiconductor layer (Act) with the third insulating layer (103) interposed therebetween. A portion of the semiconductor layer (Act) that overlaps the gate electrode (GE) in a plane may function as a channel region. The gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials.

[0127] The third insulating layer (103) is a type of gate insulating layer and may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0128] The voltage line (VL) may be arranged on the repair line (RPL) so as to overlap with the repair line (RPL) on a plane. The voltage line (VL) may be arranged on a different layer from the repair line (RPL), but may be arranged on any one of the conductive layers arranged between the substrate (100) and the light emitting diode (LED). The voltage line (VL) may be any one of the voltage lines that transmit a constant voltage to the pixel circuit (PC) and the repair circuit (RPC). For example, the voltage line (VL) may be any one of the first voltage line (VL1), the second voltage line (VL2), and the third voltage line (VL3), as described with reference to FIGS. 4A, 5A, and 5B. Alternatively, the voltage line (VL) may be a common voltage line (VSSL).

[0129] Since the voltage line (VL) and the repair line (RPL) overlap on a plane, the area required for arranging the wires can be reduced, thereby implementing a high-resolution display panel (1). In one embodiment, the voltage line (VL) can be arranged on the second insulating layer (102) with the third insulating layer (103) therebetween. The voltage line (VL) can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and can include a single-layer or multi-layer structure including the aforementioned materials.

[0130] The fourth insulating layer (105) may be disposed on the voltage line (VL) and the gate electrode (GE). The fourth insulating layer (105) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0131] A source electrode (SE), a drain electrode (DE), a second connection line (CNL2), and a third connection line (CNL3) may be disposed on a fourth insulating layer (105). The source electrode (SE) may be connected to a source region of the semiconductor layer (Act), and the drain electrode (DE) may be connected to a drain region of the semiconductor layer (Act). In one embodiment, the source electrode (SE) of the first thin-film transistor (TFT1) may be formed integrally with the second connection line (CNL2), and the source electrode (SE) of the second thin-film transistor (TFT2) may be formed integrally with the third connection line (CNL3).

[0132] The second connection line (CNL2) may extend from the source electrode (SE) of the first thin film transistor (TFT1) so as to overlap the repair line (RPL) on a plane. At least one insulating layer, for example, a fourth insulating layer (105), may be disposed between the second connection line (CNL2) and the repair line (RPL). In one embodiment, the fourth insulating layer (105) may have a groove that is thinner in a region where the second connection line (CNL2) and the repair line (RPL) overlap than in a surrounding region.

[0133] The third connection line (CNL3) may extend from the source electrode (SE) of the second thin film transistor (TFT2) so as to overlap the repair line (RPL) on a plane. At least one insulating layer, for example, a fourth insulating layer (105), may be disposed between the third connection line (CNL3) and the repair line (RPL). In one embodiment, the fourth insulating layer (105) may have a groove that is thinner in a region where the third connection line (CNL3) and the repair line (RPL) overlap than in a surrounding region.

[0134] The source electrode (SE), drain electrode (DE), second connection line (CNL2), and third connection line (CNL3) may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials.

[0135] The fifth insulating layer (107) is disposed on the source electrode (SE), the drain electrode (DE), the second connection line (CNL2), and the third connection line (CNL3), and may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0136] A light emitting diode (LED) may include a pixel electrode (210), a counter electrode (230), and an intermediate layer (220) disposed between the pixel electrode (210) and the counter electrode (230). The intermediate layer (220) may further include a light emitting layer (222) disposed corresponding to the pixel electrode (210), and a first functional layer (221) and a second functional layer (223) disposed below and / or above the light emitting layer (222).

[0137] The pixel electrode (210) may be disposed on the fifth insulating layer (107). The pixel electrode (210) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the pixel electrode (210) may further include a conductive oxide layer on and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, the pixel electrode (210) may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0138] The bank layer (109) may be arranged on the pixel electrode (210). The bank layer (109) may include an opening that overlaps the pixel electrode (210), but may cover the edge of the pixel electrode (210). The opening of the bank layer (109) may define an emission area of ​​a light-emitting diode (LED).

[0139] The intermediate layer (220) may be disposed on the bank layer (109) and the pixel electrode (210). The intermediate layer (220) may include a light-emitting layer (222) disposed within an opening of the bank layer (109) corresponding to the pixel electrode (210). The light-emitting layer (222) may include a polymer or low-molecular organic material that emits light of a predetermined color.

[0140] A functional layer may be further included below and / or above the light-emitting layer (222). For example, a first functional layer (221) may be further included between the pixel electrode (210) and the light-emitting layer (222), and a second functional layer (223) may be further included between the light-emitting layer (222) and a counter electrode (230) to be described later. The first functional layer (221) may include a hole transport layer and / or a hole injection layer. The second functional layer (223) may include an electron transport layer and / or an electron injection layer.

[0141] The counter electrode (230) may be formed of a conductive material having a low work function. For example, the counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material. The counter electrode (230) may be formed in common to correspond to a plurality of pixel electrodes (210).

[0142] When the pixel circuit (PC) is a normal circuit, the light emitting diode (LED) can be electrically connected to the source electrode (SE) of the first thin film transistor (TFT1) through the second connection line (CNL2). For example, the pixel electrode (210) of the light emitting diode (LED) can be electrically connected to the second connection line (CNL2) through a contact hole penetrating the fifth insulating layer (107). The second connection line (CNL2) can be provided integrally with the source electrode (SE) of the first thin film transistor (TFT1). The voltage line (VL) can be electrically connected to the repair line (RPL) to transmit a constant voltage to the driving voltage line (PL).

[0143] The encapsulating layer (300) is disposed on a light-emitting diode (LED) and may include at least one inorganic encapsulating layer and at least one organic encapsulating layer. In one embodiment, FIG. 6A illustrates that the encapsulating layer (300) includes a first inorganic encapsulating layer (310), an organic encapsulating layer (320), and a second inorganic encapsulating layer (330).

[0144] The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may have a single layer or multilayer structure including the aforementioned materials. The organic sealing layer (320) may include a polymer-based material. Examples of polymer-based materials include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic sealing layer (320) may include acrylate.

[0145] Fig. 6b illustrates the connection relationship between the repair line (RPL), the second connection line (CNL2), and the third connection line (CNL3), assuming that a defect has occurred in the pixel circuit (PC). Referring to Fig. 6b, a portion of the second connection line (CNL2) connected to the source electrode (SE) of the first thin film transistor (TFT1) may be removed. Accordingly, the second connection line (CNL2) and the source electrode (SE) may be spaced apart from each other, and the second connection line (CNL2) and the pixel circuit (PC) may be electrically separated. A portion of the second connection line (CNL2) may be removed using a laser. At this time, a portion of the first connection line (CNL1) electrically connecting the repair line (RPL) to the voltage line (VL) may be removed, so that the repair line (RPL) and the voltage line (VL) may be electrically separated.

[0146] Each of the second connection line (CNL2) and the third connection line (CNL3) may be electrically connected to the repair line (RPL). For example, a laser may be irradiated from the back surface of the substrate (100) toward the lower surface of the second connection line (CNL2) and the lower surface of the third connection line (CNL3). The laser may form contact holes in the second insulating layer (102) and the fourth insulating layer (105), and heat and melt the second connection line (CNL2) and the third connection line (CNL3). The second connection line (CNL2) melted by the laser may be connected to the repair line (RPL) through the contact hole. Similarly, the third connection line (CNL3) melted by the laser may be connected to the repair line (RPL) through the contact hole. In one embodiment, the fourth insulating layer (105) may have a groove that overlaps each of the areas where the laser is irradiated, i.e., the area where the second connection line (CNL2) and the repair line (RPL) are connected and the area where the third connection line (CNL3) and the repair line (RPL) are connected.

[0147] A light emitting diode (LED) and a repair circuit (RPC) can be electrically connected via a second connection line (CNL2), a repair line (RPL), and a third connection line (CNL3). The light emitting diode (LED) can emit light with a brightness corresponding to the magnitude of the current received from the repair circuit (RPC).

[0148] FIG. 7 is a plan view schematically illustrating a portion of a display panel according to an embodiment of the present invention, and FIG. 8A is a cross-sectional view schematically illustrating a display panel according to an embodiment of the present invention. FIG. 8B is a cross-sectional view for explaining a method of repairing a defective pixel in the display panel illustrated in FIG. 8A. FIGS. 8A and 8B illustrate cross-sections taken along line Ⅲ-Ⅲ' of the display panel illustrated in FIG. 7.

[0149] Referring to FIGS. 7 and 8a, the display panel (1) includes a peripheral area (PA), and a voltage line (VL) and a repair line (RPL) may be arranged in the peripheral area (PA). The voltage line (VL) and the repair line (RPL) may extend from the peripheral area (PA) to the display area (DA) along a first direction (e.g., the x direction).

[0150] A first connection electrode (131) and a second connection electrode (133) may be placed between the substrate (100) and the first insulating layer (101). The first connection electrode (131) and the second connection electrode (133) may include a conductive material such as a metal, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material.

[0151] A first insulating layer (101) may be disposed on the first connecting electrode (131) and the second connecting electrode (133), and a third connecting electrode (135) and a repair line (RPL) may be disposed on the first insulating layer (101). The third connecting electrode (135) may be disposed on the same layer as the repair line (RPL), and the third connecting electrode (135) may include the same material as the repair line (RPL). The third connecting electrode (135) may be connected to the second connecting electrode (133) through a contact hole penetrating the first insulating layer (101), and the repair line (RPL) may be connected to the first connecting electrode (131) through a contact hole penetrating the first insulating layer (101).

[0152] A second insulating layer (102) may be disposed on the third connecting electrode (135) and the repair line (RPL), and a first connecting line (CNL1) may be disposed on the second insulating layer (102). One end of the first connecting line (CNL1) may be connected to the third connecting electrode (135) through a contact hole penetrating the second insulating layer (102), and the other end of the first connecting line (CNL1) may be connected to the repair line (RPL) through a contact hole penetrating the second insulating layer (102). In one embodiment, the first connecting line (CNL1) may be disposed on the same layer as the semiconductor layer (Act) described with reference to the drawings, and may include the same material. For example, the first connecting line (CNL1) may include at least one conductive oxide selected from the group consisting of indium (In), gallium (Ga), stannium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). The thickness of the first connecting line (CNL1) may be about 100 Å to about 200 Å. In one embodiment, the thickness of the first connecting line (CNL1) may be about 150 Å. The first connecting line (CNL1) may be made conductive by injecting impurities into the oxide or by plasma treatment.

[0153] The voltage line (VL) is disposed on a different layer from the repair line (RPL), but may be disposed on any one of the conductive layers disposed between the substrate (100) and the light emitting diode (LED). For example, as illustrated in FIGS. 8 a and 8b, the voltage line (VL) may be disposed on the second insulating layer (102) with the third insulating layer (103) interposed therebetween. The voltage line (VL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned materials.

[0154] On a plane, a voltage line (VL) can overlap a repair line (RPL). The voltage line (VL) and the repair line (RPL) extend in a first direction (e.g., the x direction), and the repair line (RPL) can have a shape corresponding to the shape of the voltage line (VL) and be arranged below the voltage line (VL). The voltage line (VL) can be electrically connected to the repair line (RPL) through the first to third connection electrodes (131, 133, 135) and the first connection line (CNL1) in the peripheral area (PA). Since the voltage line (VL) and the repair line (RPL) overlap on a plane, an area required for arranging wires can be reduced, thereby implementing a high-resolution display panel (1). Depending on the layer arrangement of the voltage line (VL) and the repair line (RPL), connection electrodes can be added or partially omitted.

[0155] Referring to Fig. 8b, a repair circuit (RPC) and a light-emitting diode (LED) of a defective pixel can be connected to a repair line (RPL) through a repair process as described with reference to Fig. 6b. A second connection line (CNL2) can be electrically separated from the pixel circuit (PC) and connected to the repair line (RPL), and a third connection line (CNL3) can be connected to the repair line (RPL). At this time, a part of the first connection line (CNL1) can be removed so that the voltage line (VL) and the repair line (RPL) can be electrically separated. For example, a laser can be irradiated to a cutting area (BR) between the first connection electrode (131) and the second connection electrode (133) so that a part of the first connection line (CNL1) can be removed.

[0156] Since the first connecting line (CNL1) is located in the peripheral area (PA), damage to surrounding pixels can be minimized or reduced during cutting. Furthermore, since the first connecting line (CNL1) includes a conductive oxide, it can be formed relatively thinly. Therefore, the first connecting line (CNL1) can be easily cut with a laser to electrically isolate the voltage line (VL) and the repair line (RPL).

[0157] Fig. 9 is a cross-sectional view schematically illustrating a display panel according to one embodiment of the present invention. Fig. 9 is similar to Fig. 8a, but differs in that the first connecting line (CNL1) includes metal.

[0158] Referring to FIG. 9, the first connecting line (CNL1) may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the first connecting line (CNL1) may be a single layer of aluminum. The first connecting line (CNL1) may have a first thickness (t1). The first thickness (t1) may be about 1,000 Å or less. As a comparative example, when the first thickness of the first connecting line exceeds about 1,000 Å, it may be difficult to cut the first connecting line by irradiating a laser.

[0159] In this embodiment, the first thickness (t1) of the first connection line (CNL1) is formed to be about 1,000 Å or less, so that the first connection line (CNL1) can be easily cut with a laser during a repair process to electrically separate the voltage line (VL) and the repair line (RPL).

[0160] FIG. 10 is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention.

[0161] Referring to FIG. 10, a display panel (1) is provided in an electronic device (2) to display moving images or still images or to input and output data. For example, the display panel (1) may be accommodated in a housing (3) of the electronic device (2). The housing (3) may be configured to protect components of the electronic device (2) and secure the display panel (1).

[0162] Although FIG. 10 illustrates that the electronic device (2) is a mobile phone, the present invention is not limited thereto. The electronic device (2) may be a portable electronic device such as a laptop, a tablet personal computer (PC), a mobile phone, a smart phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc.

[0163] Alternatively, the electronic device (2) may be an electronic device for a television, a monitor, a billboard, an Internet of Things (IOT), or a wearable electronic device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the electronic device (2) according to one embodiment may be an electronic device for a display placed on the back of a front seat, such as an instrument panel of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, or an entertainment device for the rear seats of a vehicle.

[0164] While the present invention has been primarily described with respect to display panels and electronic devices including them, it is not limited thereto. For example, a method for repairing defective pixels using such a display panel and a method for manufacturing a display panel are also within the scope of the present invention.

[0165] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and equivalent alternative embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. Pixel circuit arranged in the display area; A light emitting diode arranged in the above display area; A repair circuit arranged in a peripheral area outside the above display area; A repair line extending from the peripheral area to the display area along the first direction; a voltage line extending in the first direction; and A display panel, comprising a first connecting line electrically connecting the repair line and the voltage line.

2. In paragraph 1, The above pixel circuit is, A first transistor comprising a semiconductor layer and a first gate electrode disposed on the semiconductor layer and electrically connected to a first node, and electrically connected between a driving voltage line and a second node; A second transistor electrically connected between the first node and the data line; A capacitor including a second electrode electrically connected between the first node and the second node; A third transistor electrically connected between the first node and the first voltage line; A fourth transistor electrically connected between the second node and the third node to which the pixel electrode of the light-emitting diode is electrically connected; and A display panel, comprising a fifth transistor electrically connected between the third node and the second voltage line.

3. In paragraph 2, A display panel, wherein the voltage line is one of the first voltage line and the second voltage line.

4. In paragraph 2, The pixel circuit further includes a sixth transistor electrically connected between the second node and the third voltage line; A display panel, wherein the voltage line is any one of the first voltage line, the second voltage line, and the third voltage line.

5. In paragraph 2, The light emitting diode includes a pixel electrode, a common electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the common electrode, The above voltage line is a display panel that transmits a common voltage applied to the common electrode.

6. In paragraph 2, The semiconductor layer includes an oxide semiconductor material, A display panel in which the first connecting line and the semiconductor layer are arranged on the same layer.

7. In paragraph 2, Further comprising a first insulating layer disposed under the semiconductor layer; A display panel wherein the above repair line is positioned below the first insulating layer.

8. In paragraph 1, The display panel, wherein the first connecting line includes a conductive oxide.

9. In paragraph 1, The above first connecting line comprises metal, A display panel, wherein the thickness of the first connecting line is about 1,000 Å or less.

10. In paragraph 1, A display panel further comprising a second connecting line electrically connecting the pixel circuit or the repair line to the light-emitting diode.

11. In paragraph 10, Further comprising a third connecting line electrically connected to the above repair circuit and overlapping the above repair line; A display panel, wherein when the second connecting line is electrically connected to the repair line, the third connecting line is electrically connected to the repair line.

12. In paragraph 10, A display panel, wherein when the second connecting line is electrically connected to the repair line, the first connecting line is cut so that the repair line and the voltage line are electrically separated.

13. In the above paragraph 1, The above repair line overlaps the above voltage line on a plane, the display panel.

14. A display panel including a display area in which a plurality of pixels are arranged and a peripheral area outside the display area; The above display panel, A pixel circuit arranged in the above display area; A light emitting diode arranged in the above display area; A repair circuit arranged in the peripheral area outside the display area; A repair line extending from the peripheral area to the display area along the first direction; a voltage line extending in the first direction; and An electronic device comprising a first connecting line electrically connecting the repair line and the voltage line.

15. In paragraph 14, The above pixel circuit is, A first transistor comprising a semiconductor layer and a first gate electrode disposed on the semiconductor layer and electrically connected to a first node, and electrically connected between a driving voltage line and a second node; A second transistor electrically connected between the first node and the data line; A capacitor including a second electrode electrically connected between the first node and the second node; A third transistor electrically connected between the first node and the first voltage line; A fourth transistor electrically connected between the second node and the third node to which the pixel electrode of the light-emitting diode is electrically connected; and An electronic device comprising a fifth transistor connected between the third node and the second voltage line.

16. In paragraph 15, An electronic device wherein the voltage line is one of the first voltage line and the second voltage line.

17. In paragraph 15, The pixel circuit further includes a sixth transistor electrically connected between the second node and the third voltage line; An electronic device wherein the voltage line is any one of the first voltage line, the second voltage line, and the third voltage line.

18. In paragraph 15, An electronic device, wherein the semiconductor layer comprises an oxide semiconductor material.

19. In paragraph 14, The display panel further includes a second connection line electrically connecting the light-emitting diode and the pixel circuit or the repair line; An electronic device, wherein when the second connecting line is electrically connected to the repair line, the first connecting line is cut so that the repair line and the voltage line are electrically separated.

20. In paragraph 14, An electronic device wherein the first connecting line comprises a conductive oxide.

21. In paragraph 14, The above first connecting line comprises metal, An electronic device wherein the thickness of the first connecting line is about 1,000 Å or less.

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