Series-connected interleaved phase-shifted full-bridges with reduced number of output inductors and a method for performing DC-DC conversion

Abstract

The disclosure relates to a phase-shifted full-bridge, PSFB, DC-DC converter topology and a method to perform DC-DC conversion using such PSFB DC-DC converter topology. At least two cascaded primary full-bridge rectifiers are coupled to an AC power source, and output rails of each one of the at least two primary full-bridge rectifiers are coupled to a primary side of a different one of at least two isolation transformers. At least two cascaded secondary full-bridge rectifiers are coupled to the secondary side of a different one of the at least two isolation transformers. An output stage is coupled to a load between a positive output rail of a first one of the at least two secondary full-bridge rectifiers and a negative output rail of a second one of the at least two secondary full-bridge rectifiers. The output stage comprises at least one output capacitor configured to be coupled in parallel with the load, and at least one output inductor only coupled between output rails of each adjacent pair of said at least two cascaded secondary full-bridge rectifiers.

Description

[0001] SERIES-CONNECTED INTERLEAVED PHASE-SHIFTED FULL-BRIDGES WITH REDUCED NUMBER OF OUTPUT INDUCTORS AND A METHOD

[0002] FOR PERFORMING DC-DC CONVERSION

[0003] FIELD OF THE DISCLOSURE

[0004] The present disclosure relates to DC-DC converter topologies, and particularly to soft-switching DC-DC converter topologies. The present disclosure also concerns a method for performing a DC-DC conversion by a DC-DC converter topology.

[0005] BACKGROUND OF THE DISCLOSURE

[0006] There is a growing need to create more energy-efficient charging infrastructure systems around the world that can charge an increasing number of electric vehicles (EVs) faster than ever before. New EVs have higher ranges and larger battery capacities than their predecessors. This necessitating development of fast DC charging solutions to support quick charging requirements.

[0007] EV charging stations are fed by the grid. A DC charging station comprises an AC-DC power stage that converts AC power from the grid into DC, and a DC- DC converter that processes power and interfaces with the battery on the EV. Typical DC-DC converters typically apply n-channel MOSFETs (metal-oxide- semiconductor field-effect-transistors) for switching.

[0008] As known in the art, the PSFB DC-DC converter operates using pulse width modulation (PWM).

[0009] Phase-shifted full-bridge (PSFB) is one soft-switching DC-DC converter topology suitable for EV charging stations. The PSFB topology can achieve zerovoltage switching for one of the primary phase legs. The PSFB topology typically has an output inductor to limit output current ripple. The output inductor is usually connected to a positive DC rail of the output, between the positive DC rail and a load, or the output inductor may be split into two output inductors to enable placing the output inductor in both DC rails coupled to the load. In this context, the term "DC rails" refer to the two output nodes of an output full-bridge rectifier, the positive DC rail refers to the DC rail with higher output voltage, and the negative DC rail refers to the DC rail with lower output voltage.

[0010] Document "Design considerations for high-voltage high-power full-bridge zero- voltage-switched PWM converter," by J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee and B. H. Cho, discloses a PSFB.

[0011] Document "A 1 kW, 500 kHz front-end converter for a distributed power supply system," by L. H. Mweene, C. A. Wright and M. F. Schlecht discloses another PSFB.

[0012] Interleaved converters have been used to increase effective switching frequency and to feed an output inductor or inductors to decrease the amplitude of current ripple. One known solution has been using parallel connected PSFBs.

[0013] Document "An Interleaved Phase-Shift Full-Bridge Converter with Dynamic Dead Time Control for Server Power Applications" by J.-Y. Lee, J.-H. Chen and K.-Y. Lo discloses an example of known interleaved PSFB converter.

[0014] US 20050270806 Al discloses another known interleaved PSFB power converter.

[0015] KR20200072982A discloses a series-coupled high voltage power supply with mutually coupled transformers and series-coupled output rectifiers.

[0016] A problem with existing interleaved PSFB DC-DC converters is amplitude of current ripple. In high-voltage applications, for example in DC charging of electric vehicles, voltage tolerance of semiconductor devices also causes challenges. Although high-voltage tolerant semiconductor devices are available, they are expensive.

[0017] BRIEF DESCRIPTION OF THE DISCLOSURE

[0018] An object of the present disclosure is to provide a series-connected interleaved PSFB DC-DC converter topology and a method to perform DC-DC conversion by a PSFB DC-DC converter topology so as to solve the above problems.

[0019] The object of the disclosure is achieved by the PSFB DC-DC converter topology and by a method for performing DC-DC conversion by a PSFC BD-DC converter topology which are characterized by what is stated in the independent claims. Some embodiments of the disclosure are disclosed in the dependent claims.

[0020] The disclosure is based on the idea of coupling an output inductor between each two cascaded secondary full-bridge rectifiers. The output inductor is coupled between output rails of secondary rectifiers that are not coupled to the load, in other words between a negative output rail of a first secondary fullbridge rectifier and a positive output rail of a second secondary full-bridge rectifier.

[0021] According to some embodiments, a phase-shifted full-bridge, PSFB, DC-DC converter topology is provided. The PSFB DC-DC converter topology comprises at least two isolation transformers and at least two cascaded primary fullbridge rectifiers configured to be coupled to an AC power source between a positive input rail of a first one of the at least two cascaded primary full-bridge rectifiers and a negative input rail of a second one of the at least two cascaded primary full-bridge rectifiers. Output rails of each one of the at least two primary full-bridge rectifiers are coupled to a primary side of a different one of the at least two isolation transformers. Said cascading is implemented by mutual coupling of a negative input rail and a positive input rail of two adjacent ones of said at least two cascaded primary full-bridge rectifiers.

[0022] The PSFB DC-DC converter topology comprises at least two cascaded secondary full-bridge rectifiers. Input rails of each one of the at least two secondary full-bridge rectifiers are coupled to the secondary side of a different one of the at least two isolation transformers. The PSFB DC-DC converter topology comprises an output stage configured for coupling a load between a positive output rail of a first one of the at least two secondary full-bridge rectifiers and a negative output rail of a second one of the at least two secondary full-bridge rectifiers. The output stage comprises at least one output capacitor configured to be coupled in parallel with the load, and at least one output inductor only coupled between output rails of each adjacent pair of said at least two cascaded secondary full-bridge rectifiers.

[0023] According to some embodiments, the PSFB DC-DC converter topology further comprises at least two series-coupled input buffer capacitors. Each input buffer capacitor is coupled to input rails of one of the at least two cascaded primary full-bridge rectifiers.

[0024] According to some embodiments, the PSFB DC-DC converter topology includes two cascaded primary full-bridge rectifiers, two isolation transformers and two cascaded secondary full-bridge rectifiers. Mutually coupled input rails of the two cascaded primary full-bridge rectifiers are further configured to be coupled to a neutral point tap of the AC power source.

[0025] According to some embodiments, the at least one output inductor is implemented as two or more mutually parallel-coupled inductors.

[0026] According to some embodiments, the at least one output capacitor comprises at least two cascaded output capacitors. The number of cascaded output capacitors preferably equals to number of cascaded secondary full-bridge rectifiers.

[0027] According to some embodiments, each primary full-bridge rectifier is further provided with an input buffer capacitor coupled between the input rails of the respective full-bridge rectifier.

[0028] According to some embodiments, switching of the at least two cascaded primary full-bridge rectifiers is configured to be mutually interleaved by determining a phase-shift between operation cycles of the at least two cascaded primary full-bridge rectifiers.

[0029] According to some embodiments, the phase shift is implemented as a phase shift between pulse width modulation (PWM) cycles that control operation of the cascaded primary full-bridge rectifiers.

[0030] According to some embodiments, the amount and / or direction of phase-shift between operation cycles of the cascaded primary full-bridge rectifiers is controllable.

[0031] According to some embodiments, amount and / or direction of phase-shift between switching of individual phase-legs of one or more of the primary fullbridge rectifiers is controllable.

[0032] According to an embodiment, a method for performing DC-DC conversion by means of a phase-shifted full-bridge, PSFB, DC-DC converter topology is provided. The method comprises coupling at least two cascaded primary fullbridge rectifiers to an AC power source. The AC power source is coupled between a positive input rail of a first one of the at least two cascaded primary full-bridge rectifiers and a negative input rail of a second one of the at least two cascaded primary full-bridge rectifiers. Said cascading is implemented by mutual coupling of a negative input rail and a positive input rail of two adjacent ones of said at least two cascaded primary full-bridge rectifiers. The method comprises coupling output rails of each one of the at least two primary fullbridge rectifiers to a primary side of a different one of at least two isolation transformers. The method comprises coupling input rails of each one of the at least two secondary full-bridge rectifiers to a secondary side of a different one of the at least two isolation transformers. The method comprises coupling a load to an output stage of the PSFB DC-DC-converter topology. The load is coupled between a positive output rail of a first one of the at least two secondary full-bridge rectifiers and a negative output rail of a second one of the at least two secondary full-bridge rectifiers by coupling at least one output capacitor of the output stage in parallel with the load, and coupling at least one output inductor only between output rails of each adjacent pair of said at least two cascaded secondary full-bridge rectifiers.

[0033] According to some embodiments, the method further comprises coupling at least two series-coupled input buffer capacitors. Each input buffer capacitor is coupled to input rails of one of the at least two cascaded primary full-bridge rectifiers.

[0034] According to some embodiments, the PSFB DC-DC converter topology has two cascaded primary full-bridge rectifiers, two isolation transformers and two cascaded secondary full-bridge rectifiers, and the method further comprises coupling mutually coupled input rails of the two cascaded primary full-bridge rectifiers to a neutral point tap of the AC power source.

[0035] According to some embodiments, the method comprises implementing the at least one output inductor as two or more mutually parallel-coupled inductors.

[0036] According to some embodiments, said coupling the at least one output capacitor comprises coupling at least two cascaded output capacitors, wherein the number of cascaded output capacitors preferably equals to number of cascaded secondary full-bridge rectifiers.

[0037] According to some embodiments, the method comprises further providing each primary full-bridge rectifier with an input buffer capacitor coupled between the input rails of the respective full-bridge rectifier.

[0038] According to some embodiments, the method comprises mutually interleaving switching of the at least two cascaded primary full-bridge rectifiers by determining a phase-shift between operation cycles of the at least two cascaded primary full-bridge rectifiers.

[0039] According to some embodiments, the phase shift is implemented as a phase shift between pulse width modulation (PWM) cycles that control operation of the cascaded primary full-bridge rectifiers.

[0040] According to some embodiments, the method comprises controlling the amount and / or direction of phase-shift between operation cycles of the cascaded primary full-bridge rectifiers.

[0041] According to some embodiments, the method comprises controlling amount and / or direction of phase-shift between switching of individual phase-legs of one or more of the primary full-bridge rectifiers.

[0042] An advantage of cascading the PSFBs is that on the primary side, switches of the primary rectifiers can be implemented using semiconductor switches designed to operate with a voltage that is less than the source voltage. Likewise, on the secondary side, diodes or semiconductor switches of the secondary full-bridge rectifiers can be implemented using circuit elements designed to operate with voltages lower than the output voltage. Furthermore, amplitude ripple of the output current is decreased by interleaving waveforms received from both cascaded secondary full-bridge rectifiers and by inductors coupled between the cascaded secondary full-bridge rectifiers.

[0043] BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the following the disclosure will be described in greater detail by means of preferred embodiments with reference to the accompanying drawings, in which: Figure 1 illustrates a first phase-shifted full-bridge (PSFB) DC-DC converter topology;

[0045] Figure 2A illustrates a primary full-bridge;

[0046] Figure 2B illustrates a secondary full-bridge rectifier;

[0047] Figure 3 illustrates timings in a PSFB DC-DC converter topology;

[0048] Figure 4 illustrates a second PSFB DC-DC converter topology;

[0049] Figure 5 illustrates a third PSFB DC-DC converter topology;

[0050] Figure 6 illustrates a fourth PSFB DC-DC converter topology;

[0051] Figure 7 illustrates an alternative PSFB DC-DC converter topology; and

[0052] Figure 8 illustrates another alternative PSFB DC-DC converter topology.

[0053] DETAILED DESCRIPTION OF THE DISCLOSURE

[0054] The disclosure relates to PSFB DC-DC converters, and in particular to interleaved PSFB DC-DC converters.

[0055] In the given exemplary schematics, primary rectifier switches are implemented using n-channel MOSFETs. Alternatively, Insulated Gate Bipolar Transistors (IGBTs), silicon carbide MOSFETs (SiC MOSFETs) or Gallium Nitride High- Electron-Mobility Transistors (GaN HEMTs) can be used for primary bridge switching in some application fields.

[0056] In the exemplary schematics, secondary full-bridge rectifiers are implemented as diode bridges. Alternatively, actively switched secondary full-bridge rectifiers can be applied, preferably using MOSFETs.

[0057] Figure 1 illustrates a first embodiment of a phase-shifted full-bridge (PSFB) DC-DC converter topology. Figure 2A illustrates a primary full-bridge rectifier 10 and figure 2B illustrates a secondary full-bridge rectifier 14, showing further details of these elements of the topology and determining terminology used herein.

[0058] According to some embodiments, the PSFB DC-DC converter topology comprises two isolation transformers 12 (12A, 12B) named herein as Tl, T2. On the primary side of the isolation transformers 12 there are first and second primary full-bridge rectifiers 10 (10A, 10B), both comprising four switches (SI, S2, S3, S4; S5, S6, S7, S8). The primary side may also be referred to as the source side, on basis of the power source 20 being coupled to the primary side, providing a DC source voltage. Looking at the source side from the power source 20, the two primary full-bridge rectifiers 10 are mutually coupled in series. In other words, the two primary full-bridge rectifiers 10 are cascaded. Series-connection is implemented between input rails of the primary full-bridge rectifiers 10. The primary full-bridge rectifiers 10 are preferably implemented with n-channel MOSFET switches, but at least IGBTs, SiC MOSFETs and GaN HEMTs are feasible alternatives. Cascading the primary full-bridge rectifiers 10 is implemented herein by mutually coupling the negative input rail 102 of the first primary full-bridge rectifier 10A and the positive input rail 101 of the second primary full-bridge rectifier 10B, while the positive input rail 101 of the first primary full-bridge rectifier 10A and the negative input rail 102 of the second primary full-bridge rectifier 10B are coupled to the power source. This cascaded configuration allows using semiconductor switches (SI, S2, S3, S4; S5, S6, S7, S8) that are rated for a lower voltage between drain and source (VDs) or between collector and emitter (VCE) of the switch than the source voltage provided by the power source 20.

[0059] An input buffer capacitor (C8, C9) is provided between input rails of each primary full bridge 10 to buffer DC-voltage between an AC-DC rectifier (not shown) and input of the primary full-bridges 10. Input buffer capacitors (C8, C9) are not necessary if the power source 20 is a battery providing a DC voltage but are preferred when the power source 20 is an AC-DC converter supplied by the grid.

[0060] On the secondary side of the isolation transformers 12 there are first and second secondary full-bridge rectifiers 14 (14A, 14B) herein implemented with diodes (DI, D2, D3, D4; D5, D6, D7, D8) in full-bridge configuration. As an alternative to diode bridges, the secondary full-bridge rectifiers may be implemented as actively switched full-bridges, preferably using MOSFETs. The secondary side may also be referred to as the load side, referring to the load 30 being coupled to the secondary side. Looking from the load 30, the two secondary full-bridge rectifiers 14 are coupled to each other in series. In other words, the two secondary full-bridge rectifiers 14 are cascaded. Cascading the secondary full-bridge rectifiers is implemented by coupling output rails of two adjacent secondary full-bridge rectifiers 14 that are not coupled to the load 30, wherein the coupling is implemented via an output inductor (L). In other words, cascading the secondary full-bridge rectifiers 14 is implemented herein by mutually coupling the negative output rail 146 of the first secondary full-bridge rectifier 14A and the positive output rail 145 of the second secondary fullbridge rectifier 14B via the output inductor (L), while the positive output rail 145 of the first secondary full-bridge rectifier 14A is coupled to the load 30, and the negative output rail 146 of the second secondary full-bridge rectifier 14B is coupled to the load 30. Thus, only one positive output rail and one negative output rail of the cascade of secondary full-bridge rectifiers are coupled to the load. Output DC voltage is provided to the load 30 by the positive output rail 145 of the first secondary full-bridge rectifier 14A and the negative output rail 146 of the second secondary full-bridge rectifier 14B. The cascaded configuration allows using diodes (DI, D2, D3, D4; D5, D6, D7, D8) or semiconductor switches in the secondary full-bridge rectifiers 14 on the secondary side that are rated for a lower voltage than the desired load voltage over the load 30.

[0061] In this embodiment, an output filtering is implemented with a single output inductor L coupled between the two cascaded secondary full-bridge rectifiers 14 and at least one output capacitor Cl, C2. This illustrates the nature of "reduced number of output inductors", since there is one less output inductor in the output circuit in comparison to the number of secondary full-bridge rectifiers 14.

[0062] The operating principle of individual PSFBs, comprising one primary full-bridge rectifier 10, one isolation transformer 12 and one secondary full-bridge rectifier 14 remains identical to the original PSFB topology well known in the art. In the cascaded PSFB DC-DC converter topology, the individual PSFBs are operated by interleaving their pulse width modulation (PWM) cycles so that there is a phase shift between the two primary full bridges 10. The phase shift of the interleaving can be controlled actively. This feature is important especially when at fractional duty-cycle to avoid simultaneous switching among the cascaded converters. The duty-cycle is determined by a controller providing control signals to the primary full-bridge rectifiers. Current ripple amplitude on the load side is reduced due to the interleaving and the frequency of the current ripple is doubled in comparison to the switching frequency of the two primary full bridges 10. Another benefit of the configuration is that the amount of electromagnetic noise is reduced compared to simultaneous switching without the interleaving.

[0063] Order of leading and lagging switching of the two primary full-bridge rectifiers 10 is preferably controlled so that it can be determined whether the first (10A) or the second (10B) primary full-bridge rectifier is leading. This enables balancing losses within the PSFB DC-DC converter topology, and also enables individually controlling voltages over the input buffer capacitors (C7, C8) and the at least one output capacitor (Cl, C2). More than one output capacitor (Cl, C2) may be beneficial because it enables using capacitors with lower voltage tolerance than a single output capacitor coupled in parallel with the load (30). For example, number of output capacitors (Cl, C2) may be equal to the number of secondary full-bridge rectifiers (14). The amount and / or direction of phaseshift between operation cycles of the cascaded primary full-bridge rectifiers may be controllable. Such controlling of timing of operation between primary full-bridge rectifiers is also applicable in case of more than two primary fullbridge rectifiers 10.

[0064] In addition, or instead of controlling mutual timings, i.e. leading and lagging of operation of entire primary full-bridge rectifiers 10, mutual timing of operation, in other words leading and lagging order of phase-legs of one or more individual primary full-bridge rectifiers may be controlled to further balance losses and controlling voltages over input buffer capacitors and the at least one output capacitor. The amount and / or the direction of phase-shift between switching of individual phase-legs of one or more of the primary full-bridge rectifiers may be controlled.

[0065] Figure 3 shows an exemplary timing diagram that is applicable to a PSFB DC- DC converter topology with two cascaded primary and secondary full-bridge rectifiers, for example those shown in figures 1, 4 and 5. Voltage and current scales are arbitrary, but time scale is common to all charts.

[0066] Chart 110A illustrates interleaved control timings of switches SI, S2, S3 and S4 in the first primary full-bridge rectifier 10A and chart 120A illustrates a first primary voltage Uprimi at the output rails 105, 106 of the first primary fullbridge rectifier 10A and at the input of the first isolation transformer 12A. Each switching period has length tl.

[0067] Chart HOB illustrates interleaved control timings of switches S5, S6, S7 and S8 in the second primary full-bridge rectifier 10B and chart 120B illustrates a second primary voltage Uprim2 at the output rails 105, 106 of the second primary full-bridge rectifier 10B and at the input of the second isolation transformer 12B. Each switching period has length tl.

[0068] Comparison of mutual timings shows how phases of the first output voltage Uprimi and the second output voltage Uprim2 are interleaved, the first output voltage leading in this example.

[0069] Chart 130 illustrates resulting load current Iioad with ripple. Interleaving causes doubling of frequency of the ripple in comparison to switching frequency of the primary full-bridge rectifiers, here illustrated by the ripple period t2, which is half of the switching period tl. This facilitates reduction of magnitude of the load current ripple.

[0070] Figure 4 illustrates a second embodiment of a PSFB DC-DC converter topology. The basic circuit topology is like that discussed in connection with figures 1, 2A and 2B, and is not repeated herein. The only difference of this embodiment in comparison to the first PSFB DC-DC converter topology shown in the Figure 1 is a neutral point connection 21 to the power source. This kind of arrangement may be used for example when a three-level inverter is used as a power source. Like in the first embodiment, more than one output capacitor (Cl, C2) may be used to enable use of capacitors with lower voltage tolerance than what would be required from a single output capacitor coupled in parallel with the load 30. For example, number of output capacitors (Cl, C2) may be equal to the number of secondary full-bridge rectifiers 14. Figure 5 illustrates a third embodiment of a phase-shifted full-bridge (PSFB) DC-DC converter topology. To increase nominal current capacity, the output inductor L is implemented with at least two parallel-coupled output inductors (LI, Ln), which together form the output inductance. Although figure 5 shows two parallel-coupled output inductors (LI,..., Ln), n can be any integer. Parallel- coupled output inductors (LI,..., Ln) are coupled between the cascaded secondary full-bridge rectifiers as the single output inductor L in Figures 1 and 4. This ensures that the interleaved waveform from the input through the secondary full-bridge rectifiers 14 is achieved as in the first and second embodiments.

[0071] Figure 6 illustrates a fourth embodiment of a phase-shifted full-bridge (PSFB) DC-DC converter topology, which extends the concept of cascading the primary and secondary full-bridges to having any number of cascaded PSFB DC-DC converters. This allows reducing design constraints of the full-bridge rectifiers by further scaling down the VDs or the VCE in comparison to the source voltage, thus enabling use of cheaper circuit elements. In comparison to the topologies illustrated in figures 1, 4 and 5, there are now n isolation transformers 12 (Tl, T2, Tn), n cascaded primary full-bridge rectifiers 10 and n cascaded secondary full-bridge rectifiers. The output circuitry is provided with at least one output capacitor (Cl, C2,..., Cn) coupled in parallel with the load. As known to a skilled person, the n series-coupled output capacitors (Cl, C2,..., Cn) may be replaced by any number of output capacitors, starting from a single output capacitor. The load side of the converter comprises one or more output capacitors, and n-1 output inductors (LI,..., Ln-1), coupled between two cascaded secondary full-bridge rectifiers 14. Each of the output inductors (LI,..., Ln-1) may be implemented with a single inductor or with two or more parallel-coupled inductors as explained in connection with Figure 5. As in the above disclosed embodiments, only one positive output rail and one negative output rail of the entire cascade of secondary full-bridge rectifiers are coupled to the load 30, while all other output rails are used for cascading via output inductors (LI, ... Ln-1). This embodiment may also benefit from having more than one output capacitor (Cl, C2, ..., CN) to enable use of capacitors with a lower voltage tolerance than what would be required from a single output capacitor coupled in parallel with the load 30. For example, number of output capacitors (Cl, C2,..., CN) may be equal to the number N of secondary full-bridge rectifiers 14. The output inductor (L) may be implemented with a single inductor or with two or more parallel-coupled inductors for increasing current tolerance, as explained in connection with Figure 5.

[0072] Figure 7 illustrates an example of an alternative PSFB DC-DC converter topology, in which an output stage 16 comprises a single output inductor (L) and two output capacitors (Cl, C2). One end of the output inductor (L) is coupled between the two cascaded output diode rectifiers 14A, 14B and the other end of the output inductor (L) is coupled between two series-coupled (cascaded) output capacitors (Cl, C2). Other ends of the two cascaded output capacitors (Cl, C2) are coupled to an output rail of one of the output diode rectifiers 14A, 14B and to the load 30.

[0073] Figure 8 illustrates another example of another alternative PSFB DC-DC converter topology, which extends the concept of cascading of primary and secondary full-bridge rectifiers 10, 14 to any number of cascaded PSFB DC-DC converters. This allows reducing design constraints by further scaling down the VDS or the VCE of the switches (SI, ..., S12) of the primary full-bridge rectifiers 10 in comparison to the source voltage, thus enabling use of cheaper circuit elements. In comparison to the topologies illustrated in figure 7, there are now n isolation transformers 12 (Tl, T2, Tn), n cascaded primary full-bridges 10 and n cascaded output diode rectifiers. Each primary full-bridge 10 is provided with an input buffer capacitor (Cl, C2, Cn). The output stage 16 comprises n output capacitors, and n-1 output inductors (LI, Ln-1). Each of the output inductors (LI, Ln-1) may be implemented with a single inductor or with two or more parallel-coupled inductors as explained in connection with Figure 5.

[0074] According to some embodiments, there may be a neutral point tap on the secondary side, in which case an end of the output inductor L that is coupled to output capacitors Cl, C2 is also coupled to a neutral tap at the load 30.

Claims

CLAIMS1. A phase-shifted full-bridge, PSFB, DC-DC converter topology comprising:- at least two isolation transformers,- at least two cascaded primary full-bridge rectifiers configured to be coupled to an AC power source between a positive input rail of a first one of the at least two cascaded primary full-bridge rectifiers and a negative input rail of a second one of the at least two cascaded primary full-bridge rectifiers, wherein output rails of each one of the at least two primary full-bridge rectifiers are coupled to a primary side of a different one of the at least two isolation transformers, and wherein said cascading is implemented by mutual coupling of a negative input rail and a positive input rail of two adjacent ones of said at least two cascaded primary full-bridge rectifiers,- at least two cascaded secondary full-bridge rectifiers, wherein input rails of each one of the at least two secondary full-bridge rectifiers are coupled to the secondary side of a different one of the at least two isolation transformers, and- an output stage configured for coupling a load between a positive output rail of a first one of the at least two secondary full-bridge rectifiers and a negative output rail of a second one of the at least two secondary full-bridge rectifiers, the output stage comprising:- at least one output capacitor configured to be coupled in parallel with the load, and- at least one output inductor only coupled between output rails of each adjacent pair of said at least two cascaded secondary fullbridge rectifiers.

2. The PSFB DC-DC converter topology according to claim 1, further comprising at least two series-coupled input buffer capacitors, wherein each input buffer capacitor is coupled to input rails of one of the at least two cascaded primary full-bridge rectifiers.

3. The PSFB DC-DC converter topology according to claim 1 or 2, including two cascaded primary full-bridge rectifiers, two isolation transformers andtwo cascaded secondary full-bridge rectifiers, wherein mutually coupled input rails of the two cascaded primary full-bridge rectifiers are further configured to be coupled to a neutral point tap of the AC power source.

4. The PSFB DC-DC converter topology according to any one of claims 1 to3, wherein the at least one output inductor is implemented as two or more mutually parallel-coupled inductors.

5. The PSFB DC-DC converter topology according to any one of claims 1 to4, wherein the at least one output capacitor comprises at least two cascaded output capacitors, wherein the number of cascaded output capacitors preferably equals to number of cascaded secondary full-bridge rectifiers.

6. The PSFB DC-DC converter topology according to any one of claims 1 to5, wherein each primary full-bridge rectifier is further provided with an input buffer capacitor coupled between the input rails of the respective full-bridge rectifier.

7. The PSFB DC-DC converter topology according to any one of claims 1 to6, wherein switching of the at least two cascaded primary full-bridge rectifiers is configured to be mutually interleaved by determining a phaseshift between operation cycles of the at least two cascaded primary fullbridge rectifiers.

8. The PSFB DC-DC converter topology according to claim 7, wherein the phase shift is implemented as a phase shift between pulse width modulation (PWM) cycles that control operation of the cascaded primary full-bridge rectifiers.

9. The PSFB DC-DC converter topology according to claim 7 or 8, wherein the amount and / or direction of phase-shift between operation cycles of the cascaded primary full-bridge rectifiers is controllable.

10. The PSFB DC-DC converter topology according to any one of claims 1 to 9, wherein amount and / or direction of phase-shift between switching ofindividual phase-legs of one or more of the primary full-bridge rectifiers is controllable.

11. A method for performing DC-DC conversion by means of a phase-shifted full-bridge, PSFB, DC-DC converter topology according to any one of claims 1 to 10, the method comprising:- coupling at least two cascaded primary full-bridge rectifiers to an AC power source, wherein the AC power source is coupled between a positive input rail of a first one of the at least two cascaded primary full-bridge rectifiers and a negative input rail of a second one of the at least two cascaded primary full-bridge rectifiers, wherein said cascading is implemented by mutual coupling of a negative input rail and a positive input rail of two adjacent ones of said at least two cascaded primary full-bridge rectifiers,- coupling output rails of each one of the at least two primary fullbridge rectifiers to a primary side of a different one of at least two isolation transformers,- coupling input rails of each one of the at least two secondary fullbridge rectifiers to a secondary side of a different one of the at least two isolation transformers, and- coupling a load to an output stage of the PSFB DC-DC-converter topology, wherein the load is coupled between a positive output rail of a first one of the at least two secondary full-bridge rectifiers and a negative output rail of a second one of the at least two secondary full-bridge rectifiers by:- coupling at least one output capacitor of the output stage in parallel with the load, and- coupling at least one output inductor only between output rails of each adjacent pair of said at least two cascaded secondary fullbridge rectifiers.

12. The method according to claim 11, further comprising coupling at least two series-coupled input buffer capacitors, wherein each input buffercapacitor is coupled to input rails of one of the at least two cascaded primary full-bridge rectifiers.

13. The method according to claim 11 or 12, when the PSFB DC-DC converter topology has two cascaded primary full-bridge rectifiers, two isolation transformers and two cascaded secondary full-bridge rectifiers, the method further comprising:- coupling mutually coupled input rails of the two cascaded primary full-bridge rectifiers to a neutral point tap of the AC power source.

14. The method according to any one of claims 11 to 13, comprising:- implementing the at least one output inductor as two or more mutually parallel-coupled inductors.

15. The method according to any one of claims 11 to 14, wherein said coupling the at least one output capacitor comprises:- coupling at least two cascaded output capacitors, wherein the number of cascaded output capacitors preferably equals to number of cascaded secondary full-bridge rectifiers.

16. The method according to any one of claims 11 to 15, comprising:- further providing each primary full-bridge rectifier with an input buffer capacitor coupled between the input rails of the respective full-bridge rectifier.

17. The method according to any one of claims 11 to 16, comprising:- mutually interleaving switching of the at least two cascaded primary full-bridge rectifiers by determining a phase-shift between operation cycles of the at least two cascaded primary full-bridge rectifiers.

18. The method according to claim 17, wherein the phase shift is implemented as a phase shift between pulse width modulation (PWM) cycles that control operation of the cascaded primary full-bridge rectifiers.

19. The method according to claim 17 or 18, the method comprising: - controlling the amount and / or direction of phase-shift between operation cycles of the cascaded primary full-bridge rectifiers.

20. The method according to any one of claims 11 to 19, the method comprising:- controlling amount and / or direction of phase-shift between switching of individual phase-legs of one or more of the primary full-bridge rectifiers.

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