Method for controlling a converter, control device for controlling a converter and converter

Abstract

The present disclosure relates to a method for controlling a DC / DC converter. The converter comprises a first and second power converter each comprising a first, second and third terminal and one or more controllable semiconductor switches for control- ling a conversion of a voltage. The converter comprises a series connection of a first and second capacitor unit. The second and third terminal of the first power converter are connected with a first and second terminal of the first capacitor unit, respectively. The second and third terminal of the second power converter are connected with a first and second terminal of the second capacitor unit, respectively. The method comprises controlling the semiconductor switches of the first and second power con- verter by performing a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit.

Description

[0001] METHOD FOR CONTROLLING A CONVERTER, CONTROL DEVICE FOR CONTROLLING A CONVERTER AND CONVERTER

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to a method for controlling a converter, a control device for controlling a converter and a converter.

[0004] BACKGROUND

[0005] Solar energy may be translated into electrical energy by solar photovoltaic (PV) panels, e.g. PV arrays. The electrical energy translated from solar energy is in the form of direct current (DC) energy. Eventually, the DC electric energy is delivered to alternating current (AC) power systems by means of power electronic conversion systems. Consumption and loads may use the electrical energy in the form of AC energy. Examples of loads may comprise home appliances, industry motors, etc.

[0006] SUMMARY

[0007] A power converter system for converting DC power to AC power may comprise two stages. A first stage may comprise or be a DC-to-DC power converter stage. That is, one level of DC voltage or current may be converted to a lower or greater level of DC voltage or current. For example, a DC voltage or current may be converted to a lower or greater DC voltage or current (i.e. voltage or current of lower or higher level), respectively. The second stage may comprise or be a DC-to-AC power converter stage, which may be referred to as inverter stage. That is, DC power may be converted to AC power. For example, a DC voltage or current may be converted to an AC voltage or current, respectively. Optionally, the power converter system may be bidirectional. In this case, the second stage may be configured to be an AC-to-DC power converter stage. That is, AC power may be converted to DC power.

[0008] In case a PV system, such as a PV array or PV panel, are electrically connected to a DC-to-DC power converter stage, the DC- to-DC converter stage may be configured to boost an input DC voltage provided by the PV array or panel to a value higher at the output of DC-to-DC converter stage. The terms “solar PV” and, thus, “solar PV system” may be used as synonyms for the terms “PV” and “PV system”, respectively.

[0009] In view of the above, this disclosure aims to provide a converter for a DC-to-DC conversion that is improved with regard to at least one of losses of semiconductor switches used in the converter for controlling the converter, costs and size. An objective of this disclosure is to provide such a converter that allows guaranteeing a maximum energy being harvested from a PV system, when the converter is directly connected with the PV system for converting the DC voltage provided by the PV system.

[0010] These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0011] Herein, the terms “electrically connect” and “connect” are used as synonyms. The term “controlled semiconductor switch” may be used as a synonym for the term “controllable semiconductor switch”. The term “controllable semiconductor switch” means a semiconductor switch comprising a control terminal, such as a transistor, a thyristor, triac etc. The controllable semiconductor switch may be controlled via the control terminal to switch between the conducting state (i.e. on-state) and the non-conducting state (i.e. off-state). Herein, controllable semiconductor switches may be power semiconductor transistors, such as an insulated- gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). Using MOSFET instead of IGBTS for the controllable semiconductor switches has the following advantages: The operation speed of a MOSFET is faster than the operation speed of a similar rated IGBT. Power losses of a MOSFET are typically lower than power losses of a similar rated IGBT.

[0012] Herein, controllable semiconductor switches may be transistors. A controllable semiconductor switch being a transistor may be an insulated-gate bipolar transistor (IGBT), a field-effect transistor (FET), a metal -oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistors (B JT) or a junction gate field-effect transistor (JFET). Optionally, a controllable semiconductor switch may be a semiconductor switch with a diode associated to it. For example, a controllable semiconductor switch may be a transistor, such as a IGBT, with a diode connected in anti -parallel to the transistor. That is, in case a controllable semiconductor switch is a transistor, optionally a diode is connected in anti -parallel to the transistor. For example, a controllable semiconductor switch may be a transistor, such as a MOSFET, comprising an intrinsic body diode. The diode and intrinsic body diode are examples of an “uncontrollable semiconductor switch”, which may be referred to as “uncontrolled semiconductor switch”. The term “bidirectional semiconductor switch” means a semiconductor switch that allows a bidirectional current flow, that is a current flow in two directions. The term “unidirectional semiconductor switch” means a semiconductor switch that allows a unidirectional current flow, that is a current flow in one direction.

[0013] The term “uncontrollable semiconductor switch” means a semiconductor switch without a control terminal that allows a unidirectional current flow, that is a current flow in one direction. Examples of an “uncontrollable semiconductor switch” are a diode (may be referred to as “p-n semiconductor diode”), a pin diode, a Schottky diode, an intrinsic body diode of a respective device / transistor etc.

[0014] A first aspect of this disclosure provides a method for controlling a converter. The converter comprises a first, second, third and fourth terminal for receiving DC voltages. The converter comprises a first and second power converter each comprising a first, second and third terminal and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal to a further voltage of lower or higher level at the second and third terminal. The converter comprises a series connection of a first and second capacitor unit. The first terminal of the first power converter is electrically connected with the second terminal of the converter. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter is electrically connected with the second terminal of the second capacitor unit. The method comprises measuring a current and a voltage at the first terminal of each of the first and second power converter. The method comprises measuring a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The method comprises controlling the semiconductor switches (i.e. the controllable semiconductor switches) of the first and second power converter by performing, using the measured currents and voltages, a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit.

[0015] Performing the MPPT algorithm by controlling the controllable semiconductor switches of the first and second power converter allows harvesting a maximum energy from electrical energy sources, e.g. voltage sources or current sources, that may be connected to the first, second, third and fourth terminal of the converter. Such electrical sources may be PV systems, such as PV panels or PV arrays. For example, the first, second, third and fourth terminal of the converter may be connected to PV systems, such as PV panels or PV arrays. In this case, performing the MPPT algorithm for controlling the switches of the first and second power converter allows ensuring that the PV systems produce the maximum available energy. The first and third terminal may be configured to be electrically connected with a first voltage source and the second and fourth terminal may be configured to be electrically connected with a second voltage source. The first and second voltage source may be a first and second PV system, the PV system comprising or being one or more PV panels and / or PV arrays. The first and second sources may be a first and second battery, optional rechargeable batteries. The term “battery energy storage (BES)” may be used as a synonym for the term “battery”. The converter controlled by the method of the first aspect allows providing a low loss MPPT operation. This allows an increase of an extraction of energy from energy sources, e.g. solar PV energy from PV systems, that may be connected to the first, second, third and fourth terminals of the converter.

[0016] Performing a balancing algorithm for controlling the controllable semiconductor switches allows maintain the electrical energies (e.g. voltages, such as DC voltages) of the first and second capacitor unit at controlled levels. This eliminates the need for any hardware for further control and balancing of the electrical energies of the first and second capacitor. This allows reducing the size of the converter, increase the energy efficiency of the conversion and reduce the overall costs for producing the converter.

[0017] The converter may be a DC-to-DC converter. Optionally, the converter may be a DC-to-DC converter stage that feeds an DC- to-AC converter stage (i.e. an inverter stage). The converter may be configured to boost DC voltage(s) received at the first, second, third and fourth terminals of the converter, i.e. convert a received DC voltage to a voltage of higher level. The converter controlled by the method of the first aspect being a DC-to-DC converter stage and a DC-to-AC converter stage being fed by the converter may interface a PV system and a grid. That is, they may be used to convert the DC voltage / direct current provided by the PV system to an AC voltage / altemating current for the grid. The first and second capacitor unit may be referred to as “first DC link capacitor unit” and “second DC link capacitor unit”, respectively.

[0018] The converter allows, due to its structure, a partial power processing for overall power conversion. In a partial power processing, a majority of the power from the source (feeding the converter) is directed to the load side (which provides power to a load when the load is connected to the converter) without any switching, while a small portion of the power is processed by means of the first power converter and second power converter of the converter. In this case, the first and second power converter may be partial power converters. The term “partially rated power converted’ may be used as a synonym for the term “partial power converter. The converter can maintain the voltage at the first and second capacitor unit at predefined level as well as maintain the MPPT point of an input source to the first, second, third and fourth terminals of the converter. At all input variations of voltage source connectable to the first, second, third and fourth terminal of the converter, first and second power converter operate a smaller portion of the total power, and therefore, may be implemented using low voltage and / or low current semiconductor devices, such as low voltage and / or low current controllable semiconductor switches. Such low voltage and / or low current semiconductor devices are lower in costs compared to semiconductor devices rated for higher voltage and / or higher current. Low voltage and / or low current semiconductor devices can be switched faster and at high frequencies compared to semiconductor devices rated for higher voltage and / or higher current. Therefore, size of passive elements (such as inductors and capacitors) used in the power converters can be reduced considerably. These devices dissipate lower losses resulting lower cooling and heatsink requirements. As a result, the converter controlled by the method of the first aspect is improved with regard to efficiency, costs and size. In addition, the converter is improved with regard to losses of semiconductor switches used in the converter for controlling the converter. Thus, the converter allows a scalability for higher voltage applications without compromising efficiency, size and cost.

[0019] The terms “converter circuit”, “converter device” or “converter module” may be used as a synonym for the term “converted ’. The components of the converter may be arranged in a housing of the converter.

[0020] Herein, a voltage at the first terminal of a power converter (e.g. first or second power converter) means a voltage between the first terminal of the power converter and a further terminal, e.g. a terminal of the converter. Herein, a voltage at the second and third terminal of a power converter (e.g. first or second power converter) means a voltage between the second and third terminal of the power converter.

[0021] Herein, measuring a voltage at the first terminal of each of the first and second power converter means measuring the voltage at the first terminal of each of the first and second power converter with regard to the fourth terminal or first terminal of the converter, respectively. That is, measuring the voltage at the first terminal of the first power converter means measuring the voltage between the second and fourth terminal of the converter (the first terminal of the first power converter is electrically connected with the second terminal of the converter). Accordingly, measuring the voltage at the first terminal of the second power converter means measuring the voltage between the third and first terminal of the converter (the first terminal of the second power converter is electrically connected with the third terminal of the converter).

[0022] Herein, controlling the controllable semiconductor switches means controlling switching of the controllable semiconductor switches.

[0023] The present disclosure is not limited to a specific type of MPPT algorithm. Thus, any known MPPT algorithm may be used.

[0024] The converter may be a MPPT-DC-to-DC converter. The converter may be configured to employ the MPPT algorithm to extract the most energy possible from a photovoltaic (PV) system. The maximum power point (MPP) is the voltage and current at which a PV system may generate its maximum power.

[0025] In an implementation form of the first aspect, the converter comprises one or more additional first power converters with the first terminal being electrically connected to a respective further terminal of the converter and the second and third terminal being electrically connected to the first and second terminal of the first capacitor unit, respectively. The converter may comprise one or more additional second power converters with the first terminal being electrically connected to a respective further terminal of the converter and the second and third terminal being electrically connected to the first and second terminal of the second capacitor unit, respectively. The method may comprise measuring a current and a voltage at the first terminal of each of the first power converter, the second power converter, the one or more additional first power converters and the one or more additional second power converters. The method may comprise measuring a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The method may comprise controlling the semiconductor switches of the power converters of the converter by performing, using the measured currents and voltages, the MPPT algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit.

[0026] This allows, connecting additional voltage sources to the converter. Therefore, the converter may be used for more than two voltage sources in order to provide a voltage and / or current conversion for the multiple voltage sources. Each of the one or more additional first power converters may be implemented like the first power converter. Thus, the description of the first power converter is correspondingly valid for the one or more additional first power converters. Each of the one or more additional second power converters may be implemented like the second power converter. Thus, the description of the second power converter is correspondingly valid for the one or more additional second power converters

[0027] In an implementation form of the first aspect, the method comprises computing, using the measured currents and voltages at the first terminal of the power converters of the converter, nominal duty cycles for switching the controllable semiconductor switches of the power converters of the converter with regard to the MPPT. The method may comprise estimating an imbalance in electrical energy between the first and second capacitor unit, computing, using the computed nominal duty cycles and the estimated imbalance, duty cycles that counterthe estimated imbalance, and controlling the controllable semiconductor switches of the power converters using the computed duty cycles. The term “nominal duty cycle” may be understood to be a duty cycle that is computed based on performing the MPPT algorithm. The term “duty cycle” or “MPPT duty cycle” may be used as a synonym for the term “nominal duty cycle”.

[0028] In an implementation form of the first aspect, computing, using the measured currents and voltages at the first terminal of the power converters of the converter, the nominal duty cycles for switching the controllable semiconductor switches of the power converters of the converter with regard to the MPPT comprises computing for the current measured at the first terminal of a power converter of the power converters of the converter an error with regard to a set value for the current, the set value being computed by performing the MPPT algorithm using the current and voltage measured at the first terminal of the power converter of the power converters of the converter, and computing, using the computed error, a nominal duty cycle of the nominal duty cycles.

[0029] In an implementation form of the first aspect, the method comprises computing the nominal duty cycle of the nominal duty cycles by inputting the computed error in a controller.

[0030] In an implementation form of the first aspect, estimating an imbalance in electrical energy between the first and second capacitor unit comprises computing a first electrical energy of the first capacitor unit using the measured voltage between the first and second terminal of the first capacitor unit, computing a second electrical energy of the second capacitor unit using the measured voltage between the first and second terminal of the second capacitor unit, and computing a difference between the first and second electrical energy.

[0031] In an implementation form of the first aspect, computing, using the computed nominal duty cycles and the estimated imbalance, duty cycles that counter the estimated imbalance comprises computing a correction duty cycle by inputting the computed difference in a controller, and computing the duty cycles that counter the estimated imbalance using the computed correction duty cycle.

[0032] In an implementation form of the first aspect, a power converter of the power converters of the converter comprises a flying capacitor, and the method comprises computing a second difference between the electrical energy of the flying capacitor of the power converter and the electrical energy of a capacitor unit of the first and second capacitor unit that is electrically connected in parallel to the power converter. The method may comprise computing a correction duty cycle by inputting the computed difference in a controller, computing a second correction duty cycle by inputting the computed second difference in a second controller, computing a total correction duty cycle by summing the correction duty cycle and the second correction duty cycle, and computing the duty cycles that counter the estimated imbalance using the computed total correction duty cycle.

[0033] In an implementation form of the first aspect, each of the first and second power converter is a partial power converter.

[0034] This allows using low voltage and / or low current semiconductor switches as the controllable semiconductor switches of the first and second power convert.

[0035] In an implementation form of the first aspect, the converter is unidirectional and each of the first, second, third and fourth terminal of the converter is an input terminal. Alternatively, the converter may be bidirectional.

[0036] In case the converter is bidirectional, rechargeable batteries may be connected to the converter. For example, a first rechargeable battery may be connected to the first and third terminal of the converter and a second rechargeable battery may be connected to the second and fourth terminal of the converter. This allows converting by the converter a DC voltage provided by the first and second battery to a voltage of lower or higher level and charging by the converter the first and second rechargeable battery. In an implementation form of the first aspect, the converter comprises a fifth and sixth terminal that are configured to be electrically connected with an electrical load. The fifth terminal is electrically connected with the first terminal of the first capacitor unit, and the sixth terminal is electrically connected with the second terminal of the second capacitor unit.

[0037] The electrical load may be for example a converter stage, such as a DC-to-AC converter stage. The electrical load may be an electrical equipment that is configured to be electrically supplied with DC power, e.g. DC voltage or DC current.

[0038] In an implementation form of the first aspect, a capacitor unit of the first and second capacitor unit comprises a capacitor or multiple capacitors electrically connected in series. In case of multiple capacitors, capacitors rated for lower voltage and / or lower current may be used. This allows reducing costs and size of the converter.

[0039] In an implementation form of the first aspect, the second terminal of the first capacitor unit is electrically connected with the first terminal of the second capacitor unit. Alternatively, the second terminal of the first capacitor unit is electrically connected to a first terminal of a third capacitor unit and the first terminal of the second capacitor unit is electrically connected to a second terminal of the third capacitor unit.

[0040] The third capacitor unit allows the first and second capacitor unit to be rated for lower voltage and / or lower current, because the series connection of the first capacitor unit, second capacitor unit and third capacitor unit splits a voltage (e.g. DC load voltage) into several lower voltage levels. This allows reducing costs and size of the converter.

[0041] In an implementation form of the first aspect, the third capacitor unit comprises a capacitor or multiple capacitors electrically connected in series. In case of multiple capacitors, capacitors rated for lower voltage and / or lower current may be used. This allows reducing costs and size of the converter.

[0042] In order to achieve the method according to the first aspect of the disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

[0043] A second aspect of this disclosure provides a control device for controlling a converter. The converter comprises a first, second, third and fourth terminal for receiving DC voltages.

[0044] The converter comprises a first and second power converter each comprising a first, second and third terminal and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal to a further voltage of lower or higher level at the second and third terminal. The converter comprises a series connection of a first and second capacitor unit. The first terminal of the first power converter is electrically connected with the second terminal of the converter. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter is electrically connected with the second terminal of the second capacitor unit. The control device is configured to obtain a measured current and voltage at the first terminal of each of the first and second power converter. The control device is configured to obtain a measured voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The control device is configured to control the semiconductor switches of the first and second power converter by performing, using the measured currents and voltages, a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit. The control device may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components.

[0045] The first and third terminal of the converter may be configured to be electrically connected with a first voltage source and the second and fourth terminal of the converter may be configured to be electrically connected with a second voltage source.

[0046] The above description of the method according to the first aspect, especially the optional features and implementation forms of the first aspect, are correspondingly valid for the control device of the second aspect. The control device of the second aspect may be configured to perform the method of the first aspect.

[0047] The control device of the second aspect and its implementation forms and optional features achieve the same advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0048] A third aspect of this disclosure provides a converter. The converter comprises a first, second, third and fourth terminal for receiving DC voltages. The converter comprises a first and second power converter each comprising a first, second and third terminal and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal to a further voltage of lower or higher level at the second and third terminal. The converter comprises a series connection of a first and second capacitor unit. The first terminal of the first power converter is electrically connected with the second terminal of the converter. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter is electrically connected with the second terminal of the second capacitor unit. The converter is configured to measure current and a voltage at the first terminal of each of the first and second power converter. The converter is configured to measure a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The converter is configured to control the semiconductor switches of the first and second power converter by performing, using the measured currents and voltages, a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit.

[0049] The first and third terminal of the converter may be configured to be electrically connected with a first voltage source and the second and fourth terminal of the converter may be configured to be electrically connected with a second voltage source.

[0050] The above description of the method according to the first aspect, especially the optional features and implementation forms of the first aspect, are correspondingly valid for the converter of the third aspect. The converter of the third aspect may be configured to perform the method of the first aspect.

[0051] The converter of the third aspect and its implementation forms and optional features achieve the similar advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0052] The converter described with regard to the method of the first aspect, the converter described with regard to the control device of the second aspect and the converter of the third aspect correspond to each other. The method of the first aspect, control device of the second aspect and converter of the third aspect allow a low cost MPPT DC-to-DC conversion. With regard to string inverters for interfacing a PV system (e.g. a PV array) to a grid, each string inverter comprising the converter described with regard to the first aspect or second aspect or the converter of the third aspect as a DC-to-DC converter stage and an DC- to-AC converter stage, the method of the first aspect, control device of the second aspect and converter of the third aspect enable having a string level optimization, rather than multiple strings to be maintained at one MPPT. The method of the first aspect, the converter described with regard to the control device of the second aspect and the converter of the third aspect allows extension of PV strings, BES integration or any combination of both.

[0053] With the method of the first aspect, control device of the second aspect and the converter of the third aspect, it is possible to improve the efficiency, power density and the cost of a MPPT DC / DC converter, e.g. when used for PV systems. Moreover, a high electrical efficiency can be achieved as lower voltage semiconductor devices can be used and by means of the integration of control and driving circuits in close proximity to switching power cells thereby minimizing delays and latencies in the control loop.

[0054] All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

[0055] BRIEF DESCRIPTION OF DRAWINGS

[0056] The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

[0057] FIG. 1 shows an example of a converter of this disclosure and an example of a control device of this disclosure for controlling a converter.

[0058] FIG. 2 shows an example of an implementation form of the converter of FIG. 1.

[0059] FIG. 3 shows an example of an implementation form of the converter of FIG. 1.

[0060] FIG. 4 a) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1,

[0061] 2 and 3.

[0062] FIG. 4 b) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1, 2 and 3.

[0063] FIG. 5 a) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1, 2 and 3.

[0064] FIG. 5 b) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1, 2 and 3.

[0065] FIG. 6 shows an example of an implementation form of the converter of FIG. 1.

[0066] FIG. 7 shows an example of an implementation form of the converter of FIG. 1. FIG. 8 shows an example of a method of this disclosure for controlling a converter of this disclosure, such as the converter of any one FIGs 1, 2, 3, 6 and 7.

[0067] FIGs 9 a), 9 b) and 9 c) show an example of implementing method steps of the method of FIG. 8.

[0068] FIGs 10 a) and 10 b) show an example of implementing method steps of the method of FIG. 8.

[0069] FIGs 11 a) and 11 b) show an example of implementing method steps of the method of FIG. 8.

[0070] Same elements shown in the Figures (FIGs) are labeled with the same reference sign, and may be implemented likewise.

[0071] DETAILED DESCRIPTION OF EMBODIMENTS

[0072] FIG. 1 shows an example of a converter of this disclosure and an example of a control device of this disclosure for controlling a converter. The converter of FIG. 1 is an example of the converter of the third aspect. Thus, the description of the converter of the third aspect is correspondingly valid for the converter of FIG. 1. The control device of FIG. 1 is an example of the control device of the second aspect. Thus, the description of the control device of the second aspect is correspondingly valid for the control device of FIG. 1.

[0073] The converter 1 of FIG. 1 comprises a first terminal Tl, second terminal T2, third terminal T3 and fourth terminal T4 for receiving DC energy sources. As shown in FIG. 1, the first and third terminal Tl, T3 may be configured to be electrically connected with a first source 100 and the second and fourth terminal T2, T4 may be configured to be electrically connected with a second source 200. The converter 1 comprises a first power converter 21 and second power converter 22. Each power converter of the first and second power converter 21, 22 comprises a first terminal X, second terminal Y1 and third terminal Y2 and one or more controllable semiconductor switches (not shown in FIG. 1) for controlling a conversion of a voltage at the first terminal X to a further voltage of lower or higher level at the second and third terminal Y1 , Y2. FIGs 4 a), 4 b), 5 a), 5 b), 6 and 7 show examples of implementation forms of the first and second power converter 21, 22. The converter 1 comprises a series connection of a first capacitor unit Cl and a second capacitor unit C2.

[0074] As shown in FIG. 1 , the first terminal X of the first power converter 21 is electrically connected with the second terminal T2 of the converter 1. The second and third terminal Y 1 , Y2 of the first power converter 21 are electrically connected with a first and second terminal of the first capacitor unit Cl, respectively. The first terminal Tl of the converter 1 is electrically connected with the first terminal of the first capacitor unit Cl. The first terminal X of the second power converter 22 is electrically connected with the third terminal T3 of the converter 1. The second and third terminal Y 1 , Y2 of the second power converter 22 are electrically connected with a first and second terminal of the second capacitor unit C2, respectively. The fourth terminal T4 of the converter 1 is electrically connected with the second terminal of the second capacitor unit C2. As shown in FIG. 1, optionally the second terminal of the first capacitor unit C 1 is connected with the first terminal of the second capacitor unit C2. In this case, the third terminal Y2 of the first power converter 21 and the second terminal Y1 of the second power converter 22 may be electrically connected to the same node. Alternatively, the first capacitor unit Cl and the second capacitor unit C2 being connected in series are optionally not directly connected with each other. Such optional implementation is shown in FIG. 2.

[0075] The converter 1 is configured to measure a current and a voltage at the first terminal X of each of the first and second power converter 21, 22. That is, with regard to the first power converter 21, the converter 1 is configured to measure a current ii at the second terminal T2 of the converter 1 and a voltage vi between the second terminal T2 and fourth terminal T4 of the converter 1 (the first terminal X of the first power converter 21 is connected with the second terminal T2 of the converter 1). With regard to the second power converter 22, the converter 1 is configured to measure a current i2 at the third terminal T3 of the converter 1 and a voltage V2 between the third terminal T3 and first terminal T1 of the converter 1 (the first terminal X of the second power converter 22 is connected with the third terminal T3 of the converter 1). The converter 1 is configured to measure a voltage between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. That is, the converter 1 is configured to measure a voltage Vdci between the first terminal and second terminal of the first capacitor unit Cl and a voltage Vdc2 between the first terminal and second terminal of the second capacitor unit C2.

[0076] For measuring the aforementioned currents and voltages the converter 1 may comprise respective measuring circuit(s) and / or element(s) (not shown). For example, for measuring current the converter 1 may comprise a resistor, such as a shunt resistor. For example, for measuring a voltage the converter 1 may comprise a voltage divider, such as two resistors electrically connected in series. The present disclosure is not limited to a specific way of measuring currents and voltages. Thus, with regard to measuring currents and voltages the converter 1 may be implemented in any known way.

[0077] The converter 1 is configured to control the semiconductor switches (i.e. controllable semiconductor switches) of the first and second power converter 21, 22 by performing, using the measured currents ii, i2 and voltages vi, V2, VDCI, VDC2, a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitorunit Cl, C2. For this the converter 1 may comprise a control unit (not shown in FIG. 1). The control unit may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components. The control unit is configured to provide control signals, such as pulse width modulated (PWM) signals, to the controllable semiconductor switches of the first and second power converter 21, 22, especially to the control terminal of the controllable semiconductor switches. The duty cycle of the control signal, e.g. PWM signal, may determine the ratio between the on-time and the sum of the on-time and off- time for a respective controllable semiconductor switch being controlled by the control signal. The sum of the on-time and off- time is the period (inverse of the frequency) of the control signal. The on-time is the time during which the controllable semiconductor switch is in the conducting state and the off-time is the time during which the controllable semiconductor switch is in the non-conducting state. The frequency (i.e. inverse period) of the control signal may be kept constant. That is, for controlling a respective controllable semiconductor switch with a control signal, the control unit may be configured to control (e.g. change) the duty cycle of the control signal. Hereby, the control unit may keep the frequency of the control signal constant. The control unit may be configured to control the duty cycle of the control signals for controlling the semiconductor switches by performing the MPPT algorithm and the balancing algorithm for balancing the electrical energies of the first and second capacitor unit Cl, C2.

[0078] Alternatively to the converter 1 , e.g. a control unit of the converter 1 , being configured to control the controllable semiconductor switches of the first and second power converter 21, 22, a control device 400 (e.g. external control device) may be used for this. This is indicated by the arrow between the box “400” indicating the control device and the box “ 1” indicating the converter 1. The box “400” may represent a housing of the control device. The box “1” may represent a housing of the converter 1. The control device 400 is an example of the control device of the second aspect.

[0079] The control device 400 is configured to obtain a measured current and voltage at the first terminal X of each of the first and second power converter 21, 22. That is, the control device 400 is configured to receive, with regard to the first power converter 21 of the converter 1, a current ii measured at the second terminal T2 of the converter 1, and a voltage vi measured between the second terminal T2 and fourth terminal T4 of the converter 1. The control device 400 is configured to receive, with regard to the second power converter 22 of the converter 1, a current i2 measured at the third terminal T3 of the converter 1, and a voltage V2 measured between the third terminal T3 and first terminal T 1 of the converter 1. The control device 400 is configured to obtain a measured voltage between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. That is, the control device 400 is configured to obtain a voltage VDCI measured between the first and second terminal of the first capacitor unit Cl and a voltage VDC2 measured between the first and second terminal of the second capacitor unit C2. The control device 400 may be configured to obtain the aforementioned currents and voltages from respective measurement circuit(s) and / or element(s) of the converter 1. The control device 400 is configured to control the semiconductor switches (i.e. controllable semiconductor switches) of the first and second power converter 21, 22 of the converter 1 by performing, using the measured currents ii, i2 and voltages vi, V2, VDCI, VDC2, a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit Cl, C2.

[0080] The above description of the optional control unit of the converter 1 is correspondingly valid for the control device 400. The control device 400 may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components.

[0081] The control device 400 is configured to provide control signals, such as pulse width modulated (PWM) signals, to the controllable semiconductor switches of the first and second power converter 21, 22, especially to the control terminal of the controllable semiconductor switches. The frequency (i.e. inverse period) of the control signal may be kept constant. That is, for controlling a respective controllable semiconductor switch with a control signal, the control device 400 may be configured to control (e.g. change) the duty cycle of the control signal. Hereby, the control device 400 may keep the frequency of the control signal constant. The control device 400 may be configured to control the duty cycle of the control signals for controlling the semiconductor switches by performing the MPPT algorithm and the balancing algorithm for balancing the electrical energies of the first and second capacitor unit Cl, C2.

[0082] Herein, a description of the converter 1 (e.g. control unit of the converter) with regard to controlling semiconductor switches and a description of the control device 400 are valid for each other.

[0083] Each of the first power converter 21 and second power converter 22 of the converter 1 may be a partial power converter. The converter 1 may be unidirectional and each of the first, second, third and fourth terminal Tl, T2, T3, T4 of the converter 1 may be an input terminal. As shown in FIG. 1, the converter 1 may comprise a fifth terminal T5 and sixth terminal T6 that are configured to be electrically connected with an electrical load 300. The fifth terminal T5 is electrically connected with the first terminal of the first capacitor unit C 1 and, thus, with the first terminal Tl of the converter 1. The sixth terminal T6 is electrically connected with the second terminal of the second capacitor unit C2 and, thus, with the fourth terminal T4 of the converter 1.

[0084] For example, the converter may be a DC-to-DC converter and the load 300 may be an DC-to-AC converter. In this case, the first and second voltage sources 100, 200 may be PV systems, such as PV panel(s) and / or PV array(s). Optionally, the sources 100, 200 may be two close strings in a PV park that are designed to generate similar DC power. The converter 1 being a DC- to-DC converter and the load 300 being a DC-to-AC converter may be used for converting DC power, e.g. DC voltage and / or direct current, provided by the first and second voltage sources 100, 200, e.g. PV systems, to AC power, e.g. AC voltage and / or alternating current, and provide the AC power to the grid. Optionally, the load 300 may be a DC load.

[0085] Alternatively, the converter 1 may be bidirectional. An example of an implementation form of the converter being bidirectional is shown in FIG. 7. In this case, the first and second voltage sources 100, 200 may be rechargeable battery energy storages (BES) and the load 300 may be configured to use electrical energy from the BES 100, 200 (power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 1) and charge the BES 100, 200 with electrical energy (power flow from the terminals T5, T6 to the terminals Tl, T2, T3, T4 of the converter 1). Thus, the converter 1 being bidirectional supports discharging and charging of BES 100, 200. As shown in FIG. 1, a capacitor unit of the first and second capacitor unit Cl, C2 may comprise or be a capacitor. For example, as shown in FIG. 1, each of the first and second capacitor unit Cl, C2 may comprise or be a capacitor. Alternatively, a capacitor unit of the first and second capacitor unit Cl, C2 may comprise or be multiple capacitors (e.g. two capacitors) electrically connected in series. Optionally, each of the first and second capacitor unit Cl, C2 may comprise or be multiple capacitors (e.g. two capacitors) electrically connected in series. The number of capacitors of the first capacitor unit C 1 and the second capacitor unit C2 may depend on the implementation form of the first power converter 21 and second power converter 22, respectively. Optionally, the first and second power converter 21, 22 may be implemented by the same power converter type. The power converters of the converter 1 may be implemented the same way. Optionally, at least one power converter of the converter 1 may be implemented differently. As outlined already above, examples of implementation forms of the power converters 21, 22 of the converter 1 are shown in FIGs 4 a), 4 b), 5 a), 5 b), 6 and 7.

[0086] For further information on the converter 1 reference is made to FIGs 2, 3, 4 a), 4 b), 5 a), 5 b), 6 and 7. For further information on how the converter 1 (e.g. control unit of the converter) and the control device 400 may control semiconductor switches references is made to FIGs 6, 8, 9 a), 9 b), 9 c), 10 a), 10 b), 11 a) and 11 b).

[0087] FIG. 2 shows an example of an implementation form of the converter of FIG. 1. The converter 1 of FIG. 2 corresponds to the converter 1 of FIG. 1. Thus, the description of the converter 1 of FIG. 1 is correspondingly valid for the converter 1 of FIG. 2 and in the following mainly a difference, especially an optional feature, of the converter 1 of FIG. 2 with regard to the converter

[0088] 1 of FIG. 1 is described.

[0089] As shown in FIG. 2, the second terminal of the first capacitor unit Cl is electrically connected to a first terminal of a third capacitor unit C3. Thus, the third terminal Y2 of the first power converter 21 is connected with the first terminal of the third capacitor unit C3. The first terminal of the second capacitor unit C2 is electrically connected to a second terminal of the third capacitor unit C3. Thus, the second terminal Y 1 of the second power converter 22 is connected with the second terminal of the third capacitor unit C3. According to FIG. 2, the capacitor unit C3 comprises two capacitors electrically connected in series. This is only by way of example. Thus, the third capacitor unit C3 may comprises or be a capacitor or multiple capacitors (two or more capacitors) electrically connected in series. The third capacitor unit C3 allows the first and second capacitor unit Cl, C2 to be rated for lower voltage and / or lower current. This allows reducing costs and size of the converter 1. As shown in FIG.

[0090] 2 the first capacitor unit Cl, third capacitor unit C3 and second capacitor unit C2 are connected in series.

[0091] FIG. 3 shows an example of an implementation form of the converter of FIG. 2. The converter 1 of FIG. 3 corresponds to the converter 1 of FIG. 2. Thus, the description of the converter 1 of FIGs 1 and 2 is correspondingly valid for the converter 1 of FIG. 3 and in the following mainly a difference, especially an optional feature, of the converter 1 of FIG. 3 with regard to the converter 1 of FIG. 2 is described. The optional feature of the converter of FIG. 3 is also valid for the implementation form of the converter 1 of FIG. 1, i.e. in case the second terminal of the first capacitor unit Cl is connected with the first terminal of the second capacitor unit C2.

[0092] As shown in FIG. 3, the converter 1 comprises one or more additional first power converters 21a with the first terminal X of the additional first power converter 21a being electrically connected to a respective further terminal Ta of the converter 1 and the second and third terminal Y 1 , Y2 being electrically connected to the first and second terminal of the first capacitor unit C 1 , respectively. According to FIG. 3 one additional first power converter 21a is shown. This is only by way of example and, thus, more than one additional first power converter 21a may be provided. The converter 1 comprises one or more additional second power converters 22a with the first terminal X of the additional second power converter 22a being electrically connected to a respective further terminal Tb of the converter 1 and the second and third terminal Yl, Y2 being electrically connected to the first and second terminal of the second capacitor unit C2, respectively. According to FIG. 3 one additional second power converter 22a is shown. This is only by way of example and, thus, more than one additional second power converter 22a may be provided.

[0093] Providing additional first and second power converters 2 la, 22a allows connecting additional voltage sources 101, 201 to the converter 1. For example, a voltage source 201 may be connected with the further terminal Ta and the fourth terminal T4 of the converter 1, and a voltage source 101 may be connected with the further terminal Tb and the first terminal T1 of the converter 1. The converter 1 may be configured to measure a current ii, i2, iia, i2a and a voltage vi, V2, via, V2a at the first terminal X of each of the first power converter 21, the second power converter 22, the one or more additional first power converters 21a and the one or more additional second power converters 22a. The converter 1 may be configured to measure the voltage VDCI, VDC2 between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. The converter 1, especially the control unit of the converter 1, or the control device 400 (shown in FIG. 1) may be configured to control the semiconductor switches (i.e. controllable semiconductor switches) of the power converters 21, 22, 21a, 22a of the converter 1 by performing, using the measured currents ii, i2, iia, i2a and voltages vi, V2, via, V2a, VDCI, VDC2, the MPPT algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit C 1 , C2.

[0094] The one or more additional first power converters 21a are implemented in line with the first power converter 21. Thus, a description of the first power converter 21 , such as a description of the structure and control of the first power converter 21 , is correspondingly valid for the one or more additional first power converters 21a. The one or more additional second power converters 22a are implemented in line with the second power converter 22. Thus, a description of the second power converter 22, such as a description of the structure and control of the second power converter 22, is correspondingly valid for the one or more additional second power converters 22a. The description with regard to the sources 100, 200 is correspondingly valid for the source 101, 201.

[0095] The implementation form of FIG. 3 allows connecting multiple 2n voltage sources, such as PV systems and / or BES to the converter 1, wherein n is an integer that is greater than one (n > 1). The number of power converters 21, 22, 21a, 22a equals to the number of voltage sources that may be connected to the converter 1. In case n equals 1 (n = 1), the converter corresponds to the implementation form of FIG. 1 for two voltage sources.

[0096] FIGs 4 a), 4 b), 5 a) and 5b) each show an example of an implementation form of a power converter of the converter of any one of FIGs 1 , 2 and 3. The implementation of the controllable semiconductor switches of the power converters of FIGs 4 a), 4 b), 5 a) and 5b) is only by way of example and, thus, they may be implemented by a different controllable semiconductor switch type, such as a different transistor type, compared to the type shown in the respective Figure. The number of capacitors of the respective capacitor unit Cl, C2 may be different compared to the shown number.

[0097] As shown in FIG. 4 a), the power converter 21 , 22 may comprise an inductor L 1 and two controllable semiconductor switches SI, S2. In the example of FIG. 4 a) the two switches SI, S2 are two IGBTs, wherein a diode is connected in anti-parallel to each IGBT. As shown in FIG. 4 a), a first terminal of the inductor LI is connected with the first terminal X of the power converter 21, 22. A first terminal of the switch SI (e.g. the emitter terminal of the IGBT SI) is connected with the second terminal of the inductor LI and a second terminal of the switch SI (e.g. the collector terminal of the IGBT SI) is connected with the second terminal Y1 of the power converter 21, 22. A first terminal of the switch S2 (e.g. the emitter terminal of the IGBT S2) is connected with the third terminal Y2 of the power converter 21, 22. A second terminal of the switch S2 (e.g. the collector terminal of the IGBT S2) is connected with the second terminal of the inductor LI. The third terminal of the controllable semiconductor switches SI, S2 are the control terminals (e.g. gate terminal of the IGBT) via which the controllable semiconductor switches SI, S2 may be controlled with control signals, such as PWM signals. As shown in FIG. 4 b), the power converter 21, 22 may have the structure of the power converter 21, 22 of FIG. 4 a) and additionally may comprise a bidirectional semiconductor switch that is formed by two controllable semiconductor switches S3 and S4 (e.g. two IGBTs, wherein a diode is connected in anti -parallel to each IGBT). The bidirectional switch may be connected between the second terminal of the inductor LI and a fourth terminal Y3 of the power converter 21, 22. The fourth terminal Y3 may be connected with a node between two capacitors of a respective capacitor unit Cl, C2.

[0098] As shown in FIG. 5 a), the power converter 21, 22 may comprise an inductor LI, four controllable semiconductor switches SI, S2, S3, S4 (e.g. four IGBTs) and a capacitor C4. A first terminal of the inductor LI is connected with the first terminal X of the power converter 21, 22. A second terminal of the inductor LI is connected with a first terminal of a first switch SI (e.g. emitter terminal of IGBT SI) and a second terminal of a second switch S2 (e.g. collector terminal of IGBT S2). The second terminal of the first switch SI (e.g. collector terminal of IGBT SI) is connected with a first terminal of the capacitor C4 and the first terminal of the second switch S2 (e.g. emitter terminal of IGBT S2) is connected with a second terminal of the capacitor C4. The third switch S3 (e.g. IGBT S3) is connected between the first terminal of the capacitor C4 and the second terminal Y1 of the power converter 21, 22, as shown in FIG. 5 a). The fourth switch S4 (e.g. IGBT S4) is connected between the second terminal of the capacitor C4 and the third terminal Y2 of the power converter 21, 22, as shown in FIG. 5 a).

[0099] As shown in FIG. 5 b), the power converter 21 , 22 may have the structure of the power converter 21 , 22 of FIG. 5 a), wherein the capacitor C4 may be replaced by a fifth and sixth controllable semiconductor switch S5, S6 (e.g. IGBTs S5, S6). The fifth switch S5 (e.g. IGBT S5) is connected between the second terminal of the first switch S 1 and a fourth terminal Y3 of the power converter 21, 22, as shown in FIG. 5 b). The sixth switch S6 (e.g. IGBT S6) is connected between the first terminal of the second switch S2 and the fourth terminal Y3 of the power converter 21, 22, as shown in FIG. 5 b). The fourth terminal Y3 may be connected with a node between two capacitors of a respective capacitor unit Cl, C2.

[0100] FIG. 6 shows an example of an implementation form of the converter of FIG. 1. The converter of FIG. 6 corresponds to the converter of FIG. 1. Thus, the description of the converter of FIG. 1 is correspondingly valid for the converter of FIG. 6 and in the following mainly the implementation of the power converters 21 and 22 are described.

[0101] As shown in FIG. 1 , each power converter of the power converters 21 , 22 comprises a capacitor Cf 1 or Cf2, a first switch unit SU1 comprising two semiconductor switches SI, S2 electrically connected in series between the second terminal Y1 of the power converter 21 or 22 and a node, and a second switch unit SU2 comprising two semiconductor switches S3, S4 electrically connected in series between the node and the third terminal of the power converter 21 or 22, the node being electrically connected via an inductor L 1 to the first terminal X of the power converter 21 or 22 and the capacitor Cf 1 or Cf2 being electrically connected with a midpoint (node) between the two semiconductor SI, S2 of the first switch unit SU1 and a midpoint (node) between the two semiconductor switches S3, S4 of the second switch unit SU2. Such a power converter may be also referred to as “three level flying capacitor boost power converter (3-L flying capacitor boost power converter)”. The capacitor Cfl of the first power converter 21 and the capacitor Cf2 of the second power converter 22 may be referred to as “flying capacitor".

[0102] According to the example of FIG. 6, the semiconductor switches S 1 , S2 of the first switch unit SU 1 of the first power converter 21 and the semiconductor switches S3, S4 of the second switch unit SU2 of the second power converter 22 are uncontrollable semiconductor switches. As shown in FIG. 6, they may be diodes. This is only by way of example and, thus, any other type of uncontrollable semiconductor switch may be used. According to the example of FIG. 6, the semiconductor switches SI, S2 of the first switch unit SU1 of the second power converter 22 and the semiconductor switches S3, S4 of the second switch unit SU2 of the first power converter 12 are controllable semiconductor switches. As shown in FIG. 6, they may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. The converter 1, especially the control unit of the converter 1 (not shown in FIG. 6), or the control device 400 may use the voltages Vfci, VfC2 of the capacitors Cf 1 and Cf2 of the power converters 21 , 22 in addition to the currents ii, i2 and voltages vi, V2, Vdci, Vdc2 for controlling the controllable semiconductor switches of the power converters 21, 22. The converter 1 may be configured to measure voltages Vfci, VrC2 of the capacitors Cfl and Cf2 of the power converters 21, 22. The control device 400 may be configured to obtained the measured voltages Vfci, VfC2 of the capacitors Cfl and Cf2 of the power converters 21 , 22. Thus, the converter 1, especially the control unit of the converter 1 (not shown in FIG. 6), or the control device 400 may be configured to control the controllable semiconductor switches of the first and second power converter 21, 22 by performing, using the measured currents ii, i2 and voltages vi, V2, Vdci, Vdc2, Vfci, V&2, a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit C 1 , C2 and the electrical energies of the capacitors Cfl, Cf2 of the two power converters 21, 22.

[0103] FIG. 6 shows the inputs to the optional control device 400 for performing the above described control of the controllable semiconductor switches of the two power converters 21 , 22 and the control signals in the form of PWM signals for controlling the controllable semiconductor switches of the two power converters 21, 22. The control signals for controlling the controllable semiconductor switches S3, S4 of the second switch unit SU2 of the first power converter 21 are labelled as “21 - PWM S3” and “21 - PWM S4”, respectively. The control signals for controlling the controllable semiconductor switches SI, S2 of the first switch unit SU 1 of the second power converter 22 are labelled as “22 - PWM SI” and “22 - PWM S2”, respectively . These inputs and outputs of the control device 400 are correspondingly valid in case the converter 1, especially a control unit of the converter 1, is configured to control controllable semiconductor switches of the two power converters 21, 22.

[0104] The power converters 21, 22 of the converter 1 of FIG. 6 may have 1 / 4 of the semiconductor blocking voltage ratings to the full voltage across the first and second capacitor units Cl, C2 (e.g. the full DC link). That is, the switches used in the power converters may have 1 / 4 of the semiconductor blocking voltage rating compared to a converter that comprises instead of the switch units SU1 and SU2 of the first and second power converters 21, 22 a series connection of four semiconductor switches that is electrically connected in parallel to the series connection of the first and second capacitor unit Cl, C2.

[0105] The converter 1 of FIG. 6 may optionally comprise the optional feature of the third capacitor unit described above with regard to FIG. 2. In this case, the second terminal of the first capacitor unit Cl is connected via the third capacitor unit with the first terminal of the second capacitor unit C2. The above description of FIG. 2 is correspondingly valid.

[0106] FIG. 7 shows an example of an implementation form of the converter of FIG. 1. The converter of FIG. 7 corresponds to the converter of FIG. 6. Thus, the description of the converter of FIG. 6 is correspondingly valid for the description of the converter of FIG. 7 and in the following mainly a difference, especially optional feature, of the converter of FIG. 7 with regard to the converter of FIG. 6 is described.

[0107] As shown in FIG. 7, the semiconductor switches SI, S2 of the first switch unit SU1 of the first power converter 21 and the semiconductor switches S3, S4 of the second switch unit SU2 of the second power converter 22 are controllable semiconductor switches. As shown in FIG. 7, they may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. The implementation form of FIG. 7 allows a bidirectional power flow over the converter 1. Thus, the converter 1 of FIG. 7 is an example of a bidirectional converter. As a result, the first and second voltage sources 100, 200 may be rechargeable battery energy storages (BES) and the load 300 may be configured to use electrical energy from the BES 100, 200 (power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 1) and charge the BES 100, 200 with electrical energy (power flow from the terminals T5, T6 to the terminals Tl, T2, T3, T4 of the converter 1). FIG. 8 shows an example of a method of this disclosure for controlling a converter of this disclosure, such as the converter according to any one FIGs 1, 2, 3, 4 a), 4 b), 5 a), 5 b), 6 and 7. The method of FIG. 8 is an example of the method of the first aspect. Thus, the description of the method of the first aspect is correspondingly valid for the method of FIG. 8.

[0108] As shown in FIG. 8, the method comprises a step 1000 of measuring a current ii, i2 and a voltage vi, V2 at the first terminal X of each of the first and second power converter 21, 22 of the converter 1. The method comprises a step 2000 of measuring a voltage VDCI, VDC2 between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. According to FIG. 8, the step 2000 follows the step 1000. This may be vice versa or the steps 1000 and 2000 may be performed simultaneously. The method comprises the step 3000 of controlling the semiconductor switches (i.e. the controllable semiconductor switches) of the first and second power converter 21, 22 by performing, using the measured currents ii, i2 and voltages vi, V2, VDCI, VDC2 a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit Cl, C2.

[0109] In case the first and second power converter each comprise a capacitor Cfl, Cf2 (flying capacitor), the method may comprise the step of measuring a voltage Viti, V&2, between the first terminal and second terminal of the capacitor Cfl of the first power converter 21 and the capacitor Cf2 of the second power converter 22 (not shown in FIG. 8). This step may be performed before the step 1000, or after the step 1000, or after the step 2000 or simultaneously to at least one of the steps 1000 and 2000. The step 3000 may then comprise or be controlling the semiconductor switches (i.e. the controllable semiconductor switches) of the first and second power converter 21 , 22 by performing, using the measured currents ii, i2 and voltages vi, V2, VDCI, VDC2, Vfci, Vfc2 a maximum power point tracking (MPPT) algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit Cl, C2 and the electrical energies of the capacitors Cfl, Cf2 of the two power converters 21, 22.

[0110] FIGs 9 a), 9 b) and 9 c), 10 a), 10 b), Il a) and 11 b) show an example of implementing method steps of the method of FIG. 8. They are described for example with regard to the implementation form of the power converters 21, 22 and, thus, converter 1 of FIG. 6. The description is correspondingly valid for other implementation forms of the power converters 21, 22.

[0111] As shown in FIG. 9 a) and 9 b), the method of FIG. 8 may comprise computing, using the measured currents ii (t), i2(t) and voltages v, (t), v2(t) at the first terminal X of the power converters 21, 22 of the converter 1, nominal duty cycles d , (t), d2(t) for switching the controllable semiconductor switches of the power converters 21, 22 of the converter 1 with regard to the MPPT. As shown in FIG. 9 c), the method may comprise estimating an imbalance in electrical energy between the first and second capacitor unit Cl, C2. That is, estimating a difference between the electrical energy Edc lof the first capacitor unit Cl and the electrical energy Edclof the second capacitor unit C2. Further, the method comprises computing, using the computed nominal duty cycles d , (t), d2(t) and the estimated imbalance, duty cycles Ad, (t), Ad2(t) that counter the estimated imbalance (as shown in FIGs 10 a) and 10 b)), and controlling the controllable semiconductor switches of the power converters using the computed duty cycles d, (t), d2(t), Ad, (t), Ad2(t), as shown in FIGs. I l a) and 11 b).

[0112] For example, as shown in FIG. 9 a), computing, using the measured current it (t) and voltage v, (t) at the first terminal X of the first power converter 21 of the converter 1, the nominal duty cycle d, (t) for switching the controllable semiconductor switches of the first power converter 21 with regard to the MPPT comprises computing for the current it (t) measured at the first terminal X of the first power converter 21 an error with regard to a set value ldfor the current, the set value ldbeing computed by performing the MPPT algorithm using the current it (t) and voltage v, (t) measured at the first terminal X of the first power converter 21 , and computing, using the computed error, the nominal duty cycle d , (t) for switching the switches of the first power converter 21. As shown in FIG. 9 a), computing the nominal duty cycle d , (t) for switching the switches of the first power converter 21 may comprise inputting the computed error in a controller Kc. The controller Kc may be a proportional controller and the result may be added with an integral controller. In FIGs 9 a) and 9 b), the box 1 J c ” represents an integrator.

[0113] That is, the nominal duty d , (t) may be obtained by proportional integral control that aims at input current control in order to maintain the MPPT point. The integral part of the control is used to achieve zero error when tracking .

[0114] Accordingly, as shown in FIG. 9 b), computing, using the measured current i2(t) and voltage v2(t) at the first terminal X of the second power converter 22 of the converter 1, the nominal duty cycle d2(t) for switching the controllable semiconductor switches of the second power converter 22 with regard to the MPPT comprises computing for the current i2(t) measured at the first terminal X of the second power converter 22 an error with regard to a set value 12for the current, the set value 12being computed by performing the MPPT algorithm using the current i2(t) and voltage v2(t) measured at the first terminal X of the second power converter 22, and computing, using the computed error, the nominal duty cycle d2(t) for switching the switches of the second power converter 22. As shown in FIG. 9 b), computing the nominal duty cycle d2(t) for switching the switches of the second power converter 22 may comprise inputting the computed error in a controller Kc. The controller Kc may be a proportional controller and the result may be added with an integral controller. That is, the nominal duty d2(t) may be obtained by proportional integral control that aims at input current control in order to maintain the MPPT point. The integral part of the control is used to achieve zero error when tracking I2.

[0115] As shown in FIG. 9 c), estimating an imbalance in electrical energy between the first and second capacitor unit Cl, C2 may comprise computing a first electrical energy Edc lof the first capacitor unit Cl using the measured voltage Vdclbetween the first and second terminal of the first capacitor unit Cl (Edcl= being the capacitance of the first capacitor unit Cl), computing a second electrical energy Edclof the second capacitor unit C2 using the measured voltage Vdc2between the first and second terminal of the second capacitor unit C2 (Edcl= - C(Vdc2) , C being the capacitance of the second capacitor unit C2), and computing a difference between the first and second electrical energy Edcl, Edcl. As shown in FIG. 9 c), a correction duty cycle Ad'lc(t) may be computed by inputting the computed difference between the first and second electrical energy Edcl, Edclin a controller Kdci. The duty cycles Ad, (t), Ad2(t) that counter the estimated imbalance may be computed using the computed correction duty cycle Addc(t).

[0116] As shown in FIG. 10 a), in case the first and second power converter 21, 22 do not comprise capacitors Cfl, Cf2 (i.e. no flying capacitors), each of the duty cycles Ad , (t), Ad2(t) that counter the estimated imbalance equal to the computed correction duty cycle Addc(t). For example, this may be the case for the implementation forms of the power converters 21 , 22 shown in FIGs. 4 a), 4 b), 5 a) and 5 b).

[0117] In case the first and second power converter 21, 22 comprise capacitors Cfl, Cf2 (flying capacitors), FIG. 10 b) shows an example of computing the duty cycles Ad, (t), Ad2(t) (may be referred to as total correction duty cycle) that counter the estimated imbalance using the computed correction duty cycle Addc(t). FIGs 6 and 7 show examples of implementation forms where the first and second power converter 21, 22 comprise capacitors Cfl, Cf2 (flying capacitors).

[0118] As shown in FIG. 10 b), for computing with regard to the first power converter 21 a total correction duty cycle Ad , (t), a second difference between the electrical energy Efclof the flying capacitor Cfl of the first power converter 21 (Efcl= - C(Vfc l) , C being the capacitance of the flying capacitor Cfl) and the electrical energy EfC1of the first capacitor unit Cl that is electrically connected in parallel to the first power converter 21 (EfC1= being the capacitance of the first capacitor unit Cl) may be computed. Next a second correction duty cycle Adfc l(t) may be computed by inputting the computed second difference in a controller KfC. The controller KfCmay be a proportional (P) controller. Next a total correction duty cycle Ad, (t) may be computed by summing the correction duty cycle Addc(t) and the second correction duty cycle Adfc l(t).

[0119] As shown in FIG. 11 a), for controlling the controllable semiconductor switches of the first power converter 21 duty cycles may be computed using the computed nominal duty cycle d, (t) and the correction duty cycle Ad, (t) for countering an imbalance between capacitors of the converter 1, wherein the computed duty cycles may be used for generating PWM control signals. In case the first power converter 21 does not comprise a flying capacitor, the duty cycle Ad, (t) is a duty cycle for countering the imbalance between electrical energies of the first and second capacitor units Cl, C2 and equals to the computed correction duty cycle Ad'lc(t). as shown in FIG. 10 (a). In case the first power converter 21 comprises a flying capacitor Cfl, the duty cycle Ad , (t) is a duty cycle for countering the imbalance between electrical energies of the first and second capacitor units C 1 , C2 and an imbalance between electrical energies of the first capacitor unit Cl and the flying capacitor Cfl and equals to the computed total correction duty cycle Ad , (t), as shown in FIG. 10 (b).

[0120] As shown in FIG. 11 b), for controlling the controllable semiconductor switches of the second power converter 22 duty cycles may be computed using the computed nominal duty cycle d2(t) and the correction duty cycle Ad2(t) for countering an imbalance between capacitors of the converter 1, wherein the computed duty cycles may be used for generating PWM control signals. In case the second power converter 22 does not comprise a flying capacitor, the duty cycle Ad2(t) is a duty cycle for countering the imbalance between electrical energies of the first and second capacitor units Cl, C2 and equals to the computed correction duty cycle Ad'lc(t), as shown in FIG. 10 (a). In case the second power converter 22 comprises a flying capacitor Cf2, the duty cycle Ad2(t) is a duty cycle for countering the imbalance between electrical energies of the first and second capacitor units Cl, C2 and an imbalance between electrical energies of the second capacitor unit C2 and the flying capacitor Cf2 and equals to the computed total correction duty cycle Ad2(t), as shown in FIG. 10 (b).

[0121] FIGs I l a) and 11 b) exemplarily show the PWM control signals for the controllable semiconductor switches of the converter of FIG. 6. The PWM control signals for the switches S3 and S4 of the second switch unit SU2 of the first power converter 21 are labelled as “PWM2i,s3” and “PWM2i,s4”, respectively. The PWM control signals for the switches SI and S2 of the first switch unit SU 1 of the second power converter 22 are labelled as “PWM22,SI” and “PWM22.S2”, respectively.

[0122] In case of the bidirectional converter 1 of FIG. 7, for controlling a power conversion from the first, second , third and fourth terminal Tl, T2, T3, T4 of the converter 1 to the fifth and sixth terminal T5, T6 of the converter 1, the switches S3, S4 of the second switch unit SU2 of the first power converter 21 and the switches SI, S2 of the first switch unit SU1 of the second power converter 22 may be controlled using the control signals PWM21.S3, PWM21.S4, PWM22,SI and PWM22.S2, respectively, while the switches S I, S2 of the first switch unit SU 1 of the first power converter 21 and the switches S3 , S4 of the second switch unit SU2 of the second power converter 22 are not switched (i.e. duty cycle = 0). In case of the bidirectional converter 1 of FIG. 7, for controlling a power conversion from the fifth and sixth terminal T5, T6 of the converter 1 to the first, second , third and fourth terminal Tl, T2, T3, T4 of the converter 1, the switches S2 SI of the first switch unit SU1 of the first power converter 21 and the switches S4, S3 of the second switch unit SU2 of the second power converter 22 may be controlled using the separate control signals PWM21.S3, PWM21.S4, PWM22,SI and PWM22.S2, respectively. The method steps of FIGs 8, 9 a), 9 b) and 9 c), 10 a), 10 b), I l a) and 11 b) may be extended with regard to using the converter 1 of FIG. 7 for discharging and charging battery energy storages 100, 200 (BES) in order to achieve the state of charge (SOC) of the BES 100, 200, where the desired current may be determined by a SOC algorithm. The converter according to this disclosure, such as the converter, especially the control unit of the converter 1, according to any one FIGs 1, 2, 3, 4 a), 4 b), 5 a), 5 b), 6 and 7, is configured to perform the method according to this disclosure, such as the method according to any one of FIGs 8, 9 a), 9 b) and 9 c), 10 a), 10 b), I l a) and 11 b). The control device according to this disclosure, such as the control device 400 according to any one FIGs 1 and 6, is configured to perform the method according to this disclosure, such as the method according to any one of FIGs 8, 9 a), 9 b) and 9 c), 10 a), 10 b), I l a) and 11 b). In case the control device performs a method, the converter may measure the current(s) and voltage(s) and the control device is configured to obtain the measured current(s) and voltage(s).

[0123] The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A method for controlling a converter (1), wherein the converter (1) comprises: a first, second, third and fourth terminal (Tl, T2, T3, T4) for receiving DC voltages, a first and second power converter (21, 22) each comprising a first, second and third terminal (X, Yl, Y2) and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal (X) to a further voltage of lower or higher level at the second and third terminal (Y 1 , Y2), and a series connection of a first and second capacitor unit (Cl, C2), wherein the first terminal (X) of the first power converter (21) is electrically connected with the second terminal (T2) of the converter (1), the second and third terminal (Yl, Y2) of the first power converter (21) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (Tl) of the converter (1) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (22) is electrically connected with the third terminal (T3) of the converter (1), the second and third terminal (Yl, Y2) of the second power converter (22) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter (1) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the method comprises: measuring ( 1000) a current and a voltage at the first terminal (X) of each of the first and second power converter (21, 22), measuring (2000) a voltage between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and controlling (3000) the semiconductor switches of the first and second power converter (21, 22) by performing, using the measured currents and voltages, a maximum power point tracking, MPPT, algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit (Cl, C2).

2. The method according to claim 1, wherein the converter (1) comprises: one or more additional first power converters (21, 21a) with the first terminal (X) being electrically connected to a respective further terminal (Ta) of the converter (1) and the second and third terminal (Yl, Y2) being electrically connected to the first and second terminal of the first capacitor unit (Cl), respectively, and one or more additional second power converters (22, 22a) with the first terminal (X) being electrically connected to a respective further terminal (Tb) of the converter (1) and the second and third terminal (Yl, Y2) being electrically connected to the first and second terminal of the second capacitor unit (C2), respectively; and the method comprises: measuring a current and a voltage at the first terminal (X) of each of the first power converter (21), the second power converter (22), the one or more additional first power converters (21, 21a) and the one or more additional second power converters (22, 22a), measuring a voltage between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), andcontrolling the semiconductor switches of the power converters (21, 22, 21a, 22a) of the converter (1) by performing, using the measured currents and voltages, the MPPT algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit (Cl, C2).

3. The method according to any one of the previous claims, wherein the method comprises: computing, using the measured currents and voltages at the first terminal (X) of the power converters (21 , 22) of the converter (1), nominal duty cycles for switching the controllable semiconductor switches of the power converters (21, 22) of the converter (1) with regard to the MPPT, estimating an imbalance in electrical energy between the first and second capacitor unit (C 1 , C2), computing, using the computed nominal duty cycles and the estimated imbalance, duty cycles that counter the estimated imbalance, and controlling the controllable semiconductor switches of the power converters (21, 22) using the computed duty cycles.

4. The method according to claim 3, wherein computing, using the measured currents and voltages at the first terminal (X) of the power converters (21, 22) of the converter (1), the nominal duty cycles for switching the controllable semiconductor switches of the power converters (21, 22) of the converter (1) with regard to the MPPT comprises: computing for the current measured at the first terminal (X) of a power converter of the power converters (21 , 22) of the converter (1) an error with regard to a set value for the current, the set value being computed by performing the MPPT algorithm using the current and voltage measured at the first terminal (X) of the power converter of the power converters (21, 22) of the converter (1), and computing, using the computed error, a nominal duty cycle of the nominal duty cycles.

5. The method according to claim 4, wherein the method comprises: computing the nominal duty cycle of the nominal duty cycles by inputting the computed error in a controller.

6. The method according to any one of claims 3 to 5, wherein estimating an imbalance in electrical energy between the first and second capacitor unit (Cl, C2) comprises: computing a first electrical energy of the first capacitor unit (Cl) using the measured voltage between the first and second terminal of the first capacitor unit (Cl), computing a second electrical energy of the second capacitor unit (C2) using the measured voltage between the first and second terminal of the second capacitor unit (C2), computing a difference between the first and second electrical energy.

7. The method according to claim 6, wherein computing, using the computed nominal duty cycles and the estimated imbalance, duty cycles that counter the estimated imbalance comprises: computing a correction duty cycle by inputting the computed difference in a controller, and computing the duty cycles that counter the estimated imbalance using the computed correction duty cycle.

8. The method according to claim 6, wherein a power converter of the power converters (21 , 22) of the converter (1) comprises a flying capacitor (Cf 1 , Cf2), and the method comprises: computing a second difference between the electrical energy of the flying capacitor (Cfl, Cf2) of the power converter and the electrical energy of a capacitor unit of the first and second capacitor unit (Cl, C2) that is electrically connected in parallel to the power converter,computing a correction duty cycle by inputting the computed difference in a controller, computing a second correction duty cycle by inputting the computed second difference in a second controller, computing a total correction duty cycle by summing the correction duty cycle and the second correction duty cycle, and computing the duty cycles that counter the estimated imbalance using the computed total correction duty cycle.

9. The method according to any one of the previous claims, wherein each of the first and second power converter (21 , 22) is a partial power converter.

10. The method according to any one of the previous claims, wherein the converter (1) is unidirectional and each of the first, second, third and fourth terminal (Tl, T2, T3, T4) of the converter (1) is an input terminal, or the converter (1) is bidirectional.

11. The method according to any one of the previous claims, wherein the converter (1) comprises a fifth and sixth terminal (T5, T6) that are configured to be electrically connected with an electrical load (300), the fifth terminal (T5) is electrically connected with the first terminal of the first capacitor unit (Cl), and the sixth terminal (T6) is electrically connected with the second terminal of the second capacitor unit (C2).

12. The method according to any one of the previous claims, wherein a capacitor unit of the first and second capacitor unit (Cl, C2) comprises a capacitor (Cl 1) or multiple capacitors (Cl 1, C12) electrically connected in series.

13. The method according to any one of the previous claims, wherein the second terminal of the first capacitor unit (C 1) is electrically connected with the first terminal of the second capacitor unit (C2), or the second terminal of the first capacitor unit (C 1) is electrically connected to a first terminal of a third capacitor unit (C3) and the first terminal of the second capacitor unit (C2) is electrically connected to a second terminal of the third capacitor unit (C3).

14. The method according to claim 13, wherein the third capacitor unit (C3) comprises a capacitor or multiple capacitors electrically connected in series.

15. A control device (400) for controlling a converter (1), wherein the converter comprises: a first, second, third and fourth terminal (Tl, T2, T3, T4) for receiving DC voltages, a first and second power converter (21, 22) each comprising a first, second and third terminal (X, Yl, Y2) and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal (X) to a further voltage of lower or higher level at the second and third terminal (Yl , Y2), and a series connection of a first and second capacitor unit (Cl, C2), wherein the first terminal (X) of the first power converter (21) is electrically connected with the second terminal (T2) of the converter (1), the second and third terminal (Y 1 , Y2) of the first power converter (21) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively,the first terminal (Tl) of the converter (1) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (22) is electrically connected with the third terminal (T3) of the converter (1), the second and third terminal (Yl, Y2) of the second power converter (22) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter (1) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the control device (400) is configured to: obtain a measured current and voltage at the first terminal (X) of each of the first and second power converter (21, 22), obtain a measured voltage between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and control the semiconductor switches of the first and second power converter (21, 22) by performing, using the measured currents and voltages, a maximum power point tracking, MPPT, algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit (C 1 , C2).

16. A converter (1), comprising: a first, second, third and fourth terminal (Tl, T2, T3, T4) for receiving DC voltages, a first and second power converter (21, 22) each comprising a first, second and third terminal (X, Yl, Y2) and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal (X) to a further voltage of lower or higher level at the second and third terminal (Y 1 , Y2), and a series connection of a first and second capacitor unit (Cl, C2), wherein the first terminal (X) of the first power converter (21) is electrically connected with the second terminal (T2) of the converter (1), the second and third terminal (Yl, Y2) of the first power converter (21) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (Tl) of the converter (1) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (22) is electrically connected with the third terminal (T3) of the converter (1), the second and third terminal (Yl, Y2) of the second power converter (22) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter (1) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the converter (1) is configured to: measure current and a voltage at the first terminal (X) of each of the first and second power converter (21, 22), measure a voltage between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and control the semiconductor switches of the first and second power converter (21, 22) by performing, using the measured currents and voltages, a maximum power point tracking, MPPT, algorithm and a balancing algorithm for balancing the electrical energies of the first and second capacitor unit (C 1 , C2).

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