Capacitor

Abstract

A capacitor according to the present invention includes a dielectric film that has a first surface and a second surface that faces the opposite direction from the first surface, a high-potential-side first electrode that is provided on the first surface of the dielectric film, and a low-potential-side second electrode that is provided on the second surface of the dielectric film. The work function of the first electrode is greater than the work function of the second electrode.

Description

capacitor

[0001] The present disclosure relates to capacitors.

[0002] Patent Document 1 describes a capacitor having an opening penetrating the front and back surfaces of a substrate, in which conductive plates and capacitor dielectric layers are alternately formed.

[0003] Special Publication No. 2014-505354

[0004] Electrons or holes that overcome the energy barrier resulting from the difference in work function between the capacitor dielectric layer and the conductive plate result in leakage current in the capacitor, degrading the performance of the capacitor.

[0005] An object of the present disclosure is to provide a capacitor with reduced leakage current.

[0006] A capacitor according to one or more embodiments of the present disclosure includes a dielectric film having a first surface and a second surface facing in a direction opposite to the first surface, a first electrode on a high potential side disposed on the first surface of the dielectric film, and a second electrode on a low potential side disposed on the second surface of the dielectric film, wherein the work function of the first electrode is greater than the work function of the second electrode.

[0007] According to one or more embodiments of the present disclosure, a capacitor with reduced leakage current can be provided.

[0008] FIG. 1 is a cross-sectional view showing the configuration of a capacitor 100 according to the first embodiment. FIG. 2 is a cross-sectional view showing an example of a manufacturing method for the capacitor 100. FIG. 3 is a cross-sectional view showing the band structure of a capacitor according to a comparative example. FIG. 4 is a cross-sectional view showing the band structure of the capacitor 100. FIG. 5 is a graph showing the relationship between applied voltage and leakage current for a capacitor according to a comparative example and the capacitor 100. FIG. 6 is a cross-sectional view showing the configuration of a capacitor 101 according to a second embodiment. FIG. 7A is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 1). FIG. 7B is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 2). FIG. 7C is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 3). FIG. 7D is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 4). FIG. 7E is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 5). FIG. 7F is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 6). FIG. 7G is a cross-sectional view showing the manufacturing process of the capacitor 101 (part 7). FIG. 8 is a cross-sectional view showing the configuration of a capacitor 102 according to a third embodiment. FIG. 9 is a cross-sectional view showing the configuration of a capacitor 103 according to the fourth embodiment.

[0009] Capacitors 100 to 103 according to the embodiments will be described in detail below with reference to the drawings. The embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, component placement locations, and connection configurations shown in the following embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts are described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. The following embodiments and their variations may include similar components, and common reference numerals will be used to denote similar components, and redundant explanations will be omitted.

[0010] First Embodiment [Capacitor 100] Figure 1 is a cross-sectional view showing the configuration of a capacitor 100 according to the first embodiment. The capacitor 100 according to the first embodiment includes a dielectric film 3 having a first surface 3A and a second surface 3B facing in the opposite direction to the first surface 3A, a first electrode 4 on the high potential side disposed on the first surface 3A of the dielectric film 3, and a second electrode 2 on the low potential side disposed on the second surface 3B of the dielectric film 3. The capacitor is formed by sandwiching both surfaces (3A, 3B) of the dielectric film 3 between a pair of electrodes (4, 2). The first electrode 4 and the second electrode 2 are flat plate-shaped and arranged in parallel. That is, the capacitor 100 is a parallel plate capacitor.

[0011] The materials of the first electrode 4 and the second electrode 2 are selected based on the magnitude of their work functions. Specifically, the materials of the first electrode 4 and the second electrode 2 are selected so that the work function of the first electrode 4 is larger than the work function of the second electrode 2.

[0012] For example, the first electrode 4 and the second electrode 2 may each include a semiconductor. In this case, the first electrode 4 includes a semiconductor doped with P-type impurities. This increases the work function of the first electrode 4. The second electrode 2 includes a semiconductor doped with N-type impurities. This decreases the work function of the first electrode 4. For example, polysilicon (poly-Si) can be used as the semiconductor. In this case, the P-type impurities include trivalent elements such as boron (B) and indium (In). The N-type impurities include pentavalent elements such as phosphorus (P) and arsenic (As).

[0013] Alternatively, the first electrode 4 and the second electrode 2 may each contain a metal. A conductive material with a large work function, such as nickel (Ni), or nickel silicide, can be used as the metal material for the first electrode 4. A metal with a small work function, such as titanium (Ti) or titanium silicide, can be used as the metal material for the second electrode 2.

[0014] The first electrode 4 and the second electrode 2 may be metal films or silicide films made of conductive materials such as polysilicon carbide (SiC), silicon germanium (SiGe), and aluminum (Al). The dielectric film 3 may be a silicon oxide film (SiO ２ ) or silicon nitride film (Si ３ N ４ ) can be used.

[0015] The capacitor 100 further includes a substrate 1 having a third surface 1A and a fourth surface 1B facing in the opposite direction to the third surface 1A. A second electrode 2, a dielectric film 3, and a first electrode 4 are stacked in this order on the third surface 1A of the substrate 1. The substrate 1 is a semiconductor substrate, and may be made of, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (GaO ３ ) is a single crystal substrate.

[0016] The capacitor 100 further has a first pad electrode 5 arranged above the third surface 1A of the substrate 1 and a second pad electrode 6 arranged on the fourth surface 1B of the substrate 1. The first pad electrode 5 is ohmically connected to the first electrode 4. The second pad electrode 6 is ohmically connected to the second electrode 2 via the substrate 1. The capacitor 100 can be electrically connected to an external electronic component via the first pad electrode 5 and the second pad electrode 6.

[0017] The basic operation of the capacitor 100 in Figure 1 will be described. A positive voltage is applied to the first electrode 4 with respect to the second electrode 2 as the reference. Alternatively, a negative voltage is applied to the second electrode 2 with respect to the first electrode 4 as the reference. A potential difference is generated between the first electrode 4 and the second electrode 2, and a positive charge is attracted to the first electrode 4 by electrostatic induction, and a negative charge is attracted to the second electrode 2. At this time, polarization occurs within the dielectric film 3, generating capacitance. In this way, the capacitor 100 can charge between the first electrode 4 and the second electrode 2 by applying a voltage between the first electrode 4 and the second electrode 2.

[0018] [Method of Manufacturing Capacitor 100] An example of a method of manufacturing the capacitor 100 will be described with reference to Fig. 2. Note that the method of manufacturing the capacitor 100 described below is just one example, and various other manufacturing methods can be used.

[0019] A semiconductor substrate doped with a high concentration of N-type or P-type impurities is prepared as the substrate 1. When a Si substrate is used, an N-type semiconductor substrate can be manufactured by adding an impurity of a pentavalent element such as phosphorus (P) or arsenic (As), and a P-type semiconductor substrate can be manufactured by adding an impurity of a trivalent element such as boron (B) or gallium (Ga).

[0020] A film containing a conductive semiconductor or metal is deposited on the third surface 1A of the substrate 1 as the second electrode 2. When a polysilicon film is used as the second electrode 2, a low-pressure CVD (chemical vapor deposition) method can be used as the polysilicon deposition method. When depositing the polysilicon, a gas containing an N-type impurity is mixed into the source gas, or a non-doped polysilicon film is formed and then annealed in POCL3 at 950°C. This dopes the polysilicon film with N-type impurities such as phosphorus (P), making the second electrode 2 conductive. Of course, instead of a polysilicon film, a titanium film or titanium silicide film may be deposited using a sputtering method or a CVD method.

[0021] Next, a silicon oxide film is deposited on the second electrode 2 as the dielectric film 3. Examples of the deposition method that can be used include thermal oxidation, thermal CVD, atomic layer deposition (ALD), and the like. A silicon nitride film may be deposited instead of or in addition to the silicon oxide film. This results in the formation of the dielectric film 3 and the second electrode 2 disposed on the second surface 3B of the dielectric film 3.

[0022] Next, a film containing a conductive semiconductor or metal is deposited on the dielectric film 3 as the first electrode 4. When a polysilicon film is used as the first electrode 4, low-pressure CVD can be used as the polysilicon deposition method. When depositing the polysilicon, a material gas containing a P-type impurity is mixed. Alternatively, after forming a non-doped polysilicon film, P-type impurity ions are implanted into the polysilicon film by ion implantation, and the P-type impurity is activated by annealing. This further forms the first electrode 4 disposed on the first surface 3A of the dielectric film 3. The state after the above steps is shown in FIG. 2.

[0023] Thereafter, pad electrodes 5 and 6 are formed on both the fourth surface 1B of the substrate 1 and the first electrode 4. A titanium / aluminum (Ti / Al) film is deposited as the pad electrodes 5 and 6. The deposition method can be sputtering, EB (Electron Beam) evaporation, or ALD. This forms the first pad electrode 5 that is ohmic-connected to the first electrode 4, and the second pad electrode 6 that is ohmic-connected to the second electrode 2 via the substrate 1. Through the above steps, the capacitor 100 shown in FIG. 1 is completed.

[0024] According to the capacitor 100 of the first embodiment, the following effects can be obtained.

[0025] FIG. 3 is a cross-sectional view showing the band structure of a capacitor according to a comparative example. FIG. 4 is a cross-sectional view showing the band structure of a capacitor 100. In the capacitor of FIG. 3, the work function of the high-potential electrode is equal to the work function of the low-potential electrode. Specifically, both the high-potential electrode and the low-potential electrode are made of polysilicon films (P+Si) doped with the same concentration of P-type impurities. On the other hand, in the capacitor 100 according to the first embodiment of FIG. 4, the work function of the first electrode 4 on the high-potential side is greater than the work function of the second electrode 2 on the low-potential side. Specifically, the first electrode 4 on the high-potential side is made of a polysilicon film (P+Si) doped with P-type impurities, and the second electrode 2 on the low-potential side is made of a polysilicon film (N+Si) doped with N-type impurities. In FIGS. 3 and 4, reference numeral 23 denotes the Fermi level.

[0026] The difference in work function causes a difference in the height of the energy barrier generated between the two electrodes sandwiching the dielectric film 3. Between the two electrodes of the comparative capacitor shown in Figure 3, the energy level of the upper end of the valence band 22A and the energy level of the lower end of the conduction band 21A are equal. Therefore, the energy barrier 24A that electrons must overcome to reach the energy level of the lower end of the conduction band 21A of the electrode on the lower potential side from the energy level of the lower end of the conduction band 21A of the electrode on the higher potential side is small, approximately equal to the difference in the conduction bands between the electrode 4 and the dielectric film 3.

[0027] 4, the energy levels of the upper end of the valence band 22B and the lower end of the conduction band 21B of the first electrode 4 on the high potential side are higher than the energy levels of the upper end of the valence band 22B and the lower end of the conduction band 21B of the second electrode 2 on the low potential side. Therefore, an energy barrier 24B that electrons must overcome to reach the energy level of the lower end of the conduction band 21B of the first electrode 4 on the high potential side from the energy level of the lower end of the conduction band 21B of the second electrode 2 on the low potential side is higher than that in FIG. 3 by the difference between the work functions of the first electrode 4 and the second electrode 2.

[0028] The results of calculations performed by the inventors of the present application will be described with reference to FIG. 5. FIG. 5 is a graph showing the relationship between the magnitude of leakage current and the applied voltage for the capacitor of the comparative example (FIG. 3) and the capacitor 100 according to the first embodiment. The capacitor of the comparative example (FIG. 3) was able to keep the leakage current low, similar to the capacitor 100, up to about 30 V. However, at applied voltages of 30 V or higher, the leakage current increased significantly depending on the applied voltage. On the other hand, the capacitor 100 was able to keep the leakage current low even at voltages of 30 V or higher. While the withstand voltage of the comparative example was 30 V, it was found that the withstand voltage of the capacitor 100 could be increased to 100 V or higher.

[0029] As described above, in the capacitor 100, the work function of the first electrode 4 on the high potential side is greater than the work function of the second electrode 2 on the low potential side. Therefore, the energy barrier 24B that electrons must overcome to reach the energy level of the lower end of the conduction band 21B of the first electrode 4 from the energy level of the lower end of the conduction band 21B of the second electrode 2 can be increased by the difference between the work functions of the first electrode and the second electrode. Therefore, compared to when there is no difference in work functions ( FIG. 3 ), the leakage current from the first electrode 4 to the second electrode 2 can be suppressed. Specifically, compared to when there is no difference in work functions ( FIG. 3 ), the voltage limit (withstand voltage) at which the leakage current can be suppressed can be increased.

[0030] 4, the energy level of the lower end of the conduction band 21B of the dielectric film 3 is higher than the energy level of the lower end of the conduction band 21B of the second electrode 2. This increases the energy barrier of the dielectric film 3 as viewed from the second electrode 2. This further reduces the leakage current from the first electrode 4 to the second electrode 2.

[0031] The first electrode 4 and the second electrode 2 may each contain a metal, which can reduce the internal resistance of the first electrode 4 and the second electrode 2.

[0032] The first electrode 4 and the second electrode 2 may each contain a semiconductor, which allows the work functions of the first electrode 4 and the second electrode 2 to be freely designed by adjusting the concentration of added impurities.

[0033] The first electrode 4 may include a semiconductor doped with P-type impurities. By doping the first electrode 4 with P-type impurities, the work function of the first electrode 4 can be increased. This increases the energy level at the bottom of the conduction band of the first electrode 4, and increases the difference in work function between the first electrode 4 and the second electrode 2. This increases the energy barrier that electrons must overcome to reach the conduction band of the second electrode 2 from the conduction band of the first electrode 4.

[0034] The second electrode 2 may include a semiconductor doped with N-type impurities. By doping the second electrode 2 with N-type impurities, the work function of the second electrode 2 can be reduced. This lowers the energy level of the lower end of the conduction band of the second electrode 2, and increases the difference in work function between the first electrode 4 and the second electrode 2. This increases the energy barrier that electrons must overcome to reach the conduction band of the second electrode 2 from the conduction band of the first electrode 4.

[0035] A second electrode 2, a dielectric film 3, and a first electrode 4 are laminated on a third surface 1A of the substrate 1. By fabricating a capacitor on the substrate 1, the capacitor can be integrated with other elements such as transistors.

[0036] The capacitor 100 further includes a first pad electrode 5 disposed above the third surface 1A of the substrate 1 and ohmically connected to the first electrode 4, and a second pad electrode 6 disposed on the fourth surface 1B of the substrate 1 and ohmically connected to the second electrode 2. This allows a plurality of chip-shaped capacitors 100 to be stacked and the pad electrodes to be electrically connected to each other. This makes it possible to easily fabricate a capacitor module with improved capacitance or voltage resistance.

[0037] Second Embodiment [Capacitor 101] FIG. 6 is a cross-sectional view showing the configuration of a capacitor 101 according to the second embodiment. The capacitor 101 according to the second embodiment differs from the capacitor 100 according to the first embodiment in that the capacitor 101 is formed not only on the third surface 1A of the substrate 1 but also inside a groove 7 formed on the third surface 1A of the substrate 1. That is, the capacitor 101 has a layered structure consisting of a first electrode 4, a dielectric film 3, and a second electrode 2 stacked along the side and bottom surfaces of the groove 7 and the third surface 1A. Furthermore, a plurality of such layered structures are formed on the side and bottom surfaces of the groove 7 and the third surface 1A. Specifically, the first electrodes 4 and the second electrodes 2 are alternately stacked in three layers with the dielectric film 3 interposed between them on the side and bottom surfaces of the groove 7 and the third surface 1A. The interior of the groove 7 is backfilled with the plurality of such layered structures.

[0038] The capacitor 101 includes a first pad electrode 15 and a second pad electrode 14 disposed above the third surface 1A of the substrate 1. A plurality of contact holes (9, 10, 13) are formed in the laminate structure on the third surface 1A. The plurality of contact holes include first contact holes 10a and 10b whose bottom surfaces reach the first electrode 4 and second contact holes 9a, 9b, and 9c whose bottom surfaces reach the second electrode 2. An interlayer film 11 is formed on the bottom and side surfaces of the first contact holes 10a and 10b and on the bottom and side surfaces of the second contact holes 9a, 9b, and 9c. The interlayer film 11 is also formed on the laminate structure on the third surface 1A. The plurality of contact holes includes an interlayer film contact hole 13. The interlayer film contact hole 13 is formed on the bottom surfaces of the first contact holes 10a and 10b and the second contact holes 9a, 9b, and 9c. The interlayer film contact hole 13 penetrates the interlayer film 11 and has a bottom surface that reaches the first electrode 4 or the second electrode 2 .

[0039] The first pad electrode 15 is ohmically connected to the first electrode 4 via contact plugs embedded in the first contact holes 10a and 10b and the interlayer film contact hole 13. The second pad electrode 14 is ohmically connected to the second electrode 2 via contact plugs embedded in the second contact holes 9a, 9b, and 9c and the interlayer film contact hole 13.

[0040] The basic operation of the capacitor 101 is the same as that of the capacitor 100 of the first embodiment, and therefore will not be described again.

[0041] 7A to 7G, an example of a method for manufacturing the capacitor 101 will be described. Note that the method for manufacturing the capacitor 101 described below is just an example, and various other manufacturing methods can be used.

[0042] As the substrate 1, a semiconductor substrate doped with a high concentration of N-type or P-type impurities is prepared.

[0043] In the groove forming process, as shown in FIG. 7A , a groove 7 is formed on the third surface 1A of the substrate 1. Specifically, a portion of the substrate 1 is etched to form the groove 7 having a side surface 7A and a bottom surface 7B. For example, first, a mask material (not shown) such as a silicon oxide film is deposited on the third surface 1A of the substrate 1, and the mask material is patterned using photolithography. The patterned mask material has openings where the grooves 7 will be formed. The silicon oxide film can be deposited using thermal CVD (chemical vapor deposition) or plasma CVD. The silicon oxide film can be etched using wet etching using hydrofluoric acid or dry etching such as reactive ion etching. The resist used in the photolithography process can be removed using oxygen plasma, sulfuric acid, or the like.

[0044] Next, the substrate 1 exposed through the openings in the mask material is dry-etched using the mask material to form the grooves 7. If the substrate 1 is a silicon substrate, it can be processed inexpensively using a wet etching technique that uses a KOH solution or a TMAH (tetramethylammonium hydroxide) solution. On the other hand, a dry etching method using plasma enables highly accurate groove processing.

[0045] In the groove formation process, an anisotropic etching technique may be used to expose the silicon (111) plane along the cleavage plane of the substrate 1 on the side surface 7A of the groove 7. For example, by adjusting the crystal orientation of the substrate 1 used and the pattern shape of the mask material, the silicon (111) plane can be exposed on the side surface 7A. This increases the strength of the groove 7. The corners where the side surface 7A of the groove 7 intersect with the third surface 1A of the substrate 1 and the corners where the side surface 7A of the groove 7 intersect with the bottom surface 7B have arc shapes with a predetermined curvature. This reduces stress concentration at the corners.

[0046] Next, in the stacking process, electrode films and dielectric films are alternately deposited on at least the third surface 1A of the substrate 1 and the side surfaces 7A and bottom surfaces 7B of the grooves 7 to form multiple stacked structures consisting of the first electrodes 4, the dielectric films 3, and the second electrodes 2.

[0047] For example, first, as shown in FIG. 7B , the second electrode 2 is deposited. When a polysilicon film is used as the second electrode 2, a low-pressure CVD method can be used as the polysilicon deposition method. After the polysilicon film is deposited, an annealing treatment is performed in POCL3 at 950° C. to form N-type polysilicon, thereby making the second electrode 2 conductive. Of course, instead of a polysilicon film, a titanium film or a titanium silicide film may be deposited using a sputtering method or a CVD method.

[0048] 7C, a dielectric film 3 is deposited to cover the second electrode 2. When the dielectric film 3 is a silicon oxide film, a thermal CVD method can be used as a method for depositing the silicon oxide film. When using the thermal CVD method, a reduced pressure condition allows the silicon oxide film to be deposited with good coverage even when the trench 7 is deep and has a complex shape.

[0049] Next, a first electrode 4 is deposited on the dielectric film 3. When a polysilicon film is used as the first electrode 4, a low-pressure CVD method can be used as a method for depositing the polysilicon. When depositing the polysilicon, a material gas containing a P-type impurity is mixed. Alternatively, after forming a non-doped polysilicon film, P-type impurity ions may be implanted into the polysilicon film by ion implantation, and the P-type impurity may be activated by annealing.

[0050] The above lamination process is repeated with the dielectric film 3 interposed between the second electrode 2 and the first electrode 4. As shown in Fig. 7D, the first electrode 4 is deposited for the third time so that the groove 7 is filled up.

[0051] Next, as shown in FIG. 7E , a mask material 8 such as photoresist is formed on the first electrode 4, and the mask material 8 is patterned using photolithography. The patterned mask material 8 has openings in areas where the first contact holes 10a and 10b and the second contact holes 9a, 9b, and 9c will be formed. Next, the second electrode 2, the first electrode 4, and the dielectric film 3 exposed through the openings in the mask material 8 are etched to the desired depths shown in FIG. 7E by dry etching using the mask material 8. This forms the first contact holes 10a and 10b and the second contact holes 9a, 9b, and 9c. The mask material 8 is then removed using oxygen plasma, sulfuric acid, or the like.

[0052] Next, as shown in FIG. 7F, a silicon oxide film is deposited as an interlayer film 11 on the first electrode 4 and on the side and bottom surfaces of the first contact holes 10a and 10b and the second contact holes 9a, 9b, and 9c.

[0053] Next, as shown in FIG. 7G , a mask material 12 such as patterned photoresist is used to selectively etch and remove the interlayer film 11 on the bottom surfaces of the first contact holes 10a, 10b and the second contact holes 9a, 9b, and 9c, forming interlayer film contact holes 13. The corresponding first electrode 4 or second electrode 2 is exposed at the bottom surface of each interlayer film contact hole 13. The interlayer film 11 remains on the side surfaces of each of the first contact holes 10a, 10b and the second contact holes 9a, 9b, and 9c. The mask material 12 is then removed. The interlayer film contact holes 13 include contact holes formed in the interlayer film 11 to connect the first electrode 4 farthest from the substrate 1.

[0054] Next, a pad electrode film is deposited on the interlayer film 11 on the third surface 1A side of the substrate 1. The pad electrode film is buried in the first contact holes 10a and 10b, the second contact holes 9a, 9b, and 9c, and the interlayer film contact hole 13. The pad electrode film is electrically connected to the first electrode 4 or the second electrode 2. When the pad electrode film is a metal film such as titanium (Ti), nickel (Ni), or molybdenum (Mo), the metal film can be formed by sputtering, electron beam (EB) evaporation, or ALD.

[0055] Finally, the pad electrode film is etched using a patterned mask material (not shown), thereby forming the first pad electrode 15 and the second pad electrode 14 as shown in Fig. 6. Through the above steps, the capacitor 101 can be manufactured.

[0056] According to the capacitor 101 of the second embodiment, the following effects can be obtained.

[0057] Since the first electrode 4, the dielectric film 3, and the second electrode 2 are stacked inside the groove 7, it is possible to fabricate the capacitor 101 inside the groove 7. The capacitance density of the capacitor 101 can be increased.

[0058] Since a plurality of laminated structures each consisting of a first electrode 4, a dielectric film 3, and a second electrode 2 are formed inside the groove 7, the capacitance density of the capacitor 101 can be further increased.

[0059] (Third Embodiment) [Capacitor 102] Figure 8 is a cross-sectional view showing the configuration of a capacitor 102 according to the third embodiment. The capacitor 102 according to the third embodiment differs from the capacitor 101 of the second embodiment in that the groove 7 penetrates from the third surface 1A to the fourth surface 1B, and the first electrode 4, the dielectric film 3, and the second electrode 2 are also laminated on the fourth surface 1B. All other points are common to the capacitor 101. Here, the differences from the capacitor 101 will be mainly described.

[0060] The capacitor 102 has a laminated structure consisting of a first electrode 4, a dielectric film 3, and a second electrode 2 laminated along the side surface of the groove 7, the third surface 1A, and the fourth surface 1B. Furthermore, a plurality of the above-described laminated structures are formed on the side surface of the groove 7, the third surface 1A, and the fourth surface 1B. Specifically, the first electrodes 4 and the second electrodes 2 are alternately laminated in three layers on the side surface of the groove 7, the third surface 1A, and the fourth surface 1B, with the dielectric film 3 interposed between them. The inside of the groove 7 is backfilled with the above-described laminated structure. On the fourth surface 1B side, an interlayer film 11 is formed on the above-described laminated structure, in the same manner as on the third surface 1A side.

[0061] Grooves 7 penetrate from third surface 1A to fourth surface 1B, thereby making it possible to further increase the capacity density.

[0062] According to the capacitor 102, the first electrode 4, the dielectric film 3, and the second electrode 2 are laminated on the fourth surface, so that the capacitance density can be further increased.

[0063] 9 is a cross-sectional view showing the configuration of a capacitor 103 according to a fourth embodiment. The capacitor 103 according to the fourth embodiment differs from the capacitor 102 according to the third embodiment in that pad electrodes 16 and 17 are also formed on the fourth surface 1B of the substrate 1. The remaining features are the same as those of the capacitor 102.

[0064] The capacitor 103 further includes a third pad electrode 17 connected to the first electrode 4 and disposed below the fourth surface 1B of the substrate 1, and a fourth pad electrode 16 connected to the second electrode 2 and disposed below the fourth surface 1B of the substrate 1. The third pad electrode 17 is ohmically connected to the first electrode 4 via contact plugs embedded in the first contact holes 10a and 10b and the interlayer film contact hole 13. The fourth pad electrode 16 is ohmically connected to the second electrode 2 via contact plugs embedded in the second contact holes 9a, 9b, and 9c and the interlayer film contact hole 13.

[0065] The third pad electrode 17 and the fourth pad electrode 16 can be manufactured using the same material and manufacturing method as the first pad electrode 15 and the second pad electrode 14 .

[0066] By forming a high-potential side pad electrode and a low-potential side pad electrode on both the third surface 1A and the fourth surface 1B of the substrate 1, chip-shaped capacitors 103 can be stacked to easily produce a capacitor module with improved capacity or voltage resistance.

[0067] The above-described embodiment is merely an example of the present invention, and therefore the present invention is not limited to the above-described embodiment, and various modifications can be made to the design and other aspects of the present invention without departing from the technical concept of the present invention.

[0068] 1 Substrate 1A Third surface 1B Fourth surface 2 Second electrode 3 Dielectric film 3A First surface 3B Second surface 4 First electrode 5 First pad electrode 6 Second pad electrode 7 Groove 7A Side surface 7B Bottom surface 9a, 9b, 9c Second contact hole 10a, 10b First contact hole 11 Interlayer film 13 Interlayer film contact hole 14 Second pad electrode 15 First pad electrode 16 Fourth pad electrode 17 Third pad electrode 21A, 21B Conduction band 22A, 22B Valence band 23 Fermi level 24A, 24B Energy barrier 100 to 103 Capacitor

Claims

a dielectric film having a first surface and a second surface facing in a direction opposite to the first surface; a first electrode on a high potential side disposed on the first surface of the dielectric film; a second electrode on a low potential side disposed on the second surface of the dielectric film, A capacitor, wherein the work function of the first electrode is greater than the work function of the second electrode.

2. The capacitor according to claim 1, wherein the energy level of the lower end of the conduction band of the dielectric film is higher than the energy level of the lower end of the conduction band of the second electrode. 　 The capacitor of claim 1 , wherein the first electrode and the second electrode each comprise a metal. 　 The capacitor of claim 1 , wherein the first electrode and the second electrode each comprise a semiconductor.

5. The capacitor of claim 4, wherein the first electrode comprises a P-type doped semiconductor.

6. The capacitor according to claim 4, wherein the second electrode comprises a semiconductor doped with N-type impurities. 　 a substrate having a third surface; The capacitor according to claim 1 , wherein the second electrode, the dielectric film, and the first electrode are stacked on the third surface of the substrate. 　 the substrate has a fourth surface facing in a direction opposite to the third surface; a first pad electrode disposed above a third surface of the substrate and ohmically connected to the first electrode; a second pad electrode that is ohmically connected to the second electrode and that is disposed above the third surface or on the fourth surface of the substrate; The capacitor of claim 7 further comprising: 　 a groove formed on a third surface of the substrate; 9. The capacitor according to claim 7, wherein the first electrode, the dielectric film, and the second electrode are stacked inside the groove. 　 a groove formed on a third surface of the substrate; 9. The capacitor according to claim 7, wherein a plurality of laminated structures each including the first electrode, the dielectric film, and the second electrode are formed inside the groove. 　 the substrate has a fourth surface facing in a direction opposite to the third surface; 11. The capacitor of claim 9, wherein the groove extends from the third surface to the fourth surface. 　 The capacitor according to claim 11 , wherein the first electrode, the dielectric film, and the second electrode are stacked on the fourth surface of the substrate. 　 a third pad electrode disposed below the fourth surface of the substrate and ohmically connected to the first electrode; a fourth pad electrode disposed below the fourth surface of the substrate and ohmically connected to the second electrode; The capacitor of claim 12 further comprising:

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