Semiconductor device, and manufacturing method for same

Abstract

This semiconductor device has: a bonding substrate; a first conductor film; and one or more dielectric films and a second conductor film. The bonding substrate comprises a first substrate having a first groove penetrating between a first main surface and a second main surface, and a second substrate having a second groove penetrating between a third main surface and a fourth main surface, the first substrate and the second substrate being bonded to form the bonding substrate. The first conductor film is formed so as to be in contact with at least, among all the surfaces of the bonding substrate, the first main surface, the fourth main surface, a wall surface of the first groove, and a wall surface of the second groove. The one or more dielectric films and the second conductor film are alternately laminated on the first conductor film.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] To increase the capacitance of a capacitor, a capacitor structure is formed inside a groove formed in a semiconductor substrate. For example, a structure in which a through hole in a semiconductor substrate is filled with a conductive film via an insulating film is disclosed (see Patent Document 1). By forming a capacitor structure inside the groove in the semiconductor substrate, a capacitor with a large capacitance can be realized.

[0003] JP 2012-089743 A

[0004] In order to increase the capacitance of a capacitor structure formed inside a trench, it is necessary to thicken the semiconductor substrate and form many narrow trenches. However, there is a limit to the aspect ratio of the depth and width of trenches that can be formed in a semiconductor substrate, making it difficult to increase the capacitance of the capacitor.

[0005] An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the capacitance of a capacitor structure formed inside a trench in a semiconductor substrate is increased.

[0006] A semiconductor device according to one aspect of the present invention includes a bonded substrate, a first conductive film, and one or more dielectric films and a second conductive film. The bonded substrate includes a first substrate having a first groove penetrating between a first main surface and a second main surface, and a second substrate having a second groove penetrating between a third main surface and a fourth main surface, the first substrate and the second substrate being bonded together. The first conductive film is formed so as to contact at least the first main surface, the fourth main surface, the wall surface of the first groove, and the wall surface of the second groove, among the entire surface of the bonded substrate. The one or more dielectric films and the second conductive film are alternately stacked on the first conductive film.

[0007] A method for manufacturing a semiconductor device according to another aspect of the present invention includes the steps of: forming a first groove penetrating between the first and second main surfaces of a first substrate; forming a second groove penetrating between the third and fourth main surfaces of a second substrate; forming a bonded substrate by bonding the first and second substrates with the second and third main surfaces facing each other; forming a first conductor film so as to contact at least the first and fourth main surfaces, the wall surfaces of the first and second grooves, and the wall surfaces of the second grooves, of the entire surface of the bonded substrate; and stacking one or more dielectric films and second conductor films alternately on the first conductor film.

[0008] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device in which the capacitance of a capacitor structure formed inside a trench in a semiconductor substrate is increased.

[0009] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device 100 according to an embodiment. FIG. 2 is a plan view showing the structure of a bonded substrate 1 including a first substrate 10 and a second substrate 11 of the semiconductor device 100 of FIG. 1. FIG. 3 is a plan view showing the structure of the first substrate 10 of the semiconductor device 100 of FIG. 1. FIG. 4 is a plan view showing the structure of the second substrate 11 of the semiconductor device 100 of FIG. 1. FIG. 5 is a cross-sectional perspective view showing a part of the first substrate 10 cut along the I-I cut plane of FIG. 3, showing a manufacturing process of the semiconductor device 100. FIG. 6 is a cross-sectional perspective view showing a part of the second substrate 11 cut along the I-I cut plane of FIG. 4, showing a manufacturing process of the semiconductor device 100. FIG. 7 is a cross-sectional perspective view showing a part of the manufacturing process of the semiconductor device 100 (part 2). FIG. 8 is a cross-sectional view taken along the I-I cut plane in the manufacturing process shown in FIG. 7. FIG. 9 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device 100 (part 3). FIG. 10 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device 100 (part 4). 11 is a cross-sectional view showing the manufacturing process of the semiconductor device 100 (part 5). FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device 100 (part 6). FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device 100 (part 7). FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device 100 (part 8).

[0010] The embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

[0011] [Configuration of Semiconductor Device 100] The configuration of a semiconductor device 100 according to an embodiment will be described with reference to Figures 1 to 4. Figure 1 is a cross-sectional view showing the configuration of the semiconductor device 100 according to an embodiment. Figure 2 is a plan view showing the structure of a bonded substrate 1 made up of a first substrate 10 and a second substrate 11 in the semiconductor device 100 of Figure 1. Figure 3 is a plan view showing the structure of the first substrate 10 in the semiconductor device 100 of Figure 1. Figure 4 is a plan view showing the structure of the second substrate 11 in the semiconductor device 100 of Figure 1. The cross-sectional view of Figure 1 is a cross-sectional view taken along the I-I cross section of Figures 2 to 4.

[0012] As shown in Fig. 1, the semiconductor device 100 includes a bonded substrate 1 formed by bonding a first substrate 10 and a second substrate 11, a first conductive film 31, one or more dielectric films 33, and second conductive films 32a and 32b. Figures 1 to 4 show a unit cell of the semiconductor device 100. The semiconductor device 100 is formed by repeatedly forming the unit cells shown in Figs. 1 to 4 within the XY plane in the figures.

[0013] 1 to 3, the first substrate 10 has a first main surface 10A, a second main surface 10B facing in the opposite direction to the first main surface 10A, and first grooves 20a and 20b that penetrate between the first main surface 10A and the second main surface 10B. On the other hand, as shown in Figures 1, 2, and 4, the second substrate 11 has a third main surface 11A, a fourth main surface 11B facing in the opposite direction to the third main surface 11A, and second grooves 21a and 21b that penetrate between the third main surface 11A and the fourth main surface 11B.

[0014] When the first grooves 20a and 20b are collectively referred to without distinction, they are called the first groove 20. When the second grooves 21a and 21b are collectively referred to without distinction, they are called the second groove 21. When the first groove 20 and the second groove 21 are collectively referred to without distinction, they are called the groove 2.

[0015] 2 and 3, the first groove 20 has a longitudinal direction (Y direction) and a lateral direction (X direction) when viewed from the normal direction (Z direction) of the first main surface 10A. The first grooves 20a and 20b are arranged in the lateral direction (X direction).

[0016] 2 and 4, the second grooves 21 have a longitudinal direction (X direction) and a lateral direction (Y direction) when viewed from the normal direction (Z direction) of the first main surface 10A. The second grooves 21a and 21b are arranged in the lateral direction (Y direction).

[0017] 2, when viewed from the normal direction (Z direction) of first main surface 10A, the longitudinal direction (Y direction) of first groove 20 intersects with the longitudinal direction (X direction) of second groove 21. When bonded substrate 1 is viewed from the normal direction (Z direction) of first main surface 10A, portions 22a to 22d of first grooves 20a, 20b overlap portions of second grooves 21a, 21b.

[0018] As shown in FIGS. 1 and 2 , the bonded substrate 1 is formed by directly bonding the first substrate 10 and the second substrate 11 together with the second main surface 10B of the first substrate 10 facing the third main surface 11A of the second substrate 11. In the embodiment, the bonded substrate 1 is described as being formed of two substrates (the first substrate 10 and the second substrate 11). However, the bonded substrate 1 may include three or more substrates. In the case of three or more substrates, the first substrate 10 and the second substrate 11 are disposed at the top and bottom in the stacking direction (Z direction), respectively, and the third and subsequent substrates are sandwiched between the first substrate 10 and the second substrate 11. Even in this case, the bonded substrate 1 is formed by bonding the first substrate 10 and the second substrate 11 together with the second main surface 10B of the first substrate 10 facing the third main surface 11A of the second substrate 11 facing each other. In other words, the first substrate 10 and the second substrate 11 may be bonded directly or indirectly. It is desirable that the third and subsequent substrates also have grooves 2 similar to those of the first substrate 10 or the second substrate 11 .

[0019] The first conductor film 31 is formed so as to be in contact with at least the first main surface 10A, the fourth main surface 11B, the wall surfaces 1A of the first grooves 20a and 20b, and the wall surfaces 1A of the second grooves 21a and 21b out of the entire surface of the bonded substrate 1. In the semiconductor device 100 shown in FIG. 1 , the first conductor film 31 is also formed on a portion of the second main surface 10B.

[0020] One or more dielectric films 33 and second conductor films 32a, 32b are alternately stacked on the first conductor film 31. That is, one or more dielectric films 33 and second conductor films 32a, 32b are alternately stacked on at least the first main surface 10A, the fourth main surface 11B, and the wall surface 1A of the groove 2. Thus, a capacitor structure is formed inside the groove 2, in which one or more dielectric films 33 and second conductor films 32a, 32b are alternately stacked.

[0021] As shown in FIG. 1 , in this embodiment, two or more dielectric films 33 and second conductor films 32a, 32b are alternately stacked on the first conductor film 31. The groove 2 is backfilled with two or more dielectric films 33 and second conductor films 32a, 32b. A high-potential second conductor film 32a is disposed on the first conductor film 31, with a dielectric film 33 interposed therebetween. A low-potential second conductor film 32b is disposed on the second conductor film 32a, with a dielectric film 33 interposed therebetween. A high-potential second conductor film 32a is again disposed on the second conductor film 32b, with a dielectric film 33 interposed therebetween. In this way, a total of two high-potential second conductor films 32a and two low-potential second conductor films 32b are alternately stacked with a dielectric film 33 interposed therebetween. Of course, three or more dielectric films 33 and second conductor films 32a, 32b may be stacked inside the groove 2.

[0022] The semiconductor device 100 further includes a first contact hole 61a and a second contact hole 62a formed above the first main surface 10A, a first electrode 51a partially embedded in the first contact hole 61a and electrically connected to the second conductive film 32a, and a second electrode 52a partially embedded in the second contact hole 62a and electrically connected to at least the first conductive film 31.

[0023] The first contact hole 61a penetrates the dielectric film 33 and the second conductor films 32a and 32b deposited above the first main surface 10A, and its bottom surface reaches the second conductor film 32a. The second contact hole 62a penetrates the dielectric film 33 and the second conductor films 32a and 32b deposited above the first main surface 10A, and its bottom surface reaches the first conductor film 31 or the second conductor film 32b.

[0024] A portion of the first electrode 51a is embedded in the first contact hole 61a via the interlayer insulating film 41, and is ohmically connected to the second conductor film 32a at the bottom of the first contact hole 61a. The first electrode 51a and the side surface of the first contact hole 61a are electrically insulated by the interlayer insulating film 41. A portion of the second electrode 52a is embedded in the second contact hole 62a via the interlayer insulating film 41, and is ohmically connected to the first conductor film 31 or the second conductor film 32b at the bottom of the second contact hole 62a. The second electrode 52a and the side surface of the second contact hole 62a are electrically insulated by the interlayer insulating film 41.

[0025] The semiconductor device 100 further includes a third contact hole 61b and a fourth contact hole 62b formed below (in the -Z direction) the fourth main surface 11B, a third electrode 51b partially embedded in the third contact hole 61b and electrically connected to the second conductive film 32a, and a fourth electrode 52b partially embedded in the fourth contact hole 62b and electrically connected to at least the first conductive film 31.

[0026] The third contact hole 61b penetrates the dielectric film 33 and the second conductor films 32a and 32b deposited below the fourth main surface 11B (in the −Z direction), with its bottom reaching the second conductor film 32a. The fourth contact hole 62b penetrates the dielectric film 33 and the second conductor films 32a and 32b deposited below the fourth main surface 11B, with its bottom reaching the first conductor film 31 or the second conductor film 32b.

[0027] A portion of the third electrode 51b is embedded in the third contact hole 61b via the interlayer insulating film 42, and is ohmically connected to the second conductor film 32a at the bottom of the third contact hole 61b. The third electrode 51b and the side surface of the third contact hole 61b are electrically insulated by the interlayer insulating film 42. A portion of the fourth electrode 52b is embedded in the fourth contact hole 62b via the interlayer insulating film 42, and is ohmically connected to the first conductor film 31 or the second conductor film 32b at the bottom of the fourth contact hole 62b. The fourth electrode 52b and the side surface of the fourth contact hole 62b are electrically insulated by the interlayer insulating film 42.

[0028] The aspect ratio of the depth and width of the grooves that can be formed in each of the substrates 10 and 11 is limited depending on the manufacturing method, etc. Therefore, the capacitance of the capacitor structure formed inside the groove is naturally limited. In contrast, the semiconductor device 100 has a capacitor structure formed inside a groove 2 of a bonded substrate 1 formed by bonding a first substrate 10 having a first groove 20 formed therein and a second substrate 11 having a second groove 21 formed therein. The bonded substrate 1 can have a larger total depth of the grooves 2 than the substrates 10 and 11 alone. This allows the capacitance of the capacitor structure formed inside the groove 2 to be increased.

[0029] Conventionally, there has been a problem in that the ESR (equivalent series resistance) of the bonded substrates increases due to native oxide films or contamination on the surfaces of the substrates. Therefore, by forming the first conductive film 31 so that it contacts at least the wall surface 1A of the groove 2 among the entire surface of the bonded substrate 1, the surface of the bonded substrate 1 is electrically connected to the first conductive film 31, allowing the bonded substrate to be used as an electrode and reducing the ESR. Furthermore, the substrates 10 and 11 can be ohmically connected to each other.

[0030] The basic operation of the semiconductor device 100 will now be described. A positive voltage is applied to the first electrode 51a and the third electrode 51b on the high potential side, and a negative voltage is applied to the second electrode 52a and the fourth electrode 52b on the low potential side. This causes a positive charge to be charged to the second conductor film 32a electrically connected to the first electrode 51a and the third electrode 51b, and a negative charge to be charged to the first conductor film 31 and the second conductor film 32b electrically connected to the second electrode 52a and the fourth electrode 52b. At this time, polarization occurs within the dielectric film 33, generating capacitance. A structure (capacitor structure) is formed in which capacitors consisting of four layers of second conductor films 32a and 32b deposited along the wall surface 1A of the groove 2 are connected in parallel. This significantly improves the capacitance density of the capacitor per unit area.

[0031] [Method for Manufacturing Semiconductor Device 100] A method for manufacturing the semiconductor device 100 according to the embodiment will be described below with reference to Figures 5 to 14. Note that the method for manufacturing the semiconductor device 100 described below is one example, and various other manufacturing methods, including modifications thereof, are possible.

[0032] 5, first grooves 20a and 20b are formed by etching a part of the first main surface 10A of the conductive first substrate 10. The first substrate 10 is made of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (GaO). ２ O ３ In this embodiment, the first substrate 10 is doped with a high concentration of n-type or p-type impurities and has conductivity. For example, the resistivity is 1×10 −４ ~1×10 −５ Ω cm ２ A silicon substrate with a high impurity concentration of about 1000 .mu.m can be used as the first substrate 10. Since the first substrate 10 can be used as a conductive layer, the capacitance density of the capacitor is improved.

[0033] Specifically, a mask material 71 is first formed on the first main surface 10A of the first substrate 10. A silicon oxide film can be used as the mask material 71, and thermal CVD or plasma CVD can be used as the deposition method. Next, resist is patterned on the mask material 71. A typical photolithography method can be used as the patterning method. The mask material 71 is etched using the patterned resist as a mask. As shown in FIG. 5 , the mask material 71 has openings where the first grooves 20a and 20b will be formed. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. Next, the resist is removed using oxygen plasma, sulfuric acid, or the like. By dry etching using the mask material 71 thus formed, the first substrate 10 exposed through the openings in the mask material 71 is etched, forming the first grooves 20 penetrating between the first main surface 10A and the second main surface 10B.

[0034] When forming the first grooves 20a, 20b in the Si substrate, wet etching using HF (hydrofluoric acid) or KOH (potassium hydroxide), or dry etching using plasma can be used as the etching method. For dry etching of the first substrate 10, plasma can be generated using fluorine gas (SF6, CF4, etc.). Wet etching is less expensive than dry etching and is suitable for mass production. Dry etching allows for more accurate and superior pattern formation than wet etching, but requires more advanced equipment and operation techniques. FIG. 5 is a cross-sectional perspective view showing the first substrate 10, including the cut surface taken along the I-I cut surface in FIGS. 2 and 3 .

[0035] As shown in Fig. 6 , a second groove 21 is formed in the second substrate 11, penetrating between the third main surface 11A and the fourth main surface 11B, using a mask material 72 as an etching mask, in the same manner as the first groove 20 in the first substrate 10. Fig. 6 is a cross-sectional perspective view showing the second substrate 11 including a cut surface cut along the I-I cut surface in Figs. 2 and 4 . A wall surface 1A of the groove 2 includes a crystal plane equivalent to the (111) plane of the first substrate 10 and the second substrate 11.

[0036] As shown in FIGS. 7 and 8 , the first substrate 10 and the second substrate 11 are bonded together with the second main surface 10B of the first substrate 10 facing the third main surface 11A of the second substrate 11. This forms a bonded substrate 1. The substrates can be bonded, for example, by a diffusion bonding method. Specifically, after cleaning the surfaces of the first substrate 10 and the second substrate 11, the first substrate 10 and the second substrate 11 are bonded together and annealed at a high temperature of 400° C. or higher to bond the two substrates. Alternatively, room-temperature bonding may be used. Alternatively, an "indirect bonding method" may be used in which an adhesive, metal, low-melting-point glass, or the like is disposed as an adhesive layer between the second main surface 10B of the first substrate 10 and the third main surface 11A of the second substrate 11.

[0037] Next, as shown in FIG. 9 , a first conductor film 31 is formed on the entire surface of the bonded substrate 1, contacting at least the first main surface 10A of the first substrate 10, the fourth main surface 11B of the second substrate 11, the wall surface 1A of the first groove 20, and the wall surface 1A of the second groove 21. The first conductor film 31 is also formed on a portion of the second main surface 10B of the first substrate 10. Here, conductive polysilicon doped with a high concentration of n-type impurities is used as the first conductor film 31, but conductive polysilicon doped with p-type impurities may also be used. Alternatively, a metal material such as titanium (Ti) or aluminum (Al), a silicide film, or conductive polysilicon carbide (SiC) may also be used. Since the first conductor film 31 is formed directly on the surface of the bonded substrate 1, it is electrically connected to the bonded substrate 1. Therefore, the bonded substrate 1 can be used as an electrode, thereby reducing ESR.

[0038] When n-type polysilicon is used, the first conductor film 31 can be formed using a CVD (chemical vapor deposition) method or a sputtering method. After the film formation, an annealing treatment is performed in POCl3 at 950°C to form an n-type polysilicon film, which can impart conductivity to the first conductor film 31. This also promotes crystallization of the first conductor film 31 and diffusion of impurities, improving the characteristics of the first conductor film 31. On the other hand, when a metal material is used, the first conductor film 31 can be formed using a vapor deposition method, a sputtering method, a CVD method, or the like.

[0039] Dielectric films 33 and second conductor films 32a, 32b are alternately stacked in four layers so as to cover the first conductor film 31. The dielectric film 33 can be, for example, a silicon oxide film. Thermal oxidation or thermal CVD can be used as a method for depositing the silicon oxide film. When using thermal CVD, reduced pressure conditions can be used to deposit the silicon oxide film with good coverage even when the trench 2 is deep. The material and deposition method for the second conductor films 32a, 32b are the same as those for the first conductor film 31. The trench 2 is backfilled with four layers of dielectric films 33 and four layers of second conductor films 32a, 32b. The state after the above steps are completed is shown in FIG. 10.

[0040] The dielectric film 33 and the second conductor films 32a and 32b are selectively etched to form a first contact hole 61a, a third contact hole 61b, a second contact hole 62a, and a fourth contact hole 62b. When the first contact hole 61a, the third contact hole 61b, the second contact hole 62a, and the fourth contact hole 62b are collectively referred to as "contact holes 6," they are not distinguished from one another. Specifically, a patterned mask material (not shown) is first formed by applying a photoresist above the first main surface 10A of the first substrate 10 and exposing it to light. A patterned mask material (not shown) is then formed by applying a photoresist below the fourth main surface 11B of the second substrate 11 and exposing it to light. The patterned mask material has openings in areas where the contact holes 6 will be formed. The mask material is used to selectively etch the dielectric film 33 and the second conductor films 32a and 32b exposed through the openings in the mask material. Anisotropic etching may be used as the etching method. The dielectric film 33 and the second conductor films 32a and 32b exposed through the openings in the mask material are removed to form the contact holes 6. The first contact hole 61a, the second contact hole 62a, the third contact hole 61b, and the fourth contact hole 62b, each having a different depth, are formed using different mask materials and in different etching processes. The state after the above processes are completed is shown in FIG.

[0041] Next, interlayer insulating films 41 and 42 are deposited on the inner surface of the contact hole 6 and on the uppermost dielectric film 33. The thickness of the interlayer insulating films 41 and 42 is preferably such that they do not backfill the contact hole 6. Silicon oxide films can be used for the interlayer insulating films 41 and 42. The state after the above steps are completed is shown in FIG.

[0042] Next, mask materials 73 and 74 made of patterned photoresist are formed on the interlayer insulating films 41 and 42. The interlayer insulating films 41 and 42 deposited on the bottom of the contact hole 6 are exposed through the openings of the patterned mask materials 73 and 74. The interlayer insulating films 41 and 42 deposited on the bottom of the contact hole 6 are selectively etched using the mask materials 73 and 74. Anisotropic etching may be used as the etching method. The state after the above steps is completed is shown in FIG. 13. The first conductor film 31 or the second conductor films 32a and 32b are exposed at the bottom of the contact hole 6. The interlayer insulating films 41 and 42 remain on the side surfaces of the contact hole 6.

[0043] Next, after removing the mask materials 73 and 74, electrode films 5a and 5b are deposited to cover the first main surface 10A and the fourth main surface 11B. The metal film can be deposited by sputtering, electron beam (EB) evaporation, or atomic layer deposition (ALD). Portions of the electrode films 5a and 5b are embedded in the contact holes 6 and electrically connected to the first conductor film 31 or the second conductor films 32a and 32b exposed at the bottom. The state after the above steps are completed is shown in FIG. 14.

[0044] Next, a mask material (not shown) made of a silicon oxide film is formed on the electrode films 5a and 5b, and the mask material is patterned using lithography and etching techniques. The patterned mask material is used to selectively etch the electrode films 5a and 5b by dry etching or wet etching. Alternatively, the electrode films 5a and 5b may be patterned using a lift-off method. As a result, the first electrode 51a, the second electrode 52a, the third electrode 51b, and the fourth electrode 52b are formed, as shown in FIG. 1. Through the above steps, the semiconductor device 100 shown in FIG. 1 is completed.

[0045] [Effects] According to the embodiment, the following effects can be obtained.

[0046] By bonding together multiple substrates 10, 11, each having a groove 2 penetrating the front and back surfaces, the capacitance of the capacitor structure formed in the groove 2 can be increased. This increases the capacitance density per unit area of ​​the semiconductor device 100. Furthermore, a problem has been encountered in the past where a natural oxide film or contamination on the surfaces of the substrates 10, 11 increases the equivalent series resistance (ESR) of the bonded substrate 1. Therefore, by forming a first conductive film 31 in contact with at least the wall surface 1A within the groove 2 of each of the multiple substrates 10, 11, the surfaces of the substrates 10, 11 are electrically connected to the first conductive film, allowing the bonded substrate 1 to be used as an electrode, thereby reducing ESR. Furthermore, the substrates 10, 11 can be ohmically connected to each other.

[0047] When viewed from the normal direction (Z direction) of first main surface 10A, the longitudinal direction (Y direction) of first grooves 20a, 20b intersects with the longitudinal direction (X direction) of second grooves 21a, 21b. By forming intersecting rectangular grooves 2 in the depth direction (Z direction) of bonded substrate 1, warping of bonded substrate 1 when dielectric film 33 is laminated thereon can be reduced.

[0048] 2, when the bonded substrate 1 is viewed in the normal direction (Z direction) of the first main surface 10A, portions of the first grooves 20a, 20b overlap with portions 22a-22d of the second grooves 21a, 21b. The portions 22a-22d are grooves that penetrate from the first main surface 10A to the fourth main surface 11B. It is possible to form grooves 2 that exceed the aspect ratio limitations that depend on the manufacturing method, etc. By forming the grooves (portions 22a-22d) that penetrate the bonded substrate 1, stress concentration on the bonded substrate 1 when the dielectric film 33 is laminated can be avoided, and warping of the bonded substrate 1 can be reduced.

[0049] The semiconductor device 100 further includes a first electrode 51 a partially embedded in a first contact hole 61 a formed above the first main surface 10 A, and a second electrode 52 a partially embedded in a second contact hole 62 a formed above the first main surface 10 A. By forming the first electrode 51 a on the high potential side and the second electrode 52 a on the low potential side on the front surface side of the bonded substrate 1, the semiconductor device 100 can be electrically connected to an external circuit element.

[0050] The semiconductor device 100 further includes a third contact hole 61b and a fourth contact hole 62b formed below the fourth main surface 11B, a third electrode 51b partially embedded in the third contact hole 61b, and a fourth electrode 52b partially embedded in the fourth contact hole 62b. The high-potential third electrode 51b and the low-potential fourth electrode 52b are also formed on the back surface of the bonding substrate 1. Thus, by stacking a plurality of chip-shaped semiconductor devices 100 in the thickness direction (Z direction) of the bonding substrate 1 and bonding the electrodes together, a module with improved capacitance or withstand voltage can be easily produced.

[0051] If the first conductive film 31 is made of a metal, the ESR can be further reduced.

[0052] When the first conductor film 31 is made of polysilicon, the first conductor film 31 can be grown uniformly on the wall surface 1A of the trench 2 by low pressure CVD.

[0053] Two or more layers of dielectric films 33 and second conductive films 32a and 32b are alternately stacked on the first conductive film 31. This can further improve the capacitance density.

[0054] The first substrate 10 and the second substrate 11 are made of single crystal silicon, and the wall surface 1A of the groove 2 includes a crystal plane equivalent to the (111) plane of the first substrate 10 and the second substrate 11. This allows the groove 2 to be formed by inexpensive anisotropic wet etching.

[0055] By making the first substrate 10 and the second substrate 11 conductive, the substrates can be used as electrodes.

[0056] By using silicon substrates for the first substrate 10 and the second substrate 11, they can be manufactured at low cost.

[0057] After forming a groove 2 that penetrates each of the first substrate 10 and the second substrate 11, the first substrate 10 and the second substrate 11 are bonded together, thereby creating a groove 2 with a large aspect ratio in the thickness direction (Z direction) of the bonded substrate 1.

[0058] Although the embodiments have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0059] Although the case where a single crystal silicon substrate is used as the bonding substrate 1 has been described, a semiconductor substrate made of other semiconductor materials with wide bandgaps may also be used, such as gallium nitride (GaN), diamond, zinc oxide (ZnO), and AlGaN-based materials.

[0060] REFERENCE SIGNS LIST 1 Bonded substrate 1A Wall surface 10 First substrate 10A First main surface 10B Second main surface 11 Second substrate 11A Third main surface 11B Fourth main surface 20a, 20b First groove 21a, 21b Second groove 31 First conductor film 32a, 32b Second conductor film 33 Dielectric film 41, 42 Interlayer insulating film 51a First electrode 51b Third electrode 52a Second electrode 52b Fourth electrode 61a First contact hole 61b Third contact hole 62a Second contact hole 62b Fourth contact hole 71 to 74 Mask material 100 Semiconductor device

Claims

a bonded substrate comprising: a first substrate having a first main surface, a second main surface facing in a direction opposite to the first main surface, and a first groove penetrating between the first main surface and the second main surface; and a second substrate having a third main surface, a fourth main surface facing in a direction opposite to the third main surface, and a second groove penetrating between the third main surface and the fourth main surface, wherein the first substrate and the second substrate are bonded together with the second main surface and the third main surface facing each other; a first conductor film formed so as to contact at least the first main surface, the fourth main surface, a wall surface of the first groove, and a wall surface of the second groove among the entire surface of the bonded substrate; one or more dielectric films and second conductive films alternately stacked on the first conductive film; A semiconductor device having:

2. The semiconductor device according to claim 1, wherein the first groove has a longitudinal direction and a lateral direction when viewed from a normal direction of the first main surface, the second groove has a longitudinal direction and a lateral direction when viewed from a normal direction of the third main surface, and the longitudinal direction of the first groove intersects with the longitudinal direction of the second groove.

3. The semiconductor device according to claim 1, wherein a portion of the first groove and a portion of the second groove overlap when the junction substrate is viewed in a direction normal to the first main surface. 　 a first contact hole and a second contact hole formed above the first main surface; a first electrode partially embedded in the first contact hole and electrically connected to the second conductive film; a second electrode partially embedded in the second contact hole and electrically connected to the first conductive film; The semiconductor device according to claim 1 , wherein the first and second electrodes are electrically connected to each other. 　 a third contact hole and a fourth contact hole formed below the fourth main surface; a third electrode partially embedded in the third contact hole and electrically connected to the second conductive film; a fourth electrode partially embedded in the fourth contact hole and electrically connected to the first conductive film; The semiconductor device according to claim 4 , comprising:

6. The semiconductor device according to claim 1, wherein the first conductive film is a metal.

6. The semiconductor device according to claim 1, wherein the first conductive film is polysilicon.

8. The semiconductor device according to claim 1, wherein two or more layers of the dielectric film and the second conductive film are alternately stacked on the first conductive film. 　 the first substrate and the second substrate are made of single crystal silicon, 9. The semiconductor device according to claim 1, wherein wall surfaces of the first and second grooves include a crystal plane equivalent to a (111) plane of the first and second substrates. 　 The semiconductor device according to claim 1 , wherein the bonding substrate is electrically conductive. 　 The semiconductor device according to claim 1 , wherein the bonding substrate is made of a silicon substrate. 　 forming a first groove penetrating between a first main surface and a second main surface of a first substrate; forming a second groove penetrating between the third main surface and the fourth main surface of the second substrate; forming a bonded substrate by bonding the first substrate and the second substrate together with the second main surface and the third main surface facing each other; forming a first conductor film so as to be in contact with at least the first main surface, the fourth main surface, a wall surface of the first groove, and a wall surface of the second groove among the entire surface of the bonded substrate; laminating one or more dielectric films and second conductive films alternately on the first conductive film; A method for manufacturing a semiconductor device having the above structure.

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